diff options
| author | Artur Artamonov <freeartman@wechall.net> | 2013-10-15 07:51:50 +0300 |
|---|---|---|
| committer | Artur Artamonov <freeartman@wechall.net> | 2013-10-15 07:51:50 +0300 |
| commit | 3b9e39f8fb790e6da476ab4cb8ad984c2b23c077 (patch) | |
| tree | cd1b2930605a266f9e8cbd96099d487a0fff78ff /toolchain | |
| parent | 7d8cdbb9844469b82ec66250b9320e9ae07fc996 (diff) | |
Big partes ported, fixed some loongsoon command generation
Diffstat (limited to 'toolchain')
| -rw-r--r-- | toolchain/binutils/patches/2.22/999_realtek_2_22.patch | 3054 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.8-linaro/999_realtek.patch | 917 |
2 files changed, 3846 insertions, 125 deletions
diff --git a/toolchain/binutils/patches/2.22/999_realtek_2_22.patch b/toolchain/binutils/patches/2.22/999_realtek_2_22.patch index f8b3713d1..0845b84d7 100644 --- a/toolchain/binutils/patches/2.22/999_realtek_2_22.patch +++ b/toolchain/binutils/patches/2.22/999_realtek_2_22.patch @@ -44,40 +44,74 @@ diff -rupN ./bu.orig/bfd/bfd-in2.h ./bu.new/bfd/bfd-in2.h BFD_RELOC_MICROMIPS_LITERAL, diff -rupN ./bu.orig/bfd/cpu-mips.c ./bu.new/bfd/cpu-mips.c --- a/bfd/cpu-mips.c 2011-07-24 17:20:05.000000000 +0300 -+++ b/bfd/cpu-mips.c 2013-09-20 11:26:11.114532953 +0300 -@@ -94,7 +94,15 @@ enum ++++ b/bfd/cpu-mips.c 2013-10-14 20:42:12.869766152 +0300 +@@ -62,6 +62,13 @@ enum + { + I_mips3000, + I_mips3900, ++ I_mips_rlx4081, ++ I_mips_rlx4180, ++ I_mips_rlx4181, ++ I_mips_rlx4281, ++ I_mips_rlx5181, ++ I_mips_rlx5280, ++ I_mips_rlx5281, + I_mips4000, + I_mips4010, + I_mips4100, +@@ -94,7 +101,7 @@ enum I_loongson_3a, I_mipsocteon, I_xlr, - I_micromips + I_micromips, -+ I_mipsrlx4081, -+ I_mipsrlx4180, -+ I_mipsrlx4181, -+ I_mipsrlx4281, -+ I_mipsrlx5181, -+ I_mipsrlx5280, -+ I_mipsrlx5281, -+ }; #define NN(index) (&arch_info_struct[(index) + 1]) -@@ -135,7 +143,14 @@ static const bfd_arch_info_type arch_inf +@@ -103,6 +110,13 @@ static const bfd_arch_info_type arch_inf + { + N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)), + N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)), ++ N (32, 32, bfd_mach_mips_rlx4081,"mips:rlx4081",FALSE, NN(I_mips_rlx4081)), ++ N (32, 32, bfd_mach_mips_rlx4180,"mips:rlx4180",FALSE, NN(I_mips_rlx4180)), ++ N (32, 32, bfd_mach_mips_rlx4181,"mips:rlx4181",FALSE, NN(I_mips_rlx4181)), ++ N (32, 32, bfd_mach_mips_rlx4281,"mips:rlx4281",FALSE, NN(I_mips_rlx4281)), ++ N (32, 32, bfd_mach_mips_rlx5181,"mips:rlx5181",FALSE, NN(I_mips_rlx5181)), ++ N (32, 32, bfd_mach_mips_rlx5280,"mips:rlx5280",FALSE, NN(I_mips_rlx5280)), ++ N (32, 32, bfd_mach_mips_rlx5281,"mips:rlx5281",FALSE, NN(I_mips_rlx5281)), + N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)), + N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)), + N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)), +@@ -135,7 +149,7 @@ static const bfd_arch_info_type arch_inf N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)), N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)), N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), - N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0) + N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0), -+ N (32, 32, bfd_mach_mips_rlx4081,"mips:rlx4081",FALSE,NN(I_mipsrlx4081)), -+ N (32, 32, bfd_mach_mips_rlx4180,"mips:rlx4180",FALSE,NN(I_mipsrlx4180)), -+ N (32, 32, bfd_mach_mips_rlx4181,"mips:rlx4181",FALSE,NN(I_mipsrlx4181)), -+ N (32, 32, bfd_mach_mips_rlx4281,"mips:rlx4281",FALSE,NN(I_mipsrlx4281)), -+ N (32, 32, bfd_mach_mips_rlx5181,"mips:rlx5181",FALSE,NN(I_mipsrlx5181)), -+ N (32, 32, bfd_mach_mips_rlx5280,"mips:rlx5280",FALSE,NN(I_mipsrlx5280)), -+ N (32, 32, bfd_mach_mips_rlx5281,"mips:rlx5281",FALSE,NN(I_mipsrlx5281)) }; /* The default architecture is mips:3000, but with a machine number of +diff -rupN ./bu.orig/bfd/doc/bfd.texinfo ./bu.new/bfd/doc/bfd.texinfo +--- a/bfd/doc/bfd.texinfo 2010-10-28 14:40:25.000000000 +0300 ++++ b/bfd/doc/bfd.texinfo 2013-10-11 16:20:58.349499163 +0300 +@@ -322,7 +322,7 @@ All of BFD lives in one directory. + @printindex cp + + @tex +-% I think something like @colophon should be in texinfo. In the ++% I think something like @@colophon should be in texinfo. In the + % meantime: + \long\def\colophon{\hbox to0pt{}\vfill + \centerline{The body of this manual is set in} +@@ -333,7 +333,7 @@ All of BFD lives in one directory. + \centerline{{\sl\fontname\tensl\/}} + \centerline{are used for emphasis.}\vfill} + \page\colophon +-% Blame: doc@cygnus.com, 28mar91. ++% Blame: doc@@cygnus.com, 28mar91. + @end tex + + @bye diff -rupN ./bu.orig/bfd/elf32-mips.c ./bu.new/bfd/elf32-mips.c --- a/bfd/elf32-mips.c 2011-07-24 17:20:05.000000000 +0300 +++ b/bfd/elf32-mips.c 2013-09-26 19:52:44.694112357 +0300 @@ -264,8 +298,31 @@ diff -rupN ./bu.orig/bfd/libbfd.h ./bu.new/bfd/libbfd.h "BFD_RELOC_MICROMIPS_7_PCREL_S1", diff -rupN ./bu.orig/bfd/reloc.c ./bu.new/bfd/reloc.c --- a/bfd/reloc.c 2011-07-24 17:20:06.000000000 +0300 -+++ b/bfd/reloc.c 2013-09-26 20:54:56.957652516 +0300 -@@ -2246,6 +2246,24 @@ ENUM ++++ b/bfd/reloc.c 2013-10-14 13:51:07.800130671 +0300 +@@ -52,6 +52,7 @@ SECTION + #include "bfd.h" + #include "bfdlink.h" + #include "libbfd.h" ++#include "elf/mips.h" + /* + DOCDD + INODE +@@ -833,6 +834,14 @@ space consuming. For each target: + } + */ + ++ /* R_RELOC_RLX_OFF6A: used in ltw instruction */ ++ if (howto->type == R_RELOC_RLX_OFF6A) ++ { ++ if ((relocation % 8) != 0) ++ return bfd_reloc_notmultipleof8_ltw; ++ } ++ ++ + relocation >>= (bfd_vma) howto->rightshift; + + /* Shift everything up to where it's going to be used. */ +@@ -2246,6 +2255,24 @@ ENUM ENUMDOC MIPS16 low 16 bits. @@ -292,7 +349,7 @@ diff -rupN ./bu.orig/bfd/reloc.c ./bu.new/bfd/reloc.c ENUMX diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c --- a/gas/config/tc-mips.c 2011-11-21 11:29:32.000000000 +0200 -+++ b/gas/config/tc-mips.c 2013-10-04 19:45:05.374380048 +0300 ++++ b/gas/config/tc-mips.c 2013-10-14 20:47:24.949783533 +0300 @@ -104,6 +104,35 @@ static char *mips_regmask_frag; #define ILLEGAL_REG (32) @@ -1388,15 +1445,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c OPTION_END_OF_ENUM }; -@@ -14303,6 +15061,7 @@ struct option md_longopts[] = - {"mips64", no_argument, NULL, OPTION_MIPS64}, - {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, - {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, -+ {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, - - /* Options which specify Application Specific Extensions (ASEs). */ - {"mips16", no_argument, NULL, OPTION_MIPS16}, -@@ -14396,6 +15155,9 @@ struct option md_longopts[] = +@@ -14396,6 +15154,9 @@ struct option md_longopts[] = {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, #endif /* OBJ_ELF */ @@ -1406,7 +1455,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c {NULL, no_argument, NULL, 0} }; -@@ -14431,6 +15193,18 @@ md_parse_option (int c, char *arg) +@@ -14431,6 +15192,18 @@ md_parse_option (int c, char *arg) mips_disable_float_construction = 1; break; @@ -1425,7 +1474,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c case OPTION_TRAP: mips_trap = 1; break; -@@ -14509,6 +15283,9 @@ md_parse_option (int c, char *arg) +@@ -14509,6 +15282,9 @@ md_parse_option (int c, char *arg) mips_set_option_string (&mips_arch_string, arg); break; @@ -1435,7 +1484,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c case OPTION_M4650: mips_set_option_string (&mips_arch_string, "4650"); mips_set_option_string (&mips_tune_string, "4650"); -@@ -15036,7 +15813,7 @@ mips_after_parse_args (void) +@@ -15036,7 +15812,7 @@ mips_after_parse_args (void) || mips_abi == O32_ABI)) mips_32bitmode = 1; @@ -1444,7 +1493,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c as_bad (_("trap exception not supported at ISA 1")); /* If the selected architecture includes support for ASEs, enable -@@ -15113,6 +15890,9 @@ mips_after_parse_args (void) +@@ -15113,6 +15889,9 @@ mips_after_parse_args (void) } } @@ -1454,7 +1503,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c void mips_init_after_args (void) { -@@ -15369,6 +16149,8 @@ md_apply_fix (fixS *fixP, valueT *valP, +@@ -15369,6 +16148,8 @@ md_apply_fix (fixS *fixP, valueT *valP, case BFD_RELOC_MIPS_TLS_DTPREL_HI16: case BFD_RELOC_MIPS_TLS_DTPREL_LO16: case BFD_RELOC_MIPS_TLS_GOTTPREL: @@ -1463,7 +1512,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c case BFD_RELOC_MIPS_TLS_TPREL_HI16: case BFD_RELOC_MIPS_TLS_TPREL_LO16: case BFD_RELOC_MICROMIPS_TLS_GD: -@@ -15378,6 +16160,13 @@ md_apply_fix (fixS *fixP, valueT *valP, +@@ -15378,6 +16159,13 @@ md_apply_fix (fixS *fixP, valueT *valP, case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: @@ -1477,7 +1526,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c S_SET_THREAD_LOCAL (fixP->fx_addsy); /* fall through */ -@@ -15570,6 +16359,35 @@ md_apply_fix (fixS *fixP, valueT *valP, +@@ -15570,6 +16358,35 @@ md_apply_fix (fixS *fixP, valueT *valP, fixP->fx_done = 0; break; @@ -1513,21 +1562,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c default: internalError (); } -@@ -16186,6 +17004,13 @@ s_mipsset (int x ATTRIBUTE_UNUSED) - case 0: - break; - case ISA_MIPS1: -+ case ISA_RLX4081: -+ case ISA_RLX4180: -+ case ISA_RLX4181: -+ case ISA_RLX4281: -+ case ISA_RLX5181: -+ case ISA_RLX5280: -+ case ISA_RLX5281: - case ISA_MIPS2: - case ISA_MIPS32: - case ISA_MIPS32R2: -@@ -16552,7 +17377,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED) +@@ -16552,7 +17369,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED) use in DWARF debug information. */ static void @@ -1537,7 +1572,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c { expressionS ex; char *p; -@@ -16561,19 +17387,13 @@ s_dtprel_internal (size_t bytes) +@@ -16561,19 +17379,13 @@ s_dtprel_internal (size_t bytes) if (ex.X_op != O_symbol) { @@ -1559,7 +1594,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c demand_empty_rest_of_line (); } -@@ -16582,7 +17402,7 @@ s_dtprel_internal (size_t bytes) +@@ -16582,7 +17394,7 @@ s_dtprel_internal (size_t bytes) static void s_dtprelword (int ignore ATTRIBUTE_UNUSED) { @@ -1568,7 +1603,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c } /* Handle .dtpreldword. */ -@@ -16590,9 +17410,26 @@ s_dtprelword (int ignore ATTRIBUTE_UNUSE +@@ -16590,9 +17402,26 @@ s_dtprelword (int ignore ATTRIBUTE_UNUSE static void s_dtpreldword (int ignore ATTRIBUTE_UNUSED) { @@ -1596,7 +1631,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC code. It sets the offset to use in gp_rel relocations. */ -@@ -16996,6 +17833,9 @@ mips16_extended_frag (fragS *fragp, asec +@@ -16996,6 +17825,9 @@ mips16_extended_frag (fragS *fragp, asec { mintiny = - (1 << (op->nbits - 1)); maxtiny = (1 << (op->nbits - 1)) - 1; @@ -1606,7 +1641,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c } sym_frag = symbol_get_frag (fragp->fr_symbol); -@@ -17203,7 +18043,7 @@ relaxed_branch_length (fragS *fragp, ase +@@ -17203,7 +18035,7 @@ relaxed_branch_length (fragS *fragp, ase { /* Additional space for PIC loading of target address. */ length += 8; @@ -1615,7 +1650,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c /* Additional space for $at-stabilizing nop. */ length += 4; } -@@ -17809,7 +18649,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU +@@ -17809,7 +18641,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU md_number_to_chars ((char *) buf, insn, 4); buf += 4; @@ -1624,24 +1659,24 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c { /* nop */ md_number_to_chars ((char *) buf, 0, 4); -@@ -18906,6 +19746,16 @@ static const struct mips_cpu_info mips_c - { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, - { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, +@@ -18911,6 +19743,16 @@ static const struct mips_cpu_info mips_c + { "r2000", 0, ISA_MIPS1, CPU_R3000 }, + { "r3900", 0, ISA_MIPS1, CPU_R3900 }, + /* RLX */ -+ { "rlx4081", MIPS_CPU_IS_ISA, ISA_RLX4081, CPU_RLX4081 }, -+ { "rlx4180", MIPS_CPU_IS_ISA, ISA_RLX4180, CPU_RLX4180 }, -+ { "rlx4181", MIPS_CPU_IS_ISA, ISA_RLX4181, CPU_RLX4181 }, -+ { "rlx4281", MIPS_CPU_IS_ISA, ISA_RLX4281, CPU_RLX4281 }, -+ { "rlx5181", MIPS_CPU_IS_ISA, ISA_RLX5181, CPU_RLX5181 }, -+ { "rlx5280", MIPS_CPU_IS_ISA, ISA_RLX5280, CPU_RLX5280 }, -+ { "rlx5281", MIPS_CPU_IS_ISA, ISA_RLX5281, CPU_RLX5281 }, -+ -+ - /* MIPS I */ - { "r3000", 0, ISA_MIPS1, CPU_R3000 }, - { "r2000", 0, ISA_MIPS1, CPU_R3000 }, -@@ -19078,7 +19928,13 @@ mips_matching_cpu_name_p (const char *ca ++ // trying to set isa to mips1 ++ { "rlx4081", 0, ISA_MIPS1, CPU_RLX4081 }, ++ { "rlx4180", 0, ISA_MIPS1, CPU_RLX4180 }, ++ { "rlx4181", 0, ISA_MIPS1, CPU_RLX4181 }, ++ { "rlx4281", 0, ISA_MIPS1, CPU_RLX4281 }, ++ { "rlx5181", 0, ISA_MIPS1, CPU_RLX5181 }, ++ { "rlx5280", 0, ISA_MIPS1, CPU_RLX5280 }, ++ { "rlx5281", 0, ISA_MIPS1, CPU_RLX5281 }, ++ + /* MIPS II */ + { "r6000", 0, ISA_MIPS2, CPU_R6000 }, + +@@ -19078,7 +19920,13 @@ mips_matching_cpu_name_p (const char *ca /* If not, try comparing based on numerical designation alone. See if GIVEN is an unadorned number, or 'r' followed by a number. */ if (TOLOWER (*given) == 'r') @@ -1656,7 +1691,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c if (!ISDIGIT (*given)) return FALSE; -@@ -19086,10 +19942,15 @@ mips_matching_cpu_name_p (const char *ca +@@ -19086,10 +19934,15 @@ mips_matching_cpu_name_p (const char *ca hoping to find a number there too. */ if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') canonical += 2; @@ -1675,7 +1710,7 @@ diff -rupN ./bu.orig/gas/config/tc-mips.c ./bu.new/gas/config/tc-mips.c return mips_strict_matching_cpu_name_p (canonical, given); } -@@ -19353,3 +20214,69 @@ tc_mips_regname_to_dw2regnum (char *regn +@@ -19353,3 +20206,69 @@ tc_mips_regname_to_dw2regnum (char *regn return regnum; } @@ -2101,7 +2136,7 @@ diff -rupN ./bu.orig/opcodes/mips16-opc.c ./bu.new/opcodes/mips16-opc.c const int bfd_mips16_num_opcodes = diff -rupN ./bu.orig/opcodes/mips-dis.c ./bu.new/opcodes/mips-dis.c --- a/opcodes/mips-dis.c 2011-08-09 18:20:03.000000000 +0300 -+++ b/opcodes/mips-dis.c 2013-09-26 23:00:05.814735292 +0300 ++++ b/opcodes/mips-dis.c 2013-10-14 20:11:22.849664241 +0300 @@ -169,6 +169,52 @@ static const char * const mips_gpr_names "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" }; @@ -2155,28 +2190,32 @@ diff -rupN ./bu.orig/opcodes/mips-dis.c ./bu.new/opcodes/mips-dis.c static const char * const mips_fpr_names_numeric[32] = { "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", -@@ -503,7 +549,20 @@ const struct mips_arch_choice mips_arch_ +@@ -503,11 +549,24 @@ const struct mips_arch_choice mips_arch_ { { "numeric", 0, 0, 0, 0, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - -+ { "rlx4081", 1, bfd_mach_mips_rlx4081, CPU_RLX4081, ISA_RLX4081, + { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, + mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, + { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, ++ { "rlx4081", 1, bfd_mach_mips_rlx4081, CPU_RLX4081, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -+ { "rlx4180", 1, bfd_mach_mips_rlx4180, CPU_RLX4180, ISA_RLX4180, ++ { "rlx4180", 1, bfd_mach_mips_rlx4180, CPU_RLX4180, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -+ { "rlx4181", 1, bfd_mach_mips_rlx4181, CPU_RLX4181, ISA_RLX4181, ++ { "rlx4181", 1, bfd_mach_mips_rlx4181, CPU_RLX4181, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -+ { "rlx4281", 1, bfd_mach_mips_rlx4281, CPU_RLX4281, ISA_RLX4281, ++ { "rlx4281", 1, bfd_mach_mips_rlx4281, CPU_RLX4281, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -+ { "rlx5181", 1, bfd_mach_mips_rlx5181, CPU_RLX5181, ISA_RLX5181, ++ { "rlx5181", 1, bfd_mach_mips_rlx5181, CPU_RLX5181, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -+ { "rlx5280", 1, bfd_mach_mips_rlx5280, CPU_RLX5280, ISA_RLX5280, ++ { "rlx5280", 1, bfd_mach_mips_rlx5280, CPU_RLX5280, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -+ { "rlx5281", 1, bfd_mach_mips_rlx5281, CPU_RLX5281, ISA_RLX5281, ++ { "rlx5281", 1, bfd_mach_mips_rlx5281, CPU_RLX5281, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, - mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, - { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, + { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, + mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, @@ -920,6 +979,7 @@ print_insn_args (const char *d, const struct mips_opcode *opp) { @@ -2361,7 +2400,7 @@ diff -rupN ./bu.orig/opcodes/mips-dis.c ./bu.new/opcodes/mips-dis.c info->insn_type = dis_branch; diff -rupN ./bu.orig/opcodes/mips-opc.c ./bu.new/opcodes/mips-opc.c --- a/opcodes/mips-opc.c 2011-08-09 18:20:03.000000000 +0300 -+++ b/opcodes/mips-opc.c 2013-09-26 23:06:37.104756976 +0300 ++++ b/opcodes/mips-opc.c 2013-10-11 16:50:51.176218785 +0300 @@ -41,15 +41,15 @@ #define TRAP INSN_NO_DELAY_SLOT #define SM INSN_STORE_MEMORY @@ -2383,3 +2422,2840 @@ diff -rupN ./bu.orig/opcodes/mips-opc.c ./bu.new/opcodes/mips-opc.c #define RD_S INSN_READ_FPR_S #define RD_T INSN_READ_FPR_T #define RD_R INSN_READ_FPR_R +@@ -166,6 +166,34 @@ + /* MIPS MT ASE support. */ + #define MT32 INSN_MT + ++/* pinfo2 */ ++#define TWORD_LOAD INSN2_TWORD_LOAD ++#define TWORD_USE INSN2_TWORD_USE ++ ++/* RLX pinfo */ ++#define RD_LXC0 INSN_COP ++#define WR_LXC0 INSN_COP ++ ++#define WRAD_d INSN_WRITE_RAD_D ++#define WRAD_t INSN_WRITE_RAD_T ++#define RRAD_d INSN_READ_RAD_D ++#define RRAD_t INSN_READ_RAD_T ++#define RRAD_s INSN_READ_RAD_S ++ ++/* simplify opcode listing */ ++#define RALL INSN_RLX_ALL ++#define RUDI INSN_RLX_UDI ++#define RT INSN_RLX_TAROKO ++#define RAD1 INSN_RLX_RAD1 ++#define RAD2 INSN_RLX_RAD2 ++#define I2_R INSN_ISA2_RLX ++#define I32_R INSN_ISA32_RALL ++ ++/* for ltw */ ++#define R4181 INSN_RLX4181 ++#define R4281 INSN_RLX4281 ++ ++ + /* Loongson support. */ + #define WR_z INSN2_WRITE_GPR_Z + #define WR_Z INSN2_WRITE_FPR_Z +@@ -195,1891 +223,962 @@ const struct mips_opcode mips_builtin_op + them first. The assemblers uses a hash table based on the + instruction name anyhow. */ + /* name, args, match, mask, pinfo, pinfo2, membership */ +-{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 }, +-{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 }, +-{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 }, +-{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +-{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +-{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +-{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ +-{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ +-{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, +-{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, +-{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ +-{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ +-{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ +-{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ +-{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ +-{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ +- +-/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 +- instructions. Put them here so that disassembler will find them first. +- The assemblers uses a hash table based on the instruction name anyhow. */ +-{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, +-{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, +-{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_s|RD_t, RD_d, IL3A }, +-{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, +-{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_s|RD_t, 0, IL3A }, +-{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_s|RD_t, 0, IL3A }, +-{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +-{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +-{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +-{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +-{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +-{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +-{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +-{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +-{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +-{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +-{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +-{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +-{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +-{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +-{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +-{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +-{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +-{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +-{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A }, +-{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A }, +-{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A }, +-{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A }, +-{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_t|RD_b|LDD, WR_z, IL3A }, +-{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_t|RD_b|SM, RD_z, IL3A }, +-{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_T|RD_b|LDD, WR_Z, IL3A }, +-{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_T|RD_b|SM, RD_Z, IL3A }, +- +-{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, +-{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +-{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +-{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, +-{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, +-{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, MC }, +-{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC }, +-{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC }, +-{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, +-{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +-{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +-{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +-{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, +-{"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, +-{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +-{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, +-{"addu", "D,S,T", 0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +-{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, I5_33 }, +-{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, +-{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, +-{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, +-{"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, MC }, +-{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC }, +-{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC }, +-{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, ++{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32 }, ++{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4_33 }, ++{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ ++{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32 }, /* sll */ ++{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, RT }, /* sll */ ++ ++{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ ++{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ ++{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ ++{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, ++{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, ++{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ ++{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ ++{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ ++{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ ++{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ ++{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ ++ ++{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, ++{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, ++{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, ++{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 }, ++{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, ++{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, ++{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, ++{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, ++{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, ++{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, ++{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, ++{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, + /* b is at the top of the table. */ + /* bal is at the top of the table. */ +-{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +-{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit032 */ +-{"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +-{"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +-{"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit132 */ +-{"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, + /* bc0[tf]l? are at the bottom of the table. */ +-{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +-{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +-{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +-{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +-{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, +-{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, +-{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, +-{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, +-{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, +-{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, +-{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, +-{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, ++{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1}, ++{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, ++{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2 }, ++{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, ++{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1}, ++{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, ++{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2 }, ++{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, ++{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, ++{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2 }, ++{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, ++{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2 }, ++{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, ++{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2 }, ++{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, ++{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2 }, + /* bc2* are at the bottom of the table. */ + /* bc3* are at the bottom of the table. */ +-{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +-{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +-{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, +-{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, +-{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, +-{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, +-{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, +-{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, +-{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, +-{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, +-{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, +-{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, +-{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, +-{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, +-{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +-{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +-{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, +-{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, +-{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, +-{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, +-{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, +-{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, +-{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, +-{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, +-{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, +-{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, +-{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +-{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +-{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, +-{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, +-{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, +-{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, +-{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, +-{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, +-{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, +-{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, +-{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +-{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +-{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, +-{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, +-{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, +-{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, +-{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, +-{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, +-{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, +-{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, +-{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +-{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +-{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, +-{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, +-{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +-{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +-{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, +-{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, +-{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, +-{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, +-{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, +-{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, +-{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, +-{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, ++{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2 }, ++{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, ++{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, ++{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2 }, ++{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2 }, ++{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, ++{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, ++{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2 }, ++{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2 }, ++{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, ++{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, ++{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2 }, ++{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2 }, ++{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, ++{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2 }, ++{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, ++{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2 }, ++{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, ++{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, ++{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2 }, ++{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2 }, ++{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, ++{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, ++{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2 }, ++{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2 }, ++{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, ++{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2 }, ++{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, ++{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, ++{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2 }, ++{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2 }, ++{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, ++{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, ++{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2 }, ++{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2 }, ++{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, ++{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2 }, ++{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, ++{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, ++{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2 }, ++{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2 }, ++{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, ++{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, ++{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2 }, ++{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2 }, ++{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, ++{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2 }, ++{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, ++{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2 }, ++{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, ++{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2 }, ++{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, ++{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, ++{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2 }, ++{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2 }, ++{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, ++{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, ++{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, ++{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, + {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, + {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, + {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +-{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, + {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ueq.ps","S,T", 0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, ++{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, + {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.olt.ps","S,T", 0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, + {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ult.ps","S,T", 0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ole.ps","S,T", 0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ule.ps","S,T", 0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ngle.ps","S,T", 0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.seq.ps","S,T", 0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ngl.ps","S,T", 0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +-{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.nge.ps","S,T", 0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +-{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +-{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +-{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +-{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +-{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +-{"c.ngt.ps","S,T", 0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +-{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +-{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +-/* CW4010 instructions which are aliases for the cache instruction. */ +-{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, +-{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, +-{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, +-{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, +-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3}, +-{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3}, +-{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +-{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +-{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +-{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +-{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, +-{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, +-{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, +-/* cfc2 is at the bottom of the table. */ +-/* cfc3 is at the bottom of the table. */ +-{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, +-{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, +-{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +-{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +-{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */ +-{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +-{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +-{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +-{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +-{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +-{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +-/* ctc2 is at the bottom of the table. */ +-/* ctc3 is at the bottom of the table. */ +-{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, +-{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, +-{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, +-{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +-{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +-{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +-{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +-{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +-{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +-{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +-{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +-{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33 }, +-{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33 }, +-{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +-{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +-{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, +-{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 }, +-{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, +-{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, +-{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +-{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, +-{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, +-{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, +-{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +-{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, +-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR }, +-{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, +-{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, +-{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, ++{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, ++{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, ++{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, ++{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, ++{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, ++{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32}, ++{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, RUDI }, ++{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32 }, ++{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, ++{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, ++{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, ++{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, ++{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, ++{"cfc0", "t,G,#H", 0x40400000, 0xffe007c0, LCD|WR_t|RD_C0, 0, RT }, ++{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, ++{"cfc1", "t,G,#H", 0x44400000, 0xffe007c0, LCD|WR_t|RD_C1|FP_S, 0, RT }, ++{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, ++{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, ++{"cfc2", "t,G,#H", 0x48400000, 0xffe007c0, LCD|WR_t|RD_C2, 0, RT }, ++{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, ++{"cfc3", "t,G,#H", 0x4c400000, 0xffe007c0, LCD|WR_t|RD_C3, 0, RT }, ++{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32 }, ++{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32 }, ++{"ctc0", "t,G,#H", 0x40c00000, 0xffe007c0, COD|RD_t|WR_CC, 0, RT }, ++{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, ++{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, ++{"ctc1", "t,G,#H", 0x44c00000, 0xffe007c0, COD|RD_t|WR_CC|FP_S, 0, RT }, ++{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, ++{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, ++{"ctc2", "t,G,#H", 0x48c00000, 0xffe007c0, COD|RD_t|WR_CC, 0, RT }, ++{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, ++{"ctc3", "t,G,#H", 0x4cc00000, 0xffe007c0, COD|RD_t|WR_CC, 0, RT }, ++{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, ++{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, ++{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, ++{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, ++{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3_33 }, ++{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3_33 }, ++{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, ++{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, ++{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 }, ++{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 }, ++{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, ++{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, ++{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5 }, ++{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, ++{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, ++{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, ++{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, ++{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, ++{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, ++{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, ++{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64 }, ++{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64 }, + /* dctr and dctw are used on the r5000. */ +-{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, +-{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, +-{"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2 }, +-{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, +-{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, +-{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, +-{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, ++{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, ++{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, ++{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32_R}, ++{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, ++{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, ++{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, ++{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, + /* For ddiv, see the comments about div. */ + {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +-{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, +-{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, ++{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, ++{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, + /* For ddivu, see the comments about div. */ + {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +-{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, +-{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, +-{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT}, +-{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT}, +-{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, +-{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, +-{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, +-{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, ++{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, ++{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, ++{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, ++{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, ++{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, ++{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, ++{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, ++{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, + /* The MIPS assembler treats the div opcode with two operands as + though the first operand appeared twice (the first operand is both + a source and a destination). To get the div machine instruction, + you must use an explicit destination of $0. */ + {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, + {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +-{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, +-{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, +-{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +-{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +-{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, ++{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, ++{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, ++{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, ++{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, + /* For divu, see the comments about div. */ + {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, + {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +-{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, +-{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, +-{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, +-{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, +-{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ +-{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ +-{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, +-{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +-{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, +-{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT }, +-{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT}, +-{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT}, +-{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, +-{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +-{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT }, +-{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT}, +-{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT}, +-{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, +-{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, +-{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, +-{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, +-/* dmfc2 is at the bottom of the table. */ +-/* dmtc2 is at the bottom of the table. */ +-/* dmfc3 is at the bottom of the table. */ +-/* dmtc3 is at the bottom of the table. */ +-{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT }, +-{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, +-{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, +-{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, +-{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, +-{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, +-{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, +-{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +-{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +-{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ +-{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ +-{"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_d|RD_s, 0, IOCT }, ++{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, ++{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, ++{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, ++{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, ++{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ ++{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ ++{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, ++{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, ++{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, ++{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, ++{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, ++{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, ++{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, ++{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, ++{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, ++{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, ++{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, ++{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, ++{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, ++{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, ++{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, ++{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, ++{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I64 }, ++{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, ++{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I64 }, ++{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, ++{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, ++{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, ++{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, ++{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, ++{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, ++{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, ++{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, ++{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ ++{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ + {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +-{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 }, +-{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, ++{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, ++{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, + {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +-{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, +-{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, +-{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, +-{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, +-{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, +-{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, +-{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, +-{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, +-{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, +-{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, +-{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, +-{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, +-{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, +-{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, +-{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, +-{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, +-{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, +-{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, +-{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +-{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, +-{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ +-{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ +-{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, +-{"dsll", "D,S,T", 0x45a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +-{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, +-{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ +-{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ +-{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, +-{"dsra", "D,S,T", 0x45e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +-{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, +-{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ +-{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ +-{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, +-{"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +-{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, +-{"dsub", "D,S,T", 0x45e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +-{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, +-{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, +-{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +-{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT}, +-{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT}, +-{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, +-{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +-{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 }, +-{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, +-{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +-{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, +-{"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +-{"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */ +-{"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +-{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +-{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +-{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +-{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +-{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, +-{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, +-{"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC }, +-{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, +-/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with +- the same hazard barrier effect. */ +-{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, +-{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ ++{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, ++{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, ++{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, ++{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, ++{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, ++{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, ++{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, I65 }, ++{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, ++{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, ++{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, ++{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, ++{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, ++{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, ++{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, ++{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, ++{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, ++{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, ++{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, ++{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, ++{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ ++{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ ++{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, ++{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, ++{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, ++{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ ++{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ ++{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, ++{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, ++{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, ++{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ ++{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ ++{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, ++{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, ++{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, ++{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, ++{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, ++{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, ++{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, ++{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 }, ++{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, ++{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, ++{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3_33 }, ++{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, ++{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, ++{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, ++{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, ++{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I33 }, ++{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ + /* SVR4 PIC code requires special handling for j, so it must be a + macro. */ +-{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, ++{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, + /* This form of j is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +-{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, +-{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, +-{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, +-/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr +- with the same hazard barrier effect. */ +-{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, +-{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, ++{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, ++{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, ++{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, ++{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I33 }, ++{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I33 }, + /* SVR4 PIC code requires special handling for jal, so it must be a + macro. */ +-{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, +-{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, +-{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, ++{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, ++{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, ++{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, + /* This form of jal is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +-{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, +-{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 }, +-{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, +-{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, +-{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, +-{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, +-/* The macro has to be first to handle o32 correctly. */ +-{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, +-{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, +-{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, +-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, +-{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, +-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +-{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ +-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, +-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, +-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, +-{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, +-{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, +-{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, +-{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, +-{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, +-{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4_33 }, +-{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, +-{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, ++{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, ++{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 }, ++{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, ++{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, ++{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, ++{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, ++{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, ++{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, ++{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, ++{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, ++{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, ++{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, ++{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, ++{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ ++{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, ++{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, ++{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, ++{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, ++{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, ++{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, ++{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, ++{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, ++{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, ++{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, ++{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4_33 }, ++{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, ++{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, + /* li is at the start of the table. */ +-{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, +-{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, +-{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, +-{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, +-{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, +-{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55}, +-{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, +-{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +-{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, +-{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, +-{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, +-{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ +-{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, +-{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +-{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, +-{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, +-{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ +-{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ +-{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +-{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, +-{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ +-{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ +-{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, +-{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, +-{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, +-{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0, I4_33 }, +-{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, +-{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +-{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, +-{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, +-{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +-{"madd.d", "D,S,T", 0x46200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"madd.d", "D,S,T", 0x72200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +-{"madd.s", "D,S,T", 0x46000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"madd.s", "D,S,T", 0x72000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +-{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +-{"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +-{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +-{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +-{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +-{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +-{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +-{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +-{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +-{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +-{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, +-{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, +-{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, +-{"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +-{"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +-{"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +-{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +-{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +-{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, +-{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, +-{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +-{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, +-{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, +-{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, +-{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, +-{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +-{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +-{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +-{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +-{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +-{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, +-{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT }, +-{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT}, +-{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT}, +-{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, +-{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, +-{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, +-{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, +-/* mfc2 is at the bottom of the table. */ +-/* mfhc2 is at the bottom of the table. */ +-/* mfc3 is at the bottom of the table. */ +-{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, +-{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, +-{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, +-{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, +-{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, +-{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, +-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR }, +-{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +-{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +-{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, +-{"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, +-{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, +-{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, +-{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +-{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +-{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, +-{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, +-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F }, +-{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A }, +-{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, +-{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, +-{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +-{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +-{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, +-{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33 }, +-{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, +-{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, +-{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +-{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +-{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, +-{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, +-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F }, +-{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, +-{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, +-{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +-{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +-{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, +-{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33 }, +-{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, ++{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, ++{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, ++{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, ++{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, ++{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2_R }, ++{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2_R }, ++{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, ++{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, ++{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, ++{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I5 }, ++{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, ++{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, ++{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, ++{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, ++{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, ++{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, ++{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, ++{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ ++{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, ++{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, ++{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, ++{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, ++{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, ++{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, ++{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ ++{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ ++{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, ++{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, ++{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ ++{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ ++{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, ++{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, ++{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4_33 }, ++{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, RALL }, ++{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, RALL }, ++{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, ++{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, ++{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, ++{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32}, ++{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32}, ++{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, ++{"mfc0", "t,G,#H", 0x40000000, 0xffe007c0, LCD|WR_t|RD_C0, 0, RT }, ++{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, ++{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, ++{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, ++{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, ++{"mfc1", "t,G,#H", 0x44000000, 0xffe007c0, LCD|WR_t|RD_S|FP_S, 0, RT }, ++{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, ++{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, ++{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, ++{"mfc2", "t,G,#H", 0x48000000, 0xffe007c0, LCD|WR_t|RD_C2, 0, RT }, ++{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, ++{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, ++{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, ++{"mfc3", "t,G,#H", 0x4c000000, 0xffe007c0, LCD|WR_t|RD_C3, 0, RT }, ++{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, ++{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, ++{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, ++{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, ++{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, ++{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 }, ++{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, ++{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, ++{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, ++{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, ++{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32 }, ++{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, ++{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, ++{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5 }, ++{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, ++{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, ++{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, ++{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, ++ ++{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32 }, ++{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, ++{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, ++{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5 }, + /* move is at the top of the table. */ +-{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR }, +-{"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR }, +-{"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR }, +-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR }, +-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR }, +-{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +-{"msub.d", "D,S,T", 0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"msub.d", "D,S,T", 0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +-{"msub.s", "D,S,T", 0x46000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"msub.s", "D,S,T", 0x72000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +-{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +-{"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +-{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +-{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +-{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +-{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, +-{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, +-{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT }, +-{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT}, +-{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT}, +-{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, +-{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, +-{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, +-{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, +-/* mtc2 is at the bottom of the table. */ +-/* mthc2 is at the bottom of the table. */ +-/* mtc3 is at the bottom of the table. */ +-{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, +-{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, +-{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, +-{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, +-{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, +-{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, +-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR }, +-{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT }, +-{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT }, +-{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT }, +-{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s, 0, IOCT }, +-{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s, 0, IOCT }, +-{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s, 0, IOCT }, +-{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +-{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +-{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +-{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, +-{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, +-{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, +-{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +-{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +-{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, +-{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, +-{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, +-{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, +-{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, +-{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +-{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +-{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +-{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +-{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, +-{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +-{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +-{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, +-{"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, +-{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, +-{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, +-{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, +-{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, +-{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, +-{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, +-{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, +-{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, +-{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +-{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +-{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +-{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D32 }, +-{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +-{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +-{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +-{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D32 }, +-{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +-{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +-{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ +-{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ +-{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +-{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +-{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, +-{"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, +-{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +-{"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +-{"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +-{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +-{"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"nmadd.ps", "D,S,T", 0x7160001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +-{"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +-{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +-{"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +-{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +-{"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"nmsub.ps", "D,S,T", 0x7160001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, ++{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, ++{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, ++{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, ++{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32_R }, ++{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32_R }, ++{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, ++{"mtc0", "t,G,#H", 0x40800000, 0xffe007c0, COD|RD_t|WR_C0|WR_CC, 0, RT }, ++{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, ++{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, ++{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, ++{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, ++{"mtc1", "t,G,#H", 0x44800000, 0xffe007c0, COD|RD_t|WR_S|FP_S, 0, RT }, ++{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, ++{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, ++{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, ++{"mtc2", "t,G,#H", 0x48800000, 0xffe007c0, COD|RD_t|WR_C2|WR_CC, 0, RT }, ++{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, ++{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, ++{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, ++{"mtc3", "t,G,#H", 0x4c800000, 0xffe007c0, COD|RD_t|WR_C3|WR_CC, 0, RT }, ++{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, ++{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, ++{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, ++{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, ++{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, ++{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32 }, ++{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, ++{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, ++{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, ++{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, ++{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, ++{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, ++{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, ++{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, ++{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ ++{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ ++{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, ++{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, ++{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 }, ++{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, ++{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, ++{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, ++{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, ++{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, ++{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, + /* nop is at the start of the table. */ +-{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, +-{"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ +-{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, +-{"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +-{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, +-{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +-{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +-{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +-{"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_d|RD_s, 0, IOCT }, ++{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, ++{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ ++{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, ++{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, ++{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, + /* pref and prefx are at the start of the table. */ +-{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +-{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +-{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, +-{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +-{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, +-{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +-{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +-{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, +-{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +-{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +-{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, +-{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +-{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, +-{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +-{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, +-{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, +-{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +-{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +-{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +-{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +-{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +-{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +-{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, +-{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, +-{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +-{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, +-{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, +-{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, +-{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, +-{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, +-{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +-{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +-{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +-{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +-{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +-{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +-{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, +-{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, +-{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, +-{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, +-{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, +-{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, +-{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, +-{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, +-{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, +-{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, +-{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, +-{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +-{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +-{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +-{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +-{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, +-{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +-{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, +-{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, +-{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +-{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +-{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +-{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +-{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +-{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +-{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +-{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, +-{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +-{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +-{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, +-{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, +-{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, +-{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, +-{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, +-/* The macro has to be first to handle o32 correctly. */ +-{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, +-{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +-{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, +-{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, +-{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, +-{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, +-{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, +-{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, +-{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +-{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +-{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +-{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +-{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, +-{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, +-{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, +-{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, +-{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, +-{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +-{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, +-{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +-{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, +-{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 }, +-{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, +-{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, +-{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, +-{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, +-{"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +-{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, +-{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, +-{"seq", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +-{"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +-{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, +-{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, +-{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, +-{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, +-{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, +-{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, +-{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, +-{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, +-{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +-{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, +-{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, +-{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, +-{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +-{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, +-{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, +-{"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +-{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +-{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ +-{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, +-{"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, +-{"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +-{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, +-{"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +-{"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +-{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, +-{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, +-{"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +-{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, +-{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +-{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +-{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +-{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ +-{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, +-{"sra", "D,S,T", 0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +-{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ +-{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, +-{"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, ++{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, ++{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, ++{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, ++{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, ++{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, ++{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, ++{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, ++{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, ++{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, ++{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, ++{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1 }, ++{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, ++{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, ++{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, ++{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, ++{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, I33 }, ++{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 }, ++{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33 }, ++{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33 }, ++{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33 }, ++{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33 }, ++{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 }, ++{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, ++{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3 }, ++{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, ++{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, ++{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, ++{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, ++{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, ++{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, ++{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2_R }, ++{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2_R }, ++{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, ++{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, ++{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, ++{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, ++{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, ++{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32_R }, ++{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32_R }, ++{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, ++{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, ++{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, ++{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, ++{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, ++{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, ++{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, ++{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, ++{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, ++{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, ++{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, ++{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, ++{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, ++{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, ++{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, ++{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 }, ++{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, ++{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, ++{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, ++{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, ++{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, ++{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, ++{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, ++{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, ++{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, ++{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, ++{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, ++{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, ++{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, ++{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, ++{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, ++{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, ++{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, ++{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, ++{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, ++{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ ++{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, ++{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, ++{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, ++{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, ++{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, ++{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, ++{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, ++{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, ++{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, ++{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, ++{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ ++{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, ++{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, ++{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ ++{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, + /* ssnop is at the start of the table. */ +-{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, +-{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, +-{"sub", "D,S,T", 0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +-{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +-{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +-{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, +-{"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, +-{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, +-{"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +-{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +-{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, +-{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55}, +-{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +-{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, +-{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, +-{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, +-{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, +-{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, +-{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ +-{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, +-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, +-{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, +-{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, +-{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +-{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, +-{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ +-{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ +-{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +-{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, +-{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ +-{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ +-{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 }, +-{"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT }, +-{"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT }, +-{"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT }, +-{"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT }, +-{"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33 }, +-{"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33 }, +-{"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33 }, +-{"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33 }, +-{"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33 }, +-{"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1 }, +-{"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32 }, +-{"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2 }, +-{"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2 }, +-{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, +-{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, +-{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, +-{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +-{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +-{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +-{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ +-{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, +-{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +-{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +-{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +-{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ +-{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, +-{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +-{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +-{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +-{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ +-{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, +-{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, +-{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, +-{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, +-{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, +-{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +-{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +-{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +-{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ +-{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, +-{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +-{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +-{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +-{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ +-{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, +-{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +-{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +-{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +-{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ +-{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, +-{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +-{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +-{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +-{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +-{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1 }, +-{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +-{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +-{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, +-{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, +-{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, +-{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, +-{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, +-{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, +-{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, +-{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, +-{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, +-{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, +-{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, +-{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, +-{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, +-{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, +-{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +-{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +-{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +-{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, +-{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, +-{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, +-{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +-{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, +-{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +-{"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32 }, +-{"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 }, +-{"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 }, +-{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, +-{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, +-{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +-{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, +-{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +-{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +-{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +-{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +-{"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, MT32 }, +-{"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, MT32 }, +- +-/* User Defined Instruction. */ +-{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +-{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +- +-/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format +- instructions so they are here for the latters to take precedence. */ +-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +-{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, +-{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +-{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, +-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +-{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, +-{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +-{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, +-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, +-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +-{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, +-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, +-{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, +-{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, +-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, +-{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, +-{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, +-{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, +-{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, +-{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, +-{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, +-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, +-{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, +-{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +-{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +-{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +- +-/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X +- instructions, so they are here for the latters to take precedence. */ +-{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +-{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +-{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +-{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +-{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +-{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +-{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, +-{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, +-{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +-{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, +-{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, +-{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, +- +- /* Conflicts with the 4650's "mul" instruction. Nobody's using the +- 4010 any more, so move this insn out of the way. If the object +- format gave us more info, we could do this right. */ +-{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, +-/* MIPS DSP ASE */ +-{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, +-{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, +-{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +-{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +-{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +-{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +-{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +-{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +-{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +-{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, +-{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, +-{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +-{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +-{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, +-{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, +-{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, +-{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, +-{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, +-{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, +-{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +-{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +-{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +-{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +-{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +-{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +-{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +-{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +-{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +-{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +-{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +-{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +-{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, +-{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +-{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +-{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, +-{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +-{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +-{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +-{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +-{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +-{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +-{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +-{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +-{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +-{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +-{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +-{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +-{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, +-{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, +-{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, +-{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, +-{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, +-{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, +-{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, +-{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, +-{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, +-{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +-{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +-{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, +-{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, +-{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, +-{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +-{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +-{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, +-{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +-{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +-{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +-{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +-{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +-{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +-{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +-{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +-{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +-{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +-{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +-{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +-{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, +-{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, +-{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +-{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +-{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, +-{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, +-/* MIPS DSP ASE Rev2 */ +-{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, +-{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +-{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, +-{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, +-{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +-{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +-{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +-{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +-{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +-{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +-{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +-{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +-{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, +-{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, +-{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, +-{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +-{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +-/* Move bc0* after mftr and mttr to avoid opcode collision. */ +-{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +-{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +-{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +-{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +-/* ST Microelectronics Loongson-2E and -2F. */ +-{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +-{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +-{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +-{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"packushb", "D,S,T", 0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddb", "D,S,T", 0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddh", "D,S,T", 0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddw", "D,S,T", 0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddd", "D,S,T", 0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddsb", "D,S,T", 0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddsh", "D,S,T", 0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"paddush", "D,S,T", 0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pandn", "D,S,T", 0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pavgb", "D,S,T", 0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pavgh", "D,S,T", 0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pminub", "D,S,T", 0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmovmskb", "D,S", 0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E }, +-{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmullh", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"biadd", "D,S", 0x46800005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E }, +-{"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A }, +-{"pshufh", "D,S,T", 0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psllh", "D,S,T", 0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psllw", "D,S,T", 0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psrah", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psraw", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psrlh", "D,S,T", 0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psrlw", "D,S,T", 0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubb", "D,S,T", 0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubh", "D,S,T", 0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubw", "D,S,T", 0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubd", "D,S,T", 0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubsb", "D,S,T", 0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubsh", "D,S,T", 0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"psubush", "D,S,T", 0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +-{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +-{"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +-{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, ++{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, ++{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, ++{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, ++{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, ++{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, ++{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5 }, ++{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, ++{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, ++{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, ++{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, ++{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, ++{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, ++{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, ++{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, ++{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ ++{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, ++{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, ++{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, ++{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, ++{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, ++{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, ++{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, ++{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ ++{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ ++{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, ++{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, ++{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ ++{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ ++{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 }, ++{"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2_R }, ++{"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I2_R }, ++{"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2 }, ++{"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2 }, ++{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, ++{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, ++{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, ++{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, ++{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, ++{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, ++{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ ++{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, ++{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, ++{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, ++{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, ++{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ ++{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, ++{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, ++{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, ++{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, ++{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ ++{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, ++{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, ++{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, ++{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, ++{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, ++{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, ++{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, ++{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, ++{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ ++{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, ++{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, ++{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, ++{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, ++{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ ++{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, ++{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, ++{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, ++{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, ++{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ ++{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, ++{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, ++{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, ++{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, ++{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, ++{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, ++{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, ++{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, ++{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, ++{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, ++{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, ++{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, ++{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, ++{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, ++{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, ++{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, ++{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, ++{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, ++{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, ++{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, ++{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, ++{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, ++{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, ++{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3_32 }, ++{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32 }, ++{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, ++{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, ++{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, ++{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, ++{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, ++ ++/* dbb: modified for supporting radiax instructions */ ++/* d1: m0(3), m1(7), m2(11), m3(15) */ ++/* d2: m0l, m0h, m0 ~ m3l, m3h, m3 */ ++/* d3: m0l, m0h, ~ m3l, m3h */ ++/* d4: LXC0 */ ++{"mta2", "s,#d2", 0x7C00005D, 0xFC1F07ff, RD_s|WRAD_d, 0, RAD1 }, ++{"mta2.g", "s,#d2", 0x7C00015D, 0xFC1F07ff, RD_s|WRAD_d, 0, RAD1 }, ++{"mfa", "d,#t3", 0x7C00001C, 0xFFE007FF, WR_d|RRAD_t, 0, RAD1 }, ++{"mfa", "d,#t3,##", 0x7C00001C, 0xFFE0007F, WR_d|RRAD_t, 0, RAD1 }, ++{"mfa2", "d,#t1", 0x7C00005C, 0xFFE007FF, WR_d|RRAD_t, 0, RAD1 }, ++{"mfa2", "d,#t1,##", 0x7C00005C, 0xFFE0007F, WR_d|RRAD_t, 0, RAD1 }, ++{"diva", "#d1,s,t", 0x7C00001A, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"divau", "#d1,s,t", 0x7C00021A, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"multa", "#d1,s,t", 0x7C000112, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"multau", "#d1,s,t", 0x7C000312, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imulta", "#d1,s,t", 0x7C000102, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"imultau", "#d1,s,t", 0x7C000302, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmulta", "#d1,s,t", 0x7C000502, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"multa2", "#d2,s,t", 0x7C000152, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imulta2", "#d2,s,t", 0x7C000142, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmulta2", "#d2,s,t", 0x7C000542, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"mulna2", "#d2,s,t", 0x7C000153, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imulna2", "#d2,s,t", 0x7C000143, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmulna2", "#d2,s,t", 0x7C000543, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"cmulta", "#d1,s,t", 0x7C00001B, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"icmulta", "#d1,s,t", 0x7C00011B, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qcmulta", "#d1,s,t", 0x7C00051B, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"madda", "#d1,s,t", 0x7C000012, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"maddau", "#d1,s,t", 0x7C000212, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imadda", "#d1,s,t", 0x7C000002, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"imaddau", "#d1,s,t", 0x7C000202, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmadda", "#d1,s,t", 0x7C000402, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"madda2", "#d2,s,t", 0x7C000052, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imadda2", "#d2,s,t", 0x7C000042, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmadda2", "#d2,s,t", 0x7C000442, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"madda2.s", "#d2,s,t", 0x7C0000D2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imadda2.s32", "#d2,s,t", 0x7C0000C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmadda2.s32", "#d2,s,t", 0x7C0004C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"imadda2.s40", "#d2,s,t", 0x7C0001C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmadda2.s40", "#d2,s,t", 0x7C0005C2, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"msuba", "#d1,s,t", 0x7C000013, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"msubau", "#d1,s,t", 0x7C000213, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imsuba", "#d1,s,t", 0x7C000003, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"imsubau", "#d1,s,t", 0x7C000203, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmsuba", "#d1,s,t", 0x7C000403, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"msuba2", "#d2,s,t", 0x7C000053, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imsuba2", "#d2,s,t", 0x7C000043, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmsuba2", "#d2,s,t", 0x7C000443, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"msuba2.s", "#d2,s,t", 0x7C0000D3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD1 }, ++{"imsuba2.s32", "#d2,s,t", 0x7C0000C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmsuba2.s32", "#d2,s,t", 0x7C0004C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"imsuba2.s40", "#d2,s,t", 0x7C0001C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"qmsuba2.s40", "#d2,s,t", 0x7C0005C3, 0xFC0007FF, RD_t|RD_s|WRAD_d, 0, RAD2 }, ++{"addma", "#d3,#s3,#t3", 0x7C00001E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 }, ++{"addma.s", "#d3,#s3,#t3", 0x7C00009E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 }, ++{"addma.s32", "#d3,#s3,#t3", 0x7C00041E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 }, ++{"addma.s40", "#d3,#s3,#t3", 0x7C00049E, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 }, ++{"subma", "#d3,#s3,#t3", 0x7C00001F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 }, ++{"subma.s", "#d3,#s3,#t3", 0x7C00009F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD1 }, ++{"subma.s32", "#d3,#s3,#t3", 0x7C00041F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 }, ++{"subma.s40", "#d3,#s3,#t3", 0x7C00049F, 0xFC0007FF, RRAD_t|RRAD_s|WRAD_d, 0, RAD2 }, ++{"rnda2", "#t2", 0x7C000056, 0xFFE0FFFF, WRAD_t, 0, RAD1 }, ++{"rnda2", "#t2,##", 0x7C000056, 0xFFE0F87F, WRAD_t, 0, RAD1 }, ++{"lt", "#`,#@(b)", 0x7C000036, 0xFC00003F, LDD|RD_b|WR_t, 0, RAD1 }, ++{"st", "#`,#@(b)", 0x7C00003E, 0xFC00003F, SM|RD_t|RD_b, 0, RAD1 }, ++{"ltp", "#`,(b)#~", 0x7C0000f2, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"ltp.c0", "#`,(b)#~", 0x7C000032, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"ltp.c1", "#`,(b)#~", 0x7C000072, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"ltp.c2", "#`,(b)#~", 0x7C0000b2, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lwp", "t,(b)#~", 0x7C0000f3, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lwp.c0", "t,(b)#~", 0x7C000033, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lwp.c1", "t,(b)#~", 0x7C000073, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lwp.c2", "t,(b)#~", 0x7C0000b3, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhp", "t,(b)#~", 0x7C0000f1, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhp.c0", "t,(b)#~", 0x7C000031, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhp.c1", "t,(b)#~", 0x7C000071, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhp.c2", "t,(b)#~", 0x7C0000b1, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhpu", "t,(b)#~", 0x7C0000f5, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhpu.c0", "t,(b)#~", 0x7C000035, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhpu.c1", "t,(b)#~", 0x7C000075, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lhpu.c2", "t,(b)#~", 0x7C0000b5, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbp", "t,(b)#~", 0x7C0000f0, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbp.c0", "t,(b)#~", 0x7C000030, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbp.c1", "t,(b)#~", 0x7C000070, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbp.c2", "t,(b)#~", 0x7C0000b0, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbpu", "t,(b)#~", 0x7C0000f4, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbpu.c0", "t,(b)#~", 0x7C000034, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbpu.c1", "t,(b)#~", 0x7C000074, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"lbpu.c2", "t,(b)#~", 0x7C0000b4, 0xFC0000FF, LDD|WR_t|RD_b, 0, RAD1 }, ++{"stp", "#`,(b)#~", 0x7C0000fa, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"stp.c0", "#`,(b)#~", 0x7C00003a, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"stp.c1", "#`,(b)#~", 0x7C00007a, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"stp.c2", "#`,(b)#~", 0x7C0000ba, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"swp", "t,(b)#~", 0x7C0000fb, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"swp.c0", "t,(b)#~", 0x7C00003b, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"swp.c1", "t,(b)#~", 0x7C00007b, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"swp.c2", "t,(b)#~", 0x7C0000bb, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"shp", "t,(b)#~", 0x7C0000f9, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"shp.c0", "t,(b)#~", 0x7C000039, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"shp.c1", "t,(b)#~", 0x7C000079, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"shp.c2", "t,(b)#~", 0x7C0000b9, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"sbp", "t,(b)#~", 0x7C0000f8, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"sbp.c0", "t,(b)#~", 0x7C000038, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"sbp.c1", "t,(b)#~", 0x7C000078, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"sbp.c2", "t,(b)#~", 0x7C0000b8, 0xFC0000FF, WR_t|RD_b, 0, RAD1 }, ++{"mtru", "t,#u", 0x7C000025, 0xFFE007FF, RD_t|WRAD_d, 0, RAD1 }, ++{"mfru", "t,#u", 0x7C000024, 0xFFE007FF, RD_t|WRAD_d, 0, RAD1 }, ++{"mtrk", "t,#k", 0x7C0000A5, 0xFFE007FF, RD_t|WRAD_d, 0, RAD1 }, ++{"mfrk", "t,#k", 0x7C0000A4, 0xFFE007FF, RD_t|WRAD_d, 0, RAD1 }, ++{"sllv2", "d,t,s", 0x7C000044, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"srlv2", "d,t,s", 0x7C000046, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"srav2", "d,t,s", 0x7C000047, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"addr", "d,s,t", 0x7C000021, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"addr.s", "d,s,t", 0x7C0000A1, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"addr2", "d,s,t", 0x7C000061, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"addr2.s", "d,s,t", 0x7C0000E1, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"subr", "d,s,t", 0x7C000023, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"subr.s", "d,s,t", 0x7C0000A3, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"subr2", "d,s,t", 0x7C000063, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"subr2.s", "d,s,t", 0x7C0000E3, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"sltr2", "d,s,t", 0x7C00006A, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"min", "d,s,t", 0x7C000028, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"min2", "d,s,t", 0x7C000068, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"max", "d,s,t", 0x7C000029, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"max2", "d,s,t", 0x7C000069, 0xFC0007FF, RD_t|RD_s|WR_d, 0, RAD1 }, ++{"absr", "d,t", 0x7C00000F, 0xFFE007FF, RD_t|WR_d, 0, RAD1 }, ++{"absr.s", "d,t", 0x7C00008F, 0xFFE007FF, RD_t|WR_d, 0, RAD1 }, ++{"absr2", "d,t", 0x7C00004F, 0xFFE007FF, RD_t|WR_d, 0, RAD1 }, ++{"absr2.s", "d,t", 0x7C0000CF, 0xFFE007FF, RD_t|WR_d, 0, RAD1 }, ++{"mux2.hh", "d,s,t", 0x7C00064D, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"mux2.hl", "d,s,t", 0x7C00044D, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"mux2.lh", "d,s,t", 0x7C00024D, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"mux2.ll", "d,s,t", 0x7C00004D, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cls", "d,t", 0x7C00000E, 0xFFE007FF, RD_t|WR_d, 0, RAD1 }, ++{"bitrev", "d,t,s", 0x7c00000c, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cmveqz", "d,s,t", 0x7C000001, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cmveqz.h", "d,s,t", 0x7C000081, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cmveqz.l", "d,s,t", 0x7C000101, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cmvnez", "d,s,t", 0x7C000041, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cmvnez.h", "d,s,t", 0x7C0000c1, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++{"cmvnez.l", "d,s,t", 0x7C000141, 0xFC0007FF, RD_s|RD_t|WR_d, 0, RAD1 }, ++/* modified for supporting radiax instructions */ ++ ++{"mflxc0", "t,#d4", 0x40600000, 0xFFE007FF, LCD|WR_t|RD_LXC0, 0, RUDI }, ++{"mflxc0", "t,#d4,#H", 0x40600000, 0xFFE007C0, LCD|WR_t|RD_LXC0, 0, RT }, ++{"mtlxc0", "t,#d4", 0x40E00000, 0xFFE007FF, COD|RD_t|WR_LXC0|WR_CC, 0, RUDI }, ++{"mtlxc0", "t,#d4,#H", 0x40E00000, 0xFFE007C0, COD|RD_t|WR_LXC0|WR_CC, 0, RT }, ++ ++/* MAC-DIV instructions */ ++{"sleep", "", 0x42000038, 0xffffffff, 0, 0, RALL }, ++{"sleep", "1", 0x42000038, 0xfffff83f, 0, 0, RT }, ++{"madh", "s,t", 0xF0000000, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"madl", "s,t", 0xF0000002, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"mazh", "s,t", 0xF0000004, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"mazl", "s,t", 0xF0000006, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"msbh", "s,t", 0xF0000010, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"msbl", "s,t", 0xF0000012, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"mszh", "s,t", 0xF0000014, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"mszl", "s,t", 0xF0000016, 0xFC00FFFF, RD_s|RD_t, 0, RALL }, ++{"ltw", "#`,#-(b)", 0x7800003C, 0xFC00003F, LDD|RD_b|WR_t, 0, INSN_RLX4181 | INSN_RLX4281 }, ++ ++/* dbb: modified for supporting 4181 instructions */ + /* No hazard protection on coprocessor instructions--they shouldn't + change the state of the processor and if they do it's up to the + user to put in nops as necessary. These are at the end so that the + disassembler recognizes more specific versions first. */ +-{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 }, +-{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 }, +-{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 }, +-{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 }, +-{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, +-{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 }, +-{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, +-{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 } ++{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, ++{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, ++{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, ++{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, ++{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, ++{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, ++{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, ++{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, ++/* Lexra opcode extensions. Register mode */ ++{"udi0", "d,v,t", 0x00000038,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"udi1", "d,v,t", 0x0000003a,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"udi2", "d,v,t", 0x0000003b,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"udi3", "d,v,t", 0x0000003c,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"udi4", "d,v,t", 0x0000003e,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++{"udi5", "d,v,t", 0x0000003f,0xfc0007ff, WR_d|RD_s|RD_t, 0, RUDI }, ++ ++/* Lexra opcode extensions. Immediate mode */ ++{"udi0i", "t,r,j", 0x60000000, 0xfc000000, WR_t | RD_s, 0, RUDI }, ++{"udi1i", "t,r,j", 0x64000000, 0xfc000000, WR_t | RD_s, 0, RUDI }, ++{"udi2i", "t,r,j", 0x68000000, 0xfc000000, WR_t | RD_s, 0, RUDI }, ++{"udi3i", "t,r,j", 0x6c000000, 0xfc000000, WR_t | RD_s, 0, RUDI }, + }; + + #define MIPS_NUM_OPCODES \ diff --git a/toolchain/gcc/patches/4.8-linaro/999_realtek.patch b/toolchain/gcc/patches/4.8-linaro/999_realtek.patch index e0f5bc237..c5a0998a7 100644 --- a/toolchain/gcc/patches/4.8-linaro/999_realtek.patch +++ b/toolchain/gcc/patches/4.8-linaro/999_realtek.patch @@ -1,11 +1,105 @@ +diff -rupN ./gcc.orig/gcc/common.opt ./gcc.new/gcc/common.opt +--- a/gcc/common.opt 2013-04-08 22:06:00.000000000 +0300 ++++ b/gcc/common.opt 2013-10-10 21:03:45.092852675 +0300 +@@ -699,6 +699,15 @@ Wvector-operation-performance + Common Var(warn_vector_operation_performance) Warning + Warn when a vector operation is compiled outside the SIMD + ++Wpossible-load-use ++Common RejectNegative Var(warn_possible_load_use) Warning ++Warn when possible load-use in branch delay slot ++ ++Wmissing-delay-slot ++Common RejectNegative Var(warn_missing_delay_slot) Warning ++Warn when missing delay ++ ++ + Xassembler + Driver Separate + +@@ -2259,6 +2268,65 @@ fvisibility= + Common Joined RejectNegative Enum(symbol_visibility) Var(default_visibility) Init(VISIBILITY_DEFAULT) + -fvisibility=[default|internal|hidden|protected] Set the default symbol visibility + ++fdafile-relative ++Common ++Put gcda file in relative instead of absolute path ++ ++finhibit-lt ++Common ++Do not output lt in function epilogue. Obsolete now ++ ++finhibit-ltw ++Common ++Do not output ltw in function epilogue. Obsolete now ++ ++finhibit-st ++Common ++Do not output st in function prologue. Obsolete now ++ ++flt ++Common ++Obsolete. Just for back compatibility ++ ++fltw ++Common ++Obsolete. Just for back compatibility ++ ++frlxcov ++Common ++Put the code coverage initialization symbols in section .rlxcov instead of .ctors ++ ++fst ++Common ++Obsolete. Just for back compatibility ++ ++ftword ++Common Report Var(flag_tword) ++Emit twin-word load/store instructions in programs except function prologue/epilogue ++ ++ftword-stack ++Common Report Var(flag_tword_stack) ++Follow MIPS convention: stack 8-byte aligned ++ ++fsuppress-outer-loop-unroll ++Common Report Var(flag_suppress_outer_loop_unroll) Optimization ++Suppress unrolling outer loops even that -O3+ is specified ++ ++ ++fuse-uls ++Common Report Var(flag_use_uls) Init(1) ++Allow compiler to emit unaligned load/store instructions ++ ++fuse-tls ++Common Report Var(flag_use_tls) ++Allow compiler to emit TLS related codes. ++ ++ ++ffix-bdsl ++Common Report Var(flag_fix_bdsl) Init(1) Optimization ++Forbid the use of load instructions in the branch delay slots for all cases ++ ++ + Enum + Name(symbol_visibility) Type(enum symbol_visibility) UnknownError(unrecognized visibility value %qs) + diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c --- a/gcc/config/mips/mips.c 2013-02-19 02:04:49.000000000 +0200 -+++ b/gcc/config/mips/mips.c 2013-09-17 15:56:40.036229582 +0300 -@@ -1121,6 +1121,27 @@ static const struct mips_rtx_cost_data - COSTS_N_INSNS (68), /* int_div_di */ ++++ b/gcc/config/mips/mips.c 2013-10-14 20:23:06.143036336 +0300 +@@ -56,6 +56,9 @@ along with GCC; see the file COPYING3. + #include "target-globals.h" + #include "opts.h" + ++extern bool default_target_can_inline_p (tree, tree); ++extern bool default_target_option_can_inline_p (tree, tree); ++ + /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ + #define UNSPEC_ADDRESS_P(X) \ + (GET_CODE (X) == UNSPEC \ +@@ -925,6 +928,27 @@ static const struct mips_rtx_cost_data 1, /* branch_cost */ 4 /* memory_latency */ -+ }, + }, + { /* RLX */ + DEFAULT_COSTS + }, @@ -26,26 +120,392 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.c ./gcc.new/gcc/config/mips/mips.c + }, + { /* RLX */ + DEFAULT_COSTS - } - }; ++ }, + { /* R6000 */ + COSTS_N_INSNS (3), /* fp_add */ + COSTS_N_INSNS (5), /* fp_mult_sf */ +@@ -1212,13 +1236,62 @@ mips_far_type_p (const_tree type) + static bool + mips_mips16_decl_p (const_tree decl) + { +- return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL; ++ tree l; ++ bool b = FALSE; ++ ++ for (l = DECL_ATTRIBUTES (decl); l; l = TREE_CHAIN (l)) ++ { ++ gcc_assert (TREE_CODE (TREE_PURPOSE (l)) == IDENTIFIER_NODE); ++ if (!strcmp ("mips16", IDENTIFIER_POINTER (TREE_PURPOSE (l)))) ++ b = TRUE; ++ else if (!strcmp ("nomips16", IDENTIFIER_POINTER (TREE_PURPOSE (l)))) ++ b = FALSE; ++ } ++ return b; + } + + static bool + mips_nomips16_decl_p (const_tree decl) + { +- return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL; ++ tree l; ++ bool b = FALSE; ++ ++ for (l = DECL_ATTRIBUTES (decl); l; l = TREE_CHAIN (l)) ++ { ++ gcc_assert (TREE_CODE (TREE_PURPOSE (l)) == IDENTIFIER_NODE); ++ if (!strcmp ("mips16", IDENTIFIER_POINTER (TREE_PURPOSE (l)))) ++ b = FALSE; ++ else if (!strcmp ("nomips16", IDENTIFIER_POINTER (TREE_PURPOSE (l)))) ++ b = TRUE; ++ } ++ return b; ++} ++ ++static bool ++mips_use_mips16_mode_p (tree decl) ++{ ++ if (decl) ++ { ++ /* Nested functions must use the same frame pointer as their ++ parent and must therefore use the same ISA mode. */ ++ tree parent = decl_function_context (decl); ++ if (parent) ++ decl = parent; ++ if (mips_mips16_decl_p (decl)) ++ return true; ++ if (mips_nomips16_decl_p (decl)) ++ return false; ++ } ++ return mips_base_mips16; ++} ++ ++static bool ++mips_can_inline_p (tree caller, tree callee) ++{ ++ if (mips_use_mips16_mode_p (caller) != mips_use_mips16_mode_p (callee)) ++ return false; ++ else ++ return default_target_option_can_inline_p (caller, callee); + } + + /* Check if the interrupt attribute is set for a function. */ +@@ -1260,24 +1333,6 @@ mips_use_debug_exception_return_p (tree + /* Return true if function DECL is a MIPS16 function. Return the ambient + setting if DECL is null. */ + +-static bool +-mips_use_mips16_mode_p (tree decl) +-{ +- if (decl) +- { +- /* Nested functions must use the same frame pointer as their +- parent and must therefore use the same ISA mode. */ +- tree parent = decl_function_context (decl); +- if (parent) +- decl = parent; +- if (mips_mips16_decl_p (decl)) +- return true; +- if (mips_nomips16_decl_p (decl)) +- return false; +- } +- return mips_base_mips16; +-} +- + /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ + + static int +@@ -2897,7 +2952,9 @@ mips_expand_thread_pointer (rtx tp) + emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn))); + } + else +- emit_insn (PMODE_INSN (gen_tls_get_tp, (tp))); ++ { ++ //emit_insn (PMODE_INSN (gen_tls_get_tp, (tp))); ++ } + return tp; + } + +@@ -2956,6 +3013,7 @@ mips_legitimize_tls_address (rtx loc) + break; + + case TLS_MODEL_INITIAL_EXEC: ++ break; + tp = mips_get_tp (); + tmp1 = gen_reg_rtx (Pmode); + tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); +@@ -2968,6 +3026,7 @@ mips_legitimize_tls_address (rtx loc) + break; + + case TLS_MODEL_LOCAL_EXEC: ++ break; + tmp1 = mips_get_tp (); + offset = mips_unspec_address (loc, SYMBOL_TPREL); + if (mips_split_p[SYMBOL_TPREL]) +@@ -7090,6 +7149,13 @@ mips_block_move_straight (rtx dest, rtx + regs[i] = gen_reg_rtx (mode); + if (MEM_ALIGN (src) >= bits) + mips_emit_move (regs[i], adjust_address (src, mode, offset)); ++ /*else if (TARGET_RLX && !TARGET_MIPS16 && !flag_use_uls) ++ { ++ rtx result_part = extract_bit_field (src, bits, ++ offset * BITS_PER_UNIT, 1, regs[i], mode, ++ mode); ++ emit_move_insn (regs[i], result_part); ++ }*/ + else + { + rtx part = adjust_address (src, BLKmode, offset); +@@ -7103,6 +7169,9 @@ mips_block_move_straight (rtx dest, rtx + for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) + if (MEM_ALIGN (dest) >= bits) + mips_emit_move (adjust_address (dest, mode, offset), regs[i]); ++ /*else if (TARGET_RLX && !TARGET_MIPS16 && !flag_use_uls) { ++ store_bit_field (dest, bits, offset * BITS_PER_UNIT, mode, regs[i]); ++ }*/ + else + { + rtx part = adjust_address (dest, BLKmode, offset); +@@ -7727,9 +7796,11 @@ static void + mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context, + const char **relocs) + { ++ /* + enum mips_symbol_type symbol_type; + const char *p; + ++ + symbol_type = mips_classify_symbolic_expression (op, context); + gcc_assert (relocs[symbol_type]); + +@@ -7738,6 +7809,7 @@ mips_print_operand_reloc (FILE *file, rt + for (p = relocs[symbol_type]; *p != 0; p++) + if (*p == '(') + fputc (')', file); ++ */ + } + + /* Start a new block with the given asm switch enabled. If we need +@@ -8165,6 +8237,7 @@ mips_print_operand_address (FILE *file, + return; + } + gcc_unreachable (); ++ + } -@@ -12794,6 +12815,9 @@ mips_issue_rate (void) + /* Implement TARGET_ENCODE_SECTION_INFO. */ +@@ -12665,9 +12738,9 @@ mips_output_division (const char *divisi + } + else + { +- output_asm_insn ("%(bne\t%2,%.,1f", operands); + output_asm_insn (s, operands); +- s = "break\t7%)\n1:"; ++ output_asm_insn ("%(bne\t%2,%.,1f", operands); ++ s = "nop\n\tbreak\t7%)\n1:"; + } + } + return s; +@@ -12794,6 +12867,9 @@ mips_issue_rate (void) case PROCESSOR_R9000: case PROCESSOR_OCTEON: case PROCESSOR_OCTEON2: -+ case PROCESSOR_RLX5280: -+ case PROCESSOR_RLX5281: -+ case PROCESSOR_RLX4281: ++ //case PROCESSOR_RLX5280: ++ //case PROCESSOR_RLX5281: ++ //case PROCESSOR_RLX4281: return 2; case PROCESSOR_SB1: +@@ -14303,11 +14379,13 @@ mips16_emit_constants_1 (enum machine_mo + if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode)) + { + rtx size = GEN_INT (GET_MODE_SIZE (mode)); +- return emit_insn_after (gen_consttable_int (value, size), insn); ++ //hck ++ return emit_insn_after (insn, insn); + } + + if (SCALAR_FLOAT_MODE_P (mode)) +- return emit_insn_after (gen_consttable_float (value), insn); ++ //hck ++ return emit_insn_after (insn, insn); + + if (VECTOR_MODE_P (mode)) + { +@@ -16218,11 +16296,13 @@ static int was_mips16_p = -1; + /* Set up the target-dependent global state so that it matches the + current function's ISA mode. */ + ++ + static void +-mips_set_mips16_mode (int mips16_p) ++mips_set_mips16_mode(int mips16_p) + { + if (mips16_p == was_mips16_p) + return; ++ return; + + /* Restore base settings of various flags. */ + target_flags = mips_base_target_flags; +@@ -16323,6 +16403,10 @@ mips_set_mips16_mode (int mips16_p) + was_mips16_p = mips16_p; + } + ++/* Remember the last target of mips_set_current_function. */ ++static GTY(()) tree mips_previous_fndecl; ++ ++ + /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current + function should use the MIPS16 ISA and switch modes accordingly. */ + +@@ -16958,6 +17042,141 @@ mips_order_regs_for_local_alloc (void) + } + } + ++const char* ++rlx_asm_app_on() ++{ ++ /* shunyen ++ Use app_on to store function status for ISA-mode switching asm ++ 1: not in mips16 function ++ 2: in mips16 leaf function ++ 3: in mips16 non-leaf function ++ */ ++ /* ++ app_on = (!(cfun && cfun->decl && mips_use_mips16_mode_p(cfun->decl))) ? ++ 1 : (current_function_is_leaf) ? 2 : 3; ++ ++ if (app_on == 1) ++ return " #APP\n"; ++ ++ if (flag_pic) ++ if (flag_fix_bdsl) ++ return " #APP PIC BDSL\n" ++ " .align 2\n" ++ " .set push\n" ++ " .set noat\n" ++ " .set noreorder\n" ++ " move $1,$3\n" ++ " addiu $3,$pc,8\n" ++ " jr $3\n" ++ " nop\n" ++ " .set pop\n" ++ " .set nomips16\n" ++ " .align 2\n" ++ "9:\n" ++ " .set push\n" ++ " .set noat\n" ++ " move $3,$1\n" ++ " .set pop\n"; ++ else ++ return " #APP PIC\n" ++ " .align 2\n" ++ " .set push\n" ++ " .set noat\n" ++ " .set noreorder\n" ++ " move $1,$3\n" ++ " addiu $3,$pc,8\n" ++ " jr $3\n" ++ " move $3,$1\n" ++ " .set pop\n" ++ " .set nomips16\n" ++ " .align 2\n" ++ "9:\n"; ++ ++ if (app_on == 2) ++ return " #APP leaf\n" ++ " addiu $sp,-4\n" ++ " sw $31,0($sp)\n" ++ " jalx 9f\n" ++ " nop\n" ++ " .set nomips16\n" ++ " .align 2\n" ++ "9:\n"; ++ ++ return " #APP\n" ++ " jalx 9f\n" ++ " nop\n" ++ " .set nomips16\n" ++ " .align 2\n" ++ "9:\n"; ++ */ ++} ++ ++const char* ++rlx_asm_app_off() ++{ ++ //if (app_on == 1) ++ return " #NO_APP\n"; ++ ++/* ++ if (flag_pic) ++ return " .set push\n" ++ " .set noat\n" ++ " .set noreorder\n" ++ " move $1,$31\n" ++ " bgezal $0,.+8\n" ++ " addiu $31,9\n" ++ " jr $31\n" ++ " move $31,$1\n" ++ " .set pop\n" ++ " .set mips16\n" ++ " .align 2\n" ++ "9:\n" ++ " #NO_APP PIC\n"; ++ ++ if (app_on == 2) ++ if (flag_fix_bdsl) ++ return " .set push\n" ++ " .set noreorder\n" ++ " .set noat\n" ++ " jalx 9f\n" ++ " move $1,$3\n" ++ " .set pop\n" ++ " .set mips16\n" ++ " .set mips16\n" ++ " .align 2\n" ++ "9:\n" ++ " .set push\n" ++ " .set noat\n" ++ " lw $3,0($sp)\n" ++ " move $31,$3\n" ++ " move $3,$1\n" ++ " .set pop\n" ++ " addiu $sp,4\n" ++ " #NO_APP leaf BDSL\n"; ++ else ++ return " .set push\n" ++ " .set noreorder\n" ++ " jalx 9f\n" ++ " lw $31,0($sp)\n" ++ " .set pop\n" ++ " .set mips16\n" ++ " .align 2\n" ++ "9:\n" ++ " addiu $sp,4\n" ++ " #NO_APP leaf\n"; ++ ++ return " .set push\n" ++ " .set noreorder\n" ++ " jalx 9f\n" ++ " nop\n" ++ " .set pop\n" ++ " .set mips16\n" ++ " .align 2\n" ++ "9:\n" ++ " #NO_APP\n"; ++ */ ++} ++ + /* Implement EH_USES. */ + + bool diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mips-cpus.def --- a/gcc/config/mips/mips-cpus.def 2013-01-10 22:38:27.000000000 +0200 -+++ b/gcc/config/mips/mips-cpus.def 2013-09-17 17:10:08.249807200 +0300 -@@ -52,6 +52,14 @@ MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, - MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0) ++++ b/gcc/config/mips/mips-cpus.def 2013-10-14 19:45:36.929578308 +0300 +@@ -53,6 +53,14 @@ MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0 MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0) MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0) + +MIPS_CPU ("rlx4081", PROCESSOR_RLX4081, 1, 0) +MIPS_CPU ("rlx4180", PROCESSOR_RLX4180, 1, 0) +MIPS_CPU ("rlx4181", PROCESSOR_RLX4181, 1, 0) @@ -54,13 +514,13 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips-cpus.def ./gcc.new/gcc/config/mips/mi +MIPS_CPU ("rlx5280", PROCESSOR_RLX5280, 1, 0) +MIPS_CPU ("rlx5281", PROCESSOR_RLX5281, 1, 0) + - /* MIPS II processors. */ MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0) + diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h --- a/gcc/config/mips/mips.h 2013-01-10 22:38:27.000000000 +0200 -+++ b/gcc/config/mips/mips.h 2013-09-17 16:38:07.036367401 +0300 -@@ -222,6 +222,32 @@ struct mips_cpu_info { ++++ b/gcc/config/mips/mips.h 2013-10-14 19:57:12.512949903 +0300 +@@ -222,6 +222,33 @@ struct mips_cpu_info { #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) #define TARGET_XLP (mips_arch == PROCESSOR_XLP) @@ -72,6 +532,7 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h +#define TARGET_RLX5280 (mips_arch == PROCESSOR_RLX5280) +#define TARGET_RLX5281 (mips_arch == PROCESSOR_RLX5281) + ++ +/* All RLX processor */ +#define TARGET_RLX (TARGET_RLX4081 || TARGET_RLX4180 \ + || TARGET_RLX4181 || TARGET_RLX4281 || TARGET_RLX5181 \ @@ -93,32 +554,126 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h /* Scheduling target defines. */ #define TUNE_20KC (mips_tune == PROCESSOR_20KC) #define TUNE_24K (mips_tune == PROCESSOR_24KC \ -@@ -695,7 +721,7 @@ struct mips_cpu_info { +@@ -250,6 +277,16 @@ struct mips_cpu_info { + #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ + || mips_tune == PROCESSOR_SB1A) + ++ ++#define TUNE_RLX4081 (mips_tune == PROCESSOR_RLX4081) ++#define TUNE_RLX4180 (mips_tune == PROCESSOR_RLX4180) ++#define TUNE_RLX4181 (mips_tune == PROCESSOR_RLX4181) ++#define TUNE_RLX4281 (mips_tune == PROCESSOR_RLX4281) ++#define TUNE_RLX5181 (mips_tune == PROCESSOR_RLX5181) ++#define TUNE_RLX5280 (mips_tune == PROCESSOR_RLX5280) ++#define TUNE_RLX5281 (mips_tune == PROCESSOR_RLX5281) ++ ++ + /* Whether vector modes and intrinsics for ST Microelectronics + Loongson-2E/2F processors should be enabled. In o32 pairs of + floating-point registers provide 64-bit values. */ +@@ -548,6 +585,43 @@ struct mips_cpu_info { + \ + if (TARGET_CACHE_BUILTIN) \ + builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ ++ if (TARGET_RLX) \ ++ { \ ++ /* RLX built-in definition */ \ ++ /* 2009-10-13 tonywu: add __RSDK__ DEFINE */ \ ++ builtin_define ("_RSDK_"); \ ++ builtin_define ("_RSDK_v15_"); \ ++ builtin_define ("__RSDK__"); \ ++ builtin_define ("__RSDK__v15__"); \ ++ \ ++ if (TARGET_RLX4180) \ ++ builtin_define ("__m4180"); \ ++ else if (TARGET_RLX4081) \ ++ builtin_define ("__m4081"); \ ++ else if (TARGET_RLX4181) \ ++ builtin_define ("__m4181"); \ ++ else if (TARGET_RLX4281) \ ++ builtin_define ("__m4281"); \ ++ else if (TARGET_RLX5181) \ ++ builtin_define ("__m5181"); \ ++ else if (TARGET_RLX5280) \ ++ builtin_define ("__m5280"); \ ++ else if (TARGET_RLX5281) \ ++ builtin_define ("__m5281"); \ ++ /* 2006-05-09 tonywu: add LX/RLX PREPROCESSOR DEFINE */ \ ++ if (TARGET_RLX_INTERLOCK) \ ++ builtin_define ("__rlx_gprlock"); \ ++ else if (TARGET_RLX_NO_INTERLOCK) \ ++ builtin_define ("__rlx_no_gprlock"); \ ++ if (flag_fix_bdsl) \ ++ builtin_define ("__FIX_BDSL__"); \ ++ if (flag_use_uls) \ ++ builtin_define ("__USE_ULS__"); \ ++ if (flag_use_tls) \ ++ builtin_define ("__USE_TLS__"); \ ++ if (TARGET_RLX1) \ ++ builtin_define ("_RLX_ISA1"); \ ++ } \ + } \ + while (0) + +@@ -695,7 +769,7 @@ struct mips_cpu_info { #define MIPS_ISA_LEVEL_SPEC \ "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ - %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ -+ %{march=mips1|march=r2000|march=r3000|march=r3900|march=rlx4081|march=rlx4180|march=rlx4181|march=rlx5181|march=rlx5280|march=rlx5281:-mips1} \ ++ %{march=mips1|march=r2000|march=r3000|march=r3900|march=rlx4081|march=rlx4180|march=rlx4181|march=rlx4281|march=rlx5181|march=rlx5280|march=rlx5281:-mips1} \ %{march=mips2|march=r6000:-mips2} \ %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ -@@ -838,7 +864,14 @@ struct mips_cpu_info { +@@ -762,6 +836,9 @@ struct mips_cpu_info { + {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ + {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ + {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ ++ {"fix_bdsl","%{!mfix-bdsl:-m%{VALUE}}"}, \ ++ {"possible_load_use","%{!mpossilbe-load-use:-m%{VALUE}}"}, \ ++ {"missing_delay_sloat","%{!missing-delay-slot:-m%{VALUE}}"}, \ + {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } + + /* A spec that infers the -mdsp setting from an -march argument. */ +@@ -819,12 +896,12 @@ struct mips_cpu_info { + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ +- && !TARGET_MIPS16) ++ && !TARGET_MIPS16 && !TARGET_RLX) + + /* ISA has a three-operand multiplication instruction. */ + #define ISA_HAS_DMUL3 (TARGET_64BIT \ + && TARGET_OCTEON \ +- && !TARGET_MIPS16) ++ && !TARGET_MIPS16 && !TARGET_RLX) + + /* ISA has the floating-point conditional move instructions introduced + in mips4. */ +@@ -838,7 +915,13 @@ struct mips_cpu_info { /* ISA has the integer conditional move instructions introduced in mips4 and ST Loongson 2E/2F. */ -#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) +#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ + || TARGET_LOONGSON_2EF \ -+ || ((TARGET_RLX5280 \ -+ || TARGET_RLX5181 \ -+ || TARGET_RLX5281 \ -+ || TARGET_RLX4181 \ -+ || TARGET_RLX4281) \ -+ && !TARGET_MIPS16)) ++ || TARGET_RLX5280 \ ++ || TARGET_RLX5181 \ ++ || TARGET_RLX5281 \ ++ || TARGET_RLX4181 \ ++ || TARGET_RLX4281) /* ISA has LDC1 and SDC1. */ #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) -@@ -1012,7 +1045,8 @@ struct mips_cpu_info { +@@ -903,7 +986,7 @@ struct mips_cpu_info { + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) \ +- && !TARGET_MIPS16) ++ && !TARGET_MIPS16 && !TARGET_RLX) + + /* ISA has three operand multiply instructions that put + the high part in an accumulator: mulhi or mulhiu. */ +@@ -1012,7 +1095,8 @@ struct mips_cpu_info { and "addiu $4,$4,1". */ #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ && !TARGET_MIPS3900 \ @@ -128,7 +683,7 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h /* Likewise mtc1 and mfc1. */ #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \ -@@ -1039,7 +1073,8 @@ struct mips_cpu_info { +@@ -1039,7 +1123,8 @@ struct mips_cpu_info { || ISA_MIPS64 \ || ISA_MIPS64R2 \ || TARGET_MIPS5500 \ @@ -138,7 +693,7 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h /* ISA includes synci, jr.hb and jalr.hb. */ #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \ -@@ -1047,7 +1082,8 @@ struct mips_cpu_info { +@@ -1047,7 +1132,8 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA includes sync. */ @@ -148,7 +703,7 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ -@@ -1056,7 +1092,7 @@ struct mips_cpu_info { +@@ -1056,7 +1142,7 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ @@ -157,13 +712,31 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.h ./gcc.new/gcc/config/mips/mips.h #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ +@@ -1165,7 +1251,16 @@ struct mips_cpu_info { + #undef CC1_SPEC + #define CC1_SPEC "\ + %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ +-%(subtarget_cc1_spec)" ++%(subtarget_cc1_spec) \ ++%{rlx4180:-march=rlx4180} \ ++%{rlx4081:-march=rlx4081} \ ++%{rlx4181:-march=rlx4181} \ ++%{rlx4281:-march=rlx4281} \ ++%{rlx5181:-march=rlx5181} \ ++%{rlx5280:-march=rlx5280} \ ++%{rlx5281:-march=rlx5281} \ ++" ++ + + /* Preprocessor specs. */ + diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md --- a/gcc/config/mips/mips.md 2013-01-24 19:46:41.000000000 +0200 -+++ b/gcc/config/mips/mips.md 2013-09-17 12:41:06.048912668 +0300 -@@ -64,6 +64,13 @@ - sr71000 - xlr - xlp ++++ b/gcc/config/mips/mips.md 2013-10-14 19:46:13.179580218 +0300 +@@ -59,6 +59,13 @@ + r8000 + r9000 + r10000 + rlx4081 + rlx4180 + rlx4181 @@ -171,9 +744,225 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips.md ./gcc.new/gcc/config/mips/mips.md + rlx5181 + rlx5280 + rlx5281 - ]) + sb1 + sb1a + sr71000 +@@ -679,11 +686,17 @@ + + ;; Can the instruction be put into a delay slot? + (define_attr "can_delay" "no,yes" +- (if_then_else (and (eq_attr "type" "!branch,call,jump") +- (and (eq_attr "hazard" "none") +- (eq_attr "single_insn" "yes"))) +- (const_string "yes") +- (const_string "no"))) ++ (if_then_else (and (ior (eq (symbol_ref "TARGET_MIPS16") (const_int 0)) ++ (eq (symbol_ref "flag_fix_bdsl") (const_int 0))) ++ (and (eq_attr "type" "!branch,call,jump") ++ (and (and (eq_attr "hazard" "none") ++ (ior (eq (symbol_ref "flag_fix_bdsl") (const_int 0)) ++ (not (and (eq_attr "type" "load") ++ (ne (symbol_ref "TARGET_RLX_INTERLOCK") (const_int 0)))))) ++ (eq_attr "single_insn" "yes")))) ++ (const_string "yes") ++ (const_string "no"))) ++ + + ;; Attribute defining whether or not we can use the branch-likely + ;; instructions. +@@ -1449,10 +1462,7 @@ + { + rtx lo; + +- if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A) +- emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1], +- operands[2])); +- else if (ISA_HAS_<D>MUL3) ++ if (ISA_HAS_<D>MUL3) + emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2])); + else if (TARGET_MIPS16) + { +@@ -1468,19 +1478,7 @@ + DONE; + }) + +-(define_insn "mul<mode>3_mul3_loongson" +- [(set (match_operand:GPR 0 "register_operand" "=d") +- (mult:GPR (match_operand:GPR 1 "register_operand" "d") +- (match_operand:GPR 2 "register_operand" "d")))] +- "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A" +-{ +- if (TARGET_LOONGSON_2EF) +- return "<d>multu.g\t%0,%1,%2"; +- else +- return "gs<d>multu\t%0,%1,%2"; +-} +- [(set_attr "type" "imul3nc") +- (set_attr "mode" "<MODE>")]) ++ + + (define_insn "mul<mode>3_mul3" + [(set (match_operand:GPR 0 "register_operand" "=d,l") +@@ -2156,7 +2154,7 @@ + (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) + (any_extend:TI (match_operand:DI 2 "register_operand"))) + (const_int 64))))] +- "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" ++ "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120) && !TARGET_RLX" + { + if (TARGET_MIPS16) + emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], +@@ -2177,6 +2175,7 @@ + (clobber (match_scratch:DI 3 "=l"))] + "TARGET_64BIT + && !TARGET_MIPS16 ++ && !TARGET_RLX + && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" + { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } + "&& reload_completed && !TARGET_FIX_R4000" +@@ -3781,6 +3780,9 @@ + (match_operand 3 "const_int_operand")))] + "!TARGET_MIPS16" + { ++ if (TARGET_RLX && !flag_use_uls) { ++ FAIL; ++ } + if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], + INTVAL (operands[2]), + INTVAL (operands[3]), +@@ -3818,6 +3820,9 @@ + (match_operand 3 "const_int_operand")))] + "!TARGET_MIPS16" + { ++ if (TARGET_RLX && !flag_use_uls) { ++ FAIL; ++ } + if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], + INTVAL (operands[2]), + INTVAL (operands[3]), +@@ -3869,6 +3874,9 @@ + (match_operand:GPR 3 "reg_or_0_operand"))] + "!TARGET_MIPS16" + { ++ if (TARGET_RLX && !flag_use_uls) { ++ FAIL; ++ } + if (mips_expand_ins_as_unaligned_store (operands[0], operands[3], + INTVAL (operands[1]), + INTVAL (operands[2]))) +@@ -6715,6 +6723,10 @@ + (match_operand:GPR 3 "reg_or_0_operand")))] + "ISA_HAS_CONDMOVE" + { ++ if (TARGET_RLX && (GET_MODE_CLASS(GET_MODE(operands[0])) == MODE_FLOAT ++ || GET_MODE_CLASS(GET_MODE(operands[1])) == MODE_FLOAT)) ++ FAIL; ++ + mips_expand_conditional_move (operands); + DONE; + }) +@@ -6731,50 +6743,6 @@ + DONE; + }) + +-;; +-;; .................... +-;; +-;; mips16 inline constant tables +-;; +-;; .................... +-;; +- +-(define_insn "consttable_tls_reloc" +- [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "") +- (match_operand 1 "const_int_operand" "")] +- UNSPEC_CONSTTABLE_INT)] +- "TARGET_MIPS16_PCREL_LOADS" +- { return mips_output_tls_reloc_directive (&operands[0]); } +- [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) +- +-(define_insn "consttable_int" +- [(unspec_volatile [(match_operand 0 "consttable_operand" "") +- (match_operand 1 "const_int_operand" "")] +- UNSPEC_CONSTTABLE_INT)] +- "TARGET_MIPS16" +-{ +- assemble_integer (mips_strip_unspec_address (operands[0]), +- INTVAL (operands[1]), +- BITS_PER_UNIT * INTVAL (operands[1]), 1); +- return ""; +-} +- [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) +- +-(define_insn "consttable_float" +- [(unspec_volatile [(match_operand 0 "consttable_operand" "")] +- UNSPEC_CONSTTABLE_FLOAT)] +- "TARGET_MIPS16" +-{ +- REAL_VALUE_TYPE d; +- +- gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE); +- REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]); +- assemble_real (d, GET_MODE (operands[0]), +- GET_MODE_BITSIZE (GET_MODE (operands[0]))); +- return ""; +-} +- [(set (attr "length") +- (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))]) + + (define_insn "align" + [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)] +@@ -6796,16 +6764,6 @@ + ;; .................... + ;; + +-(define_insn "*mips16e_save_restore" +- [(match_parallel 0 "" +- [(set (match_operand:SI 1 "register_operand") +- (plus:SI (match_dup 1) +- (match_operand:SI 2 "const_int_operand")))])] +- "operands[1] == stack_pointer_rtx +- && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)" +- { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); } +- [(set_attr "type" "arith") +- (set_attr "extended_mips16" "yes")]) + + ;; Thread-Local Storage - (define_c_enum "unspec" [ +@@ -6822,33 +6780,7 @@ + ;; If we leave the use of $3 implicit in the constraints until + ;; reload, we may end up making a $3 return value live across + ;; the instruction, leading to a spill failure when reloading it. +-(define_insn_and_split "tls_get_tp_<mode>" +- [(set (match_operand:P 0 "register_operand" "=d") +- (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) +- (clobber (reg:P TLS_GET_TP_REGNUM))] +- "HAVE_AS_TLS && !TARGET_MIPS16" +- "#" +- "&& reload_completed" +- [(set (reg:P TLS_GET_TP_REGNUM) +- (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) +- (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] +- "" +- [(set_attr "type" "unknown") +- ; Since rdhwr always generates a trap for now, putting it in a delay +- ; slot would make the kernel's emulation of it much slower. +- (set_attr "can_delay" "no") +- (set_attr "mode" "<MODE>") +- (set_attr "length" "8")]) + +-(define_insn "*tls_get_tp_<mode>_split" +- [(set (reg:P TLS_GET_TP_REGNUM) +- (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))] +- "HAVE_AS_TLS && !TARGET_MIPS16" +- ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop" +- [(set_attr "type" "unknown") +- ; See tls_get_tp_<mode> +- (set_attr "can_delay" "no") +- (set_attr "mode" "<MODE>")]) + + ;; In MIPS16 mode, the TLS base pointer is accessed by a + ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not diff -rupN ./gcc.orig/gcc/config/mips/mips-tables.opt ./gcc.new/gcc/config/mips/mips-tables.opt --- a/gcc/config/mips/mips-tables.opt 2013-01-10 22:38:27.000000000 +0200 +++ b/gcc/config/mips/mips-tables.opt 2013-09-17 17:12:22.506481307 +0300 @@ -201,3 +990,59 @@ diff -rupN ./gcc.orig/gcc/config/mips/mips-tables.opt ./gcc.new/gcc/config/mips/ + +EnumValue +Enum(mips_arch_opt_value) String(rlx5281) Value(92) Canonical +diff -rupN ./gcc.orig/gcc/final.c ./gcc.new/gcc/final.c +--- a/gcc/final.c 2013-02-01 18:54:14.000000000 +0200 ++++ b/gcc/final.c 2013-10-14 07:56:06.309676515 +0300 +@@ -179,9 +179,6 @@ CC_STATUS cc_prev_status; + + static int block_depth; + +-/* Nonzero if have enabled APP processing of our assembler output. */ +- +-static int app_on; + + /* If we are outputting an insn sequence, this contains the sequence rtx. + Zero otherwise. */ +@@ -225,6 +222,8 @@ static int align_fuzz (rtx, rtx, int, un + + /* Initialize data in final at the beginning of a compilation. */ + ++static int app_on; ++ + void + init_final (const char *filename ATTRIBUTE_UNUSED) + { +diff -rupN ./gcc.orig/gcc/tree.h ./gcc.new/gcc/tree.h +--- a/gcc/tree.h 2013-04-08 22:06:00.000000000 +0300 ++++ b/gcc/tree.h 2013-10-14 08:06:20.523022902 +0300 +@@ -31,6 +31,11 @@ along with GCC; see the file COPYING3. + #include "alias.h" + #include "flags.h" + ++#ifndef __APP_ON ++#define __APP_ON ++//extern int app_on; ++#endif ++ + /* Codes of tree nodes */ + + #define DEFTREECODE(SYM, STRING, TYPE, NARGS) SYM, +diff -rupN ./gcc.orig/libgcc/libgcc2.c ./gcc.new/libgcc/libgcc2.c +--- a/libgcc/libgcc2.c 2013-02-04 21:06:20.000000000 +0200 ++++ b/libgcc/libgcc2.c 2013-10-14 08:51:59.643080973 +0300 +@@ -212,6 +212,7 @@ __negvDI2 (DWtype a) + } + #endif + ++#undef L_absvsi2 + #ifdef L_absvsi2 + Wtype + __absvSI2 (Wtype a) +@@ -251,6 +252,7 @@ __absvsi2 (SItype a) + #endif /* COMPAT_SIMODE_TRAPPING_ARITHMETIC */ + #endif + ++#undef L_absvdi2 + #ifdef L_absvdi2 + DWtype + __absvDI2 (DWtype a) |