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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-17 16:01:51 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-17 16:01:51 +0000
commit140ea29a53385a99321b1fa68df5ed20e4fd43e5 (patch)
treef56c8444a6c938de216918cd982d73f51ee0e019 /target/linux
parent477b3dc642bb1450fe9207858b06162d72ceb18a (diff)
[adm5120] remove invalid GPIO definitions for the RB153
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9789 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/adm5120/files/arch/mips/adm5120/boards/mikrotik.c23
1 files changed, 5 insertions, 18 deletions
diff --git a/target/linux/adm5120/files/arch/mips/adm5120/boards/mikrotik.c b/target/linux/adm5120/files/arch/mips/adm5120/boards/mikrotik.c
index 744c82f15..8846545e5 100644
--- a/target/linux/adm5120/files/arch/mips/adm5120/boards/mikrotik.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/boards/mikrotik.c
@@ -61,9 +61,6 @@
#define RB150_NAND_WRITE(v) \
writeb((v), (void __iomem *)KSEG1ADDR(RB150_NAND_BASE))
-#define RB153_GPIO_CF_RDY ADM5120_GPIO_P1L1
-#define RB153_GPIO_CF_WT ADM5120_GPIO_P0L0
-
/*--------------------------------------------------------------------------*/
static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
@@ -242,20 +239,6 @@ static void __init rb1xx_flash_setup(void)
adm5120_nand_data.chip.options = NAND_NO_AUTOINCR;
}
-static void __init rb153_cf_setup(void)
-{
- /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */
- adm5120_gpio_csx1_enable();
- /* enable the wait state pin GPIO[0] for external I/O control */
- adm5120_gpio_ew_enable();
-
- gpio_request(RB153_GPIO_CF_RDY, "cf-ready");
- gpio_direction_input(RB153_GPIO_CF_RDY);
- gpio_request(RB153_GPIO_CF_WT, "cf-wait");
- gpio_direction_output(RB153_GPIO_CF_WT, 1);
- gpio_direction_input(RB153_GPIO_CF_WT);
-}
-
static void __init rb1xx_setup(void)
{
/* enable NAND flash interface */
@@ -294,7 +277,11 @@ static void __init rb150_setup(void)
static void __init rb153_setup(void)
{
- rb153_cf_setup();
+ /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */
+ adm5120_gpio_csx1_enable();
+ /* enable the wait state pin GPIO[0] for external I/O control */
+ adm5120_gpio_ew_enable();
+
rb1xx_setup();
}