diff options
| author | Roman Yeryomin <roman@advem.lv> | 2012-09-13 00:40:35 +0300 |
|---|---|---|
| committer | Roman Yeryomin <roman@advem.lv> | 2012-12-03 00:13:21 +0200 |
| commit | 5deb3317cb51ac52de922bb55f8492624018906d (patch) | |
| tree | c2fbe6346699d9bb0f2100490c3029519bb8fde8 /target/linux/realtek/patches-2.6.30/005-tls-support.diff | |
| parent | 0239d37124f9184b478a42de8a7fa1bc85a6a6fe (diff) | |
Add realtek target files
Signed-off-by: Roman Yeryomin <roman@advem.lv>
Diffstat (limited to 'target/linux/realtek/patches-2.6.30/005-tls-support.diff')
| -rw-r--r-- | target/linux/realtek/patches-2.6.30/005-tls-support.diff | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/target/linux/realtek/patches-2.6.30/005-tls-support.diff b/target/linux/realtek/patches-2.6.30/005-tls-support.diff new file mode 100644 index 000000000..2b3ce831d --- /dev/null +++ b/target/linux/realtek/patches-2.6.30/005-tls-support.diff @@ -0,0 +1,78 @@ +Index: linux-2.6.30.9/arch/rlx/kernel/traps.c +=================================================================== +--- linux-2.6.30.9.orig/arch/rlx/kernel/traps.c 2011-12-04 15:31:07.000000000 +0000 ++++ linux-2.6.30.9/arch/rlx/kernel/traps.c 2011-12-04 15:31:39.000000000 +0000 +@@ -451,6 +451,55 @@ + } + #endif + ++ ++/* ++ * Simulate trapping 'rdhwr' instructions to provide user accessible ++ * registers not implemented in hardware. ++ */ ++static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) ++{ ++ struct thread_info *ti = task_thread_info(current); ++ ++ if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { ++ int rd = (opcode & RD) >> 11; ++ int rt = (opcode & RT) >> 16; ++ switch (rd) { ++ case 0: /* CPU number */ ++ regs->regs[rt] = smp_processor_id(); ++ return 0; ++ case 1: /* SYNCI length */ ++ regs->regs[rt] = min(current_cpu_data.dcache.linesz, ++ current_cpu_data.icache.linesz); ++ return 0; ++ case 2: /* Read count register */ ++ regs->regs[rt] = read_c0_count(); ++ return 0; ++ case 3: /* Count register resolution */ ++ switch (current_cpu_data.cputype) { ++#if 0 ++ case CPU_20KC: ++ case CPU_25KF: ++ regs->regs[rt] = 1; ++ break; ++#endif ++ default: ++ regs->regs[rt] = 2; ++ } ++ return 0; ++ case 29: ++ regs->regs[rt] = ti->tp_value; ++ return 0; ++ default: ++ return -1; ++ } ++ } ++ ++ /* Not ours. */ ++ return -1; ++} ++ ++ ++ + #ifndef CONFIG_CPU_HAS_SYNC + static int simulate_sync(struct pt_regs *regs, unsigned int opcode) + { +@@ -567,7 +616,7 @@ + status = simulate_llsc(regs, opcode); + #endif + +-#if 0 ++#if 1 + if (status < 0) + status = simulate_rdhwr(regs, opcode); + #endif +@@ -616,7 +665,7 @@ + status = simulate_llsc(regs, opcode); + #endif + +-#if 0 ++#if 1 + if (status < 0) + status = simulate_rdhwr(regs, opcode); + #endif |