Move to rsdk 3.2.4. Compiles cleanly.

Signed-off-by: Roman Yeryomin <roman@advem.lv>

13 files changed, 1 insertions, 2273 deletions

diff --git a/target/linux/realtek/files/arch/rlx/bsp b/target/linux/realtek/files/arch/rlx/bsp
new file mode 120000
index 000000000..ec617b832
--- /dev/null
+++ b/target/linux/realtek/files/arch/rlx/bsp
@@ -0,0 +1 @@
+bsp_rtl8196c
\ No newline at end of file
diff --git a/target/linux/realtek/files/arch/rlx/bsp/Makefile b/target/linux/realtek/files/arch/rlx/bsp/Makefile
deleted file mode 100644
index 32d2cb07a..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-# Realtek Semiconductor Corp.
-#
-# Tony Wu (tonywu@realtek.com)
-# Oct. 18, 2008
-#
-
-#
-# RTL8196C
-#
-#include $(DIR_LINUX)/.config
-
-core-y   += arch/rlx/bsp/
-cflags-y += -Iinclude/asm-rlx -Iarch/rlx/bsp/
-#load-y   += 0xffffffff80000000
-load-y   += 0x80000000
-
-extra-y  += vmlinux.lds
-
-obj-y := prom.o setup.o irq.o timer.o serial.o
-obj-$(CONFIG_PCI) += pci.o
-
-EXTRA_AFLAGS := $(CFLAGS)
-EXTRA_CFLAGS += -I$(TOPDIR)/drivers/net/rtl819x/AsicDriver
-EXTRA_CFLAGS += -I$(TOPDIR)/drivers/net/rtl819x/common
-ifdef CONFIG_RTL_819X_SWCORE
-EXTRA_CFLAGS += -DCONFIG_RTL_819X_SWCORE
-endif
diff --git a/target/linux/realtek/files/arch/rlx/bsp/bspchip.h b/target/linux/realtek/files/arch/rlx/bsp/bspchip.h
deleted file mode 100644
index 0f65e1945..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/bspchip.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * Copyright 2006, Realtek Semiconductor Corp.
- *
- * rtl8196b/bsp/bspchip.h:
- *   RTL8196B chip-level header file
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Nov. 07, 2006
- */
-
-#ifndef _BSPCHIP_H_
-#define _BSPCHIP_H_
-
-#include <linux/autoconf.h>
-#define RTL8196C 1
-/*
- * Register access macro
- */
-#define REG32(reg)	(*(volatile unsigned int   *)((unsigned int)reg))
-#define REG16(reg)	(*(volatile unsigned short *)((unsigned int)reg))
-#define REG08(reg)	(*(volatile unsigned char  *)((unsigned int)reg))
-#define REG8(reg)   (*(volatile unsigned char  *)((unsigned int)reg))
-
-#define WRITE_MEM32(addr, val)   (*(volatile unsigned int *)   (addr)) = (val)
-#define READ_MEM32(addr)         (*(volatile unsigned int *)   (addr))
-#define WRITE_MEM16(addr, val)   (*(volatile unsigned short *) (addr)) = (val)
-#define READ_MEM16(addr)         (*(volatile unsigned short *) (addr))
-#define WRITE_MEM8(addr, val)    (*(volatile unsigned char *)  (addr)) = (val)
-#define READ_MEM8(addr)          (*(volatile unsigned char *)  (addr))
-
-#define PADDR(addr)  ((addr) & 0x1FFFFFFF)
-
-/*
- * IRQ Controller
- */
-#define BSP_IRQ_CPU_BASE   0
-#define BSP_IRQ_CPU_NUM    8
-
-#define BSP_IRQ_LOPI_BASE   (BSP_IRQ_CPU_BASE + BSP_IRQ_CPU_NUM)
-#define BSP_IRQ_LOPI_NUM   8
-
-#define BSP_IRQ_ICTL_BASE  (BSP_IRQ_LOPI_BASE + BSP_IRQ_LOPI_NUM)
-#define BSP_IRQ_ICTL_NUM   32
-
-/*
- *  ====================================
- *  Platform Configurable Common Options
- *  ====================================
- */
-
-#define PROM_DEBUG      0
-
-#ifdef CONFIG_FPGA_PLATFORM
-//#define BSP_SYS_CLK_RATE	  	(33860000)      //33.86MHz
-#define BSP_SYS_CLK_RATE	  	(27000000)      //27MHz
-#else
-#define BSP_SYS_CLK_RATE	  	(200000000)     //HS1 clock : 200 MHz
-#endif
-
-#define BSP_BAUDRATE        38400  /* ex. 19200 or 38400 or 57600 or 115200 */ 
-                               /* For Early Debug */
-
-/*
- *   RTL8196b Interrupt Scheme (Subject to change)
- *
- *   Source     EXT_INT  CPU INT    LOPI    IRQ      
- *   --------   -------  -------  -------  ------   
- *   PCIB0TO    0           2        -      16+0     
- *   PCIB1TO    1           2        -      16+1     
- *   LBCTMOm0   2           2        -      16+2     
- *   LBCTMOm1   3           2        -      16+3     
- *   LBCTMOs    4           2        -      16+4     
- *   TIMER0     8           -        5       8+5 
- *   TIMER1     9           2        -      16+9     
- *   USB        10          -        1       8+1
- *   UART0      12          2        -      16+12
- *   UART1      13          2        -      16+13    
- *   VoIP       14          2        -      16+14    
- *   SWCORE     15          -        4       8+4        
- *   GPIO_ABCD  16          2        -      16+16    
- *   GPIO_EFGH  17          2        -      16+17    
- *   NFBI       18          2        -      16+18    
- *   PCM        19          2        -      16+19    
- *   CRYPTO     20          2        -      16+20
- *   PCIE0      21          -        2       8+2
- *   PCIE1      22          -        3       8+3
- */                               
-/*                        
- * IRQ Mapping
- */
-#define BSP_ICTL_IRQ            (BSP_IRQ_CPU_BASE + 2) //for irq cascade
-
-#if defined(RTL8196C) || defined(CONFIG_RTL_8196C)
-#define BSP_ICTL_IRQ			(BSP_IRQ_CPU_BASE + 2) //for irq cascade
-#define BSP_TC0_IRQ             (13)	/* BSP_IRQ_LOPI_BASE + 5	*/
-#define BSP_TC1_IRQ             (BSP_IRQ_ICTL_BASE + 15)
-#define BSP_USB_IRQ             (10)	/* BSP_IRQ_LOPI_BASE + 2	*/
-//#define BSP_UART0_IRQ           (BSP_IRQ_ICTL_BASE + 0)
-#define BSP_UART0_IRQ           (BSP_IRQ_ICTL_BASE + 7)	/* BSP_IRQ_LOPI_BASE + 0	*/
-#define BSP_SWCORE_IRQ          (12)	/* BSP_IRQ_LOPI_BASE + 4	*/
-#define BSP_GPIO_ABCD_IRQ	(BSP_IRQ_ICTL_BASE + 9)
-#define BSP_PCIE_IRQ            (11)	/* BSP_IRQ_LOPI_BASE + 3	*/
-#define BSP_NFBI_IRQ            (15)	/* BSP_IRQ_LOPI_BASE + 7	*/
-#else
-#define BSP_PCIB0TMO_IRQ        (BSP_IRQ_ICTL_BASE + 0)
-#define BSP_PCIB1TMO_IRQ        (BSP_IRQ_ICTL_BASE + 1)
-#define BSP_LBCTMOm0_IRQ        (BSP_IRQ_ICTL_BASE + 2)
-#define BSP_LBCTMOm1_IRQ        (BSP_IRQ_ICTL_BASE + 3)
-#define BSP_LBCTMOs_IRQ         (BSP_IRQ_ICTL_BASE + 4)
-#define BSP_TC0_IRQ             (5)
-#define BSP_TC1_IRQ             (BSP_IRQ_ICTL_BASE + 9)
-#define BSP_USB_IRQ             (BSP_IRQ_LOPI_BASE + 1)
-//#define BSP_UART0_IRQ           (BSP_IRQ_LOPI_BASE + 0)
-#define BSP_UART0_IRQ           (BSP_IRQ_ICTL_BASE + 12)
-#define BSP_UART1_IRQ           (BSP_IRQ_ICTL_BASE + 13)
-#define BSP_SWCORE_IRQ          (4)
-#define BSP_GPIO_ABCD_IRQ       (BSP_IRQ_LOPI_BASE + 6)
-#define BSP_GPIO_EFGH_IRQ       (BSP_IRQ_LOPI_BASE + 7)
-#define BSP_NFBI_IRQ            (BSP_IRQ_ICTL_BASE + 18)
-#define BSP_PCM_IRQ             (BSP_IRQ_ICTL_BASE + 19)
-#define BSP_CRYPTO_IRQ          (BSP_IRQ_ICTL_BASE + 20)
-#define BSP_GDMA_IRQ            (BSP_IRQ_ICTL_BASE + 23)
-#define BSP_PCIE_IRQ            (3)  // shall be 22
-#endif
-/*
- * Interrupt Routing Selection
- */
-#define BSP_IRQ_CASCADE     2
-#define BSP_PTM_RS          BSP_IRQ_CASCADE
-#define BSP_LBCTMOs2_RS     BSP_IRQ_CASCADE
-#define BSP_LBCTMOs1_RS     BSP_IRQ_CASCADE
-#define BSP_PKT_RS          BSP_IRQ_CASCADE
-#define BSP_SPI_RS          BSP_IRQ_CASCADE
-#define BSP_NIC100_RS       BSP_IRQ_CASCADE
-#define BSP_SAR_RS          BSP_IRQ_CASCADE
-#define BSP_DMT_RS          BSP_IRQ_CASCADE
-#define BSP_PCIE_RS		BSP_PCIE_IRQ
-#define BSP_PCIE2_RS	BSP_PCIE2_IRQ
-#define BSP_GDMA_RS         BSP_IRQ_CASCADE
-#define BSP_SECURITY_RS     BSP_IRQ_CASCADE
-#define BSP_PCM_RS          BSP_IRQ_CASCADE
-#define BSP_NFBI_RS         BSP_NFBI_IRQ
-#define BSP_GPIO_EFGH_RS    BSP_IRQ_CASCADE
-#define BSP_GPIO_ABCD_RS    BSP_IRQ_CASCADE
-#define BSP_SW_RS           BSP_SWCORE_IRQ
-//#define BSP_UART0_RS      BSP_UART0_IRQ
-#define BSP_UART0_RS        BSP_IRQ_CASCADE
-#define BSP_UART1_RS        BSP_IRQ_CASCADE
-#define BSP_USB_D_RS        BSP_IRQ_CASCADE
-#define BSP_USB_H_RS        BSP_USB_IRQ
-#define BSP_TC0_RS			BSP_TC0_IRQ//13
-#define BSP_TC1_RS          		BSP_IRQ_CASCADE
-#define BSP_LBCTMOm2_RS     BSP_IRQ_CASCADE
-#define BSP_LBCTMOm1_RS     BSP_IRQ_CASCADE
-#define BSP_SPEED_RS        BSP_IRQ_CASCADE
-#define BSP_LBCTMOs0_RS     BSP_IRQ_CASCADE
-#define BSP_LBCTMOm0_RS     BSP_IRQ_CASCADE
-#define BSP_OCPTMO_RS       BSP_IRQ_CASCADE
-#define BSP_PCIB0TO_RS      BSP_IRQ_CASCADE
-#define BSP_NONE            BSP_IRQ_CASCADE
-#define BSP_PCIB0TMO_RS     BSP_IRQ_CASCADE
-#define BSP_PCIB1TMO_RS     BSP_IRQ_CASCADE
-#define BSP_LBCTMOs_RS      BSP_IRQ_CASCADE
-#define BSP_CRYPTO_RS       BSP_IRQ_CASCADE
-
-
-#define BSP_DIVISOR         1000
-
-#if BSP_DIVISOR > (1 << 16)
-#error "Exceed the Maximum Value of DivFactor"
-#endif
-
-/*
- *  ==========================
- *  Platform Register Settings
- *  ==========================
- */
-
-/*
- * CPU
- */
-#define BSP_IMEM_BASE       0x00C00000
-#define BSP_IMEM_TOP        0x00C03FFF
-
-#define BSP_DMEM_BASE       0x00C04000
-#define BSP_DMEM_TOP        0x00C05FFF
-
-/*
- * Memory Controller
- */
-#define BSP_MC_MCR          0xB8001000
-   #define BSP_MC_MCR_VAL      0x92A28000
-
-#define BSP_MC_MTCR0        0xB8001004
-   #define BSP_MC_MTCR0_VAL    0x12120000
-
-#define BSP_MC_MTCR1        0xB8001008
-   #define BSP_MC_MTCR1_VAL    0x00000FEB
-
-#define BSP_MC_PFCR         0xB8001010
-   #define BSP_MC_PFCR_VAL     0x00000101
-
-
-#define BSP_MC_BASE         0xB8001000
-#define BSP_NCR             (BSP_MC_BASE + 0x100)
-#define BSP_NSR             (BSP_MC_BASE + 0x104)
-#define BSP_NCAR            (BSP_MC_BASE + 0x108)
-#define BSP_NADDR           (BSP_MC_BASE + 0x10C)
-#define BSP_NDR             (BSP_MC_BASE + 0x110)
-
-#define BSP_SFCR            (BSP_MC_BASE + 0x200)
-#define BSP_SFDR            (BSP_MC_BASE + 0x204)
-
-/*
- * UART
- */
-#define BSP_UART0_BASE      0xB8002000
-#define BSP_UART0_MAP_BASE  0x18002000
-#define BSP_UART0_RBR       (BSP_UART0_BASE + 0x000)
-#define BSP_UART0_THR       (BSP_UART0_BASE + 0x000)
-#define BSP_UART0_DLL       (BSP_UART0_BASE + 0x000)
-#define BSP_UART0_IER       (BSP_UART0_BASE + 0x004)
-#define BSP_UART0_DLM       (BSP_UART0_BASE + 0x004)
-#define BSP_UART0_IIR       (BSP_UART0_BASE + 0x008)
-#define BSP_UART0_FCR       (BSP_UART0_BASE + 0x008)
-#define BSP_UART0_LCR       (BSP_UART0_BASE + 0x00C)
-#define BSP_UART0_MCR       (BSP_UART0_BASE + 0x010)
-#define BSP_UART0_LSR       (BSP_UART0_BASE + 0x014)
-
-#define BSP_UART1_BASE      0xB8002100
-#define BSP_UART1_RBR       (BSP_UART1_BASE + 0x000)
-#define BSP_UART1_THR       (BSP_UART1_BASE + 0x000)
-#define BSP_UART1_DLL       (BSP_UART1_BASE + 0x000)
-#define BSP_UART1_IER       (BSP_UART1_BASE + 0x004)
-#define BSP_UART1_DLM       (BSP_UART1_BASE + 0x004)
-#define BSP_UART1_IIR       (BSP_UART1_BASE + 0x008)
-#define BSP_UART1_FCR       (BSP_UART1_BASE + 0x008)
-   #define BSP_FCR_EN          0x01
-   #define BSP_FCR_RXRST       0x02
-   #define     BSP_RXRST             0x02
-   #define BSP_FCR_TXRST       0x04
-   #define     BSP_TXRST             0x04
-   #define BSP_FCR_DMA         0x08
-   #define BSP_FCR_RTRG        0xC0
-   #define     BSP_CHAR_TRIGGER_01   0x00
-   #define     BSP_CHAR_TRIGGER_04   0x40
-   #define     BSP_CHAR_TRIGGER_08   0x80
-   #define     BSP_CHAR_TRIGGER_14   0xC0
-#define BSP_UART1_LCR       (BSP_UART1_BASE + 0x00C)
-   #define BSP_LCR_WLN         0x03
-   #define     BSP_CHAR_LEN_5        0x00
-   #define     BSP_CHAR_LEN_6        0x01
-   #define     BSP_CHAR_LEN_7        0x02
-   #define     BSP_CHAR_LEN_8        0x03
-   #define BSP_LCR_STB         0x04
-   #define     BSP_ONE_STOP          0x00
-   #define     BSP_TWO_STOP          0x04
-   #define BSP_LCR_PEN         0x08
-   #define     BSP_PARITY_ENABLE     0x01
-   #define     BSP_PARITY_DISABLE    0x00
-   #define BSP_LCR_EPS         0x30
-   #define     BSP_PARITY_ODD        0x00
-   #define     BSP_PARITY_EVEN       0x10
-   #define     BSP_PARITY_MARK       0x20
-   #define     BSP_PARITY_SPACE      0x30
-   #define BSP_LCR_BRK         0x40
-   #define BSP_LCR_DLAB        0x80
-   #define     BSP_DLAB              0x80
-#define BSP_UART1_MCR       (BSP_UART1_BASE + 0x010)
-#define BSP_UART1_LSR       (BSP_UART1_BASE + 0x014)
-   #define BSP_LSR_DR          0x01
-   #define     BSP_RxCHAR_AVAIL      0x01
-   #define BSP_LSR_OE          0x02
-   #define BSP_LSR_PE          0x04
-   #define BSP_LSR_FE          0x08
-   #define BSP_LSR_BI          0x10
-   #define BSP_LSR_THRE        0x20
-   #define     BSP_TxCHAR_AVAIL      0x00
-   #define     BSP_TxCHAR_EMPTY      0x20
-   #define BSP_LSR_TEMT        0x40
-   #define BSP_LSR_RFE         0x80
-
-
-/*
- * Interrupt Controller
- */
-#define BSP_GIMR            0xB8003000
-#if defined(RTL8196C) || defined(CONFIG_RTL_8196C)
-   #define BSP_USB_H_IE        (1 << 16)
-   #define BSP_TC1_IE          (1 << 15)
-   #define BSP_TC0_IE          (1 << 14)
-   #define BSP_GDMA_IE         (1 << 11)
-   #define BSP_PCIE_IE         (1 << 10)  // shall be 22
-   #define BSP_PCI_IE          (1 << 10)
-   #define BSP_GPIO_ABCD_IE    (1 << 9)
-   #define BSP_SW_IE           (1 << 8)
-   #define BSP_UART0_IE        (1 << 7)
-#else   
-   #define BSP_GDMA_IE         (1 << 23)
-   #define BSP_PCIE2_IE        (1 << 22)
-   #define BSP_PCIE_IE         (1 << 21)  // shall be 22
-   #define BSP_CRYPTO_IE       (1 << 20)
-   #define BSP_PCM_IE          (1 << 19)
-   #define BSP_NFBI_IE         (1 << 18)
-   #define BSP_GPIO_EFGH_IE    (1 << 17)
-   #define BSP_GPIO_ABCD_IE    (1 << 16)
-   #define BSP_SW_IE           (1 << 15)
-   #define BSP_PCI_IE          (1 << 14)
-   #define BSP_UART1_IE        (1 << 13)
-   #define BSP_UART0_IE        (1 << 12)
-   #define BSP_USB_H_IE        (1 << 16)
-   #define BSP_TC1_IE          (1 << 9)
-   #define BSP_TC0_IE          (1 << 8)
-   #define BSP_LBCTMOs_IE      (1 << 4)
-   #define BSP_LBCTMOm1_IE     (1 << 3)
-   #define BSP_LBCTMOm0_IE     (1 << 2)
-   #define BSP_PCIB1TO_IE      (1 << 1)
-   #define BSP_PCIB0TO_IE      (1 << 0)
-#endif
-#define BSP_GISR            0xB8003004
-#if defined(RTL8196C) || defined(CONFIG_RTL_8196C)
-   #define BSP_USB_H_IP        (1 << 16)
-   #define BSP_TC1_IP          (1 << 15)
-   #define BSP_TC0_IP          (1 << 14)
-   #define BSP_GDMA_IP         (1 << 11)
-   #define BSP_PCIE_IP         (1 << 10)  
-   #define BSP_PCI_IP          (1 << 10)
-   #define BSP_GPIO_ABCD_IP    (1 << 9)
-   #define BSP_SW_IP           (1 << 8)
-   #define BSP_UART0_IP        (1 << 7)
-   #else
-   	#define BSP_GDMA_IP         (1 << 23)
-   	#define BSP_PCIE2_IP        (1 << 22)
-  	#define BSP_PCIE_IP         (1 << 21) // shall be 22
-   	#define BSP_CRYPTO_IP       (1 << 20)
-   	#define BSP_PCM_IP          (1 << 19)
-   	#define BSP_NFBI_IP         (1 << 18)
-   	#define BSP_GPIO_EFGH_IP    (1 << 17)
-   	//#define BSP_GPIO_ABCD_IP    (1 << 16)
-   	#define BSP_SW_IP           (1 << 15)
-   	#define BSP_PCI_IP          (1 << 14)
-   	#define BSP_UART1_IP        (1 << 13)
-   	#define BSP_UART0_IP        (1 << 12)
-   	#define BSP_USB_H_IP        (1 << 16)
-   	#define BSP_TC1_IP          (1 << 9)
-   	#define BSP_TC0_IP          (1 << 8)
-   	#define BSP_LBCTMOs_IP      (1 << 4)
-   	#define BSP_LBCTMOm1_IP     (1 << 3)
-   	#define BSP_LBCTMOm0_IP     (1 << 2)
-   	#define BSP_PCIB1TO_IP      (1 << 1)
-   	#define BSP_PCIB0TO_IP      (1 << 0)
-   #endif
-#define BSP_IRR0            0xB8003008
-#define BSP_IRR0_SETTING    ((BSP_UART0_RS << 28) | \
-                         (BSP_NONE << 24) | \
-                         (BSP_NONE    << 20) | \
-                         (BSP_NONE << 16) | \
-                         (BSP_NONE << 12) | \
-                         (BSP_NONE   << 8)  | \
-                         (BSP_NONE        << 4)  | \
-                         (BSP_NONE  << 0)    \
-                        )
-
-#define BSP_IRR1            0xB800300C
-#define BSP_IRR1_SETTING    ((BSP_TC1_RS<<28)|\
-			(BSP_TC0_RS<<24)|\
-			(BSP_NONE<<20)|\
-			(BSP_OCPTMO_RS<<16)|\
-			(BSP_GDMA_RS<<12)|\
-			(BSP_PCIE_RS<<8)|\
-			(BSP_GPIO_ABCD_RS<<4)|\
-			(BSP_SW_RS<<0))
-
-#define BSP_IRR2            0xB8003010
-#define BSP_IRR2_SETTING    ((BSP_NONE      << 28) | \
-                         (BSP_NONE     << 24) | \
-                         (BSP_NONE      << 20) | \
-                         (BSP_NONE  << 16) | \
-                         (BSP_NONE       << 12) | \
-                         (BSP_NONE      << 8)  | \
-                         (BSP_PCM_RS << 4)  | \
-                         (BSP_USB_H_RS << 0)    \
-                        )
-
-#define BSP_IRR3            0xB8003014
-#define BSP_IRR3_SETTING    ((BSP_NONE      << 28) | \
-                         (BSP_NONE << 24) | \
-                         (BSP_NONE << 20) | \
-                         (BSP_NONE      << 16) | \
-                         (BSP_NONE      << 12) | \
-                         (BSP_NONE   << 8)  | \
-                         (BSP_NONE      << 4)  | \
-                         (BSP_NONE      << 0)    \
-                        )
-/*
- * Timer/Counter
- */
-#define BSP_TC_BASE         0xB8003100
-#define BSP_TC0DATA         (BSP_TC_BASE + 0x00)
-#define BSP_TC1DATA         (BSP_TC_BASE + 0x04)
-   #define BSP_TCD_OFFSET      8
-#define BSP_TC0CNT          (BSP_TC_BASE + 0x08)
-#define BSP_TC1CNT          (BSP_TC_BASE + 0x0C)
-#define BSP_TCCNR           (BSP_TC_BASE + 0x10)
-   #define BSP_TC0EN           (1 << 31)
-   #define BSP_TC0MODE_TIMER   (1 << 30)
-   #define BSP_TC1EN           (1 << 29)
-   #define BSP_TC1MODE_TIMER   (1 << 28)
-#define BSP_TCIR            (BSP_TC_BASE + 0x14)
-   #define BSP_TC0IE           (1 << 31)
-   #define BSP_TC1IE           (1 << 30)
-   #define BSP_TC0IP           (1 << 29)
-   #define BSP_TC1IP           (1 << 28)
-#define BSP_CDBR            (BSP_TC_BASE + 0x18)
-   #define BSP_DIVF_OFFSET     16
-#define BSP_WDTCNR          (BSP_TC_BASE + 0x1C)
-
-/*
- * PCIE Host Controller
- */
-#define BSP_PCIE0_H_CFG     0xB8B00000
-#define BSP_PCIE0_H_EXT     0xB8B01000
-#define BSP_PCIE0_H_MDIO    (BSP_PCIE0_H_EXT + 0x00)
-#define BSP_PCIE0_H_INTSTR  (BSP_PCIE0_H_EXT + 0x04)
-#define BSP_PCIE0_H_PWRCR   (BSP_PCIE0_H_EXT + 0x08)
-#define BSP_PCIE0_H_IPCFG   (BSP_PCIE0_H_EXT + 0x0C)
-#define BSP_PCIE0_H_MISC    (BSP_PCIE0_H_EXT + 0x10)
-#define BSP_PCIE0_D_CFG0    0xB8B10000
-#define BSP_PCIE0_D_CFG1    0xB8B11000
-#define BSP_PCIE0_D_MSG     0xB8B12000
-
-#define BSP_PCIE1_H_CFG     0xB8B20000
-#define BSP_PCIE1_H_EXT     0xB8B21000
-#define BSP_PCIE1_H_MDIO    (BSP_PCIE1_H_EXT + 0x00)
-#define BSP_PCIE1_H_INTSTR  (BSP_PCIE1_H_EXT + 0x04)
-#define BSP_PCIE1_H_PWRCR   (BSP_PCIE1_H_EXT + 0x08)
-#define BSP_PCIE1_H_IPCFG   (BSP_PCIE1_H_EXT + 0x0C)
-#define BSP_PCIE1_H_MISC    (BSP_PCIE1_H_EXT + 0x10)
-#define BSP_PCIE1_D_CFG0    0xB8B30000
-#define BSP_PCIE1_D_CFG1    0xB8B31000
-#define BSP_PCIE1_D_MSG     0xB8B32000
-
-#define BSP_PCIE0_D_IO      0xB8C00000
-#define BSP_PCIE1_D_IO      0xB8E00000
-#define BSP_PCIE_FUN_OFS      0xC00000
-#define BSP_PCIE0_D_MEM     0xB9000000
-#define BSP_PCIE0_F1_D_MEM  (BSP_PCIE0_D_MEM + BSP_PCIE_FUN_OFS)
-#define BSP_PCIE1_D_MEM     0xBA000000
-#define BSP_PCIE1_F1_D_MEM  (BSP_PCIE1_D_MEM + BSP_PCIE_FUN_OFS)
-
-#ifndef REVR
-#define REVR                                    0xB8000000
-#endif
- 
-#ifndef RTL8196C_REVISION_A
-#define RTL8196C_REVISION_A     0x80000001
-#endif
- 
-#ifndef RTL8196C_REVISION_B
-#define RTL8196C_REVISION_B     0x80000002
-#endif
-
-#endif   /* _BSPCHIP_H */
diff --git a/target/linux/realtek/files/arch/rlx/bsp/bspcpu.h b/target/linux/realtek/files/arch/rlx/bsp/bspcpu.h
deleted file mode 100644
index 468760c97..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/bspcpu.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Realtek Semiconductor Corp.
- *
- * bspcpu.h:
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Dec. 7, 2007
- */
-#ifndef __BSPCPU_H_
-#define __BSPCPU_H_
-
-#define cpu_scache_size     0
-#define cpu_dcache_size     ( 8 << 10)
-#define cpu_icache_size     (16 << 10)
-#define cpu_scache_line     0
-#define cpu_dcache_line     16
-#define cpu_icache_line     16
-#define cpu_dcache_line_mask     0xF  /*cpu_dcache_line-1*/
-#define cpu_icache_line_mask     0xF  /*cpu_icache_line-1*/
-#define cpu_tlb_entry       32
-//#define cpu_mem_size        (64 << 20)
-#define cpu_mem_size        (32 << 20)
-//#define cpu_mem_size        ((7 << 20)-16) //reserve 16 byte for firmware header
-
-#define cpu_imem_size       0
-#define cpu_dmem_size       0
-#define cpu_smem_size       0
-
-#endif
diff --git a/target/linux/realtek/files/arch/rlx/bsp/bspinit.h b/target/linux/realtek/files/arch/rlx/bsp/bspinit.h
deleted file mode 100644
index e7dddccb4..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/bspinit.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Realtek Semiconductor Corp.
- *
- * bspinit.h:
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Dec. 7, 2007
- */
-#ifndef __BSPINIT_H_
-#define __BSPINIT_H_
-
-.macro  kernel_entry_setup 
-.endm
-
-.macro  smp_slave_setup
-.endm
-
-#endif
diff --git a/target/linux/realtek/files/arch/rlx/bsp/irq.c b/target/linux/realtek/files/arch/rlx/bsp/irq.c
deleted file mode 100644
index 80d5a3b71..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/irq.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Realtek Semiconductor Corp.
- *
- * arch/rlx/rlxocp0/irq.c
- *   Interrupt and exception initialization for RLX OCP Platform
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Nov. 7, 2006
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/irq.h>
-
-#include <asm/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/irq_vec.h>
-#include <asm/system.h>
-
-#include <asm/rlxregs.h>
-#include <asm/rlxbsp.h>
-#include <net/rtl/rtl_types.h>
-#include "bspchip.h"
-
-static struct irqaction irq_cascade = { 
-  .handler = no_action,
-  .mask = CPU_MASK_NONE,
-  .name = "cascade",
-};
-
-static void bsp_ictl_irq_mask(unsigned int irq)
-{
-	REG32(BSP_GIMR) &= ~(1 << (irq - BSP_IRQ_ICTL_BASE));
-}
-
-static void bsp_ictl_irq_unmask(unsigned int irq)
-{
-	REG32(BSP_GIMR) |= (1 << (irq - BSP_IRQ_ICTL_BASE));
-}
-
-static struct irq_chip bsp_ictl_irq = {
-    .typename = "ICTL",
-    .ack = bsp_ictl_irq_mask,
-    .mask = bsp_ictl_irq_mask,
-    .mask_ack = bsp_ictl_irq_mask,
-    .unmask = bsp_ictl_irq_unmask,
-};
-
-static void bsp_ictl_irq_dispatch(void)
-{
-	volatile unsigned int pending;
-
-	pending = REG32(BSP_GIMR) & REG32(BSP_GISR);
-
-	if (pending & BSP_UART0_IP)
-		do_IRQ(BSP_UART0_IRQ);
-	else if (pending & BSP_TC1_IP)
-		do_IRQ(BSP_TC1_IRQ);
-	else if (pending & BSP_GPIO_ABCD_IP)
-		do_IRQ(BSP_GPIO_ABCD_IRQ);
-	else {
-		REG32(BSP_GIMR) &= (~pending);
-		REG32(BSP_GISR) = REG32(BSP_GISR);
-		printk("Unknown Interrupt0:%x\n", pending);
-		#if defined(CONFIG_RTK_VOIP) || defined(CONFIG_RTL_819X)
-		spurious_interrupt(SPURIOS_INT_CASCADE);
-		#else
-		spurious_interrupt();
-		#endif
-	}
-}
-
-void bsp_irq_dispatch(void)
-{
-	volatile unsigned int pending;
-	pending = read_c0_cause() & read_c0_status();
-	
-	if (pending & CAUSEF_IP2)
-		bsp_ictl_irq_dispatch();
-	else if (pending & CAUSEF_IP0)
-		do_IRQ(0);
-	else if (pending & CAUSEF_IP1)
-		do_IRQ(1);
-	else {
-#if defined(CONFIG_RTK_VOIP) || defined(CONFIG_RTL_819X)
-	spurious_interrupt(SPURIOS_INT_CPU);
-#else
-	spurious_interrupt();
-#endif
-	}
-}
-
-static void __init bsp_ictl_irq_init(unsigned int irq_base)
-{
-    int i;
-
-    for (i=0; i < BSP_IRQ_ICTL_NUM; i++) 
-        set_irq_chip_and_handler(irq_base + i, &bsp_ictl_irq, handle_level_irq);
-
-    setup_irq(BSP_ICTL_IRQ, &irq_cascade);
-}
-
-void __init bsp_irq_init(void)
-{
-	//unsigned int	status;
-	//volatile unsigned int status;
-	/* disable ict interrupt */
-	REG32(BSP_GIMR) = 0;
-
-	/* initialize IRQ action handlers */
-	rlx_cpu_irq_init(BSP_IRQ_CPU_BASE);
-	rlx_vec_irq_init(BSP_IRQ_LOPI_BASE);
-	bsp_ictl_irq_init(BSP_IRQ_ICTL_BASE);
-
-	/* Set IRR */
-	REG32(BSP_IRR0) = BSP_IRR0_SETTING;
-	REG32(BSP_IRR1) = BSP_IRR1_SETTING;
-	REG32(BSP_IRR2) = BSP_IRR2_SETTING;
-	REG32(BSP_IRR3) = BSP_IRR3_SETTING;  
-
-	//status = read_c0_status();
-	//status = (status&(~ST0_IM))|(CAUSEF_IP2|CAUSEF_IP3|CAUSEF_IP4|CAUSEF_IP5|CAUSEF_IP6);
-	//write_c0_status(status);
-}
-
-#if defined(CONFIG_RTL_8196C) && defined(CONFIG_ARCH_SUSPEND_POSSIBLE)//michaelxxx 
-   #define CONFIG_RTL819X_SUSPEND_CHECK_INTERRUPT 
-    
-   #ifdef CONFIG_RTL819X_SUSPEND_CHECK_INTERRUPT 
-   #include <linux/proc_fs.h> 
-   #include <linux/kernel_stat.h> 
-   #include <asm/uaccess.h> 
-   //#define INT_HIGH_WATER_MARK 1850 //for window size = 1, based on LAN->WAN test result 
-   //#define INT_LOW_WATER_MARK  1150 
-   //#define INT_HIGH_WATER_MARK 9190 //for window size = 5, based on LAN->WAN test result 
-   //#define INT_LOW_WATER_MARK  5500 
-   #define INT_HIGH_WATER_MARK 3200  //for window size = 5, based on WLAN->WAN test result 
-   #define INT_LOW_WATER_MARK  2200 
-   #define INT_WINDOW_SIZE_MAX 10 
-   static int suspend_check_enable = 1; 
-   static int suspend_check_high_water_mark = INT_HIGH_WATER_MARK; 
-   static int suspend_check_low_water_mark = INT_LOW_WATER_MARK; 
-   static int suspend_check_win_size = 5; 
-   static struct timer_list suspend_check_timer; 
-   static int index=0; 
-   static int eth_int_count[INT_WINDOW_SIZE_MAX]; 
-   static int wlan_int_count[INT_WINDOW_SIZE_MAX]; 
-   int cpu_can_suspend = 1; 
-   int cpu_can_suspend_check_init = 0; 
-    
-   static int read_proc_suspend_check(char *page, char **start, off_t off, 
-           int count, int *eof, void *data) 
-   { 
-       int len; 
-    
-       len = sprintf(page, "enable=%d, winsize=%d(%d), high=%d, low=%d, suspend=%d\n", 
-                   suspend_check_enable, suspend_check_win_size, INT_WINDOW_SIZE_MAX, 
-                   suspend_check_high_water_mark, suspend_check_low_water_mark, cpu_can_suspend); 
-    
-       if (len <= off+count) 
-           *eof = 1; 
-       *start = page + off; 
-       len -= off; 
-       if (len > count) 
-           len = count; 
-       if (len < 0) 
-           len = 0; 
-       return len; 
-   } 
-    
-   static int write_proc_suspend_check(struct file *file, const char *buffer, 
-                 unsigned long count, void *data) 
-   { 
-           char tmp[128]; 
-    
-           if (buffer && !copy_from_user(tmp, buffer, 128)) { 
-                   sscanf(tmp, "%d %d %d %d", 
-                           &suspend_check_enable, &suspend_check_win_size, 
-                           &suspend_check_high_water_mark, &suspend_check_low_water_mark); 
-                   if (suspend_check_win_size >= INT_WINDOW_SIZE_MAX) 
-                           suspend_check_win_size = INT_WINDOW_SIZE_MAX - 1; 
-                   if (suspend_check_enable) { 
-                           mod_timer(&suspend_check_timer, jiffies + 100); 
-                   } 
-                   else { 
-                           del_timer(&suspend_check_timer); 
-                   } 
-           } 
-           return count; 
-   } 
-    
-   static void suspend_check_timer_fn(unsigned long arg) 
-   { 
-           int count, j; 
-    
-           index++; 
-           if (INT_WINDOW_SIZE_MAX <= index) 
-                   index = 0; 
-           eth_int_count[index] = kstat_irqs(BSP_SWCORE_IRQ); 
-           wlan_int_count[index] = kstat_irqs(BSP_PCIE_IRQ); 
-           j = index - suspend_check_win_size; 
-           if (j < 0) 
-                   j += INT_WINDOW_SIZE_MAX; 
-           count = (eth_int_count[index] - eth_int_count[j]) + 
-                   (wlan_int_count[index]- wlan_int_count[j]); //unit: number of interrupt occurred 
-    
-           if (cpu_can_suspend) { 
-                   if (count > suspend_check_high_water_mark) { 
-                           cpu_can_suspend = 0; 
-                           //printk("\n<<<RTL8196C LEAVE SLEEP>>>\n"); /* for Debug Only*/ 
-                   } 
-           } 
-           else { 
-                   if (count < suspend_check_low_water_mark) { 
-                           cpu_can_suspend = 1; 
-                           //printk("\n<<<RTL8196C ENTER SLEEP>>>\n"); /* for Debug Only*/ 
-                   } 
-           } 
-   #if 0 /* for Debug Only*/ 
-           printk("###index=%d, count=%d (%d+%d) suspend=%d###\n",index, count, 
-                   (eth_int_count[index] - eth_int_count[j]), 
-                   (wlan_int_count[index]- wlan_int_count[j]), 
-                   cpu_can_suspend); 
-   #endif 
-           mod_timer(&suspend_check_timer, jiffies + 100); 
-   } 
-    
-   void suspend_check_interrupt_init(void) 
-   { 
-           struct proc_dir_entry *res; 
-           int i; 
-    
-           res = create_proc_entry("suspend_check", 0, NULL); 
-           if (res) { 
-                   res->read_proc = read_proc_suspend_check; 
-                   res->write_proc = write_proc_suspend_check; 
-           } 
-           else { 
-                   printk("unable to create /proc/suspend_check\n"); 
-           } 
-    
-           for (i=0; i<INT_WINDOW_SIZE_MAX; i++) { 
-                   wlan_int_count[i] = 0; 
-                   eth_int_count[i] = 0; 
-           } 
-           init_timer(&suspend_check_timer); 
-           suspend_check_timer.data = 0; 
-           suspend_check_timer.function = suspend_check_timer_fn; 
-           suspend_check_timer.expires = jiffies + 100; /* in jiffies */ 
-           add_timer(&suspend_check_timer); 
-   	}
-   #endif // CONFIG_RTL819X_SUSPEND_CHECK_INTERRUPT 
-   #endif //CONFIG_RTL8196C 
-
diff --git a/target/linux/realtek/files/arch/rlx/bsp/kgdb.c b/target/linux/realtek/files/arch/rlx/bsp/kgdb.c
deleted file mode 100644
index 93960b21f..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/kgdb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Realtek semiconductor Corp.
- *
- *   arch/rlx/rlxocp/kgdb.c:
- *      Kernel debugging on the rtl5739.
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Dec. 7, 2007
- */
-#include <asm/system.h>
-#include <asm/tx3912.h>
-
-static int remoteDebugInitialized = 0;
-
-void debugInit(void)
-{
-/*
- * If low-level debugging (before GDB or console operational) is
- * configured, then we do not need to re-initialize the UART.
- */
-#ifndef CONFIG_DEBUG_LL
-//      earlyInitUartPR31700();
-#endif
-}
-
-char getDebugChar(void)
-{
-    char buf;
-    unsigned long int2, flags;
-
-    if (!remoteDebugInitialized) {
-        debugInit();
-        remoteDebugInitialized = 1;
-    }
-
-    save_and_cli(flags);
-
-    int2 = IntEnable2;
-
-    IntEnable2 = 0;
-
-    while (!(UartA_Ctrl1 & UART_RX_HOLD_FULL));
-
-    buf = UartA_Data;
-
-    IntEnable2 = int2;
-
-    restore_flags(flags);
-
-    return buf;
-}
-
-int putDebugChar(char c)
-{
-    int i;
-    unsigned long int2;
-
-    if (!remoteDebugInitialized) {
-        debugInit();
-        remoteDebugInitialized = 1;
-    }
-
-    int2 = IntEnable2;
-
-    IntEnable2 &=
-        ~(INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY);
-
-    for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++);
-
-    IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY;
-
-    UartA_Data = c;
-
-    for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++);
-
-    IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY;
-
-    IntEnable2 = int2;
-
-    return 1;
-}
diff --git a/target/linux/realtek/files/arch/rlx/bsp/pci.c b/target/linux/realtek/files/arch/rlx/bsp/pci.c
deleted file mode 100644
index 11b295e8b..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/pci.c
+++ /dev/null
@@ -1,621 +0,0 @@
-/*
- * RTL8196B PCIE Host Controller Glue Driver
- * Author: ghhuang@realtek.com.tw
- *
- * Notes:
- * - Two host controllers available.
- * - Each host direcly connects to one device
- * - Supports PCI devices through PCIE-to-PCI bridges
- * - If no PCI devices are connected to RC. Timeout monitor shall be 
- *   enabled to prevent bus hanging.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <asm/rlxregs.h>
-#include "bspchip.h"
-
-#define PCI_8BIT_ACCESS    1
-#define PCI_16BIT_ACCESS   2
-#define PCI_32BIT_ACCESS   4
-#define PCI_ACCESS_READ    8
-#define PCI_ACCESS_WRITE   16
-
-#define MAX_NUM_DEV  4
-
-#define DEBUG_PRINTK 0
-//#define PIN_208
-
-static int pci0_bus_number = 0xff;
-static int pci1_bus_number = 0xff;
-
-static struct resource rtl8196b_pci0_io_resource = {
-   .name   = "RTL8196B PCI0 IO",
-   .flags  = IORESOURCE_IO,
-   .start  = PADDR(BSP_PCIE0_D_IO),
-   .end    = PADDR(BSP_PCIE0_D_IO + 0x1FFFFF)
-};
-
-static struct resource rtl8196b_pci0_mem_resource = {
-   .name   = "RTL8196B PCI0 MEM",
-   .flags  = IORESOURCE_MEM,
-   .start  = PADDR(BSP_PCIE0_D_MEM),
-   .end    = PADDR(BSP_PCIE0_D_MEM + 0xFFFFFF)
-};
-
-#ifdef PIN_208
-static struct resource rtl8196b_pci1_io_resource = {
-   .name   = "RTL8196B PCI1 IO",
-   .flags  = IORESOURCE_IO,
-   .start  = PADDR(BSP_PCIE1_D_IO),
-   .end    = PADDR(BSP_PCIE1_D_IO + 0x1FFFFF)
-};
-
-static struct resource rtl8196b_pci1_mem_resource = {
-   .name   = "RTL8196B PCI1 MEM",
-   .flags  = IORESOURCE_MEM,
-   .start  = PADDR(BSP_PCIE1_D_MEM),
-   .end    = PADDR(BSP_PCIE1_D_MEM + 0xFFFFFF)
-};
-#endif
-
-
- 
- 
-//HOST PCIE
-#define PCIE0_RC_EXT_BASE (0xb8b01000)
-//RC Extended register
-#define PCIE0_MDIO (PCIE0_RC_EXT_BASE+0x00)
-//MDIO
-#define PCIE_MDIO_DATA_OFFSET (16)
-#define PCIE_MDIO_DATA_MASK (0xffff <<PCIE_MDIO_DATA_OFFSET)
-#define PCIE_MDIO_REG_OFFSET (8)
-#define PCIE_MDIO_RDWR_OFFSET (0)
- 
-
-void HostPCIe_SetPhyMdioWrite(unsigned int regaddr, unsigned short val)
-{
- REG32(PCIE0_MDIO)= ( (regaddr&0x1f)<<PCIE_MDIO_REG_OFFSET) | ((val&0xffff)<<PCIE_MDIO_DATA_OFFSET)  | (1<<PCIE_MDIO_RDWR_OFFSET) ; 
- //delay 
-mdelay(1);//mdelay(10);
-}
-
-void PCIE_reset_procedure(int PCIE_Port0and1_8196B_208pin, int Use_External_PCIE_CLK, int mdio_reset)
-{
-        #define SYS_PCIE_PHY0   (0xb8000000 +0x50)
- //PCIE Register
-  #define CLK_MANAGE  0xb8000010
- 
-  #define PCIE_PHY0_REG  0xb8b01000
-  //#define PCIE_PHY1_REG  0xb8b21000
-  #define PCIE_PHY0  0xb8b01008
- // #define PCIE_PHY1  0xb8b21008
- 
-
-  
-//JSW:PCIE reset procedure
-#if 0
-        //1. "Enable internal PCIE PLL
-//#if Use_External_PCIE_CLK
-if(Use_External_PCIE_CLK)
-    REG32(PIE_PLL) = 0x358;                        //Use External PCIE CLK (clock chip)
-//#else  
-else
-    REG32(PCIE_PLL) = 0x9;                          //Use Internal PCIE CLK and PCIE fine-tune
-//#endif
- 
-
-//prom_printf("\nPCIE_PLL(0x%x)=0x%x\n",PCIE_PLL,READ_MEM32(PCIE_PLL));
-    mdelay(100);//mdelay(10);
-#endif
- 
-        //2.Active LX & PCIE Clock
-    REG32(CLK_MANAGE) |=  (1<<11);        //enable active_pcie0
-    mdelay(100);
- 
-#if 1
- if(mdio_reset)
- {
-  printk("Do MDIO_RESET\n");
-        // 3.MDIO Reset  
-     REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (0<<0);     //mdio reset=0,          
-     REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (1<<0);     //mdio reset=1,   
-     REG32(SYS_PCIE_PHY0) = (1<<3) |(1<<1) | (1<<0);     //bit1 load_done=1
- } 
-        //4. PCIE PHY Reset       
-    REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0   bit0 Enable LTSSM=1
-    REG32(PCIE_PHY0) = 0x81;   //bit7 PHY reset=1   bit0 Enable LTSSM=1
-      mdelay(100);
-   
-#endif
- 
-        mdelay(100);    
- 
-#if 0
- //#if Use_External_PCIE_CLK
- if(Use_External_PCIE_CLK)
- {
-  //5. PCIE P0 PHY external clock
-   mdelay(100); 
-   REG32(PCIE_PHY0_REG) = 0xC3930301; //bit[3] must be "0" for external clock
-   //REG32(PCIE_PHY0_REG) = 0xC39B0301; //20090304:RDC for for PCIE port 0 Refine-tune
-    mdelay(100);       
-   
-       
-          REG32(PCIE_PHY0_REG) = 0x3c011901; //close PHY 0 ,"0"=R,"1"=W
-          mdelay(100);
- } 
- //#endif
- #endif
- 
- 
-   //----------------------------------------
-   if(mdio_reset)
-    {
- //fix 8196C test chip pcie tx problem. 
-/* 
- HostPCIe_SetPhyMdioWrite( 8, HostPCIe_SetPhyMdioRead(8) | (1<<3) );
- HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (5<<5) );
- HostPCIe_SetPhyMdioWrite(0x0d,  HostPCIe_SetPhyMdioRead(0x0d) | (1<<4) );
- HostPCIe_SetPhyMdioWrite(0x0f, HostPCIe_SetPhyMdioRead(0x0f) & ~(1<<4));
- HostPCIe_SetPhyMdioWrite(0x06, HostPCIe_SetPhyMdioRead(0x06) | (1<<11) ); 
-*/ 
-  HostPCIe_SetPhyMdioWrite(0, 0x5027);
-  HostPCIe_SetPhyMdioWrite(2, 0x6d18);
-  HostPCIe_SetPhyMdioWrite(6, 0x8828);
-  HostPCIe_SetPhyMdioWrite(7, 0x30ff);
-  HostPCIe_SetPhyMdioWrite(8, 0x18d7);
-  HostPCIe_SetPhyMdioWrite(0xa, 0xe9);
-  HostPCIe_SetPhyMdioWrite(0xb, 0x0511);
-  HostPCIe_SetPhyMdioWrite(0xd, 0x15b6);  
-  HostPCIe_SetPhyMdioWrite(0xf, 0x0f0f);    
-#if 1 // PHY_EAT_40MHZ
-		HostPCIe_SetPhyMdioWrite(5, 0xbcb);    //[9:3]=1111001 (binary)   121 (10)
-		HostPCIe_SetPhyMdioWrite(6, 0x8128);  //[11]=0   [9:8]=01
-#endif  
-/* 
-emdiow 0 5027
-emdiow 2 6d18
-emdiow 6 8828
-emdiow 7 30ff
-emdiow 8 18dd
-emdiow a e9
-emdiow b 0511
-emdiow d 15b6
-emdiow f 0f0f
-*/
-    }
- 
- //---------------------------------------
-         // 6. PCIE Device Reset
-     REG32(CLK_MANAGE) &= ~(1<<12);    //perst=0 off.
-        mdelay(100);   
-        mdelay(100);   
-        mdelay(100);   
-  
-    REG32(CLK_MANAGE) |=  (1<<12);   //PERST=1
-    //prom_printf("\nCLK_MANAGE(0x%x)=0x%x\n\n",CLK_MANAGE,READ_MEM32(CLK_MANAGE));
- 
- 
-        //4. PCIE PHY Reset       
-    REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0   bit0 Enable LTSSM=1
-    REG32(PCIE_PHY0) = 0x81;   //bit7 PHY reset=1   bit0 Enable LTSSM=1
-      mdelay(100);
-  mdelay(1000);
-  #if 1  //wait for LinkUP
- int i=100;
- while(--i)
- {
-       if( (REG32(0xb8b00728)&0x1f)==0x11)
-     break;
-          mdelay(100);
- }
- if(i==0)
-  printk("i=%x Cannot LinkUP \n",i);
-#endif
- 
-printk("devid=%x\n",REG32(0xb8b10000));
-   
- 
-}
-
-
-
-static int rtl8196b_pcibios_config_access(unsigned char access_type,
-       unsigned int addr, unsigned int *data)
-{
-   /* Do 8bit/16bit/32bit access */
-   if (access_type & PCI_ACCESS_WRITE)
-   {
-      if (access_type & PCI_8BIT_ACCESS)
-         WRITE_MEM8(addr, *data);
-      else if (access_type & PCI_16BIT_ACCESS)
-         WRITE_MEM16(addr, *data);
-      else
-         WRITE_MEM32(addr, *data);
-   }
-   else if (access_type & PCI_ACCESS_READ)
-   {
-      if (access_type & PCI_8BIT_ACCESS)
-         *data = READ_MEM8(addr);
-      else if (access_type & PCI_16BIT_ACCESS)
-         *data = READ_MEM16(addr);
-      else
-         *data = READ_MEM32(addr);
-   }
-
-   /* If need to check for PCIE access timeout, put code here */
-   /* ... */
-
-   return 0;
-}
-
-
-
-/*
- * RTL8196b supports config word read access for 8/16/32 bit
- *
- * FIXME: currently only utilize 32bit access
- */
-static int rtl8196b_pcibios0_read(struct pci_bus *bus, unsigned int devfn,
-                                  int where, int size, unsigned int *val)
-{
-   unsigned int data = 0;
-   unsigned int addr = 0;
-
-   if (pci0_bus_number == 0xff)
-      pci0_bus_number = bus->number;
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-   #endif
-
-   if (bus->number == pci0_bus_number)
-   {
-      /* PCIE host controller */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE0_H_CFG + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-
-         if (size == 1)
-            *val = (data >> ((where & 3) << 3)) & 0xff;
-         else if (size == 2)
-            *val = (data >> ((where & 3) << 3)) & 0xffff;
-         else
-            *val = data;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else if (bus->number == (pci0_bus_number + 1))
-   {
-      /* PCIE devices directly connected */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else
-   {
-      /* Devices connected through bridge */
-      if (PCI_SLOT(devfn) < MAX_NUM_DEV)
-      {
-         WRITE_MEM32(BSP_PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn));
-         addr = BSP_PCIE0_D_CFG1 + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("Read Value: 0x%08X\n", *val);
-   #endif
-
-   return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int rtl8196b_pcibios0_write(struct pci_bus *bus, unsigned int devfn,
-                                   int where, int size, unsigned int val)
-{
-   unsigned int data = 0;
-   unsigned int addr = 0;
-
-   static int pci0_bus_number = 0xff;
-   if (pci0_bus_number == 0xff)
-      pci0_bus_number = bus->number;
-
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-   #endif
-
-   if (bus->number == pci0_bus_number)
-   {
-      /* PCIE host controller */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE0_H_CFG + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-
-         if (size == 1)
-            data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
-         else if (size == 2)
-            data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
-         else
-            data = val;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | PCI_32BIT_ACCESS, addr & ~(0x3), &data))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else if (bus->number == (pci0_bus_number + 1))
-   {
-      /* PCIE devices directly connected */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else
-   {
-      /* Devices connected through bridge */
-      if (PCI_SLOT(devfn) < MAX_NUM_DEV)
-      {
-         WRITE_MEM32(BSP_PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn));
-         addr = BSP_PCIE0_D_CFG1 + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-
-   return PCIBIOS_SUCCESSFUL;
-}
-
-
-/*
- * RTL8196b supports config word read access for 8/16/32 bit
- *
- * FIXME: currently only utilize 32bit access
- */
-#ifdef PIN_208
-static int rtl8196b_pcibios1_read(struct pci_bus *bus, unsigned int devfn,
-                                  int where, int size, unsigned int *val)
-{
-   unsigned int data = 0;
-   unsigned int addr = 0;
-
-   if (pci1_bus_number == 0xff)
-      pci1_bus_number = bus->number;
-
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-   #endif
-
-   if (bus->number == pci1_bus_number)
-   {
-      /* PCIE host controller */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE1_H_CFG + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-
-         if (size == 1)
-            *val = (data >> ((where & 3) << 3)) & 0xff;
-         else if (size == 2)
-            *val = (data >> ((where & 3) << 3)) & 0xffff;
-         else
-            *val = data;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else if (bus->number == (pci1_bus_number + 1))
-   {
-      /* PCIE devices directly connected */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else
-   {
-      /* Devices connected through bridge */
-      if (PCI_SLOT(devfn) < MAX_NUM_DEV)
-      {
-         WRITE_MEM32(BSP_PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn));
-         addr = BSP_PCIE1_D_CFG1 + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("Read Value: 0x%08X\n", *val);
-   #endif
-
-   return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int rtl8196b_pcibios1_write(struct pci_bus *bus, unsigned int devfn,
-                                   int where, int size, unsigned int val)
-{
-   unsigned int data = 0;
-   unsigned int addr = 0;
-
-   static int pci1_bus_number = 0xff;
-
-   if (pci1_bus_number == 0xff)
-      pci1_bus_number = bus->number;
-
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-   #endif
-
-
-   if (bus->number == pci1_bus_number)
-   {
-      /* PCIE host controller */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE1_H_CFG + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-
-         if (size == 1)
-            data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
-         else if (size == 2)
-            data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
-         else
-            data = val;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | PCI_32BIT_ACCESS, addr & ~(0x3), &data))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else if (bus->number == (pci1_bus_number + 1))
-   {
-      /* PCIE devices directly connected */
-      if (PCI_SLOT(devfn) == 0)
-      {
-         addr = BSP_PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-   else
-   {
-      /* Devices connected through bridge */
-      if (PCI_SLOT(devfn) < MAX_NUM_DEV)
-      {
-         WRITE_MEM32(BSP_PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn));
-         addr = BSP_PCIE1_D_CFG1 + where;
-
-         if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val))
-            return PCIBIOS_DEVICE_NOT_FOUND;
-      }
-      else
-         return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-
-   return PCIBIOS_SUCCESSFUL;
-}
-#endif
-
-struct pci_ops rtl8196b_pci0_ops = {
-   .read = rtl8196b_pcibios0_read,
-   .write = rtl8196b_pcibios0_write
-};
-
-#ifdef PIN_208
-struct pci_ops rtl8196b_pci1_ops = {
-   .read = rtl8196b_pcibios1_read,
-   .write = rtl8196b_pcibios1_write
-};
-#endif
-
-static struct pci_controller rtl8196b_pci0_controller = {
-   .pci_ops        = &rtl8196b_pci0_ops,
-   .mem_resource   = &rtl8196b_pci0_mem_resource,
-   .io_resource    = &rtl8196b_pci0_io_resource,
-};
-
-#ifdef PIN_208
-static struct pci_controller rtl8196b_pci1_controller = {
-   .pci_ops        = &rtl8196b_pci1_ops,
-   .mem_resource   = &rtl8196b_pci1_mem_resource,
-   .io_resource    = &rtl8196b_pci1_io_resource,
-};
-#endif
-
-int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-{
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   printk("**Slot: %d\n", slot);
-   printk("**Pin: %d\n", pin);
-   printk("**Dev->BUS->Number: %d\n", dev->bus->number);
-   #endif
-
-   if (dev->bus->number < pci1_bus_number)
-      return BSP_PCIE_IRQ;
-   else
-      return BSP_PCIE2_IRQ;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-   #if DEBUG_PRINTK
-   printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__);
-   #endif
-
-   return 0;
-}
-
-static __init int bsp_pcie_init(void)
-{
-   //rtl8196b_pci_reset();
-   PCIE_reset_procedure(0,0,1);
-
-#if DEBUG_PRINTK
-   printk("<<<<<Register 1st PCI Controller>>>>>\n");
-#ifdef PIN_208
-   printk("<<<<<Register 2nd PCI Controller>>>>>\n");
-#endif
-#endif
-
-   register_pci_controller(&rtl8196b_pci0_controller);
-#ifdef PIN_208
-   register_pci_controller(&rtl8196b_pci1_controller);
-#endif
-   return 0;
-}
-
-arch_initcall(bsp_pcie_init);
diff --git a/target/linux/realtek/files/arch/rlx/bsp/prom.c b/target/linux/realtek/files/arch/rlx/bsp/prom.c
deleted file mode 100644
index 5e4458c1b..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/prom.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2006, Realtek Semiconductor Corp.
- *
- * arch/rlx/rlxocp/prom.c
- *   Early initialization code for the RLX OCP Platform
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Nov. 7, 2006
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-#include <asm/cpu.h>
-
-#include <asm/rlxbsp.h>
-
-#include "bspcpu.h"
-
-#if defined(CONFIG_RTL_819X)
-#include "bspchip.h"
-#endif
-
-extern char arcs_cmdline[];
-
-#ifdef CONFIG_EARLY_PRINTK
-static int promcons_output __initdata = 0;
-                                                                                                    
-void unregister_prom_console(void)
-{
-    if (promcons_output) {
-        promcons_output = 0;
-    }
-}
-                                                                                                    
-void disable_early_printk(void)
-    __attribute__ ((alias("unregister_prom_console")));
-#endif
-                                                                                                    
-
-const char *get_system_type(void)
-{
-    return "RTL8196C";
-}
-
-/* Do basic initialization */
-void __init bsp_init(void)
-{
-    u_long mem_size;
-
-    /*user CMLLINE created by menuconfig*/
-    /*
-    arcs_cmdline[0] = '\0';
-    strcpy(arcs_cmdline, "console=ttyS0,38400");
-    */
-
-#if defined(CONFIG_RTL_819X)
-       	/*now: alway believe DRAM configuration register*/
-        {
-                unsigned int DCRvalue = 0;
-                unsigned int bus_width = 0, chip_sel = 0, row_cnt = 0, col_cnt = 0,bank_cnt = 0;
- 
-                DCRvalue = ( (*(volatile unsigned int *)BSP_MC_MTCR0));
- 
-                /*bit 19,0:2 bank; 1: 4 bank*/
-                switch(DCRvalue & 0x080000)
-                {
-                        case 0x0:
-                                bank_cnt = 2;
-                                break;
-                        case 0x080000:
-                                bank_cnt = 4;
-                                break;
-                        default:
-                                bank_cnt = 0;
-                                break;
-                }
- 
-                /*bit 22~24: colomn count*/
-                switch(DCRvalue & 0x01C00000)
-                {
-                        case 0x00000000:
-                                col_cnt = 256;
-                                break;
-                        case 0x00400000:
-                                col_cnt = 512;
-                                break;
-                        case 0x00800000:
-                                col_cnt = 1024;
-                                break;
-                        case 0x00C00000:
-                                col_cnt = 2048;
-                                break;
-                        case 0x01000000:
-                                col_cnt = 4096;
-                                break;
-                        default:
-                                printk("unknow colomn count(0x%x)\n",DCRvalue & 0x01C00000);
-                                break;
-                }
- 
-                /*bit 25~26: row count*/
-                switch(DCRvalue & 0x06000000)
-                {
-                        case 0x00000000:
-                                row_cnt = 2048;
-                                break;
-                        case 0x02000000:
-                                row_cnt = 4096;
-                                break;
-                        case 0x04000000:
-                                row_cnt = 8192;
-                                break;
-                        case 0x06000000:
-                                row_cnt = 16384;
-                                break;
-                }
- 
-                /*bit 27: chip select*/
-                switch(DCRvalue & 0x08000000)
-                {
-                        case 0x0:
-                                chip_sel = 1;
-                                break;
-                        case 0x08000000:
-                                chip_sel = 2;
-                                break;
-                }
- 
-                /*bit 28~29: bus width*/
-                switch(DCRvalue & 0x30000000)
-                {
-                        case 0x0:
-                                bus_width = 8;
-                                break;
-                        case 0x10000000:
-                                bus_width = 16;
-                                break;
-                        case 0x20000000:
-                                bus_width = 32;
-                                break;
-                        default:
-                                printk("bus width is reseved!\n");
-                                break;
-                }
- 
-                /*total size(Byte)*/
-                mem_size = (row_cnt * col_cnt *bank_cnt) * (bus_width >> 3) * chip_sel;     
- 
-        }
-#else
-    mem_size = cpu_mem_size;
-#endif
-    add_memory_region(0, mem_size, BOOT_MEM_RAM);
-}
-
-void __init bsp_free_prom_memory(void)
-{
-  return;
-}
diff --git a/target/linux/realtek/files/arch/rlx/bsp/serial.c b/target/linux/realtek/files/arch/rlx/bsp/serial.c
deleted file mode 100644
index 134a99810..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/serial.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 2006, Realtek Semiconductor Corp.
- *
- * arch/rlx/rlxocp/serial.c
- *     RLXOCP serial port initialization
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Nov. 07, 2006
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/string.h>
-
-#include <asm/serial.h>
-
-#include "bspchip.h"
-
-void __init bsp_serial_init(void)
-{
-	struct uart_port s;
-
-	/* clear memory */
-	memset(&s, 0, sizeof(s));
-
-    /*
-     * UART0
-     */
-	s.line = 0;
-    s.type = PORT_16550A;
-    s.irq = BSP_UART0_IRQ;
-    s.iotype = UPIO_MEM;
-    s.regshift = 2;
-#if 1
-	s.uartclk = BSP_SYS_CLK_RATE;
-    s.fifosize = 16;
-	//s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY;
-	s.flags = UPF_SKIP_TEST;
-	s.mapbase = BSP_UART0_MAP_BASE;
-	//s.membase = ioremap_nocache(s.mapbase, BSP_UART0_MAPSIZE);
-	s.membase = ioremap_nocache(s.mapbase, 0x20);
-#else
-	s.uartclk = BSP_SYS_CLK_RATE - BSP_BAUDRATE * 24; //???
-    s.fifosize = 1;                           //???
-    s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_SPD_CUST;
-    s.membase = (unsigned char *)BSP_UART0_BASE;
-    s.custom_divisor = BSP_SYS_CLK_RATE / (BSP_BAUDRATE * 16) - 1;
-#endif
-
-	if (early_serial_setup(&s) != 0) {
-		panic("RTL8196C: bsp_serial_init failed!");
-	}
-}
diff --git a/target/linux/realtek/files/arch/rlx/bsp/setup.c b/target/linux/realtek/files/arch/rlx/bsp/setup.c
deleted file mode 100644
index edb6d830b..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/setup.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright 2006, Realtek Semiconductor Corp.
- *
- * arch/rlx/rlxocp/setup.c
- *   Interrupt and exception initialization for RLX OCP Platform
- *
- * Tony Wu (tonywu@realtek.com.tw)
- * Nov. 7, 2006
- */
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/netdevice.h>
-#include <linux/rtnetlink.h>
-
-#include <asm/addrspace.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-#include <asm/reboot.h>
-#include <asm/rlxbsp.h>
-
-#include <asm/rtl865x/rtl865xc_asicregs.h>
-
-#include "bspchip.h"
-
-extern int bsp_swcore_init(unsigned int version);
-
-static void prom_putchar(char c)
-{
-#define UART0_BASE		0xB8002000
-#define UART0_THR		(UART0_BASE + 0x000)
-#define UART0_FCR		(UART0_BASE + 0x008)
-#define UART0_LSR       (UART0_BASE + 0x014)
-#define TXRST			0x04
-#define CHAR_TRIGGER_14	0xC0
-#define LSR_THRE		0x20
-#define TxCHAR_AVAIL	0x00
-#define TxCHAR_EMPTY	0x20
-unsigned int busy_cnt = 0;
-
-	do
-	{
-		/* Prevent Hanging */
-		if (busy_cnt++ >= 30000)
-		{
-		 /* Reset Tx FIFO */
-		 REG8(UART0_FCR) = TXRST | CHAR_TRIGGER_14;
-		 return;
-		}
-	} while ((REG8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL);
-
-	/* Send Character */
-	REG8(UART0_THR) = c;
-}
-
-static void early_console_write(const char *s, unsigned n)
-{
-	while (n-- && *s) {
-		if (*s == '\n')
-			prom_putchar('\r');
-		prom_putchar(*s);
-		s++;
-	}
-}
-
-
-static void shutdown_netdev(void)
-{
-	struct net_device *dev;
-	
-	printk("Shutdown network interface\n");
-	read_lock(&dev_base_lock);
-
-	for_each_netdev(&init_net, dev)
-	{
-		if(dev->flags &IFF_UP) 
-		{
-			printk("%s:===>\n",dev->name);			
-			rtnl_lock();
-#if defined(CONFIG_COMPAT_NET_DEV_OPS)
-			if(dev->stop)
-				dev->stop(dev);
-#else
-			if ((dev->netdev_ops)&&(dev->netdev_ops->ndo_stop))
-				dev->netdev_ops->ndo_stop(dev);
-#endif
-			rtnl_unlock();
-		}
-      	}
-#if defined(CONFIG_RTL8192CD)
-	{
-		extern void force_stop_wlan_hw(void);
-		force_stop_wlan_hw();
-	}
-#endif
-	read_unlock(&dev_base_lock);
-}
-
-static void bsp_machine_restart(char *command)
-{
-    static void (*back_to_prom)(void) = (void (*)(void)) 0xbfc00000;
-	
-    REG32(GIMR)=0;
-	
-    local_irq_disable();
-#ifdef CONFIG_NET    
-    shutdown_netdev();
-#endif    
-    REG32(BSP_WDTCNR) = 0; //enable watch dog
-    while (1) ;
-    /* Reboot */
-    back_to_prom();
-}
-                                                                                                    
-static void bsp_machine_halt(void)
-{
-    while(1);
-}
-                                                                                                    
-static void bsp_machine_power_off(void)
-{
-    while(1);
-}
-
-/*
- * callback function
- */
-extern void _imem_dmem_init(void);
-void __init bsp_setup(void)
-{
-	int ret= -1;
-	unsigned int version = 0;
-
-    /* define io/mem region */
-    ioport_resource.start = 0x18000000; 
-    ioport_resource.end = 0x1fffffff;
-
-    iomem_resource.start = 0x18000000;
-    iomem_resource.end = 0x1fffffff;
-
-    /* set reset vectors */
-    _machine_restart = bsp_machine_restart;
-    _machine_halt = bsp_machine_halt;
-    pm_power_off = bsp_machine_power_off;
-
-	version = 15;
-    /* initialize uart */
-    bsp_serial_init();
-    _imem_dmem_init();
-
-	/* initialize switch core */
-#if defined(CONFIG_RTL_819X)
-	ret = bsp_swcore_init(version);
-	if(ret != 0)
-	{
-		bsp_machine_halt();
-	}
-#endif
-}
diff --git a/target/linux/realtek/files/arch/rlx/bsp/timer.c b/target/linux/realtek/files/arch/rlx/bsp/timer.c
deleted file mode 100644
index 48d1fa38a..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/timer.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  linux/arch/rlx/rlxocp/time.c
- *
- *  Copyright (C) 1999 Harald Koerfgen
- *  Copyright (C) 2000 Pavel Machek (pavel@suse.cz)
- *  Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Time handling functinos for Philips Nino.
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/delay.h>
-
-#include <asm/time.h>
-#include <asm/rlxbsp.h>
-
-#include  "bspchip.h"
-
-#ifdef CONFIG_RTL_TIMER_ADJUSTMENT
-#include <net/rtl/rtl_types.h>
-#include <rtl865xc_asicregs.h>
-
-void rtl865x_setupTimer1(void)
-{
-	WRITE_MEM32( BSP_TCCNR, READ_MEM32(BSP_TCCNR) & ~BSP_TC1EN );/* Disable timer1 */
-	#ifdef CONFIG_RTL8196C_REVISION_B
-	WRITE_MEM32( BSP_TC1DATA, 0xfffffff0);	
-	#else
-	WRITE_MEM32( BSP_TC1DATA, 0xffffff00);	
-	#endif
-	WRITE_MEM32( BSP_TCCNR, ( READ_MEM32(BSP_TCCNR) | BSP_TC1EN ) | BSP_TC1MODE_TIMER );/* Enable timer1 - timer mode */
-	WRITE_MEM32( BSP_TCIR, READ_MEM32(BSP_TCIR) & ~BSP_TC1IE ); /* Disable timer1 interrupt */
-}
-#endif
-
-void inline bsp_timer_ack(void)
-{
-    REG32(BSP_TCIR) |= BSP_TC0IP;
-}
-
-void __init bsp_timer_init(void)
-{
-	unsigned int sys_clock_rate;
-	
-    sys_clock_rate =  BSP_SYS_CLK_RATE;
-
-   /* Clear Timer IP status */
-   if (REG32(BSP_TCIR) & BSP_TC0IP)
-      REG32(BSP_TCIR) |= BSP_TC0IP;
-            
-    /* disable timer */
-    REG32(BSP_TCCNR) = 0; /* disable timer before setting CDBR */
-
-    /* initialize timer registers */
-	REG32(BSP_CDBR)=(BSP_DIVISOR*8) << BSP_DIVF_OFFSET;
-#ifdef CONFIG_RTL8196C_REVISION_B
-	if (REG32(REVR) == RTL8196C_REVISION_B)
-		REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*8))/HZ)) << 4;	
-	else
-#endif
-		REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*8))/HZ)) << BSP_TCD_OFFSET;
-
-	// extend timer base to 4 times
-	//REG32(BSP_CDBR)=(BSP_DIVISOR*4) << BSP_DIVF_OFFSET;
-	//REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*4))/HZ)) << BSP_TCD_OFFSET;
-#if defined(CONFIG_RTL_WTDOG)
-	REG32(BSP_WDTCNR) = 0x00600000;
-#endif
-
-    /* hook up timer interrupt handler */
-    rlx_clockevent_init(BSP_TC0_IRQ);
-    
-    /* enable timer */
-	REG32(BSP_TCCNR) = BSP_TC0EN | BSP_TC0MODE_TIMER;
-	REG32(BSP_TCIR) = BSP_TC0IE;
-#ifdef CONFIG_RTL_TIMER_ADJUSTMENT
-   	rtl865x_setupTimer1();
-#endif   
-
-}
diff --git a/target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S b/target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S
deleted file mode 100644
index 80048359f..000000000
--- a/target/linux/realtek/files/arch/rlx/bsp/vmlinux.lds.S
+++ /dev/null
@@ -1,296 +0,0 @@
-#include <asm/asm-offsets.h>
-#include <asm-generic/vmlinux.lds.h>
-
-#undef mips
-#define mips mips
-OUTPUT_ARCH(mips)
-ENTRY(kernel_entry)
-PHDRS {
-	text PT_LOAD FLAGS(7);	/* RWX */
-	note PT_NOTE FLAGS(4);	/* R__ */
-}
-jiffies = JIFFIES;
-
-SECTIONS
-{
-	. = LOADADDR;
-	/* read-only */
-	_text = .;	/* Text and read-only data */
-	.text : {
-		TEXT_TEXT
-		SCHED_TEXT
-		LOCK_TEXT
-		KPROBES_TEXT
-		*(.text.*)
-		*(.fixup)
-		*(.gnu.warning)
-/*#ifdef CONFIG_RTL8192SE*/
-#if 1
-		/* start of wlan f/w definition */
-		__fw_start = . ;
-		*(.rtl8192sfw.bin)
-		__fw_end = . ;
-
-		__AGC_TAB_start = . ;
-		*(.AGC_TAB.txt)
-		__AGC_TAB_end = . ;
-
-		__phy_reg_start = . ;
-		*(.phy_reg.txt)
-		__phy_reg_end = . ;
-
-		__phy_reg_MP_start = . ;
-		*(.phy_reg_MP.txt)
-		__phy_reg_MP_end = . ;
-
-		__MACPHY_REG_start = . ;
-		*(.MACPHY_REG.txt)
-		__MACPHY_REG_end = . ;
-
-		__radio_a_start = . ;
-		*(.radio_a.txt)
-		__radio_a_end = . ;                                                       
-
-		__radio_b_start = . ;
-		*(.radio_b.txt)
-		__radio_b_end = . ;
-
-		__PHY_REG_PG_start = .;
-		*(.PHY_REG_PG.txt)
-		__PHY_REG_PG_end = .;
-
-		__PHY_to1T2R_start = .;
-		*(.PHY_to1T2R.txt)
-		__PHY_to1T2R_end = .;
-
-		__PHY_to1T2R_b_start = .;
-		*(.PHY_to1T2R_b.txt)
-		__PHY_to1T2R_b_end = .;
-
-		__PHY_to1T1R_start = .;
-		*(.PHY_to1T1R.txt)
-		__PHY_to1T1R_end = .;
-
-		__PHY_to1T1R_b_start = .;
-		*(.PHY_to1T1R_b.txt)
-		__PHY_to1T1R_b_end = .;
-
-		__radio_a_hp_start = . ;
-		*(.radio_a_hp.txt)
-		__radio_a_hp_end = . ;
-
-		/* end of wlan f/w definition */
-#endif
-
-	} :text = 0
-	_etext = .;	/* End of text section */
-
-	/* Exception table */
-	. = ALIGN(16);
-	__ex_table : {
-		__start___ex_table = .;
-		*(__ex_table)
-		__stop___ex_table = .;
-	}
-
-	/* Exception table for data bus errors */
-	__dbe_table : {
-		__start___dbe_table = .;
-		*(__dbe_table)
-		__stop___dbe_table = .;
-	}
-
-   	. = ALIGN(16384);
-   	__iram = . ;
-   	.iram        :
-   	{
-		*(.iram-gen)		/* general usage (essential) */
-		*(.iram-fwd)            /* general packet forwarding used */
-		*(.iram-rtkwlan)	/* realtek wlan driver */
-		*(.iram-l2-fwd)         /* L2 packet forwarding */
-		*(.iram-l34-fwd)        /* L34 packet forwarding */
-		*(.iram-tx)		/* protocol stack TX */
-		*(.iram-extdev)		/* ROMEDRV extension device fwd */
-		*(.iram-crypto)		/* authetication / crypto-engine */
-		*(.iram-voip)		/* voip */
-		*(.iram)		/* other usage */
-		*(.iram.1)
-   	}
-  
-   	. = ALIGN(8192);
-   	__dram = . ;
-   	__dram_start = . ;
-   	.dram	:
-   	{
-		*(.dram-wapi)           /*wapi encryption/decryption used*/
-   		*(.dram-gen)		/* general usage (essential) */
-		*(.dram-fwd)            /* general packet forwarding used */
-   		*(.dram-l2-fwd)		/* L2 packet forwarding */
-		*(.dram-l34-fwd)        /* L34 packet forwarding */
-   		*(.dram-extdev)		/* ROMEDRV extension device fwd */
-   		*(.dram-rtkwlan)	/* realtek wlan driver */
-		*(.dram-crypto)		/* authetication / crypto-engine */
-   		*(.dram-voip)		/* voip */
-		*(.dram-tx)		/* protocol stack TX */
-		*(.dram)		/* other usage */
-		*(.dram.1)
-   	}
-   	. = ALIGN(8192);
-   	__dram_end = . ;
-
-	NOTES :text :note
-	.dummy : { *(.dummy) } :text
-
-	RODATA
-
-	/* writeable */
-	.data : {	/* Data */
-		. = . + DATAOFFSET;		/* for CONFIG_MAPPED_KERNEL */
-		/*
-		 * This ALIGN is needed as a workaround for a bug a
-		 * gcc bug upto 4.1 which limits the maximum alignment
-		 * to at most 32kB and results in the following
-		 * warning:
-		 *
-		 *  CC      arch/mips/kernel/init_task.o
-		 * arch/mips/kernel/init_task.c:30: warning: alignment
-		 * of ‘init_thread_union�is greater than maximum
-		 * object file alignment.  Using 32768
-		 */
-		. = ALIGN(_PAGE_SIZE);
-		*(.data.init_task)
-
-		DATA_DATA
-		CONSTRUCTORS
-	}
-	_gp = . + 0x8000;
-	.lit8 : {
-		*(.lit8)
-	}
-	.lit4 : {
-		*(.lit4)
-	}
-	/* We want the small data sections together, so single-instruction offsets
-	   can access them all, and initialized data all before uninitialized, so
-	   we can shorten the on-disk segment size.  */
-	.sdata : {
-		*(.sdata)
-	}
-
-	. = ALIGN(_PAGE_SIZE);
-	.data_nosave : {
-		__nosave_begin = .;
-		*(.data.nosave)
-	}
-	. = ALIGN(_PAGE_SIZE);
-	__nosave_end = .;
-
-	. = ALIGN(1 << 5);
-	.data.cacheline_aligned : {
-		*(.data.cacheline_aligned)
-	}
-	_edata =  .;			/* End of data section */
-
-	/* will be freed after init */
-	. = ALIGN(_PAGE_SIZE);		/* Init code and data */
-	__init_begin = .;
-	.init.text : {
-		_sinittext = .;
-		INIT_TEXT
-		_einittext = .;
-	}
-	.init.data : {
-		INIT_DATA
-	}
-	. = ALIGN(16);
-	.init.setup : {
-		__setup_start = .;
-		*(.init.setup)
-		__setup_end = .;
-	}
-
-	.initcall.init : {
-		__initcall_start = .;
-		INITCALLS
-		__initcall_end = .;
-	}
-
-	.con_initcall.init : {
-		__con_initcall_start = .;
-		*(.con_initcall.init)
-		__con_initcall_end = .;
-	}
-	SECURITY_INIT
-
-	/* .exit.text is discarded at runtime, not link time, to deal with
-	 * references from .rodata
-	 */
-	.exit.text : {
-		EXIT_TEXT
-	}
-	.exit.data : {
-		EXIT_DATA
-	}
-#if defined(CONFIG_BLK_DEV_INITRD)
-	. = ALIGN(_PAGE_SIZE);
-	.init.ramfs : {
-		__initramfs_start = .;
-		*(.init.ramfs)
-		__initramfs_end = .;
-	}
-#endif
-	PERCPU(_PAGE_SIZE)
-	. = ALIGN(_PAGE_SIZE);
-	__init_end = .;
-	/* freed after init ends here */
-
-	__bss_start = .;	/* BSS */
-	.sbss  : {
-		*(.sbss)
-		*(.scommon)
-	}
-	.bss : {
-		*(.bss)
-		*(COMMON)
-	}
-	__bss_stop = .;
-
-	_end = . ;
-
-	/* Sections to be discarded */
-	/DISCARD/ : {
-		*(.exitcall.exit)
-
-		/* ABI crap starts here */
-		*(.MIPS.options)
-		*(.options)
-		*(.pdr)
-		*(.reginfo)
-	}
-
-	/* These mark the ABI of the kernel for debuggers.  */
-	.mdebug.abi32 : {
-		KEEP(*(.mdebug.abi32))
-	}
-	.mdebug.abi64 : {
-		KEEP(*(.mdebug.abi64))
-	}
-
-	/* This is the MIPS specific mdebug section.  */
-	.mdebug : {
-		*(.mdebug)
-	}
-
-	STABS_DEBUG
-	DWARF_DEBUG
-
-	/* These must appear regardless of  .  */
-	.gptab.sdata : {
-		*(.gptab.data)
-		*(.gptab.sdata)
-	}
-	.gptab.sbss : {
-		*(.gptab.bss)
-		*(.gptab.sbss)
-	}
-}