diff options
| author | Roman Yeryomin <roman@advem.lv> | 2012-09-13 00:40:35 +0300 |
|---|---|---|
| committer | Roman Yeryomin <roman@advem.lv> | 2012-12-03 00:13:21 +0200 |
| commit | 5deb3317cb51ac52de922bb55f8492624018906d (patch) | |
| tree | c2fbe6346699d9bb0f2100490c3029519bb8fde8 /target/linux/realtek/files/arch/mips | |
| parent | 0239d37124f9184b478a42de8a7fa1bc85a6a6fe (diff) | |
Add realtek target files
Signed-off-by: Roman Yeryomin <roman@advem.lv>
Diffstat (limited to 'target/linux/realtek/files/arch/mips')
48 files changed, 12172 insertions, 0 deletions
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196b/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196b/platform.h new file mode 100644 index 000000000..3faab2692 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196b/platform.h @@ -0,0 +1,376 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+#define CONFIG_RTL_TIMER_ADJUSTMENT
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG16(reg) (*(volatile unsigned short *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+#define WRITE_MEM32(addr, val) (*(volatile unsigned int *) (addr)) = (val)
+#define READ_MEM32(addr) (*(volatile unsigned int *) (addr))
+#define WRITE_MEM16(addr, val) (*(volatile unsigned short *) (addr)) = (val)
+#define READ_MEM16(addr) (*(volatile unsigned short *) (addr))
+#define WRITE_MEM8(addr, val) (*(volatile unsigned char *) (addr)) = (val)
+#define READ_MEM8(addr) (*(volatile unsigned char *) (addr))
+
+#define PADDR(addr) ((addr) & 0x1FFFFFFF)
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 200
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define PCIB0TMO_IRQ 0
+#define PCIB1TMO_IRQ 1
+#define LBCTMOm0_IRQ 2
+#define LBCTMOm1_IRQ 3
+#define LBCTMOs_IRQ 4
+#define TC0_IRQ 8
+#define TC1_IRQ 9
+#define USB_IRQ 10
+#define UART0_IRQ 12
+#define UART1_IRQ 13
+#define PCI_IRQ 14
+#define SWCORE_IRQ 15
+#define GPIO_ABCD_IRQ 16
+#define GPIO_EFGH_IRQ 17
+#define HCI_IRQ 18
+#define PCM_IRQ 19
+#define CRYPTO_IRQ 20
+#define GDMA_IRQ 23
+#define PCIE2_IRQ 22
+#define PCIE_IRQ 21 // shall be 22
+
+/*
+ * Interrupt Routing Selection
+ */
+#define PTM_RS 2
+#define LBCTMOs2_RS 2
+#define LBCTMOs1_RS 2
+#define PKT_RS 2
+#define SPI_RS 2
+#define NIC100_RS 2
+#define SAR_RS 2
+#define DMT_RS 2
+#define PCIE2_RS 4
+#define PCIE_RS 5
+#define GDMA_RS 2
+#define SECURITY_RS 2
+#define PCM_RS 2
+#define NFBI_RS 2
+#define GPIO_EFGH_RS 2
+#define GPIO_ABCD_RS 2
+#define SW_RS 6
+#define PCI_RS 3
+#define UART1_RS 2
+#define UART0_RS 2
+#define USB_D_RS 2
+#define USB_H_RS 4
+#define TC1_RS 2
+#define TC0_RS 7
+#define LBCTMOm2_RS 2
+#define LBCTMOm1_RS 2
+#define SPEED_RS 2
+#define LBCTMOs0_RS 2
+#define LBCTMOm0_RS 2
+#define OCPTMO_RS 2
+#define PCIB0TO_RS 2
+#define NONE 2
+#define PCIB0TMO_RS 2
+#define PCIB1TMO_RS 2
+#define LBCTMOs_RS 2
+
+
+#define HCI_RS 2
+#define CRYPTO_RS 2
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C03FFF
+
+#define DMEM_BASE 0x00C04000
+#define DMEM_TOP 0x00C05FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x92A28000
+
+#define MC_MTCR0 0xB8001004
+ #define MC_MTCR0_VAL 0x12120000
+
+#define MC_MTCR1 0xB8001008
+ #define MC_MTCR1_VAL 0x00000FEB
+
+#define MC_PFCR 0xB8001010
+ #define MC_PFCR_VAL 0x00000101
+
+
+#define MC_BASE 0xB8001000
+#define NCR (MC_BASE + 0x100)
+#define NSR (MC_BASE + 0x104)
+#define NCAR (MC_BASE + 0x108)
+#define NADDR (MC_BASE + 0x10C)
+#define NDR (MC_BASE + 0x110)
+
+#define SFCR (MC_BASE + 0x200)
+#define SFDR (MC_BASE + 0x204)
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_MAP_BASE 0x18002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define GDMA_IE (1 << 23)
+ #define PCIE2_IE (1 << 22)
+ #define PCIE_IE (1 << 21) // shall be 22
+ #define CRYPTO_IE (1 << 20)
+ #define PCM_IE (1 << 19)
+ #define HCI_IE (1 << 18)
+ #define GPIO_EFGH_IE (1 << 17)
+ #define GPIO_ABCD_IE (1 << 16)
+ #define SW_IE (1 << 15)
+ #define PCI_IE (1 << 14)
+ #define UART1_IE (1 << 13)
+ #define UART0_IE (1 << 12)
+ #define USB_H_IE (1 << 10)
+ #define TC1_IE (1 << 9)
+ #define TC0_IE (1 << 8)
+ #define LBCTMOs_IE (1 << 4)
+ #define LBCTMOm1_IE (1 << 3)
+ #define LBCTMOm0_IE (1 << 2)
+ #define PCIB1TO_IE (1 << 1)
+ #define PCIB0TO_IE (1 << 0)
+
+#define GISR 0xB8003004
+ #define GDMA_IP (1 << 23)
+ #define PCIE2_IP (1 << 22)
+ #define PCIE_IP (1 << 21) // shall be 22
+ #define CRYPTO_IP (1 << 20)
+ #define PCM_IP (1 << 19)
+ #define HCI_IP (1 << 18)
+ #define GPIO_EFGH_IP (1 << 17)
+ #define GPIO_ABCD_IP (1 << 16)
+ #define SW_IP (1 << 15)
+ #define PCI_IP (1 << 14)
+ #define UART1_IP (1 << 13)
+ #define UART0_IP (1 << 12)
+ #define USB_H_IP (1 << 10)
+ #define TC1_IP (1 << 9)
+ #define TC0_IP (1 << 8)
+ #define LBCTMOs_IP (1 << 4)
+ #define LBCTMOm1_IP (1 << 3)
+ #define LBCTMOm0_IP (1 << 2)
+ #define PCIB1TO_IP (1 << 1)
+ #define PCIB0TO_IP (1 << 0)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((LBCTMOm2_RS << 28) | \
+ (LBCTMOm1_RS << 24) | \
+ (SPEED_RS << 20) | \
+ (LBCTMOs0_RS << 16) | \
+ (LBCTMOm0_RS << 12) | \
+ (OCPTMO_RS << 8) | \
+ (NONE << 4) | \
+ (PCIB0TO_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((SW_RS << 28) | \
+ (PCIE_RS << 24) | \
+ (UART1_RS << 20) | \
+ (UART0_RS << 16) | \
+ (USB_D_RS << 12) | \
+ (USB_H_RS << 8) | \
+ (TC1_RS << 4) | \
+ (TC0_RS << 0) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING ((GDMA_RS << 28) | \
+ (PCIE2_RS << 24) | \
+ (PCIE_RS << 20) | \
+ (SECURITY_RS << 16) | \
+ (PCM_RS << 12) | \
+ (NFBI_RS << 8) | \
+ (GPIO_EFGH_RS << 4) | \
+ (GPIO_ABCD_RS << 0) \
+ )
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING ((PTM_RS << 28) | \
+ (LBCTMOs2_RS << 24) | \
+ (LBCTMOs1_RS << 20) | \
+ (PKT_RS << 16) | \
+ (SPI_RS << 12) | \
+ (NIC100_RS << 8) | \
+ (SAR_RS << 4) | \
+ (DMT_RS << 0) \
+ )
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+/*
+ * HCI
+ */
+#define HCI_BASE 0xB8007000
+#define HCI_GCR (HCI_BASE + 0x00)
+#define HCI_TRFFDR (HCI_BASE + 0x04)
+#define HCI_TRFFAR (HCI_BASE + 0x08)
+#define HCI_FFCR_CS(i) (HCI_BASE + 0x0C + ((i) << 2))
+#define HCI_IER_CS(i) (HCI_BASE + 0x1C + ((i) << 2))
+#define HCI_LSR_CS(i) (HCI_BASE + 0x2C + ((i) << 2))
+#define HCI_CR_CS(i) (HCI_BASE + 0x3C + ((i) << 2))
+#define HCI_TR_CS(i) (HCI_BASE + 0x4C + ((i) << 2))
+/*
+ * PCIE Host Controller
+ */
+#define PCIE0_H_CFG 0xB8B00000
+#define PCIE0_H_EXT 0xB8B01000
+#define PCIE0_H_MDIO (PCIE0_H_EXT + 0x00)
+#define PCIE0_H_INTSTR (PCIE0_H_EXT + 0x04)
+#define PCIE0_H_PWRCR (PCIE0_H_EXT + 0x08)
+#define PCIE0_H_IPCFG (PCIE0_H_EXT + 0x0C)
+#define PCIE0_H_MISC (PCIE0_H_EXT + 0x10)
+#define PCIE0_D_CFG0 0xB8B10000
+#define PCIE0_D_CFG1 0xB8B11000
+#define PCIE0_D_MSG 0xB8B12000
+
+#define PCIE1_H_CFG 0xB8B20000
+#define PCIE1_H_EXT 0xB8B21000
+#define PCIE1_H_MDIO (PCIE1_H_EXT + 0x00)
+#define PCIE1_H_INTSTR (PCIE1_H_EXT + 0x04)
+#define PCIE1_H_PWRCR (PCIE1_H_EXT + 0x08)
+#define PCIE1_H_IPCFG (PCIE1_H_EXT + 0x0C)
+#define PCIE1_H_MISC (PCIE1_H_EXT + 0x10)
+#define PCIE1_D_CFG0 0xB8B30000
+#define PCIE1_D_CFG1 0xB8B31000
+#define PCIE1_D_MSG 0xB8B32000
+
+#define PCIE0_D_IO 0xB8C00000
+#define PCIE1_D_IO 0xB8E00000
+#define PCIE0_D_MEM 0xB9000000
+#define PCIE1_D_MEM 0xBA000000
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196b/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196b/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196b/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196c/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196c/platform.h new file mode 100644 index 000000000..7bc50c98c --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196c/platform.h @@ -0,0 +1,409 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+#define CONFIG_RTL_TIMER_ADJUSTMENT
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG16(reg) (*(volatile unsigned short *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+#define WRITE_MEM32(addr, val) (*(volatile unsigned int *) (addr)) = (val)
+#define READ_MEM32(addr) (*(volatile unsigned int *) (addr))
+#define WRITE_MEM16(addr, val) (*(volatile unsigned short *) (addr)) = (val)
+#define READ_MEM16(addr) (*(volatile unsigned short *) (addr))
+#define WRITE_MEM8(addr, val) (*(volatile unsigned char *) (addr)) = (val)
+#define READ_MEM8(addr) (*(volatile unsigned char *) (addr))
+
+#define PADDR(addr) ((addr) & 0x1FFFFFFF)
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 200
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#if 0
+#define PCIB0TMO_IRQ 0
+#define PCIB1TMO_IRQ 1
+#define LBCTMOm0_IRQ 2
+#define LBCTMOm1_IRQ 3
+#define LBCTMOs_IRQ 4
+#define TC0_IRQ 8
+#define TC1_IRQ 9
+#define USB_IRQ 10
+#define UART0_IRQ 12
+#define UART1_IRQ 13
+#define PCI_IRQ 14
+#define SWCORE_IRQ 15
+#define GPIO_ABCD_IRQ 16
+#define GPIO_EFGH_IRQ 17
+#define HCI_IRQ 18
+#define PCM_IRQ 19
+#define CRYPTO_IRQ 20
+#define GDMA_IRQ 23
+#define PCIE2_IRQ 22
+#define PCIE_IRQ 21 // shall be 22
+#endif
+#define UART0_IRQ 7
+#define SWCORE_IRQ 8
+#define GPIO_ABCD_IRQ 9
+#define PCIE_IRQ 10
+#define GDMA_IRQ 11
+
+#define TC0_IRQ 14
+#define TC1_IRQ 15
+#define PCI_IRQ 16
+#define USB_IRQ 17
+/*
+ * Interrupt Routing Selection
+ */
+#define PTM_RS 2
+#define LBCTMOs2_RS 2
+#define LBCTMOs1_RS 2
+#define PKT_RS 2
+#define SPI_RS 2
+#define NIC100_RS 2
+#define SAR_RS 2
+#define DMT_RS 2
+#define PCIE2_RS 4
+#define PCIE_RS 5
+#define GDMA_RS 2
+#define SECURITY_RS 2
+#define PCM_RS 2
+#define NFBI_RS 2
+#define GPIO_EFGH_RS 2
+#define GPIO_ABCD_RS 2
+#define SW_RS 6
+#define PCI_RS 3
+#define UART1_RS 2
+#define UART0_RS 2
+#define USB_D_RS 2
+#define USB_H_RS 4
+#define TC1_RS 2
+#define TC0_RS 7
+#define LBCTMOm2_RS 2
+#define LBCTMOm1_RS 2
+#define SPEED_RS 2
+#define LBCTMOs0_RS 2
+#define LBCTMOm0_RS 2
+#define OCPTMO_RS 2
+#define PCIB0TO_RS 2
+#define NONE 2
+#define PCIB0TMO_RS 2
+#define PCIB1TMO_RS 2
+#define LBCTMOs_RS 2
+
+
+#define HCI_RS 2
+#define CRYPTO_RS 2
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C03FFF
+
+#define DMEM_BASE 0x00C04000
+#define DMEM_TOP 0x00C05FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x92A28000
+
+#define MC_MTCR0 0xB8001004
+ #define MC_MTCR0_VAL 0x12120000
+
+#define MC_MTCR1 0xB8001008
+ #define MC_MTCR1_VAL 0x00000FEB
+
+#define MC_PFCR 0xB8001010
+ #define MC_PFCR_VAL 0x00000101
+
+
+#define MC_BASE 0xB8001000
+#define NCR (MC_BASE + 0x100)
+#define NSR (MC_BASE + 0x104)
+#define NCAR (MC_BASE + 0x108)
+#define NADDR (MC_BASE + 0x10C)
+#define NDR (MC_BASE + 0x110)
+
+#define SFCR (MC_BASE + 0x200)
+#define SFDR (MC_BASE + 0x204)
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_MAP_BASE 0x18002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define GDMA_IE (1 << 23)
+ #define PCIE2_IE (1 << 22)
+ #define PCIE_IE (1 << 10) // shall be 22
+ #define CRYPTO_IE (1 << 20)
+ #define PCM_IE (1 << 19)
+ #define NFBI_IE (1 << 18)
+ #define GPIO_EFGH_IE (1 << 17)
+ #define GPIO_ABCD_IE (1 << 9)
+ #define SW_IE (1 << 8)
+ #define PCI_IE (1 << 10)
+ #define UART1_IE (1 << 13)
+ #define UART0_IE (1 << 7)
+ #define USB_H_IE (1 << 10)
+ #define TC1_IE (1 << 15)
+ #define TC0_IE (1 << 14)
+ #define LBCTMOs_IE (1 << 3)
+ #define LBCTMOm1_IE (1 << 3)
+ #define LBCTMOm0_IE (1 << 2)
+ #define PCIB1TO_IE (1 << 1)
+ #define PCIB0TO_IE (1 << 0)
+
+#define GISR 0xB8003004
+#if 0
+ #define GDMA_IP (1 << 23)
+ #define PCIE2_IP (1 << 22)
+ #define PCIE_IP (1 << 21) // shall be 22
+ #define CRYPTO_IP (1 << 20)
+ #define PCM_IP (1 << 19)
+ #define HCI_IP (1 << 18)
+ #define GPIO_EFGH_IP (1 << 17)
+ #define GPIO_ABCD_IP (1 << 16)
+ #define SW_IP (1 << 15)
+ #define PCI_IP (1 << 14)
+ #define UART1_IP (1 << 13)
+ #define UART0_IP (1 << 12)
+ #define USB_H_IP (1 << 10)
+ #define TC1_IP (1 << 9)
+ #define TC0_IP (1 << 8)
+ #define LBCTMOs_IP (1 << 4)
+ #define LBCTMOm1_IP (1 << 3)
+ #define LBCTMOm0_IP (1 << 2)
+ #define PCIB1TO_IP (1 << 1)
+ #define PCIB0TO_IP (1 << 0)
+#endif
+ #define GDMA_IP (1 << 23)
+ #define PCIE2_IP (1 << 22)
+ #define PCIE_IP (1 << 10)
+ #define CRYPTO_IP (1 << 20)
+ #define PCM_IP (1 << 19)
+ #define NFBI_IP (1 << 18)
+ #define EFGH_IP (1 << 17)
+ #define GPIO_ABCD_IP (1 << 9)
+ #define SW_IP (1 << 8)
+ #define PCI_IP (1 << 10)
+ #define UART1_IP (1 << 13)
+ #define UART0_IP (1 << 7)
+ #define USB_H_IP (1 << 10)
+ #define TC1_IP (1 << 15)
+ #define TC0_IP (1 << 14)
+ #define LBCTMOs_IP (1 << 3)
+ #define LBCTMOm1_IP (1 << 3)
+ #define LBCTMOm0_IP (1 << 2)
+ #define PCIB1TO_IP (1 << 1)
+ #define PCIB0TO_IP (1 << 0)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((UART0_RS << 28) | \
+ (LBCTMOm1_RS << 24) | \
+ (SPEED_RS << 20) | \
+ (LBCTMOs0_RS << 16) | \
+ (LBCTMOm0_RS << 12) | \
+ (OCPTMO_RS << 8) | \
+ (NONE << 4) | \
+ (PCIB0TO_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((SW_RS << 0) | \
+ (TC0_RS << 24) | \
+ (UART1_RS << 20) | \
+ (OCPTMO_RS << 16) | \
+ (GDMA_RS << 12) | \
+ (GPIO_ABCD_RS << 4) | \
+ (TC1_RS << 28) | \
+ (PCIE_RS << 8) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING ((GDMA_RS << 28) | \
+ (PCIE2_RS << 24) | \
+ (PCIE_RS << 20) | \
+ (SECURITY_RS << 16) | \
+ (PCM_RS << 12) | \
+ (NFBI_RS << 8) | \
+ (GPIO_EFGH_RS << 4) | \
+ (GPIO_ABCD_RS << 0) \
+ )
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING ((PTM_RS << 28) | \
+ (LBCTMOs2_RS << 24) | \
+ (LBCTMOs1_RS << 20) | \
+ (PKT_RS << 16) | \
+ (SPI_RS << 12) | \
+ (NIC100_RS << 8) | \
+ (SAR_RS << 4) | \
+ (DMT_RS << 0) \
+ )
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+/*
+ * HCI
+ */
+#define HCI_BASE 0xB8007000
+#define HCI_GCR (HCI_BASE + 0x00)
+#define HCI_TRFFDR (HCI_BASE + 0x04)
+#define HCI_TRFFAR (HCI_BASE + 0x08)
+#define HCI_FFCR_CS(i) (HCI_BASE + 0x0C + ((i) << 2))
+#define HCI_IER_CS(i) (HCI_BASE + 0x1C + ((i) << 2))
+#define HCI_LSR_CS(i) (HCI_BASE + 0x2C + ((i) << 2))
+#define HCI_CR_CS(i) (HCI_BASE + 0x3C + ((i) << 2))
+#define HCI_TR_CS(i) (HCI_BASE + 0x4C + ((i) << 2))
+/*
+ * PCIE Host Controller
+ */
+#define PCIE0_H_CFG 0xB8B00000
+#define PCIE0_H_EXT 0xB8B01000
+#define PCIE0_H_MDIO (PCIE0_H_EXT + 0x00)
+#define PCIE0_H_INTSTR (PCIE0_H_EXT + 0x04)
+#define PCIE0_H_PWRCR (PCIE0_H_EXT + 0x08)
+#define PCIE0_H_IPCFG (PCIE0_H_EXT + 0x0C)
+#define PCIE0_H_MISC (PCIE0_H_EXT + 0x10)
+#define PCIE0_D_CFG0 0xB8B10000
+#define PCIE0_D_CFG1 0xB8B11000
+#define PCIE0_D_MSG 0xB8B12000
+
+#define PCIE1_H_CFG 0xB8B20000
+#define PCIE1_H_EXT 0xB8B21000
+#define PCIE1_H_MDIO (PCIE1_H_EXT + 0x00)
+#define PCIE1_H_INTSTR (PCIE1_H_EXT + 0x04)
+#define PCIE1_H_PWRCR (PCIE1_H_EXT + 0x08)
+#define PCIE1_H_IPCFG (PCIE1_H_EXT + 0x0C)
+#define PCIE1_H_MISC (PCIE1_H_EXT + 0x10)
+#define PCIE1_D_CFG0 0xB8B30000
+#define PCIE1_D_CFG1 0xB8B31000
+#define PCIE1_D_MSG 0xB8B32000
+
+#define PCIE0_D_IO 0xB8C00000
+#define PCIE1_D_IO 0xB8E00000
+#define PCIE0_D_MEM 0xB9000000
+#define PCIE1_D_MEM 0xBA000000
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196c/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196c/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8196c/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/hsModel.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/hsModel.h new file mode 100644 index 000000000..65879a4c9 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/hsModel.h @@ -0,0 +1,288 @@ +#ifndef _HS_MODEL_H_
+#define _HS_MODEL_H_
+
+#include "rtl_types.h"
+/* HSB (Header Stamp Before):
+ * Software-friendly structure definition */
+typedef struct hsb_param_s
+{
+ uint32 cfi:1; /* CFI */
+ uint32 patternMatch:2; /* MAC Ingress pattern match key. */
+ uint32 flowLabel:20; /* IPv6 Flow Lable */
+ uint32 dstPort:16; /* TCP/UDP Destination Port */
+ uint32 srcPort:16; /* TCP/UDP Source Port */
+ uint32 tcpFlags:8; /* TCP Flags */
+ uint32 ipProto:8; /* IP Protocol */
+ uint32 svid:12; /* SVID */
+ uint32 spri:3; /* S Priority */
+ uint32 rxDrop:1; /* ??? */
+ uint32 cpuTagif:1; /* If CPU tagged */
+ uint32 cpuIntPri:3; /* The Internal Priority in CPU tag, used for HSA */
+ uint32 cpuPortMask:28; /* The Port mask in CPU tag, used for HSA */
+ uint32 ethType:16; /* EtherType or Length */
+ uint32 ipv6MLD:1; /* IPv6 MLD control packet */
+ uint32 cpri:3; /* C Priority */
+ uint32 cvid:12; /* CVID */
+ uint32 dip:32; /* Destination IP Address */
+ uint32 sip:32; /* Source IP Address */
+ uint8 dmac[6]; /* Destination MAC */
+ uint8 smac[6]; /* Source MAC */
+ uint32 tos:8; /* TOS */
+ uint32 cpuasp:1; /* CPU Tag Assigns Internal Priority */
+ uint32 cpuasdpm:1; /* CPU Tag Assigns Destination Port Mask */
+ uint32 cpuaspRmk:1; /* CPU Tag Allows MAC Tx Remarking */
+ uint32 ipv6:1; /* IPv6 packet (ver=6) */
+ uint32 ipv4:1; /* IPv4 packet (ver=4) and length >= 20 bytes */
+ uint32 pppoe:1; /* PPPoE packet */
+ uint32 stagif:1; /* If SVID Tagged */
+ uint32 ctagif:1; /* If CVID Tagged (ethertype==0x8100) */
+ uint32 frameType:2; /* 0:Ethrnet;1:RFC1042;2-LLC_Other ??? */
+ uint32 pktLen:14; /* Packet Length (included CRC) */
+ uint32 l4csok:1; /* L4 Checksum OK */
+ uint32 l3csok:1; /* L3 Checksum OK */
+ uint32 endPage:11; /* the last page address of packet */
+ uint32 startPage:11; /* the first page address of packet */
+ uint32 startBank:3; /* the first bank of packet */
+ uint32 spa:5; /* Source Port Address (physical) */
+}hsb_param_t;
+
+/* HSA (Header Stamp After):
+ * Software-friendly structure definition */
+typedef struct hsa_param_s
+{
+ uint32 newsvid:12; /* New SVID */
+ uint32 newcvid:12; /* New CVID*/
+ uint32 cpuTagif:1; /* If CPU tagged */
+ uint32 dpCnt:5; /* Destination Port Count */
+ uint32 rvid:12; /* Relay VID */
+ uint32 reason:16; /* CPU reason */
+ uint32 intPri:3; /* Internal Priority */
+ uint32 dpMask:29; /* Destination Port Mask */
+ uint32 mir1dpa:5; /* Physical Port Address of the egress mirrored port 1 (30-ingress matched, 31-not hit) */
+ uint32 mir0dpa:5; /* Physical Port Address of the egress mirrored port 0 (30-ingress matched, 31-not hit) */
+ uint32 cpuaspRmk:1; /* CPU Tag Allows MAC Tx Remarking */
+ uint32 ipv6:1; /* IPv6 packet (ver=6) */
+ uint32 ipv4:1; /* IPv4 packet (ver=4)*/
+ uint32 pppoe:1; /* PPPoE packet */
+ uint32 stagif:1; /* If SVID Tagged */
+ uint32 ctagif:1; /* If CVID Tagged */
+ uint32 frameType:2; /* 0:Ethrnet;1:RFC1042;2-LLC_Other ??? */
+ uint32 pktLen:14; /* Packet Length (included CRC) */
+ uint32 l4csok:1; /* L4 Checksum OK */
+ uint32 l3csok:1; /* L3 Checksum OK */
+ uint32 endPage:11; /* the last page address of packet */
+ uint32 startPage:11; /* the first page address of packet */
+ uint32 startBank:3; /* the first bank of packet */
+ uint32 spa:5; /* Source Port Address (physical) */
+}hsa_param_t;
+
+
+/* RAW HSB: Raw structure to access ASIC.
+ * The structure is directly mapped to ASIC, however, it is not friendly for software. */
+typedef struct hsb_table_s
+{
+#ifdef _BIG_ENDIAN
+ uint32 sel_hsb:1; /* W0[31] */
+ uint32 valid_hsb:1; /* W0[30] */
+ uint32 reserved:7; /* W0[29:23] */
+ uint32 cfi:1; /* W0[22] */
+ uint32 patternmatch:2; /* W0[21:20] */
+ uint32 flowlabel:20; /* W0[19:0] */
+#else
+ uint32 flowlabel:20; /* W0[19:0] */
+ uint32 patternmatch:2; /* W0[21:20] */
+ uint32 cfi:1; /* W0[22] */
+ uint32 resevered:7; /* W0[29:23] */
+ uint32 valid_hsb:1; /* W0[30] */
+ uint32 sel_hsb:1; /* W0[31] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 dstport:16; /* W1[31:16] */
+ uint32 srcport:16; /* W1[15:0] */
+#else
+ uint32 srcport:16; /* W1[15:0] */
+ uint32 dstport:16; /* W1[31:16] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 tcpflags:8; /* W2[31:24] */
+ uint32 ipproto:8; /* W2[23:16] */
+ uint32 svid:12; /* W2[15:4] */
+ uint32 spri:3; /* W2[3:1] */
+ uint32 rxdrop:1; /* W2[0] */
+#else
+ uint32 rxdrop:1; /* W2[0] */
+ uint32 spri:3; /* W2[3:1] */
+ uint32 svid:12; /* W2[15:4] */
+ uint32 ipproto:8; /* W2[23:16] */
+ uint32 tcpflags:8; /* W2[31:24] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 cputagif:1; /* W3[31] */
+ uint32 cpuintpri:3; /* W3[30:28] */
+ uint32 cpuportmask:28; /* W3[27:0] */
+#else
+ uint32 cpuportmask:28; /* W3[27:0] */
+ uint32 cpuintpri:3; /* W3[30:28] */
+ uint32 cputagif:1; /* W3[31] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 ethertype:16; /* W4[31:16] */
+ uint32 ipv6mld:1; /* W4[15] */
+ uint32 cpri:3; /* W4[14:12] */
+ uint32 cvid:12; /* W4[11:0] */
+#else
+ uint32 cvid:12; /* W4[11:0] */
+ uint32 cpri:3; /* W4[14:12] */
+ uint32 ipv6mld:1; /* W4[15] */
+ uint32 ethertype:16; /* W4[31:16] */
+#endif
+
+ uint32 dip; /* W5[31:0] */
+ uint32 sip; /* W6[31:0] */
+ uint32 dmac47_16; /* W7[31:0] */
+
+#ifdef _BIG_ENDIAN
+ uint32 dmac15_0:16; /* W8[31:16] */
+ uint32 smac47_32:16; /* W8[15:0] */
+#else
+ uint32 smac47_32:16; /* W8[15:0] */
+ uint32 dmac15_0:16; /* W8[31:16] */
+#endif
+
+ uint32 smac31_0; /* W9[31:0] */
+
+#ifdef _BIG_ENDIAN
+ uint32 tos:8; /* W10[31:24] */
+ uint32 cpuasp:1; /* W10[23] */
+ uint32 cpuasdpm:1; /* W10[22] */
+ uint32 cpuasprmk:1; /* W10[21] */
+ uint32 ipv6:1; /* W10[20] */
+ uint32 ipv4:1; /* W10[19] */
+ uint32 pppoe:1; /* W10[18] */
+ uint32 stagif:1; /* W10[17] */
+ uint32 ctagif:1; /* W10[16] */
+ uint32 frametype:2; /* W10[15:14] */
+ uint32 pktlen:14; /* W10[13:0] */
+#else
+ uint32 pktlen:14; /* W10[13:0] */
+ uint32 frametype:2; /* W10[15:14] */
+ uint32 ctagif:1; /* W10[16] */
+ uint32 stagif:1; /* W10[17] */
+ uint32 pppoe:1; /* W10[18] */
+ uint32 ipv4:1; /* W10[19] */
+ uint32 ipv6:1; /* W10[20] */
+ uint32 cpuasprmk:1; /* W10[21] */
+ uint32 cpuasdpm:1; /* W10[22] */
+ uint32 cpuasp:1; /* W10[23] */
+ uint32 tos:8; /* W10[31:24] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 l4csok:1; /* W11[31] */
+ uint32 l3csok:1; /* W11[30] */
+ uint32 endpage:11; /* W11[29:19] */
+ uint32 startpage:11; /* W11[18:8] */
+ uint32 startbank:3; /* W11[7:5] */
+ uint32 spa:5; /* W11[4:0] */
+#else
+ uint32 spa:5; /* W11[4:0] */
+ uint32 startbank:3; /* W11[7:5] */
+ uint32 startpage:11; /* W11[18:8] */
+ uint32 endpage:11; /* W11[29:19] */
+ uint32 l3csok:1; /* W11[30] */
+ uint32 l4csok:1; /* W11[31] */
+#endif
+} hsb_table_t;
+
+/* RAW HSA: Raw structure to access ASIC.
+ * The structure is directly mapped to ASIC, however, it is not friendly for software. */
+typedef struct hsa_table_s
+{
+#ifdef _BIG_ENDIAN
+ uint32 hsa_busy:1; /* W0[31] */
+ uint32 reserved:5; /* W0[30:26] */
+ uint32 newsvid:12; /* W0[25:14] */
+ uint32 newcvid:12; /* W0[13:2] */
+ uint32 cputagif:1; /* W0[1] */
+ uint32 dpcnt4_4:1; /* W0[0] */
+#else
+ uint32 dpcnt4_4:1; /* W0[0] */
+ uint32 cputagif:1; /* W0[1] */
+ uint32 newcvid:12; /* W0[13:2] */
+ uint32 newsvid:12; /* W0[25:14] */
+ uint32 reserved:5; /* W0[30:26] */
+ uint32 hsa_busy:1; /* W0[31] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 dpcnt3_0:4; /* W1[31:28] */
+ uint32 rvid:12; /* W1[27:16] */
+ uint32 reason:16; /* W1[15:0] */
+#else
+ uint32 reason:16; /* W1[15:0] */
+ uint32 rvid:12; /* W1[27:16] */
+ uint32 dpcnt3_0:4; /* W1[31:28] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 intpri:3; /* W2[31:29] */
+ uint32 dpmask:29; /* W2[28:0] */
+#else
+ uint32 dpmask:29; /* W2[28:0] */
+ uint32 intpri:3; /* W2[31:29] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 mir1dpa:5; /* W3[31:27] */
+ uint32 mir0dpa:5; /* W3[26:22] */
+ uint32 cpuasdprmk:1; /* W3[21] */
+ uint32 ipv6:1; /* W3[20] */
+ uint32 ipv4:1; /* W3[19] */
+ uint32 pppoe:1; /* W3[18] */
+ uint32 stagif:1; /* W3[17] */
+ uint32 ctagif:1; /* W3[16] */
+ uint32 frametype:2; /* W3[15:14] */
+ uint32 pktlen:14; /* W3[13:0] */
+#else
+ uint32 pktlen:14; /* W3[13:0] */
+ uint32 frametype:2; /* W3[15:14] */
+ uint32 ctagif:1; /* W3[16] */
+ uint32 stagif:1; /* W3[17] */
+ uint32 pppoe:1; /* W3[18] */
+ uint32 ipv4:1; /* W3[19] */
+ uint32 ipv6:1; /* W3[20] */
+ uint32 cpuasdprmk:1; /* W3[21] */
+ uint32 mir0dpa:5; /* W3[26:22] */
+ uint32 mir1dpa:5; /* W3[31:27] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 l4csok:1; /* W4[31] */
+ uint32 l3csok:1; /* W4[30] */
+ uint32 endpage:11; /* W4[29:19] */
+ uint32 startpage:11; /* W4[18:8] */
+ uint32 startbank:3; /* W4[7:5] */
+ uint32 spa:5; /* W4[4:0] */
+#else
+ uint32 spa:5; /* W4[4:0] */
+ uint32 startbank:3; /* W4[7:5] */
+ uint32 startpage:11; /* W4[18:8] */
+ uint32 endpage:11; /* W4[29:19] */
+ uint32 l3csok:1; /* W4[30] */
+ uint32 l4csok:1; /* W4[31] */
+#endif
+} hsa_table_t;
+
+
+
+extern int32 modelGetHsb(hsb_param_t* hsb);
+extern int32 modelSetHsb(hsb_param_t* hsb);
+extern int32 modelGetHsa(hsa_param_t* hsa);
+extern int32 modelSetHsa(hsa_param_t* hsa);
+
+#endif/*_HS_MODEL_H_*/
+
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/platform.h new file mode 100644 index 000000000..8d66ab514 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/platform.h @@ -0,0 +1,229 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 20
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define UART0_IRQ 31
+#define UART1_IRQ 30
+#define TC0_IRQ 29
+#define TC1_IRQ 28
+#define OCPTO_IRQ 27
+#define HLXTO_IRQ 26
+#define SLXTO_IRQ 25
+#define NIC_IRQ 24
+#define GPIO_ABCD_IRQ 23
+#define GPIO_EFGH_IRQ 22
+#define RTC_IRQ 21
+
+/*
+ * Interrupt Routing Selection
+ */
+#define UART0_RS 2
+#define UART1_RS 1
+#define TC0_RS 5
+#define TC1_RS 1
+#define OCPTO_RS 1
+#define HLXTO_RS 1
+#define SLXTO_RS 1
+#define NIC_RS 4
+#define GPIO_ABCD_RS 4
+#define GPIO_EFGH_RS 4
+#define RTC_RS 4
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x00000000
+
+#define MC_DCR 0xB8001004
+ #define MC_DCR0_VAL 0x54480000
+
+#define MC_DTCR 0xB8001008
+ #define MC_DTCR_VAL 0xFFFF05C0
+
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define UART0_IE (1 << 31)
+ #define UART1_IE (1 << 30)
+ #define TC0_IE (1 << 29)
+ #define TC1_IE (1 << 28)
+ #define OCPTO_IE (1 << 27)
+ #define HLXTO_IE (1 << 26)
+ #define SLXTO_IE (1 << 25)
+ #define NIC_IE (1 << 24)
+ #define GPIO_ABCD_IE (1 << 23)
+ #define GPIO_EFGH_IE (1 << 22)
+ #define RTC_IE (1 << 21)
+
+#define GISR 0xB8003004
+ #define UART0_IP (1 << 31)
+ #define UART1_IP (1 << 30)
+ #define TC0_IP (1 << 29)
+ #define TC1_IP (1 << 28)
+ #define OCPTO_IP (1 << 27)
+ #define HLXTO_IP (1 << 26)
+ #define SLXTO_IP (1 << 25)
+ #define NIC_IP (1 << 24)
+ #define GPIO_ABCD_IP (1 << 23)
+ #define GPIO_EFGH_IP (1 << 22)
+ #define RTC_IP (1 << 21)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((UART0_RS << 28) | \
+ (UART1_RS << 24) | \
+ (TC0_RS << 20) | \
+ (TC1_RS << 16) | \
+ (OCPTO_RS << 12) | \
+ (HLXTO_RS << 8) | \
+ (SLXTO_RS << 4) | \
+ (NIC_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((GPIO_ABCD_RS << 28) | \
+ (GPIO_EFGH_RS << 24) | \
+ (RTC_RS << 20) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING 0
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING 0
+
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8389/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8652/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8652/platform.h new file mode 100644 index 000000000..2a7d38374 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8652/platform.h @@ -0,0 +1,298 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 200
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define PCIB0TMO_IRQ 0
+#define PCIB1TMO_IRQ 1
+#define LBCTMOm0_IRQ 2
+#define LBCTMOm1_IRQ 3
+#define LBCTMOs_IRQ 4
+#define TC0_IRQ 8
+#define TC1_IRQ 9
+#define USB_IRQ 10
+#define UART0_IRQ 12
+#define UART1_IRQ 13
+#define PCI_IRQ 14
+#define SWCORE_IRQ 15
+#define GPIO_ABCD_IRQ 16
+#define GPIO_EFGH_IRQ 17
+#define HCI_IRQ 18
+#define PCM_IRQ 19
+#define CRYPTO_IRQ 20
+#define GDMA_IRQ 21
+
+/*
+ * Interrupt Routing Selection
+ */
+#define PCIB0TMO_RS 2
+#define PCIB1TMO_RS 2
+#define LBCTMOm0_RS 2
+#define LBCTMOm1_RS 2
+#define LBCTMOs_RS 2
+#define TC0_RS 7
+#define TC1_RS 2
+#define USB_H_RS 4
+#define UART0_RS 3
+#define UART1_RS 2
+#define PCI_RS 5
+#define SW_RS 6
+#define GPIO_ABCD_RS 2
+#define GPIO_EFGH_RS 2
+#define HCI_RS 2
+#define PCM_RS 2
+#define CRYPTO_RS 2
+#define GDMA_RS 2
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C03FFF
+
+#define DMEM_BASE 0x00C04000
+#define DMEM_TOP 0x00C05FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x92A28000
+
+#define MC_MTCR0 0xB8001004
+ #define MC_MTCR0_VAL 0x12120000
+
+#define MC_MTCR1 0xB8001008
+ #define MC_MTCR1_VAL 0x00000FEB
+
+#define MC_PFCR 0xB8001010
+ #define MC_PFCR_VAL 0x00000101
+
+
+#define MC_BASE 0xB8001000
+#define NCR (MC_BASE + 0x100)
+#define NSR (MC_BASE + 0x104)
+#define NCAR (MC_BASE + 0x108)
+#define NADDR (MC_BASE + 0x10C)
+#define NDR (MC_BASE + 0x110)
+
+#define SFCR (MC_BASE + 0x200)
+#define SFDR (MC_BASE + 0x204)
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define GDMA_IE (1 << 21)
+ #define CRYPTO_IE (1 << 20)
+ #define PCM_IE (1 << 19)
+ #define HCI_IE (1 << 18)
+ #define GPIO_EFGH_IE (1 << 17)
+ #define GPIO_ABCD_IE (1 << 16)
+ #define SW_IE (1 << 15)
+ #define PCI_IE (1 << 14)
+ #define UART1_IE (1 << 13)
+ #define UART0_IE (1 << 12)
+ #define USB_H_IE (1 << 10)
+ #define TC1_IE (1 << 9)
+ #define TC0_IE (1 << 8)
+ #define LBCTMOs_IE (1 << 4)
+ #define LBCTMOm1_IE (1 << 3)
+ #define LBCTMOm0_IE (1 << 2)
+ #define PCIB1TO_IE (1 << 1)
+ #define PCIB0TO_IE (1 << 0)
+
+#define GISR 0xB8003004
+ #define GDMA_IP (1 << 21)
+ #define CRYPTO_IP (1 << 20)
+ #define PCM_IP (1 << 19)
+ #define HCI_IP (1 << 18)
+ #define GPIO_EFGH_IP (1 << 17)
+ #define GPIO_ABCD_IP (1 << 16)
+ #define SW_IP (1 << 15)
+ #define PCI_IP (1 << 14)
+ #define UART1_IP (1 << 13)
+ #define UART0_IP (1 << 12)
+ #define USB_H_IP (1 << 10)
+ #define TC1_IP (1 << 9)
+ #define TC0_IP (1 << 8)
+ #define LBCTMOs_IP (1 << 4)
+ #define LBCTMOm1_IP (1 << 3)
+ #define LBCTMOm0_IP (1 << 2)
+ #define PCIB1TO_IP (1 << 1)
+ #define PCIB0TO_IP (1 << 0)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((LBCTMOs_RS << 16) | \
+ (LBCTMOm1_RS << 12) | \
+ (LBCTMOm0_RS << 8) | \
+ (PCIB1TMO_RS << 4) | \
+ (PCIB0TMO_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((SW_RS << 28) | \
+ (PCI_RS << 24) | \
+ (UART1_RS << 20) | \
+ (UART0_RS << 16) | \
+ (USB_H_RS << 8) | \
+ (TC1_RS << 4) | \
+ (TC0_RS << 0) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING ((GDMA_RS << 20) | \
+ (CRYPTO_RS << 16) | \
+ (PCM_RS << 12) | \
+ (HCI_RS << 8) | \
+ (GPIO_EFGH_RS << 4) | \
+ (GPIO_ABCD_RS << 0) \
+ )
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING 0
+
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+/*
+ * HCI
+ */
+#define HCI_BASE 0xB8007000
+#define HCI_GCR (HCI_BASE + 0x00)
+#define HCI_TRFFDR (HCI_BASE + 0x04)
+#define HCI_TRFFAR (HCI_BASE + 0x08)
+#define HCI_FFCR_CS(i) (HCI_BASE + 0x0C + ((i) << 2))
+#define HCI_IER_CS(i) (HCI_BASE + 0x1C + ((i) << 2))
+#define HCI_LSR_CS(i) (HCI_BASE + 0x2C + ((i) << 2))
+#define HCI_CR_CS(i) (HCI_BASE + 0x3C + ((i) << 2))
+#define HCI_TR_CS(i) (HCI_BASE + 0x4C + ((i) << 2))
+
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8652/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8652/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl8652/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl865xb/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl865xb/platform.h new file mode 100644 index 000000000..637c74b16 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl865xb/platform.h @@ -0,0 +1,260 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 100
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define PCIBTMO_IRQ 16
+#define GPIO_DEFGHI_IRQ 17
+#define PCM_IRQ 18
+#define AUTH_IRQ 19
+#define CRYPTO_IRQ 20
+#define LBCTMO_IRQ 21
+#define EXT_IRQ 23
+#define GPIO_ABC_IRQ 24
+#define SWCORE_IRQ 25
+#define PCI_IRQ 26
+#define UART1_IRQ 27
+#define UART0_IRQ 28
+#define PCMCIA_IRQ 29
+#define USB_IRQ 30
+#define TC_IRQ 31
+
+/*
+ * Interrupt Routing Selection
+ */
+#define PCIBTMO_RS 0
+#define GPIO_DEFGHI_RS 0
+#define PCM_RS 0
+#define AUTH_RS 0
+#define CRYPTO_RS 0
+#define LBCTMO_RS 0
+#define EXT_RS 0
+#define GPIO_ABC_RS 0
+#define SWCORE_RS 3
+#define PCI_RS 2
+#define UART1_RS 0
+#define UART0_RS 1
+#define PCMCIA_RS 0
+#define USB_RS 0
+#define TC_RS 4
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C01FFF
+
+#define DMEM_BASE 0x00C02000
+#define DMEM_TOP 0x00C03FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xBD013000
+ #define MC_MCR_VAL 0xFAA00000
+
+#define MC_MTCR0 0xBD013004
+ #define MC_MTCR0_VAL 0x1B1B0000
+
+#define MC_MTCR1 0xBD013008
+ #define MC_MTCR1_VAL 0x00000CEA
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xBD011000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xBD011100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xBD012000
+ #define TC_IE (1 << 31)
+ #define USB_IE (1 << 30)
+ #define PCMICA_IE (1 << 29)
+ #define UART0_IE (1 << 28)
+ #define UART1_IE (1 << 27)
+ #define PCI_IE (1 << 26)
+ #define SWCORE_IE (1 << 25)
+ #define GPIO_ABC_IE (1 << 24)
+ #define EXT_IE (1 << 23)
+ #define LBCTMO_IE (1 << 21)
+ #define CRYPTO_IE (1 << 20)
+ #define AUTH_IE (1 << 19)
+ #define PCM_IE (1 << 18)
+ #define GPIO_DEFGHI_IE (1 << 17)
+ #define PCIBTMO_IE (1 << 16)
+
+#define GISR 0xBD012004
+ #define TC_IP (1 << 31)
+ #define USB_IP (1 << 30)
+ #define PCMICA_IP (1 << 29)
+ #define UART0_IP (1 << 28)
+ #define UART1_IP (1 << 27)
+ #define PCI_IP (1 << 26)
+ #define SWCORE_IP (1 << 25)
+ #define GPIO_ABC_IP (1 << 24)
+ #define EXT_IP (1 << 23)
+ #define LBCTMO_IP (1 << 21)
+ #define CRYPTO_IP (1 << 20)
+ #define AUTH_IP (1 << 19)
+ #define PCM_IP (1 << 18)
+ #define GPIO_DEFGHI_IP (1 << 17)
+ #define PCIBTMO_IP (1 << 16)
+
+#define IRR1 0xBD012008
+#define IRR1_SETTING (((TC_RS & 0x3) << 30) | \
+ ((USB_RS & 0x3) << 28) | \
+ ((PCMCIA_RS & 0x3) << 26) | \
+ ((UART0_RS & 0x3) << 24) | \
+ ((UART1_RS & 0x3) << 22) | \
+ ((PCI_RS & 0x3) << 20) | \
+ ((SWCORE_RS & 0x3) << 18) | \
+ ((GPIO_ABC_RS & 0x3) << 16) | \
+ ((EXT_RS & 0x3) << 14) | \
+ ((LBCTMO_RS & 0x3) << 12) | \
+ ((TC_RS & 0x4) >> 2 << 9) | \
+ ((USB_RS & 0x4) >> 2 << 8) | \
+ ((PCMCIA_RS & 0x4) >> 2 << 7) | \
+ ((UART0_RS & 0x4) >> 2 << 6) | \
+ ((UART1_RS & 0x4) >> 2 << 5) | \
+ ((PCI_RS & 0x4) >> 2 << 4) | \
+ ((SWCORE_RS & 0x4) >> 2 << 3) | \
+ ((GPIO_ABC_RS & 0x4) >> 2 << 2) | \
+ ((EXT_RS & 0x4) >> 2 << 1) | \
+ ((LBCTMO_RS & 0x4) >> 2 << 0) \
+ )
+
+#define IRR2 0xBD0120A0
+#define IRR2_SETTING (((CRYPTO_RS & 0x7) << 29) | \
+ ((AUTH_RS & 0x7) << 26) | \
+ ((PCM_RS & 0x7) << 23) | \
+ ((GPIO_DEFGHI_RS & 0x7) << 20) | \
+ ((PCIBTMO_RS & 0x7) << 17) \
+ )
+
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xBD012020
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl865xb/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl865xb/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl865xb/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_assert.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_assert.h new file mode 100644 index 000000000..dba893beb --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_assert.h @@ -0,0 +1,13 @@ + + +#ifndef RTL865X_DEBUG +#define assert(expr) do {} while (0) +#else +#define assert(expr) \ + if(!(expr)) { \ + rtlglue_printf( "\033[33;41m%s:%d: assert(%s)\033[m\n", \ + __FILE__,__LINE__,#expr); \ + } +#endif + + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_glue.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_glue.h new file mode 100644 index 000000000..9d1cdea79 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_glue.h @@ -0,0 +1,609 @@ +/* +* -------------------------------------------------------------------- +* Copyright c Realtek Semiconductor Corporation, 2002 +* All rights reserved. +* +* Program : rtl_glue.h +* Abstract :Header of porting layer +* Author : Edward Jin-Ru Chen +* +* $Id: rtl_glue.h,v 1.1.1.1 2007-11-12 13:27:50 alva_zhang Exp $ +* $Log: not supported by cvs2svn $ +* Revision 1.32 2007/04/09 14:14:01 michaelhuang +* +: added rtlglue_read() function +* +* Revision 1.31 2007/03/02 13:31:59 chenyl +* *: enable range based D-cache flush function. +* +* Revision 1.30 2007/01/09 02:36:08 michaelhuang +* *: Prepare implement test module for RTL8672 +* +* Revision 1.29 2006/12/21 06:57:00 yjlou +* -: remove the following usages: +* printk +* printfByPolling +* +* Revision 1.28 2006/11/28 02:15:14 hyking_liu +* *: Mofify function related with usrDefineTunnel +* +* Revision 1.27 2006/11/21 12:28:35 chenyl +* *: rearrange some code +* *: bug fix - Src VLAN decision +* *: bug fix - D-cache invalidation for FAST extension device forwarding +* *: bug fix - m_unused1 and ph_reserved are needed for FAST extension device forwarding +* +* Revision 1.26 2006/10/26 02:15:32 qy_wang +* *:remove the inculed file net_device.h in rtl8651_layer2fwd.c +* +* Revision 1.25 2006/10/25 07:10:15 qy_wang +* +:add a function to block extension device when link up +* +* Revision 1.24 2006/08/31 15:44:48 chenyl +* *: add some declarations of external APIs +* +* Revision 1.23 2006/07/13 15:55:49 chenyl +* *: modify code for RTL865XC driver compilation. +* *: dos2unix process +* +* Revision 1.22 2006/06/20 05:53:22 brian_bin +* +: brian_bin move open, write, close declaration into __RTL_GLUE__ define brace +* +* Revision 1.21 2006/01/12 08:32:37 brian_bin +* +: brian_bin add kernel system call of file operations +* +* Revision 1.20 2006/01/02 02:52:14 chenyl +* +: VLAN-tag support extension port forwarding and software Rome Driver forwarding. +* +* Revision 1.19 2005/09/16 11:34:48 tony +* *: bug fixed: support kernel space swNic model code for RTL865XC. +* +* Revision 1.18 2005/09/06 02:36:38 yjlou +* +: add random and time glue functions. +* +* Revision 1.17 2005/07/20 15:29:38 yjlou +* +: porting Model Code to Linux Kernel: check RTL865X_MODEL_KERNEL. +* +* Revision 1.16 2005/07/01 09:34:41 yjlou +* *: porting swNic2.c into model code. +* +* Revision 1.15 2005/06/19 05:41:19 yjlou +* *: merge ASIC driver into model code. +* +* Revision 1.14 2005/06/07 15:00:57 chenyl +* *: modify mutex Lock / Unlock code to check the balance of Lock/Unlock function call +* +* Revision 1.13 2004/11/29 07:35:44 chenyl +* *: fix bug : multiple-PPPoE MTU setting bug +* *: fix bug : Never add second session's ip into ASIC in multiple-PPPoE WAN type. +* *: fix bug : Tunekey abnormal behavior when multiple-PPPoE Dial-on-demand Dynamically turn ON/OFF +* *: in forwarding engine Init function, the parameter == 0xffffffff means user want to set as default value +* *: add Mutex-Lock/Unlock checking in testing code +* +* Revision 1.12 2004/11/05 09:54:08 yjlou +* +: support more precise timeUpdate() function. +* +: add EVENT_TRIGGER_TIMEUPDATE==2 +* *: modify #ifdef EVENT_TRIGGER_TIMEUPDATE +* +* Revision 1.11 2004/07/27 10:47:08 cfliu +* -: Remove RTL865x external loopback port related code for PPTP/L2TP/WLAN +* +* Revision 1.10 2004/06/23 08:11:55 yjlou +* *: change the declaration of rtlglue_getmstime() +* +* Revision 1.9 2004/05/03 14:56:18 cfliu +* Add 8650B extension port support. +* Revise all WLAN/extport related code. +* +* Revision 1.8 2004/05/03 02:53:03 chenyl +* *: swNic_getRingSize -> rtlglue_getRingSize and move it from swNic2.c to rtl_glue.c +* *: set default upstream ip to 0 if we config interface to dhcp +* +* Revision 1.7 2004/04/30 08:58:08 chenyl +* +: ip multicast/igmp proxy +* +* Revision 1.6 2004/04/08 12:11:20 cfliu +* Change extension port API.....define rtlglue_extDeviceSend() +* +* Revision 1.5 2004/03/31 09:37:01 cfliu +* Add WDS support +* +* Revision 1.4 2004/03/19 13:13:35 cfliu +* Reorganize ROME driver local header files. Put all private data structures into different .h file corrsponding to its layering +* Rename printf, printk, malloc, free with rtlglue_XXX prefix +* +* Revision 1.1 2004/03/10 11:42:36 cfliu +* Move rtl_glue.* from rtl865x/ +* +* Revision 1.2 2004/03/03 10:40:38 yjlou +* *: commit for mergence the difference in rtl86xx_tbl/ since 2004/02/26. +* +* Revision 1.1 2004/02/25 14:26:33 chhuang +* *** empty log message *** +* +* Revision 1.2 2004/02/25 14:24:52 chhuang +* *** empty log message *** +* +* Revision 1.7 2004/02/24 04:15:43 cfliu +* add API for WLAN acceleration +* +* Revision 1.6 2004/02/18 13:54:37 chhuang +* *** empty log message *** +* +* Revision 1.5 2003/12/26 09:27:50 orlando +* add rtl_glue.h +* +* Revision 1.3 2003/09/30 06:07:50 orlando +* check in RTL8651BLDRV_V20_20030930 +* +* Revision 1.4 2003/06/10 05:33:30 cfliu +* Remove rtl8651_tblDrvFwdSend registration. +* Add rtlglue_drvSend to replace rtl8651_tblDrvFwdSend function pointer +* +* Revision 1.3 2003/06/09 04:48:43 cfliu +* add 3 OS dependent glue functions to support mbuf external cluster allocation. +* Rewrite all help messages using Autoduck's syntax so documentation could generated automatically. +* +* Revision 1.2 2003/05/23 07:47:06 cfliu +* Extract porting function and fix compile warning. +* +* Revision 1.1 2003/05/23 04:55:25 jzchen +* Add rtl glue to solve porting issue +* +*/ + +#ifndef _RTL_GLUE_ +#define _RTL_GLUE_ + +#include "rtl_types.h" +#if defined(CONFIG_RTL865X) +#include "mbuf.h" +#endif + + +/* @doc RTLGLUE_API + + @module rtl_glue.h - Glue interface for Realtek 8651 Home gateway controller driver | + This guide documents the glue interface for porting 8651 driver to targeted operating system + @normal Chun-Feng Liu (cfliu@realtek.com.tw) <date> + + Copyright <cp>2003 Realtek<tm> Semiconductor Cooperation, All Rights Reserved. + + @head3 List of Symbols | + Here is the list of all functions and variables in this module. + + @index | RTLGLUE_API +*/ + + +extern int32 rtlglue_init(void); +/* +@func int32 | rtlglue_init | Initialize all OS dependent mutex, semaphore objects, etc. here +@rvalue SUCCESS | if initialization succeed +@rvalue FAILED | if initialization failed. This aborts system initialization. +@comm +All required OS supporting capabilities such as mutex, semaphore, and timer service are initialized here. + */ + +extern int32 rtlglue_registerTimerMs(uint32 *eventId,uint32 *eventSerialNumber, + int32 (* callback_func)(uint32 eventSerialNumber,void *), void *callback_func_arg, uint32 msec); +/* +@func int32 | rtlglue_registerTimerMs | OS dependent timer registration function. +@parm uint32 * | eventId | placeholder for saving registered timer event id. +@parm uint32 * | eventSerialNumber | placeholder for saving the unique serial number returned with event id. +@parm int32 (*)(uint32,void *) | callback_func | the registering callback function for execution +@parm void * | callback_func_arg | arguments for callback_func +@parm uint32 | msec | timeout in units of milli-seconds. + +@rvalue SUCCESS | if timer event registration failed. +@rvalue FAILED | if timer event successfully registered. +@comm +a) If the timer service provided by the ported OS is a kernel service(which guarantees atomic operation), +then return value of <p eventSerialNumber> MUST always be zero. + +b) If the timer service is provided by a "soft" timer, ie. a timer thread/task, then the return value of <p eventSerialNumber> must +NOT be zero and MUST be unique every time this glue function is called. This returned value would then be saved by caller and +checked by the callback function upon called-back to prevent race condition between running thread and timer thread. + */ + + +extern int32 rtlglue_cancelTimer(uint32 eventId,uint32 eventSerialNumber); +/* +@func int32 | rtlglue_cancelTimer |OS dependent timer deregistration function. +@parm uint32 | eventId | The identifier of timer event to be cancelled. +@parm uint32 | eventSerialNumber | The serial number of timer event identifier <p eventId>. + +@rvalue SUCCESS | Timer event successfully cancelled. If the OS timer is a kernel service, the registered callback function would NOT be called. If the OS timer is provided via timer thread, the registered callback function may still/may not be called. +@rvalue FAILED | Failed to cancel timer event <p eventId> + */ + +#ifndef RTL865X_TEST +extern int32 rtlglue_mbufMutexLock(void); +#endif +/* +@func int32 | rtlglue_mbufMutexLock | The mutex lock function for mbuf module to protect internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + + +#ifndef RTL865X_TEST +extern int32 rtlglue_mbufMutexUnlock(void); +#endif +/* +@func int32 | rtlglue_mbufMutexLock | The mutex unlock function for mbuf module to protect internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + + +extern int32 rtlglue_mbufTsleep(uint32 wait_channel); +/* +@func int32 | rtlglue_mbufTsleep | Used by mbuf module, to let calling thread blocking when requested resource not readily available. +@parm uint32 | wait_channel | Identifier of requesting resource. May be an memory address, resource handle, etc. +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +Ref FreeBSD's tsleep() or Steven's TCP/IP Vol2 pp456 + */ + + +extern int32 rtlglue_mbufTwakeup(uint32 wait_channel); +/* +@func int32 | rtlglue_mbufTwakeup | Used by mbuf module, to wakeup blocked waiting thread when requesed resource is available +@parm uint32 | wait_channel | Identifier of waiting channel to be waked up. +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +Ref FreeBSD's tsleep() or Steven's TCP/IP Vol2 pp456 + */ + +extern int32 rtlglue_mbufAllocCluster(void **buffer, uint32 size, uint32 *id); +/* +@func int32 | rtlglue_mbufAllocCluster | Used by mbuf module, to allocate a cluster externally from OS +@parm void ** | buffer | For output, address of allocated cluster. +@parm uint32 | size | number of bytes requested. +@parm uint32 * | id | For output, identifier of allocated cluster, up to OS memory allocator's interpretation. +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +each allocation must set returned buffer's reference count to 1. +But if you are sure you WON'T call any of mbuf's spliting(<p mBuf_split>), cloning(<p mBuf_clonePacket>, +<p mBuf_cloneMbufChain>) or trimming(<p mBuf_trimHead>, <p mBuf_trimTail>) APIs in your code, never mind about reference counts. + */ + +extern int32 rtlglue_mbufFreeCluster(void *buffer, uint32 size, uint32 id); +/* +@func int32 | rtlglue_mbufFreeCluster | Used by mbuf module, to free allocated cluster +@parm void * | buffer | buffer address to free +@parm uint32 | size | identifier of buffer to free +@parm uint32 | id | size of buffer to free +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +each buffer returned must has its reference count decremented to exactly 0. mbuf module would query buffer's reference count and make sure it's 1 before calling this function. +But if you are sure you WON'T call any of mbuf's spliting(<p mBuf_split>), cloning(<p mBuf_clonePacket>, +<p mBuf_cloneMbufChain>) or trimming(<p mBuf_trimHead>, <p mBuf_trimTail>) APIs in your code, never mind about reference counts. + */ + +extern int32 rtlglue_mbufClusterRefcnt(void *buffer, uint32 id, uint32 *count, int8 operation); +/* +@func int32 | rtlglue_mbufClusterRefcnt | Used by mbuf module, to free allocated cluster +@parm void * | buffer | buffer address to free +@parm uint32 | id | identifier of designated buffer +@parm uint32 * | count | For output. Placeholder for returned reference number *AFTER* <p operation> done. +@parm int8 | operation | 0: Query, 1: Increment, 2: Decrement +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +1) For parameter <p count>: <p count> is the reference count of designated cluster *AFTER* 'operation' done. MUST not be NULL for Query operation, MAY be NULL for Increment o Decrement operation. + +2) When clusters are allocated externally by OS, <p mBuf_data2Mbuf()>, <p mBuf_clusterIsWritable()> +become void. Also, since mbuf module no longer knows which mbuf is the first referee (which owns the write priviledge to +cluster). Design decision here simply grants write priviledge to ALL cluster referees. + +3) Porting Note: If you are sure you WON'T call any of mbuf's spliting(<p mBuf_split>), cloning(<p mBuf_clonePacket>, +<p mBuf_cloneMbufChain>), or trimming(<p mBuf_trimHead>, <p mBuf_trimTail>) APIs, you can always return +1 when operation=0(Query), and do nothing when operation=1(Increment) or 2(Decrement). +*/ + +extern void * rtlglue_mbufClusterToData(void *buffer); +/* +@parm void * | buffer | find mbuf cluster's m_data's position +@rvalue 0 | failed +@rvalue Non-0 | succeed +@comm +return mbuf cluster's m_data's position +*/ +#ifndef RTL865X_TEST +extern int32 rtlglue_drvMutexLock(void); +#endif +/* +@func int32 | rtlglue_drvMutexLock | Used by driver, to safeguard driver internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + +#ifndef RTL865X_TEST +extern int32 rtlglue_drvMutexUnlock(void); +#endif +/* +@func int32 | rtlglue_drvMutexLock | Used by driver, to safeguard driver internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + + +extern void rtlglue_getMacAddress(ether_addr_t * macAddress, uint32 * number); +/* +@func void | rtlglue_getMacAddress | Used during board initialization, to read the total number of configured MAC addresses and their values in flash. +@parm ether_addr_t * | macAddress | For output. The base MAC address configured for this board. +@parm uint32 * | number | For output. Total (consecutive) number of MAC addresses starting from <p *macAddress>. + +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +Read from the flash to get the base MAC address and total number of MAC addresses configured to the board. +If anything goes wrong, a default MAC address would be written back to the flash. + */ + +#if defined(CONFIG_RTL865X) +extern void rtlglue_drvSend(void * pkthdr);//void * assumed to be packet header +/* +@func void | rtlglue_drvSend | The OS dependent raw driver send function for high level driver to send pkt. +@parm void * | pkthdr | The pkthdr address of outgoing mbuf chain +@rdesc None +@comm +Implement this function to provide table driver and upper layer protocols such as PPPoE module to send packet to driver. +The sending packet must have already in mbuf chain format. + */ +#endif /* defined(CONFIG_RTL865X) */ + +#if defined(CONFIG_RTL865X) +/* +@func int32 | rtlglue_extPortMbufFastRecv | Fast Path for packet from Extension device to HW. +@parm struct rtl_pktHdr* | pkt | packet from extension device. +@parm uint16 | myvid | RX VID of this packet. +@parm uint32 | myportmask | RX Port mask of this packet. +@rvalue SUCCESS | Always return SUCCESS. +@comm + +Glue Interface for <p rtl8651_fwdEngineExtPortUcastFastRecv> + +Fast path for extension device to HW Accelerated forwarding. +Note that this function would NOT do + 1. SMAC learning. + 2. Extension Device Bridge. + +Therefore, if extension device would like to use Fast path, it would do these by itself. +*/ +int32 rtlglue_extPortMbufFastRecv( struct rtl_pktHdr *pkt, + uint16 myvid, + uint32 myportmask); +#endif /* defined(CONFIG_RTL865X) */ + +/* +@func int32 | rtlglue_regWlanSta | Register (LinkID<->Port Number) binding into Rome Driver +@parm uint32 | portNumber | Extension Port Number to bind. +@parm uint16 | defaultVID | Default VID of this extension device. +@parm uint32* | linkID_p | pointer to the LinkID of current extension device. +@parm void* | extDevice | extension device's own pointer ( can NOT be NULL ). +@rvalue FAILED | No free LinkID or extDevice == NULL. +@rvalue SUCCESS | Registration OK. +@comm + +Glue Interface for <p rtl8651_fwdEngineRegExtDevice> + +Register Extension Device into Rome Driver: + Extension device would need to provide it's binding <p portNumber> and <p extDevice>. + Rome Driver would fill the <p linkID> if registration success. + <p defaultVID> indicates the default VLAN ID of this extension device. It is used in TX vlan filtering + now. + + - Note: We don't support per-LinkID's untag set setting yet. +*/ + +int32 rtlglue_regWlanSta( uint32 portNumber, + uint16 defaultVID, + uint32 *linkID_p, + void *extDevice); + +/* +@func int32 | rtlglue_unregWlanSta | Un-Register (LinkID<->Port Number) binding. +@parm uint32 | linkID | pointer to the LinkID of current extension device. +@rvalue FAILED | LinkID is not found. +@rvalue SUCCESS | UnRegistration OK. +@comm + +Glue Interface for <p rtl8651_fwdEngineUnregExtDevice> + +UnRegister exist LinkID from Rome Driver. + Extension device would need to provide it's <p linkID> which gotten from registration function. + Rome Driver would remove the related information for this <p linkID>. + */ + +int32 rtlglue_unregWlanSta(uint32 linkID); + +#if defined(CONFIG_RTL865X) +void rtlglue_extDeviceSend(struct rtl_pktHdr *pktHdr, void *txExtDev); +// This function is called back by RTL8651 driver when it wants to send a pkt to WLAN interface. +//First input parameter represents the destination vlan ID, second parameter is the destination link ID +//which was given and learnt from rtl8651_fwdEngineExtPortRecv() during L2 SA learning process. +// It's WLAN driver's job to find out to which card or WDS link the pkt should be sent by maintaining a +//small database keeping linkId<-> device mapping. +// The 'linkId' was assigned by WLAN driver and is not interpreted by 8651 driver. However, linkId=0 +//has special usage reserved for "Broadcast to all vlan member ports" therefore linkId=0 can't be associated +//to any WLAN card or WDS link. +// ***This function is called by 8651 driver and MUST be implemented. +#endif /* defined(CONFIG_RTL865X) */ + +//#endif +#if defined(CONFIG_RTL865X) +int32 rtlglue_reclaimRxBD(uint32 rxDescIdx,struct rtl_pktHdr *pThisPkthdr, struct rtl_mBuf *pThisMbuf); +#endif /* defined(CONFIG_RTL865X) */ +#ifdef CONFIG_RTL865XC +void rtlglue_getRingSize(uint32 *rx, uint32 *tx,int whichDesc); +#else +void rtlglue_getRingSize(uint32 *rx, uint32 *tx); +#endif +uint32 rtlglue_getsectime(void) ; +uint32 rtlglue_getmstime( uint32* ); +void *rtlglue_malloc(uint32); +void rtlglue_free(void *APTR); + +uint32 rtl865x_getHZ(void); + +#if defined(RTL865X_TEST) || defined(RTL865X_MODEL_USER) || defined(RTL867X_MODEL_USER) || defined(RTL8389_MODEL_USER) +#include <stdio.h> +#include <stdlib.h> +#include <ctype.h> +#include <string.h> + + +int32 rtlglue_getDrvMutex(void); +int32 rtlglue_reinitDrvMutex(void); +int32 rtlglue_getMbufMutex(void); +int32 rtlglue_reinitMbufMutex(void); + +extern int test_drvMutex; +extern int test_mbufMutex; + +#define rtlglue_drvMutexLock() \ + do { \ + test_drvMutex ++;\ + } while (0) +#define rtlglue_drvMutexUnlock()\ + do {\ + test_drvMutex --;\ + if (test_drvMutex < 0)\ + {\ + printf("%s (%d) Error: Driver Mutex Lock/Unlcok is not balance (%d).\n", __FUNCTION__, __LINE__, test_drvMutex);\ + }\ + } while (0) + +#define rtlglue_mbufMutexLock() \ + do { \ + test_mbufMutex ++;\ + } while (0) +#define rtlglue_mbufMutexUnlock()\ + do {\ + test_mbufMutex --;\ + if (test_mbufMutex < 0)\ + {\ + printf("%s (%d) Error: Mbuffer Mutex Lock/Unlcok is not balance (%d).\n", __FUNCTION__, __LINE__, test_mbufMutex);\ + }\ + } while (0) + +#define wmb() do {} while(0) + +#define spin_lock(x) do {x=x;} while(0) +#define spin_unlock(x) do {x=x;} while(0) + +#ifdef RTL865X_TEST +int32 spin_lock_irqsave(spinlock_t *spinlock, int32 s); +int32 spin_unlock_irqrestore(spinlock_t *spinlock, int32 s); +#else +#define spin_lock_irqsave(sp,s) do { sp=sp; s=s; } while(0) +#define spin_unlock_irqrestore(sp,s) do { sp=sp; s=s; } while(0) +#endif/*RTL865X_TEST*/ + +#endif /* RTL865X_TEST || RTL865X_MODEL_USER || RTL867X_MODEL_USER || defined(RTL8389_MODEL_USER)*/ + +#define bzero( p, s ) memset( p, 0, s ) + + +/* +@func void | rtlglue_srandom | The OS dependent seed function for random. +@parm uint32 | seed | seed +@comm + */ +void rtlglue_srandom( uint32 seed ); + +/* +@func uint32 | rtlglue_random | The OS dependent random function. +@parm void | | +@comm + */ +uint32 rtlglue_random( void ); + +/* +@func uint32 | rtlglue_time | The OS dependent time function. +@parm uint32* | t | address to store time +@comm + */ +uint32 rtlglue_time( uint32* t ); + +/* +@func int | rtlglue_open | The OS dependent open function. +@parm const char* | path | filename or path +@parm int | flags | file attribute +@parm int | mode | file mode +@comm + */ +int rtlglue_open(const char *path, int flags, int mode ); + +/* +@func int | rtlglue_read | The OS dependent read function. +@parm int | fd | file descriptor +@parm void* | buf | read buffer +@parm int | nbytes | number of bytes to read in buffer +@comm + */ +int rtlglue_read(int fd, void* buf, int nbytes); + +/* +@func int | rtlglue_write | The OS dependent write function. +@parm int | fd | file descriptor +@parm void* | buf | write buffer +@parm int | nbytes | number of bytes to write in buffer +@comm + */ +int rtlglue_write(int fd, void* buf, int nbytes); + +/* +@func int | rtlglue_close | The OS dependent close function. +@parm int | fd | file descriptor +@comm + */ +int rtlglue_close(int fd); + +#if defined(CONFIG_RTL865X) +struct sk_buff *re865x_mbuf2skb(struct rtl_pktHdr* pPkt); +#endif /* defined(CONFIG_RTL865X) */ + +/* +@func void | rtl8651_extDevMakeBlocking | make extension device port STP blocking . +@parm void* | extDev | extension device +@comm + */ +int32 rtlglue_extDevMakeBlocking(void * extDev); + +/* +@func void | rtlglue_getExtDeviceName | Get device NAME of "device" +@parm void* | device | pointer of device to get name. +@parm void* | name | pointer of name to be filled by this API. +@comm + */ +int32 rtlglue_getExtDeviceName(void * device, char* name); + +/* +@func void | rtlglue_pktToProtocolStackPreprocess | Process before packet is trapped to protocol stack. +@comm + */ +inline int32 rtlglue_pktToProtocolStackPreprocess(void); + +/* +@func int32 | rtlglue_flushDCache | Flush D-cache. +@parm uint32 | start | start address to flush +@parm uint32 | size | total size to flush +@comm +Flush D-cache from <p start> with size being <p size>. +Set <p start> = 0 and <p size> = 0 if we need to flush ALL D-cache entries. + */ +inline int32 rtlglue_flushDCache(uint32 start, uint32 size); + +#endif/*#ifndef _RTL_GLUE_*/ + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_queue.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_queue.h new file mode 100644 index 000000000..515a19663 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_queue.h @@ -0,0 +1,940 @@ + +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: src/sys/sys/queue.h,v 1.32.2.4 2001/03/31 03:33:39 hsu Exp $ + */ + +#ifndef _RTL_QUEUE_H_ +#define _RTL_QUEUE_H_ + +////#include <machine/ansi.h> /* for __offsetof */ + +/* + * This file defines five types of data structures: singly-linked lists, + * singly-linked tail queues, lists, tail queues, and circular queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * A circle queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or after + * an existing element, at the head of the list, or at the end of the list. + * A circle queue may be traversed in either direction, but has a more + * complex end of list detection. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ CIRCLEQ + * _HEAD + + + + + + * _ENTRY + + + + + + * _INIT + + + + + + * _EMPTY + + + + + + * _FIRST + + + + + + * _NEXT + + + + + + * _PREV - - - + + + * _LAST - - + + + + * _FOREACH + + + + + + * _FOREACH_REVERSE - - - + + + * _INSERT_HEAD + + + + + + * _INSERT_BEFORE - + - + + + * _INSERT_AFTER + + + + + + * _INSERT_TAIL - - + + + + * _REMOVE_HEAD + - + - - + * _REMOVE + + + + + + * + */ + +#ifndef __offsetof +#define __offsetof(type, field) ((unsigned long)(&((type *)0)->field)) +#endif + +/* + * Singly-linked List definitions. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next) + +#define SLIST_INIT(head) { \ + (head)->slh_first = NULL; \ +} + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ +} while (0) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = (head)->slh_first; \ + while( curelm->field.sle_next != (elm) ) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = \ + curelm->field.sle_next->field.sle_next; \ + } \ +} while (0) + +/* + * Counting Singly-linked List definitions. + */ +#define CSLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ + int slh_count;\ +} + +#define CSLIST_HEAD_INITIALIZER(head) \ + {0, NULL } + +#define CSLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define CSLIST_EMPTY(head) ((head)->slh_first == NULL) +#define CSLIST_FIRST(head) ((head)->slh_first) +#define CSLIST_TOTAL(head) ((head)->slh_count) +#define CSLIST_FOREACH(var, head, field) \ + for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next) + +#define CSLIST_INIT(head) { \ + (head)->slh_count=0;\ + (head)->slh_first = NULL; \ +} + +#define CSLIST_INSERT_AFTER(head, slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ + (head)->slh_count++;\ +} while (0) + +#define CSLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ + (head)->slh_count++;\ +} while (0) + +#define CSLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define CSLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ + (head)->slh_count--;\ +} while (0) + +#define CSLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + CSLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = (head)->slh_first; \ + while( curelm->field.sle_next != (elm) ) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = curelm->field.sle_next->field.sle_next;\ + (head)->slh_count--;\ + }\ +} while (0) + +/* + * Singly-linked Tail queue definitions. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_INIT(head) do { \ + (head)->stqh_first = NULL; \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY(head) ? \ + NULL : \ + ((struct type *) \ + ((int8 *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = (head)->stqh_first; (var); (var) = (var)->field.stqe_next) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_first = (elm); \ +} while (0) + +/*if the header->stqh_first == NULL,we should modify it*/ +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + if((head)->stqh_first == NULL) \ + STAILQ_INSERT_HEAD(head, elm, field); \ + else { \ + (elm)->field.stqe_next = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + } \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if (((elm)->field.stqe_next = (tqelm)->field.stqe_next) == NULL)\ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (tqelm)->field.stqe_next = (elm); \ +} while (0) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if (((head)->stqh_first = \ + (head)->stqh_first->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \ + if (((head)->stqh_first = (elm)->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if ((head)->stqh_first == (elm)) { \ + STAILQ_REMOVE_HEAD(head, field); \ + } \ + else { \ + struct type *curelm = (head)->stqh_first; \ + while( curelm->field.stqe_next != (elm) ) \ + curelm = curelm->field.stqe_next; \ + if((curelm->field.stqe_next = \ + curelm->field.stqe_next->field.stqe_next) == NULL) \ + (head)->stqh_last = &(curelm)->field.stqe_next; \ + } \ +} while (0) + + +/* + * Counting Singly-linked Tail queue definitions. + */ +#define CSTAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ + int stqh_count;\ +} + +#define CSTAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first, 0 } + +#define CSTAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Counting Singly-linked Tail queue functions. + */ +#define CSTAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define CSTAILQ_INIT(head) do { \ + (head)->stqh_count=0;\ + (head)->stqh_first = NULL; \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define CSTAILQ_FIRST(head) ((head)->stqh_first) +#define CSTAILQ_TOTAL(head) ((head)->stqh_count) +#define CSTAILQ_LAST(head, type, field) \ + (CSTAILQ_EMPTY(head) ? \ + NULL : \ + ((struct type *) \ + ((int8 *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define CSTAILQ_FOREACH(var, head, field) \ + for((var) = (head)->stqh_first; (var); (var) = (var)->field.stqe_next) + +#define CSTAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_first = (elm); \ + (head)->stqh_count++;\ +} while (0) + +#define CSTAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.stqe_next = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_count++;\ +} while (0) + +#define CSTAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if (((elm)->field.stqe_next = (tqelm)->field.stqe_next) == NULL)\ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (tqelm)->field.stqe_next = (elm); \ + (head)->stqh_count++;\ +} while (0) + +#define CSTAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define CSTAILQ_REMOVE_HEAD(head, field) do { \ + if (((head)->stqh_first = \ + (head)->stqh_first->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ + (head)->stqh_count--;\ +} while (0) + +#define CSTAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \ + if (((head)->stqh_first = (elm)->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ + (head)->stqh_count--;\ +} while (0) + +#define CSTAILQ_REMOVE(head, elm, type, field) do { \ + if ((head)->stqh_first == (elm)) { \ + CSTAILQ_REMOVE_HEAD(head, field); \ + } \ + else { \ + struct type *curelm = (head)->stqh_first; \ + while( curelm->field.stqe_next != (elm) ) \ + curelm = curelm->field.stqe_next; \ + if((curelm->field.stqe_next = \ + curelm->field.stqe_next->field.stqe_next) == NULL) \ + (head)->stqh_last = &(curelm)->field.stqe_next; \ + (head)->stqh_count--;\ + } \ +} while (0) + +#ifndef __linux__ + +/* + * List definitions. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for((var) = (head)->lh_first; (var); (var) = (var)->field.le_next) + +#define LIST_INIT(head) do { \ + (head)->lh_first = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.le_next = (head)->lh_first) != NULL) \ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_REMOVE(elm, field) do { \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ +} while (0) + +#endif /* __linux__ */ + +/* + * Counting List definitions. + */ +#define CLIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ + int lh_count;\ +} + +#define CLIST_HEAD_INITIALIZER(head) \ + { 0, NULL } + +#define CLIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * Counting List functions. + */ + +#define CLIST_EMPTY(head) ((head)->lh_first == NULL) +#define CLIST_TOTAL(head) ((head)->lh_count) +#define CLIST_FIRST(head) ((head)->lh_first) + +#define CLIST_FOREACH(var, head, field) \ + for((var) = (head)->lh_first; (var); (var) = (var)->field.le_next) + +#define CLIST_INIT(head) do { \ + (head)->lh_count=0;\ + (head)->lh_first = NULL; \ +} while (0) + +#define CLIST_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ + (head)->lh_count++;\ +} while (0) + +#define CLIST_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ + (head)->lh_count++;\ +} while (0) + +#define CLIST_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.le_next = (head)->lh_first) != NULL) \ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ + (head)->lh_count++;\ +} while (0) + +#define CLIST_NEXT(elm, field) ((elm)->field.le_next) + +#define CLIST_REMOVE(head, elm, field) do { \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ + (head)->lh_count--;\ +} while (0) + + +/* + * Tail queue definitions. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ +} + +/* + * Tail queue functions. + */ +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FOREACH(var, head, field) \ + for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_INIT(head) do { \ + (head)->tqh_first = NULL; \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.tqe_next = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ +} while (0) + +#define TAILQ_REMOVE(head, elm, field) do { \ + if (((elm)->field.tqe_next) != NULL) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ +} while (0) + +/* + * Counting Tail queue definitions. + */ +#define CTAILQ_HEAD(name, type) \ +struct name {\ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + int tqh_count;\ +} + +#define CTAILQ_HEAD_INITIALIZER(head) \ + { 0, NULL, &(head).tqh_first } + +#define CTAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ +} + +/* + * Counting Tail queue functions. + */ +#define CTAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define CTAILQ_FOREACH(var, head, field) \ + for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) + +#define CTAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define CTAILQ_FIRST(head) ((head)->tqh_first) +#define CTAILQ_TOTAL(head) ((head)->tqh_count) +#define CTAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define CTAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define CTAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define CTAILQ_INIT(head) do { \ + (head)->tqh_count=0;\ + (head)->tqh_first = NULL; \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (0) + +#define CTAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ + (head)->tqh_count++;\ +} while (0) + +#define CTAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.tqe_next = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_count++;\ +} while (0) + +#define CTAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ + (head)->tqh_count++; \ +} while (0) + +#define CTAILQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ + (head)->tqh_count++;\ +} while (0) + +#define CTAILQ_REMOVE(head, elm, field) do { \ + if (((elm)->field.tqe_next) != NULL) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ + (head)->tqh_count--;\ +} while (0) + + + +/* + * Circular queue definitions. + */ +#define CIRCLEQ_HEAD(name, type) \ +struct name { \ + struct type *cqh_first; /* first element */ \ + struct type *cqh_last; /* last element */ \ +} + +#define CIRCLEQ_ENTRY(type) \ +struct { \ + struct type *cqe_next; /* next element */ \ + struct type *cqe_prev; /* previous element */ \ +} + +/* + * Circular queue functions. + */ +#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) + +#define CIRCLEQ_FIRST(head) ((head)->cqh_first) + +#define CIRCLEQ_FOREACH(var, head, field) \ + for((var) = (head)->cqh_first; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_next) + +#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \ + for((var) = (head)->cqh_last; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_prev) + +#define CIRCLEQ_INIT(head) do { \ + (head)->cqh_first = (void *)(head); \ + (head)->cqh_last = (void *)(head); \ +} while (0) + +#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm)->field.cqe_next; \ + (elm)->field.cqe_prev = (listelm); \ + if ((listelm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (listelm)->field.cqe_next->field.cqe_prev = (elm); \ + (listelm)->field.cqe_next = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm); \ + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ + if ((listelm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (listelm)->field.cqe_prev->field.cqe_next = (elm); \ + (listelm)->field.cqe_prev = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.cqe_next = (head)->cqh_first; \ + (elm)->field.cqe_prev = (void *)(head); \ + if ((head)->cqh_last == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (head)->cqh_first->field.cqe_prev = (elm); \ + (head)->cqh_first = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.cqe_next = (void *)(head); \ + (elm)->field.cqe_prev = (head)->cqh_last; \ + if ((head)->cqh_first == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (head)->cqh_last->field.cqe_next = (elm); \ + (head)->cqh_last = (elm); \ +} while (0) + +#define CIRCLEQ_LAST(head) ((head)->cqh_last) + +#define CIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next) + +#define CIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev) + +#define CIRCLEQ_REMOVE(head, elm, field) do { \ + if ((elm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm)->field.cqe_prev; \ + else \ + (elm)->field.cqe_next->field.cqe_prev = \ + (elm)->field.cqe_prev; \ + if ((elm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm)->field.cqe_next; \ + else \ + (elm)->field.cqe_prev->field.cqe_next = \ + (elm)->field.cqe_next; \ +} while (0) + +/* + * Counting Circular queue definitions. + */ +#define CCIRCLEQ_HEAD(name, type) \ +struct name { \ + struct type *cqh_first; /* first element */ \ + struct type *cqh_last; /* last element */ \ +} + +#define CCIRCLEQ_ENTRY(type) \ +struct { \ + int cqe_count;\ + struct type *cqe_next; /* next element */ \ + struct type *cqe_prev; /* previous element */ \ +} + +/* + * Counting Circular queue functions. + */ +#define CCIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) +#define CCIRCLEQ_FIRST(head) ((head)->cqh_first) +#define CCIRCLEQ_TOTAL(head) ((head))->cqh_count) +#define CCIRCLEQ_FOREACH(var, head, field) \ + for((var) = (head)->cqh_first; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_next) + +#define CCIRCLEQ_FOREACH_REVERSE(var, head, field) \ + for((var) = (head)->cqh_last; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_prev) + +#define CCIRCLEQ_INIT(head) do { \ + (head)->cqh_count=0;\ + (head)->cqh_first = (void *)(head); \ + (head)->cqh_last = (void *)(head); \ +} while (0) + +#define CCIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm)->field.cqe_next; \ + (elm)->field.cqe_prev = (listelm); \ + if ((listelm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (listelm)->field.cqe_next->field.cqe_prev = (elm); \ + (listelm)->field.cqe_next = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm); \ + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ + if ((listelm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (listelm)->field.cqe_prev->field.cqe_next = (elm); \ + (listelm)->field.cqe_prev = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.cqe_next = (head)->cqh_first; \ + (elm)->field.cqe_prev = (void *)(head); \ + if ((head)->cqh_last == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (head)->cqh_first->field.cqe_prev = (elm); \ + (head)->cqh_first = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.cqe_next = (void *)(head); \ + (elm)->field.cqe_prev = (head)->cqh_last; \ + if ((head)->cqh_first == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (head)->cqh_last->field.cqe_next = (elm); \ + (head)->cqh_last = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_LAST(head) ((head)->cqh_last) + +#define CCIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next) + +#define CCIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev) + +#define CCIRCLEQ_REMOVE(head, elm, field) do { \ + if ((elm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm)->field.cqe_prev; \ + else \ + (elm)->field.cqe_next->field.cqe_prev = \ + (elm)->field.cqe_prev; \ + if ((elm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm)->field.cqe_next; \ + else \ + (elm)->field.cqe_prev->field.cqe_next = \ + (elm)->field.cqe_next; \ + (head)->cqh_count--;\ +} while (0) +#endif /* !_RTL_QUEUE_H_ */ diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_types.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_types.h new file mode 100644 index 000000000..24f1a2d29 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_types.h @@ -0,0 +1,541 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2002 +* All rights reserved. +* +* Program : The header file of realtek type definition +* Abstract : +* Author : +* $Id: rtl_types.h,v 1.1.1.1 2007-11-12 13:27:50 alva_zhang Exp $ +* $Log: not supported by cvs2svn $ +* Revision 1.20 2007/04/04 15:48:54 chenyl +* +: cleshell commend for asic register configuration : mmtu ( multicast mtu ) +* +* Revision 1.19 2006/08/29 13:00:00 chenyl +* *: New SWNIC driver for RTL865xC +* *: some rearrange in re_core.c for Bootstrap sequence being more readable. +* +* Revision 1.18 2006/02/27 07:47:06 ympan +* +: No change by ympan +* +* Revision 1.17 2005/09/27 05:59:44 chenyl +* *: modify IRAM / DRAM layout: +* IRAM/DRAM-FWD : external used, swNic ... blahblah +* IRAM/DRAM-L2-FWD : fwdengine internal used, L2 and below (ex. preprocess, postprocess) +* IRAM/DRAM-L34-FWD : fwdengine internal used, L3/L4 process only (ex. Routing, decision table...etc). +* +* => If L34 is used, we strongly suggest L2 must be used, too. +* +* Revision 1.16 2005/08/23 14:38:26 chenyl +* +: apply prioirty IRAM/DRAM usage +* +* Revision 1.15 2005/08/22 07:33:55 chenyl +* *: don't set DRAM/IRAM for other OSs yet. +* +* Revision 1.14 2005/08/18 09:14:08 chenyl +* *: add code to porting to other OSs +* +* Revision 1.13 2005/08/18 06:29:29 chenyl +* +: always define the rtlglue_printf in rtl_types.h +* +* Revision 1.12 2005/07/01 09:34:41 yjlou +* *: porting swNic2.c into model code. +* +* Revision 1.11 2005/06/19 05:29:37 yjlou +* *: use 'unsigned int' to replace 'size_t' +* *: define spinlock_t when RTL865X_MODEL_USER defined. +* +* Revision 1.10 2005/06/10 05:32:22 yjlou +* +: Porting CLE Shell to Linux user space for model test. +* See RTL865X_MODEL_USER compile flags. +* +* Revision 1.9 2005/01/10 03:21:43 yjlou +* *: always define __IRAM and __DRAM +* +* Revision 1.8 2004/07/23 13:42:45 tony +* *: remove all warning messages +* +* Revision 1.7 2004/07/05 08:25:32 chenyl +* +: define __IRAM, __DRAM for module test +* +* Revision 1.6 2004/07/04 15:04:55 cfliu +* +: add IRAM and DRAM +* +* Revision 1.5 2004/04/20 03:44:03 tony +* if disable define "RTL865X_OVER_KERNEL" and "RTL865X_OVER_LINUX", __KERNEL__ and __linux__ will be undefined. +* +* Revision 1.4 2004/03/19 13:13:35 cfliu +* Reorganize ROME driver local header files. Put all private data structures into different .h file corrsponding to its layering +* Rename printf, printk, malloc, free with rtlglue_XXX prefix +* +* Revision 1.3 2004/03/05 07:44:27 cfliu +* fix header file problem for ctype.h +* +* Revision 1.2 2004/03/03 10:40:38 yjlou +* *: commit for mergence the difference in rtl86xx_tbl/ since 2004/02/26. +* +* Revision 1.1 2004/02/25 14:26:33 chhuang +* *** empty log message *** +* +* Revision 1.3 2004/02/25 14:24:52 chhuang +* *** empty log message *** +* +* Revision 1.8 2003/12/10 06:30:12 tony +* add linux/config.h, disable define CONFIG_RTL865X_NICDRV2 in mbuf.c by default +* +* Revision 1.7 2003/12/03 14:25:43 cfliu +* change SIZE_T to _SIZE_T. Linux kernel seems to recognize _SIZE_T +* +* Revision 1.6 2003/10/01 12:29:02 tony +* #define DEBUG_P(args...) while(0); +* +* Revision 1.5 2003/10/01 10:31:47 tony +* solve all the compiler warnning messages in the board.c +* +* Revision 1.4 2003/09/30 06:07:50 orlando +* check in RTL8651BLDRV_V20_20030930 +* +* Revision 1.30 2003/07/21 06:27:49 cfliu +* no message +* +* Revision 1.29 2003/04/30 15:32:30 cfliu +* move macros to types.h +* +* Revision 1.28 2003/03/13 10:29:22 cfliu +* Remove unused symbols +* +* Revision 1.27 2003/03/06 05:00:04 cfliu +* Move '#pragma ghs inlineprologue' to rtl_depend.h since it is compiler dependent +* +* Revision 1.26 2003/03/06 03:41:46 danwu +* Prevent compiler from generating internal sub-routine call code at the +* function prologue and epilogue automatically +* +* Revision 1.25 2003/03/03 09:16:35 hiwu +* remove ip4a +* +* Revision 1.24 2003/02/18 10:04:06 jzchen +* Add ether_addr_t to compatable with protocol stack's ether_addr +* +* Revision 1.23 2003/01/21 05:59:51 cfliu +* add min, max, SETBITS, CLEARBITS, etc. +* +* Revision 1.22 2002/11/25 07:31:30 cfliu +* Remove _POSIX_SOURCE since it is cygwin specific +* +* Revision 1.21 2002/09/30 11:51:49 jzchen +* Add ASSERT_ISR for not print inside ISR +* +* Revision 1.20 2002/09/18 01:43:24 jzchen +* Add type limit definition +* +* Revision 1.19 2002/09/16 00:14:34 elvis +* remove struct posix_handle_t (change the handle type from +* structure to uint32) +* +* Revision 1.18 2002/08/20 01:40:40 danwu +* Add definitions of ipaddr_t & macaddr_t. +* +* Revision 1.17 2002/07/30 04:36:30 danwu +* Add ASSERT_CSP. +* +* Revision 1.16 2002/07/19 06:47:30 cfliu +* Add _POSIX_SOURCE symbol +* +* Revision 1.15 2002/07/05 02:10:39 elvis +* Add new types for OSK +* +* Revision 1.14 2002/07/03 12:36:21 orlando +* <rtl_depend.h> will use type definitions. Has to be moved to +* be after the type declaration lines. +* +* Revision 1.13 2002/07/03 09:19:00 cfliu +* Removed all standard header files from source code. They would be included by <core/types.h>-><rtl_depend.h> +* +* Revision 1.12 2002/07/03 09:16:48 cfliu +* Removed all standard header files from source code. They would be included by <core/types.h>-><rtl_depend.h> +* +* Revision 1.11 2002/07/03 07:14:47 orlando +* Add "struct posix_handle_t_", used by POSIX module. +* +* Revision 1.9 2002/06/21 03:15:36 cfliu +* Add time.h for struct timeval +* +* Revision 1.8 2002/06/14 01:58:03 cfliu +* Move sa_family_t to socket +* +* Revision 1.7 2002/06/13 09:37:42 cfliu +* Move byte order conversion routines to socket +* +* Revision 1.6 2002/05/23 04:24:37 hiwu +* change memaddr_t to calladdr_t +* +* Revision 1.5 2002/05/13 10:15:16 hiwu +* add new type definition +* +* Revision 1.4 2002/05/09 05:21:51 cfliu +* Add parenthesis around swaps16, swapl32 +* +* Revision 1.3 2002/04/30 03:07:34 orlando +* Remove UIxx_T definitions to conform with new +* naming conventions. +* +* Revision 1.2 2002/04/29 10:10:32 hiwu +* add NTOHS macro +* +* Revision 1.1.1.1 2002/04/26 08:53:53 orlando +* Initial source tree creation. +* +* Revision 1.9 2002/04/25 03:59:05 cfliu +* no message +* +* Revision 1.8 2002/04/08 08:08:04 hiwu +* initial version +* +*/ + + +#ifndef _RTL_TYPES_H +#define _RTL_TYPES_H + +/* + * Internal names for basic integral types. Omit the typedef if + * not possible for a machine/compiler combination. + */ +#ifdef __linux__ +#ifdef __KERNEL__ +#include <linux/version.h> +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) +#include <linux/config.h> +#endif +#include <linux/ctype.h> +#include <linux/module.h> +#include <linux/string.h> +#endif /*__KERNEL__*/ +#endif /*__linux__*/ + +/* =============================================================================== + IRAM / DRAM definition + =============================================================================== */ +#undef __DRAM_GEN +#undef __DRAM_FWD +#undef __DRAM_L2_FWD +#undef __DRAM_L34_FWD +#undef __DRAM_EXTDEV +#undef __DRAM_AIRGO +#undef __DRAM_RTKWLAN +#undef __DRAM_CRYPTO +#undef __DRAM_VOIP +#undef __DRAM_TX +#undef __DRAM + +#undef __IRAM_GEN +#undef __IRAM_FWD +#undef __IRAM_L2_FWD +#undef __IRAM_L34_FWD +#undef __IRAM_EXTDEV +#undef __IRAM_AIRGO +#undef __IRAM_RTKWLAN +#undef __IRAM_CRYPTO +#undef __IRAM_VOIP +#undef __IRAM_TX +#undef __IRAM + +#if defined(__linux__)&&defined(__KERNEL__)&&defined(CONFIG_RTL865X) + #define __DRAM_GEN __attribute__ ((section(".dram-gen"))) + #define __DRAM_FWD __attribute__ ((section(".dram-fwd"))) + #define __DRAM_L2_FWD __attribute__ ((section(".dram-l2-fwd"))) + #define __DRAM_L34_FWD __attribute__ ((section(".dram-l34-fwd"))) + #define __DRAM_EXTDEV __attribute__ ((section(".dram-extdev"))) + #define __DRAM_AIRGO __attribute__ ((section(".dram-airgo"))) + #define __DRAM_RTKWLAN __attribute__ ((section(".dram-rtkwlan"))) + #define __DRAM_CRYPTO __attribute__ ((section(".dram-crypto"))) + #define __DRAM_VOIP __attribute__ ((section(".dram-voip"))) + #define __DRAM_TX __attribute__ ((section(".dram-tx"))) + #define __DRAM __attribute__ ((section(".dram"))) + + #define __IRAM_GEN __attribute__ ((section(".iram-gen"))) + #define __IRAM_FWD __attribute__ ((section(".iram-fwd"))) + #define __IRAM_L2_FWD __attribute__ ((section(".iram-l2-fwd"))) + #define __IRAM_L34_FWD __attribute__ ((section(".iram-l34-fwd"))) + #define __IRAM_EXTDEV __attribute__ ((section(".iram-extdev"))) + #define __IRAM_AIRGO __attribute__ ((section(".iram-airgo"))) + #define __IRAM_RTKWLAN __attribute__ ((section(".iram-rtkwlan"))) + #define __IRAM_CRYPTO __attribute__ ((section(".iram-crypto"))) + #define __IRAM_VOIP __attribute__ ((section(".iram-voip"))) + #define __IRAM_TX __attribute__ ((section(".iram-tx"))) + #define __IRAM __attribute__ ((section(".iram"))) +#else + #define __DRAM_GEN + #define __DRAM_FWD + #define __DRAM_L2_FWD + #define __DRAM_L34_FWD + #define __DRAM_EXTDEV + #define __DRAM_AIRGO + #define __DRAM_RTKWLAN + #define __DRAM_CRYPTO + #define __DRAM_VOIP + #define __DRAM_TX + #define __DRAM + + #define __IRAM_GEN + #define __IRAM_FWD + #define __IRAM_L2_FWD + #define __IRAM_L34_FWD + #define __IRAM_EXTDEV + #define __IRAM_AIRGO + #define __IRAM_RTKWLAN + #define __IRAM_CRYPTO + #define __IRAM_VOIP + #define __IRAM_TX + #define __IRAM +#endif + +#if defined(CONFIG_RTL_DYNAMIC_IRAM_MAPPING_FOR_WAPI) + #define __IRAM_GEN_WAPI __attribute__ ((section(".iram-gen-wapi"))) + #define __IRAM_FWD_WAPI __attribute__ ((section(".iram-fwd-wapi"))) + #define __IRAM_L2_FWD_WAPI __attribute__ ((section(".iram-l2-fwd-wapi"))) + #define __IRAM_L34_FWD_WAPI __attribute__ ((section(".iram-l34-fwd-wapi"))) + #define __IRAM_RTKWLAN_WAPI __attribute__ ((section(".iram-rtkwlan-wapi"))) + #define __IRAM_TX_WAPI __attribute__ ((section(".iram-tx-wapi"))) + + #define FUNCTION_CHECK(x) do \ + { \ + if((x)==NULL) \ + printk("---%s %s(%d) function is NULL!!\n",__FILE__,__FUNCTION__,__LINE__); \ + } while(0) +#endif + +/* =============================================================================== + print macro + =============================================================================== */ +#if defined(__linux__)&&defined(__KERNEL__) + + #define rtlglue_printf printk + +#else /* defined(__linux__)&&defined(__KERNEL__) */ + +#ifdef RTL865X_TEST + #include <ctype.h> +#endif /* RTL865X_TEST */ + +#define rtlglue_printf printf + +#endif /* defined(__linux__)&&defined(__KERNEL__) */ + +/* =============================================================================== + Type definition + =============================================================================== */ + +typedef unsigned long long uint64; +typedef long long int64; +typedef unsigned int uint32; +typedef int int32; +typedef unsigned short uint16; +typedef short int16; +typedef unsigned char uint8; +typedef char int8; + + +typedef uint32 memaddr; +typedef uint32 ipaddr_t; +typedef struct { + uint16 mac47_32; + uint16 mac31_16; + uint16 mac15_0; +} macaddr_t; + +#define ETHER_ADDR_LEN 6 +typedef struct ether_addr_s { + uint8 octet[ETHER_ADDR_LEN]; +} ether_addr_t; + + + +#ifndef NULL +#define NULL 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAILED +#define FAILED -1 +#endif + + + +#define DEBUG_P(args...) while(0); +#ifndef OK +#define OK 0 +#endif +#ifndef NOT_OK +#define NOT_OK 1 +#endif + +#ifndef CLEARBITS +#define CLEARBITS(a,b) ((a) &= ~(b)) +#endif + +#ifndef SETBITS +#define SETBITS(a,b) ((a) |= (b)) +#endif + +#ifndef ISSET +#define ISSET(a,b) (((a) & (b))!=0) +#endif + +#ifndef ISCLEARED +#define ISCLEARED(a,b) (((a) & (b))==0) +#endif + +#ifndef max +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#endif /* max */ + +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif /* min */ + +//round down x to multiple of y. Ex: ROUNDDOWN(20, 7)=14 +#ifndef ROUNDDOWN +#define ROUNDDOWN(x, y) (((x)/(y))*(y)) +#endif + +//round up x to multiple of y. Ex: ROUNDUP(11, 7) = 14 +#ifndef ROUNDUP +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ +#endif + +#ifndef ROUNDUP2 +#define ROUNDUP2(x, y) (((x)+((y)-1))&(~((y)-1))) /* if y is powers of two */ +#endif + +#ifndef ROUNDUP4 +#define ROUNDUP4(x) ((1+(((x)-1)>>2))<<2) +#endif + +#ifndef IS4BYTEALIGNED +#define IS4BYTEALIGNED(x) ((((x) & 0x3)==0)? 1 : 0) +#endif + +#ifndef __offsetof +#define __offsetof(type, field) ((unsigned long)(&((type *)0)->field)) +#endif + +#ifndef offsetof +#define offsetof(type, field) __offsetof(type, field) +#endif + +#ifndef RTL_PROC_CHECK +#define RTL_PROC_CHECK(expr, success) \ + do {\ + int __retval; \ + if ((__retval = (expr)) != (success))\ + {\ + rtlglue_printf("ERROR >>> [%s]:[%d] failed -- return value: %d\n", __FUNCTION__,__LINE__, __retval);\ + return __retval; \ + }\ + }while(0) +#endif + +#ifndef RTL_STREAM_SAME +#define RTL_STREAM_SAME(s1, s2) \ + ((strlen(s1) == strlen(s2)) && (strcmp(s1, s2) == 0)) +#endif + +#define ASSERT_ISR(x) if(!(x)) {while(1);} +#define RTL_STATIC_INLINE static __inline__ + +#define ASSERT_CSP(x) if (!(x)) {rtlglue_printf("\nAssert Fail: %s %d", __FILE__, __LINE__); while(1);} + +#if defined(RTL865X_TEST) || defined(RTL865X_MODEL_USER) +/* Only model code needs to define the following code. */ +typedef struct { } spinlock_t; +typedef uint8 u8; +typedef uint16 u16; +typedef uint32 u32; +#endif + +#if defined(DRTL_TBLDRV)||defined(RTL865X_TEST) +//only ROME driver and module test code need to include this header file +#include "rtl_glue.h" +#endif + +#if defined(RTL865X_TEST)||defined(RTL865X_MODEL_USER) +#define UNCACHE_MASK 0 +#define UNCACHE(addr) (addr) +#define CACHED(addr) ((uint32)(addr)) +#else +#define UNCACHE_MASK 0x20000000 +#define UNCACHE(addr) ((UNCACHE_MASK)|(uint32)(addr)) +#define CACHED(addr) ((uint32)(addr) & ~(UNCACHE_MASK)) +#endif + + +#define swapl32(x)\ + ((((x) & 0xff000000U) >> 24) | \ + (((x) & 0x00ff0000U) >> 8) | \ + (((x) & 0x0000ff00U) << 8) | \ + (((x) & 0x000000ffU) << 24)) +#define swaps16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) + +#ifdef _LITTLE_ENDIAN + +/*#ifndef __linux__*/ + #define ntohs(x) (swaps16(x)) + #define ntohl(x) (swapl32(x)) + #define htons(x) (swaps16(x)) + #define htonl(x) (swapl32(x)) +/*#endif*/ + #define NTOHL(d) ((d) = ntohl((d))) + #define NTOHS(d) ((d) = ntohs((uint16)(d))) + #define HTONL(d) ((d) = htonl((d))) + #define HTONS(d) ((d) = htons((uint16)(d))) + + #define GET_UINT16_UNALIGNED( ptr ) GET_UINT16_LITTLE_ENDIAN_UNALIGNED(ptr) + #define SET_UINT16_UNALIGNED( u16value, ptr ) SET_UINT16_LITTLE_ENDIAN_UNALIGNED( u16value, ptr ) + #define GET_UINT32_UNALIGNED( ptr ) GET_UINT32_LITTLE_ENDIAN_UNALIGNED(ptr) + #define SET_UINT32_UNALIGNED( u32value, ptr ) SET_UINT32_LITTLE_ENDIAN_UNALIGNED( u32value,ptr) + #define PKTGET_UINT16_UNALIGNED( ptr ) GET_UINT16_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT16_UNALIGNED( u16value, ptr ) SET_UINT16_BIG_ENDIAN_UNALIGNED( u16value, ptr ) + #define PKTGET_UINT32_UNALIGNED( ptr ) GET_UINT32_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT32_UNALIGNED( u32value, ptr ) SET_UINT32_BIG_ENDIAN_UNALIGNED( u32value,ptr) + +#else /*Big endian system */ + +/* chhuang */ +#ifdef __linux__ + #undef ntohs + #undef ntohl + #undef htons + #undef htonl + #define ntohs(x) (x) + #define ntohl(x) (x) + #define htons(x) (x) + #define htonl(x) (x) + #define _LINUX_BYTEORDER_GENERIC_H +#endif /* __linux__ */ + #define NTOHL(d) ((d) = ntohl(d)) + #define NTOHS(d) ((d) = ntohs((uint16)(d))) + #define HTONL(d) ((d) = htonl(d)) + #define HTONS(d) ((d) = htons((uint16)(d))) + #define GET_UINT16_UNALIGNED( ptr ) GET_UINT16_BIG_ENDIAN_UNALIGNED(ptr) + #define SET_UINT16_UNALIGNED( u16value, ptr ) SET_UINT16_BIG_ENDIAN_UNALIGNED( u16value, ptr ) + #define GET_UINT32_UNALIGNED( ptr ) GET_UINT32_BIG_ENDIAN_UNALIGNED(ptr) + #define SET_UINT32_UNALIGNED( u32value, ptr ) SET_UINT32_BIG_ENDIAN_UNALIGNED( u32value,ptr) + #define PKTGET_UINT16_UNALIGNED( ptr ) GET_UINT16_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT16_UNALIGNED( u16value, ptr) SET_UINT16_BIG_ENDIAN_UNALIGNED( u16value, ptr ) + #define PKTGET_UINT32_UNALIGNED( ptr ) GET_UINT32_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT32_UNALIGNED( u32value, ptr) SET_UINT32_BIG_ENDIAN_UNALIGNED( u32value,ptr) +#endif + +#endif/*_LITTLE_ENDIAN*/ + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_utils.h b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_utils.h new file mode 100644 index 000000000..767432f5f --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mach-realtek/rtl_utils.h @@ -0,0 +1,80 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2002 +* All rights reserved. +* +* Program : Header File for RTL utilities +* Abstract : +* Author : +* $Id: rtl_utils.h,v 1.1.1.1 2007-11-12 13:27:50 alva_zhang Exp $ +*/ + +#ifndef __RTL_UTILS_H__ +#define __RTL_UTILS_H__ + +#include "rtl_types.h" + + + +void __strlowerncpy(char *dst, const char *src, int32 len); +int8 *_strncpy(int8 *dst0, const int8 *src0, int32 count); +int _strncasecmp(const char *s1, const char *s2, unsigned int n); +int32 _strncmp(const int8 *s1, const int8 *s2, int32 n); +void rtl8651_memcpy(void *dst,void*src,int32 len); +int32 isPowerOf2(uint32 number, uint32 *exponent); +int32 IpStrToAscii(const int8 *cp, uint32 *addr); +void IntToAscii(int32 n, int8 s[]); +int AsciiToInt( char **s); +uint8 charToInt(char c); +int32 ether_aton_r(int8 *a, ether_addr_t *eth); +int32 ether_ntoa_r(ether_addr_t *n, uint8 *a); +int8 *inet_ntoa_r(ipaddr_t ipaddr, int8 *p); +void memDump (void *start, uint32 size, int8 * strHeader); +int32 memComp( void* _p1, void *_p2, int32 len, uint8* strHeader ); +uint8* strtomac(ether_addr_t *mac, int8 *str); + +#define PROFILING_START(x) do{}while(0) +#define PROFILING_END(x) do{}while(0) + + + +/*=================================================================== + * ONE's COMPLEMENT OPERATION + * All the operands and return value are 'host-order'. + * Please notice the endian problem. + *===================================================================*/ +/* One's Complement ADD */ +inline static uint16 OCADD( uint16 a, uint16 b ) +{ + uint32 t; /* temp */ + t = ((a)&0xffff)+((b)&0xffff); + t = (t&0xffff)+(t>>16); + return (uint16)t; +} + +/* One's Complement NEGtive */ +inline static uint16 OCNEG( uint16 a ) +{ + return (~a)&0xffff; +} + +/* One's Complement SUBtract */ +inline static uint16 OCSUB( uint16 a, uint16 b ) +{ + return OCADD( a, OCNEG(b) ); +} + +ipaddr_t convPrefix(int prefixLen); + + +#if defined(RTL8389_MODEL_USER) + /* User mode, compiler use STDINC, said that, bezro is defined. */ +#else + /* Not user mode, we need define. */ + #ifndef bzero + #define bzero( p, s ) memset( p, 0, s ) + #endif +#endif + + +#endif /* __RTL_UTILS_H__ */ + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8196b/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8196b/platform.h new file mode 100644 index 000000000..3faab2692 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8196b/platform.h @@ -0,0 +1,376 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+#define CONFIG_RTL_TIMER_ADJUSTMENT
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG16(reg) (*(volatile unsigned short *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+#define WRITE_MEM32(addr, val) (*(volatile unsigned int *) (addr)) = (val)
+#define READ_MEM32(addr) (*(volatile unsigned int *) (addr))
+#define WRITE_MEM16(addr, val) (*(volatile unsigned short *) (addr)) = (val)
+#define READ_MEM16(addr) (*(volatile unsigned short *) (addr))
+#define WRITE_MEM8(addr, val) (*(volatile unsigned char *) (addr)) = (val)
+#define READ_MEM8(addr) (*(volatile unsigned char *) (addr))
+
+#define PADDR(addr) ((addr) & 0x1FFFFFFF)
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 200
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define PCIB0TMO_IRQ 0
+#define PCIB1TMO_IRQ 1
+#define LBCTMOm0_IRQ 2
+#define LBCTMOm1_IRQ 3
+#define LBCTMOs_IRQ 4
+#define TC0_IRQ 8
+#define TC1_IRQ 9
+#define USB_IRQ 10
+#define UART0_IRQ 12
+#define UART1_IRQ 13
+#define PCI_IRQ 14
+#define SWCORE_IRQ 15
+#define GPIO_ABCD_IRQ 16
+#define GPIO_EFGH_IRQ 17
+#define HCI_IRQ 18
+#define PCM_IRQ 19
+#define CRYPTO_IRQ 20
+#define GDMA_IRQ 23
+#define PCIE2_IRQ 22
+#define PCIE_IRQ 21 // shall be 22
+
+/*
+ * Interrupt Routing Selection
+ */
+#define PTM_RS 2
+#define LBCTMOs2_RS 2
+#define LBCTMOs1_RS 2
+#define PKT_RS 2
+#define SPI_RS 2
+#define NIC100_RS 2
+#define SAR_RS 2
+#define DMT_RS 2
+#define PCIE2_RS 4
+#define PCIE_RS 5
+#define GDMA_RS 2
+#define SECURITY_RS 2
+#define PCM_RS 2
+#define NFBI_RS 2
+#define GPIO_EFGH_RS 2
+#define GPIO_ABCD_RS 2
+#define SW_RS 6
+#define PCI_RS 3
+#define UART1_RS 2
+#define UART0_RS 2
+#define USB_D_RS 2
+#define USB_H_RS 4
+#define TC1_RS 2
+#define TC0_RS 7
+#define LBCTMOm2_RS 2
+#define LBCTMOm1_RS 2
+#define SPEED_RS 2
+#define LBCTMOs0_RS 2
+#define LBCTMOm0_RS 2
+#define OCPTMO_RS 2
+#define PCIB0TO_RS 2
+#define NONE 2
+#define PCIB0TMO_RS 2
+#define PCIB1TMO_RS 2
+#define LBCTMOs_RS 2
+
+
+#define HCI_RS 2
+#define CRYPTO_RS 2
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C03FFF
+
+#define DMEM_BASE 0x00C04000
+#define DMEM_TOP 0x00C05FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x92A28000
+
+#define MC_MTCR0 0xB8001004
+ #define MC_MTCR0_VAL 0x12120000
+
+#define MC_MTCR1 0xB8001008
+ #define MC_MTCR1_VAL 0x00000FEB
+
+#define MC_PFCR 0xB8001010
+ #define MC_PFCR_VAL 0x00000101
+
+
+#define MC_BASE 0xB8001000
+#define NCR (MC_BASE + 0x100)
+#define NSR (MC_BASE + 0x104)
+#define NCAR (MC_BASE + 0x108)
+#define NADDR (MC_BASE + 0x10C)
+#define NDR (MC_BASE + 0x110)
+
+#define SFCR (MC_BASE + 0x200)
+#define SFDR (MC_BASE + 0x204)
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_MAP_BASE 0x18002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define GDMA_IE (1 << 23)
+ #define PCIE2_IE (1 << 22)
+ #define PCIE_IE (1 << 21) // shall be 22
+ #define CRYPTO_IE (1 << 20)
+ #define PCM_IE (1 << 19)
+ #define HCI_IE (1 << 18)
+ #define GPIO_EFGH_IE (1 << 17)
+ #define GPIO_ABCD_IE (1 << 16)
+ #define SW_IE (1 << 15)
+ #define PCI_IE (1 << 14)
+ #define UART1_IE (1 << 13)
+ #define UART0_IE (1 << 12)
+ #define USB_H_IE (1 << 10)
+ #define TC1_IE (1 << 9)
+ #define TC0_IE (1 << 8)
+ #define LBCTMOs_IE (1 << 4)
+ #define LBCTMOm1_IE (1 << 3)
+ #define LBCTMOm0_IE (1 << 2)
+ #define PCIB1TO_IE (1 << 1)
+ #define PCIB0TO_IE (1 << 0)
+
+#define GISR 0xB8003004
+ #define GDMA_IP (1 << 23)
+ #define PCIE2_IP (1 << 22)
+ #define PCIE_IP (1 << 21) // shall be 22
+ #define CRYPTO_IP (1 << 20)
+ #define PCM_IP (1 << 19)
+ #define HCI_IP (1 << 18)
+ #define GPIO_EFGH_IP (1 << 17)
+ #define GPIO_ABCD_IP (1 << 16)
+ #define SW_IP (1 << 15)
+ #define PCI_IP (1 << 14)
+ #define UART1_IP (1 << 13)
+ #define UART0_IP (1 << 12)
+ #define USB_H_IP (1 << 10)
+ #define TC1_IP (1 << 9)
+ #define TC0_IP (1 << 8)
+ #define LBCTMOs_IP (1 << 4)
+ #define LBCTMOm1_IP (1 << 3)
+ #define LBCTMOm0_IP (1 << 2)
+ #define PCIB1TO_IP (1 << 1)
+ #define PCIB0TO_IP (1 << 0)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((LBCTMOm2_RS << 28) | \
+ (LBCTMOm1_RS << 24) | \
+ (SPEED_RS << 20) | \
+ (LBCTMOs0_RS << 16) | \
+ (LBCTMOm0_RS << 12) | \
+ (OCPTMO_RS << 8) | \
+ (NONE << 4) | \
+ (PCIB0TO_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((SW_RS << 28) | \
+ (PCIE_RS << 24) | \
+ (UART1_RS << 20) | \
+ (UART0_RS << 16) | \
+ (USB_D_RS << 12) | \
+ (USB_H_RS << 8) | \
+ (TC1_RS << 4) | \
+ (TC0_RS << 0) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING ((GDMA_RS << 28) | \
+ (PCIE2_RS << 24) | \
+ (PCIE_RS << 20) | \
+ (SECURITY_RS << 16) | \
+ (PCM_RS << 12) | \
+ (NFBI_RS << 8) | \
+ (GPIO_EFGH_RS << 4) | \
+ (GPIO_ABCD_RS << 0) \
+ )
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING ((PTM_RS << 28) | \
+ (LBCTMOs2_RS << 24) | \
+ (LBCTMOs1_RS << 20) | \
+ (PKT_RS << 16) | \
+ (SPI_RS << 12) | \
+ (NIC100_RS << 8) | \
+ (SAR_RS << 4) | \
+ (DMT_RS << 0) \
+ )
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+/*
+ * HCI
+ */
+#define HCI_BASE 0xB8007000
+#define HCI_GCR (HCI_BASE + 0x00)
+#define HCI_TRFFDR (HCI_BASE + 0x04)
+#define HCI_TRFFAR (HCI_BASE + 0x08)
+#define HCI_FFCR_CS(i) (HCI_BASE + 0x0C + ((i) << 2))
+#define HCI_IER_CS(i) (HCI_BASE + 0x1C + ((i) << 2))
+#define HCI_LSR_CS(i) (HCI_BASE + 0x2C + ((i) << 2))
+#define HCI_CR_CS(i) (HCI_BASE + 0x3C + ((i) << 2))
+#define HCI_TR_CS(i) (HCI_BASE + 0x4C + ((i) << 2))
+/*
+ * PCIE Host Controller
+ */
+#define PCIE0_H_CFG 0xB8B00000
+#define PCIE0_H_EXT 0xB8B01000
+#define PCIE0_H_MDIO (PCIE0_H_EXT + 0x00)
+#define PCIE0_H_INTSTR (PCIE0_H_EXT + 0x04)
+#define PCIE0_H_PWRCR (PCIE0_H_EXT + 0x08)
+#define PCIE0_H_IPCFG (PCIE0_H_EXT + 0x0C)
+#define PCIE0_H_MISC (PCIE0_H_EXT + 0x10)
+#define PCIE0_D_CFG0 0xB8B10000
+#define PCIE0_D_CFG1 0xB8B11000
+#define PCIE0_D_MSG 0xB8B12000
+
+#define PCIE1_H_CFG 0xB8B20000
+#define PCIE1_H_EXT 0xB8B21000
+#define PCIE1_H_MDIO (PCIE1_H_EXT + 0x00)
+#define PCIE1_H_INTSTR (PCIE1_H_EXT + 0x04)
+#define PCIE1_H_PWRCR (PCIE1_H_EXT + 0x08)
+#define PCIE1_H_IPCFG (PCIE1_H_EXT + 0x0C)
+#define PCIE1_H_MISC (PCIE1_H_EXT + 0x10)
+#define PCIE1_D_CFG0 0xB8B30000
+#define PCIE1_D_CFG1 0xB8B31000
+#define PCIE1_D_MSG 0xB8B32000
+
+#define PCIE0_D_IO 0xB8C00000
+#define PCIE1_D_IO 0xB8E00000
+#define PCIE0_D_MEM 0xB9000000
+#define PCIE1_D_MEM 0xBA000000
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8196b/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8196b/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8196b/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/hsModel.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/hsModel.h new file mode 100644 index 000000000..65879a4c9 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/hsModel.h @@ -0,0 +1,288 @@ +#ifndef _HS_MODEL_H_
+#define _HS_MODEL_H_
+
+#include "rtl_types.h"
+/* HSB (Header Stamp Before):
+ * Software-friendly structure definition */
+typedef struct hsb_param_s
+{
+ uint32 cfi:1; /* CFI */
+ uint32 patternMatch:2; /* MAC Ingress pattern match key. */
+ uint32 flowLabel:20; /* IPv6 Flow Lable */
+ uint32 dstPort:16; /* TCP/UDP Destination Port */
+ uint32 srcPort:16; /* TCP/UDP Source Port */
+ uint32 tcpFlags:8; /* TCP Flags */
+ uint32 ipProto:8; /* IP Protocol */
+ uint32 svid:12; /* SVID */
+ uint32 spri:3; /* S Priority */
+ uint32 rxDrop:1; /* ??? */
+ uint32 cpuTagif:1; /* If CPU tagged */
+ uint32 cpuIntPri:3; /* The Internal Priority in CPU tag, used for HSA */
+ uint32 cpuPortMask:28; /* The Port mask in CPU tag, used for HSA */
+ uint32 ethType:16; /* EtherType or Length */
+ uint32 ipv6MLD:1; /* IPv6 MLD control packet */
+ uint32 cpri:3; /* C Priority */
+ uint32 cvid:12; /* CVID */
+ uint32 dip:32; /* Destination IP Address */
+ uint32 sip:32; /* Source IP Address */
+ uint8 dmac[6]; /* Destination MAC */
+ uint8 smac[6]; /* Source MAC */
+ uint32 tos:8; /* TOS */
+ uint32 cpuasp:1; /* CPU Tag Assigns Internal Priority */
+ uint32 cpuasdpm:1; /* CPU Tag Assigns Destination Port Mask */
+ uint32 cpuaspRmk:1; /* CPU Tag Allows MAC Tx Remarking */
+ uint32 ipv6:1; /* IPv6 packet (ver=6) */
+ uint32 ipv4:1; /* IPv4 packet (ver=4) and length >= 20 bytes */
+ uint32 pppoe:1; /* PPPoE packet */
+ uint32 stagif:1; /* If SVID Tagged */
+ uint32 ctagif:1; /* If CVID Tagged (ethertype==0x8100) */
+ uint32 frameType:2; /* 0:Ethrnet;1:RFC1042;2-LLC_Other ??? */
+ uint32 pktLen:14; /* Packet Length (included CRC) */
+ uint32 l4csok:1; /* L4 Checksum OK */
+ uint32 l3csok:1; /* L3 Checksum OK */
+ uint32 endPage:11; /* the last page address of packet */
+ uint32 startPage:11; /* the first page address of packet */
+ uint32 startBank:3; /* the first bank of packet */
+ uint32 spa:5; /* Source Port Address (physical) */
+}hsb_param_t;
+
+/* HSA (Header Stamp After):
+ * Software-friendly structure definition */
+typedef struct hsa_param_s
+{
+ uint32 newsvid:12; /* New SVID */
+ uint32 newcvid:12; /* New CVID*/
+ uint32 cpuTagif:1; /* If CPU tagged */
+ uint32 dpCnt:5; /* Destination Port Count */
+ uint32 rvid:12; /* Relay VID */
+ uint32 reason:16; /* CPU reason */
+ uint32 intPri:3; /* Internal Priority */
+ uint32 dpMask:29; /* Destination Port Mask */
+ uint32 mir1dpa:5; /* Physical Port Address of the egress mirrored port 1 (30-ingress matched, 31-not hit) */
+ uint32 mir0dpa:5; /* Physical Port Address of the egress mirrored port 0 (30-ingress matched, 31-not hit) */
+ uint32 cpuaspRmk:1; /* CPU Tag Allows MAC Tx Remarking */
+ uint32 ipv6:1; /* IPv6 packet (ver=6) */
+ uint32 ipv4:1; /* IPv4 packet (ver=4)*/
+ uint32 pppoe:1; /* PPPoE packet */
+ uint32 stagif:1; /* If SVID Tagged */
+ uint32 ctagif:1; /* If CVID Tagged */
+ uint32 frameType:2; /* 0:Ethrnet;1:RFC1042;2-LLC_Other ??? */
+ uint32 pktLen:14; /* Packet Length (included CRC) */
+ uint32 l4csok:1; /* L4 Checksum OK */
+ uint32 l3csok:1; /* L3 Checksum OK */
+ uint32 endPage:11; /* the last page address of packet */
+ uint32 startPage:11; /* the first page address of packet */
+ uint32 startBank:3; /* the first bank of packet */
+ uint32 spa:5; /* Source Port Address (physical) */
+}hsa_param_t;
+
+
+/* RAW HSB: Raw structure to access ASIC.
+ * The structure is directly mapped to ASIC, however, it is not friendly for software. */
+typedef struct hsb_table_s
+{
+#ifdef _BIG_ENDIAN
+ uint32 sel_hsb:1; /* W0[31] */
+ uint32 valid_hsb:1; /* W0[30] */
+ uint32 reserved:7; /* W0[29:23] */
+ uint32 cfi:1; /* W0[22] */
+ uint32 patternmatch:2; /* W0[21:20] */
+ uint32 flowlabel:20; /* W0[19:0] */
+#else
+ uint32 flowlabel:20; /* W0[19:0] */
+ uint32 patternmatch:2; /* W0[21:20] */
+ uint32 cfi:1; /* W0[22] */
+ uint32 resevered:7; /* W0[29:23] */
+ uint32 valid_hsb:1; /* W0[30] */
+ uint32 sel_hsb:1; /* W0[31] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 dstport:16; /* W1[31:16] */
+ uint32 srcport:16; /* W1[15:0] */
+#else
+ uint32 srcport:16; /* W1[15:0] */
+ uint32 dstport:16; /* W1[31:16] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 tcpflags:8; /* W2[31:24] */
+ uint32 ipproto:8; /* W2[23:16] */
+ uint32 svid:12; /* W2[15:4] */
+ uint32 spri:3; /* W2[3:1] */
+ uint32 rxdrop:1; /* W2[0] */
+#else
+ uint32 rxdrop:1; /* W2[0] */
+ uint32 spri:3; /* W2[3:1] */
+ uint32 svid:12; /* W2[15:4] */
+ uint32 ipproto:8; /* W2[23:16] */
+ uint32 tcpflags:8; /* W2[31:24] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 cputagif:1; /* W3[31] */
+ uint32 cpuintpri:3; /* W3[30:28] */
+ uint32 cpuportmask:28; /* W3[27:0] */
+#else
+ uint32 cpuportmask:28; /* W3[27:0] */
+ uint32 cpuintpri:3; /* W3[30:28] */
+ uint32 cputagif:1; /* W3[31] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 ethertype:16; /* W4[31:16] */
+ uint32 ipv6mld:1; /* W4[15] */
+ uint32 cpri:3; /* W4[14:12] */
+ uint32 cvid:12; /* W4[11:0] */
+#else
+ uint32 cvid:12; /* W4[11:0] */
+ uint32 cpri:3; /* W4[14:12] */
+ uint32 ipv6mld:1; /* W4[15] */
+ uint32 ethertype:16; /* W4[31:16] */
+#endif
+
+ uint32 dip; /* W5[31:0] */
+ uint32 sip; /* W6[31:0] */
+ uint32 dmac47_16; /* W7[31:0] */
+
+#ifdef _BIG_ENDIAN
+ uint32 dmac15_0:16; /* W8[31:16] */
+ uint32 smac47_32:16; /* W8[15:0] */
+#else
+ uint32 smac47_32:16; /* W8[15:0] */
+ uint32 dmac15_0:16; /* W8[31:16] */
+#endif
+
+ uint32 smac31_0; /* W9[31:0] */
+
+#ifdef _BIG_ENDIAN
+ uint32 tos:8; /* W10[31:24] */
+ uint32 cpuasp:1; /* W10[23] */
+ uint32 cpuasdpm:1; /* W10[22] */
+ uint32 cpuasprmk:1; /* W10[21] */
+ uint32 ipv6:1; /* W10[20] */
+ uint32 ipv4:1; /* W10[19] */
+ uint32 pppoe:1; /* W10[18] */
+ uint32 stagif:1; /* W10[17] */
+ uint32 ctagif:1; /* W10[16] */
+ uint32 frametype:2; /* W10[15:14] */
+ uint32 pktlen:14; /* W10[13:0] */
+#else
+ uint32 pktlen:14; /* W10[13:0] */
+ uint32 frametype:2; /* W10[15:14] */
+ uint32 ctagif:1; /* W10[16] */
+ uint32 stagif:1; /* W10[17] */
+ uint32 pppoe:1; /* W10[18] */
+ uint32 ipv4:1; /* W10[19] */
+ uint32 ipv6:1; /* W10[20] */
+ uint32 cpuasprmk:1; /* W10[21] */
+ uint32 cpuasdpm:1; /* W10[22] */
+ uint32 cpuasp:1; /* W10[23] */
+ uint32 tos:8; /* W10[31:24] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 l4csok:1; /* W11[31] */
+ uint32 l3csok:1; /* W11[30] */
+ uint32 endpage:11; /* W11[29:19] */
+ uint32 startpage:11; /* W11[18:8] */
+ uint32 startbank:3; /* W11[7:5] */
+ uint32 spa:5; /* W11[4:0] */
+#else
+ uint32 spa:5; /* W11[4:0] */
+ uint32 startbank:3; /* W11[7:5] */
+ uint32 startpage:11; /* W11[18:8] */
+ uint32 endpage:11; /* W11[29:19] */
+ uint32 l3csok:1; /* W11[30] */
+ uint32 l4csok:1; /* W11[31] */
+#endif
+} hsb_table_t;
+
+/* RAW HSA: Raw structure to access ASIC.
+ * The structure is directly mapped to ASIC, however, it is not friendly for software. */
+typedef struct hsa_table_s
+{
+#ifdef _BIG_ENDIAN
+ uint32 hsa_busy:1; /* W0[31] */
+ uint32 reserved:5; /* W0[30:26] */
+ uint32 newsvid:12; /* W0[25:14] */
+ uint32 newcvid:12; /* W0[13:2] */
+ uint32 cputagif:1; /* W0[1] */
+ uint32 dpcnt4_4:1; /* W0[0] */
+#else
+ uint32 dpcnt4_4:1; /* W0[0] */
+ uint32 cputagif:1; /* W0[1] */
+ uint32 newcvid:12; /* W0[13:2] */
+ uint32 newsvid:12; /* W0[25:14] */
+ uint32 reserved:5; /* W0[30:26] */
+ uint32 hsa_busy:1; /* W0[31] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 dpcnt3_0:4; /* W1[31:28] */
+ uint32 rvid:12; /* W1[27:16] */
+ uint32 reason:16; /* W1[15:0] */
+#else
+ uint32 reason:16; /* W1[15:0] */
+ uint32 rvid:12; /* W1[27:16] */
+ uint32 dpcnt3_0:4; /* W1[31:28] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 intpri:3; /* W2[31:29] */
+ uint32 dpmask:29; /* W2[28:0] */
+#else
+ uint32 dpmask:29; /* W2[28:0] */
+ uint32 intpri:3; /* W2[31:29] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 mir1dpa:5; /* W3[31:27] */
+ uint32 mir0dpa:5; /* W3[26:22] */
+ uint32 cpuasdprmk:1; /* W3[21] */
+ uint32 ipv6:1; /* W3[20] */
+ uint32 ipv4:1; /* W3[19] */
+ uint32 pppoe:1; /* W3[18] */
+ uint32 stagif:1; /* W3[17] */
+ uint32 ctagif:1; /* W3[16] */
+ uint32 frametype:2; /* W3[15:14] */
+ uint32 pktlen:14; /* W3[13:0] */
+#else
+ uint32 pktlen:14; /* W3[13:0] */
+ uint32 frametype:2; /* W3[15:14] */
+ uint32 ctagif:1; /* W3[16] */
+ uint32 stagif:1; /* W3[17] */
+ uint32 pppoe:1; /* W3[18] */
+ uint32 ipv4:1; /* W3[19] */
+ uint32 ipv6:1; /* W3[20] */
+ uint32 cpuasdprmk:1; /* W3[21] */
+ uint32 mir0dpa:5; /* W3[26:22] */
+ uint32 mir1dpa:5; /* W3[31:27] */
+#endif
+
+#ifdef _BIG_ENDIAN
+ uint32 l4csok:1; /* W4[31] */
+ uint32 l3csok:1; /* W4[30] */
+ uint32 endpage:11; /* W4[29:19] */
+ uint32 startpage:11; /* W4[18:8] */
+ uint32 startbank:3; /* W4[7:5] */
+ uint32 spa:5; /* W4[4:0] */
+#else
+ uint32 spa:5; /* W4[4:0] */
+ uint32 startbank:3; /* W4[7:5] */
+ uint32 startpage:11; /* W4[18:8] */
+ uint32 endpage:11; /* W4[29:19] */
+ uint32 l3csok:1; /* W4[30] */
+ uint32 l4csok:1; /* W4[31] */
+#endif
+} hsa_table_t;
+
+
+
+extern int32 modelGetHsb(hsb_param_t* hsb);
+extern int32 modelSetHsb(hsb_param_t* hsb);
+extern int32 modelGetHsa(hsa_param_t* hsa);
+extern int32 modelSetHsa(hsa_param_t* hsa);
+
+#endif/*_HS_MODEL_H_*/
+
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/platform.h new file mode 100644 index 000000000..8d66ab514 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/platform.h @@ -0,0 +1,229 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 20
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define UART0_IRQ 31
+#define UART1_IRQ 30
+#define TC0_IRQ 29
+#define TC1_IRQ 28
+#define OCPTO_IRQ 27
+#define HLXTO_IRQ 26
+#define SLXTO_IRQ 25
+#define NIC_IRQ 24
+#define GPIO_ABCD_IRQ 23
+#define GPIO_EFGH_IRQ 22
+#define RTC_IRQ 21
+
+/*
+ * Interrupt Routing Selection
+ */
+#define UART0_RS 2
+#define UART1_RS 1
+#define TC0_RS 5
+#define TC1_RS 1
+#define OCPTO_RS 1
+#define HLXTO_RS 1
+#define SLXTO_RS 1
+#define NIC_RS 4
+#define GPIO_ABCD_RS 4
+#define GPIO_EFGH_RS 4
+#define RTC_RS 4
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x00000000
+
+#define MC_DCR 0xB8001004
+ #define MC_DCR0_VAL 0x54480000
+
+#define MC_DTCR 0xB8001008
+ #define MC_DTCR_VAL 0xFFFF05C0
+
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define UART0_IE (1 << 31)
+ #define UART1_IE (1 << 30)
+ #define TC0_IE (1 << 29)
+ #define TC1_IE (1 << 28)
+ #define OCPTO_IE (1 << 27)
+ #define HLXTO_IE (1 << 26)
+ #define SLXTO_IE (1 << 25)
+ #define NIC_IE (1 << 24)
+ #define GPIO_ABCD_IE (1 << 23)
+ #define GPIO_EFGH_IE (1 << 22)
+ #define RTC_IE (1 << 21)
+
+#define GISR 0xB8003004
+ #define UART0_IP (1 << 31)
+ #define UART1_IP (1 << 30)
+ #define TC0_IP (1 << 29)
+ #define TC1_IP (1 << 28)
+ #define OCPTO_IP (1 << 27)
+ #define HLXTO_IP (1 << 26)
+ #define SLXTO_IP (1 << 25)
+ #define NIC_IP (1 << 24)
+ #define GPIO_ABCD_IP (1 << 23)
+ #define GPIO_EFGH_IP (1 << 22)
+ #define RTC_IP (1 << 21)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((UART0_RS << 28) | \
+ (UART1_RS << 24) | \
+ (TC0_RS << 20) | \
+ (TC1_RS << 16) | \
+ (OCPTO_RS << 12) | \
+ (HLXTO_RS << 8) | \
+ (SLXTO_RS << 4) | \
+ (NIC_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((GPIO_ABCD_RS << 28) | \
+ (GPIO_EFGH_RS << 24) | \
+ (RTC_RS << 20) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING 0
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING 0
+
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8389/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8652/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8652/platform.h new file mode 100644 index 000000000..2a7d38374 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8652/platform.h @@ -0,0 +1,298 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 200
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define PCIB0TMO_IRQ 0
+#define PCIB1TMO_IRQ 1
+#define LBCTMOm0_IRQ 2
+#define LBCTMOm1_IRQ 3
+#define LBCTMOs_IRQ 4
+#define TC0_IRQ 8
+#define TC1_IRQ 9
+#define USB_IRQ 10
+#define UART0_IRQ 12
+#define UART1_IRQ 13
+#define PCI_IRQ 14
+#define SWCORE_IRQ 15
+#define GPIO_ABCD_IRQ 16
+#define GPIO_EFGH_IRQ 17
+#define HCI_IRQ 18
+#define PCM_IRQ 19
+#define CRYPTO_IRQ 20
+#define GDMA_IRQ 21
+
+/*
+ * Interrupt Routing Selection
+ */
+#define PCIB0TMO_RS 2
+#define PCIB1TMO_RS 2
+#define LBCTMOm0_RS 2
+#define LBCTMOm1_RS 2
+#define LBCTMOs_RS 2
+#define TC0_RS 7
+#define TC1_RS 2
+#define USB_H_RS 4
+#define UART0_RS 3
+#define UART1_RS 2
+#define PCI_RS 5
+#define SW_RS 6
+#define GPIO_ABCD_RS 2
+#define GPIO_EFGH_RS 2
+#define HCI_RS 2
+#define PCM_RS 2
+#define CRYPTO_RS 2
+#define GDMA_RS 2
+
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C03FFF
+
+#define DMEM_BASE 0x00C04000
+#define DMEM_TOP 0x00C05FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xB8001000
+ #define MC_MCR_VAL 0x92A28000
+
+#define MC_MTCR0 0xB8001004
+ #define MC_MTCR0_VAL 0x12120000
+
+#define MC_MTCR1 0xB8001008
+ #define MC_MTCR1_VAL 0x00000FEB
+
+#define MC_PFCR 0xB8001010
+ #define MC_PFCR_VAL 0x00000101
+
+
+#define MC_BASE 0xB8001000
+#define NCR (MC_BASE + 0x100)
+#define NSR (MC_BASE + 0x104)
+#define NCAR (MC_BASE + 0x108)
+#define NADDR (MC_BASE + 0x10C)
+#define NDR (MC_BASE + 0x110)
+
+#define SFCR (MC_BASE + 0x200)
+#define SFDR (MC_BASE + 0x204)
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xB8002000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xB8002100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xB8003000
+ #define GDMA_IE (1 << 21)
+ #define CRYPTO_IE (1 << 20)
+ #define PCM_IE (1 << 19)
+ #define HCI_IE (1 << 18)
+ #define GPIO_EFGH_IE (1 << 17)
+ #define GPIO_ABCD_IE (1 << 16)
+ #define SW_IE (1 << 15)
+ #define PCI_IE (1 << 14)
+ #define UART1_IE (1 << 13)
+ #define UART0_IE (1 << 12)
+ #define USB_H_IE (1 << 10)
+ #define TC1_IE (1 << 9)
+ #define TC0_IE (1 << 8)
+ #define LBCTMOs_IE (1 << 4)
+ #define LBCTMOm1_IE (1 << 3)
+ #define LBCTMOm0_IE (1 << 2)
+ #define PCIB1TO_IE (1 << 1)
+ #define PCIB0TO_IE (1 << 0)
+
+#define GISR 0xB8003004
+ #define GDMA_IP (1 << 21)
+ #define CRYPTO_IP (1 << 20)
+ #define PCM_IP (1 << 19)
+ #define HCI_IP (1 << 18)
+ #define GPIO_EFGH_IP (1 << 17)
+ #define GPIO_ABCD_IP (1 << 16)
+ #define SW_IP (1 << 15)
+ #define PCI_IP (1 << 14)
+ #define UART1_IP (1 << 13)
+ #define UART0_IP (1 << 12)
+ #define USB_H_IP (1 << 10)
+ #define TC1_IP (1 << 9)
+ #define TC0_IP (1 << 8)
+ #define LBCTMOs_IP (1 << 4)
+ #define LBCTMOm1_IP (1 << 3)
+ #define LBCTMOm0_IP (1 << 2)
+ #define PCIB1TO_IP (1 << 1)
+ #define PCIB0TO_IP (1 << 0)
+
+#define IRR0 0xB8003008
+#define IRR0_SETTING ((LBCTMOs_RS << 16) | \
+ (LBCTMOm1_RS << 12) | \
+ (LBCTMOm0_RS << 8) | \
+ (PCIB1TMO_RS << 4) | \
+ (PCIB0TMO_RS << 0) \
+ )
+
+#define IRR1 0xB800300C
+#define IRR1_SETTING ((SW_RS << 28) | \
+ (PCI_RS << 24) | \
+ (UART1_RS << 20) | \
+ (UART0_RS << 16) | \
+ (USB_H_RS << 8) | \
+ (TC1_RS << 4) | \
+ (TC0_RS << 0) \
+ )
+
+#define IRR2 0xB8003010
+#define IRR2_SETTING ((GDMA_RS << 20) | \
+ (CRYPTO_RS << 16) | \
+ (PCM_RS << 12) | \
+ (HCI_RS << 8) | \
+ (GPIO_EFGH_RS << 4) | \
+ (GPIO_ABCD_RS << 0) \
+ )
+
+#define IRR3 0xB8003014
+#define IRR3_SETTING 0
+
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xB8003100
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+/*
+ * HCI
+ */
+#define HCI_BASE 0xB8007000
+#define HCI_GCR (HCI_BASE + 0x00)
+#define HCI_TRFFDR (HCI_BASE + 0x04)
+#define HCI_TRFFAR (HCI_BASE + 0x08)
+#define HCI_FFCR_CS(i) (HCI_BASE + 0x0C + ((i) << 2))
+#define HCI_IER_CS(i) (HCI_BASE + 0x1C + ((i) << 2))
+#define HCI_LSR_CS(i) (HCI_BASE + 0x2C + ((i) << 2))
+#define HCI_CR_CS(i) (HCI_BASE + 0x3C + ((i) << 2))
+#define HCI_TR_CS(i) (HCI_BASE + 0x4C + ((i) << 2))
+
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8652/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8652/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl8652/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl865xb/platform.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl865xb/platform.h new file mode 100644 index 000000000..637c74b16 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl865xb/platform.h @@ -0,0 +1,260 @@ +#ifndef _PLATFORM_H
+#define _PLATFORM_H
+
+
+/*
+ * =============
+ * Utilty Macros
+ * =============
+ */
+#define REG8(reg) (*(volatile unsigned char *)((unsigned int)reg))
+#define REG32(reg) (*(volatile unsigned int *)((unsigned int)reg))
+
+
+/*
+ * ====================================
+ * Platform Configurable Common Options
+ * ====================================
+ */
+
+#define PROM_DEBUG 0
+
+#define MHZ 100
+#define SYSCLK MHZ * 1000 * 1000
+
+#define BAUDRATE 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
+ /* For Early Debug */
+
+/*
+ * Interrupt IRQ Assignments
+ */
+#define PCIBTMO_IRQ 16
+#define GPIO_DEFGHI_IRQ 17
+#define PCM_IRQ 18
+#define AUTH_IRQ 19
+#define CRYPTO_IRQ 20
+#define LBCTMO_IRQ 21
+#define EXT_IRQ 23
+#define GPIO_ABC_IRQ 24
+#define SWCORE_IRQ 25
+#define PCI_IRQ 26
+#define UART1_IRQ 27
+#define UART0_IRQ 28
+#define PCMCIA_IRQ 29
+#define USB_IRQ 30
+#define TC_IRQ 31
+
+/*
+ * Interrupt Routing Selection
+ */
+#define PCIBTMO_RS 0
+#define GPIO_DEFGHI_RS 0
+#define PCM_RS 0
+#define AUTH_RS 0
+#define CRYPTO_RS 0
+#define LBCTMO_RS 0
+#define EXT_RS 0
+#define GPIO_ABC_RS 0
+#define SWCORE_RS 3
+#define PCI_RS 2
+#define UART1_RS 0
+#define UART0_RS 1
+#define PCMCIA_RS 0
+#define USB_RS 0
+#define TC_RS 4
+
+#define DIVISOR 1000
+
+#if DIVISOR > (1 << 16)
+#error "Exceed the Maximum Value of DivFactor"
+#endif
+
+/*
+ * ==========================
+ * Platform Register Settings
+ * ==========================
+ */
+
+/*
+ * CPU
+ */
+#define IMEM_BASE 0x00C00000
+#define IMEM_TOP 0x00C01FFF
+
+#define DMEM_BASE 0x00C02000
+#define DMEM_TOP 0x00C03FFF
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR 0xBD013000
+ #define MC_MCR_VAL 0xFAA00000
+
+#define MC_MTCR0 0xBD013004
+ #define MC_MTCR0_VAL 0x1B1B0000
+
+#define MC_MTCR1 0xBD013008
+ #define MC_MTCR1_VAL 0x00000CEA
+
+/*
+ * UART
+ */
+#define UART0_BASE 0xBD011000
+#define UART0_RBR (UART0_BASE + 0x000)
+#define UART0_THR (UART0_BASE + 0x000)
+#define UART0_DLL (UART0_BASE + 0x000)
+#define UART0_IER (UART0_BASE + 0x004)
+#define UART0_DLM (UART0_BASE + 0x004)
+#define UART0_IIR (UART0_BASE + 0x008)
+#define UART0_FCR (UART0_BASE + 0x008)
+#define UART0_LCR (UART0_BASE + 0x00C)
+#define UART0_MCR (UART0_BASE + 0x010)
+#define UART0_LSR (UART0_BASE + 0x014)
+
+#define UART1_BASE 0xBD011100
+#define UART1_RBR (UART1_BASE + 0x000)
+#define UART1_THR (UART1_BASE + 0x000)
+#define UART1_DLL (UART1_BASE + 0x000)
+#define UART1_IER (UART1_BASE + 0x004)
+#define UART1_DLM (UART1_BASE + 0x004)
+#define UART1_IIR (UART1_BASE + 0x008)
+#define UART1_FCR (UART1_BASE + 0x008)
+ #define FCR_EN 0x01
+ #define FCR_RXRST 0x02
+ #define RXRST 0x02
+ #define FCR_TXRST 0x04
+ #define TXRST 0x04
+ #define FCR_DMA 0x08
+ #define FCR_RTRG 0xC0
+ #define CHAR_TRIGGER_01 0x00
+ #define CHAR_TRIGGER_04 0x40
+ #define CHAR_TRIGGER_08 0x80
+ #define CHAR_TRIGGER_14 0xC0
+#define UART1_LCR (UART1_BASE + 0x00C)
+ #define LCR_WLN 0x03
+ #define CHAR_LEN_5 0x00
+ #define CHAR_LEN_6 0x01
+ #define CHAR_LEN_7 0x02
+ #define CHAR_LEN_8 0x03
+ #define LCR_STB 0x04
+ #define ONE_STOP 0x00
+ #define TWO_STOP 0x04
+ #define LCR_PEN 0x08
+ #define PARITY_ENABLE 0x01
+ #define PARITY_DISABLE 0x00
+ #define LCR_EPS 0x30
+ #define PARITY_ODD 0x00
+ #define PARITY_EVEN 0x10
+ #define PARITY_MARK 0x20
+ #define PARITY_SPACE 0x30
+ #define LCR_BRK 0x40
+ #define LCR_DLAB 0x80
+ #define DLAB 0x80
+#define UART1_MCR (UART1_BASE + 0x010)
+#define UART1_LSR (UART1_BASE + 0x014)
+ #define LSR_DR 0x01
+ #define RxCHAR_AVAIL 0x01
+ #define LSR_OE 0x02
+ #define LSR_PE 0x04
+ #define LSR_FE 0x08
+ #define LSR_BI 0x10
+ #define LSR_THRE 0x20
+ #define TxCHAR_AVAIL 0x00
+ #define TxCHAR_EMPTY 0x20
+ #define LSR_TEMT 0x40
+ #define LSR_RFE 0x80
+
+
+/*
+ * Interrupt Controller
+ */
+#define GIMR 0xBD012000
+ #define TC_IE (1 << 31)
+ #define USB_IE (1 << 30)
+ #define PCMICA_IE (1 << 29)
+ #define UART0_IE (1 << 28)
+ #define UART1_IE (1 << 27)
+ #define PCI_IE (1 << 26)
+ #define SWCORE_IE (1 << 25)
+ #define GPIO_ABC_IE (1 << 24)
+ #define EXT_IE (1 << 23)
+ #define LBCTMO_IE (1 << 21)
+ #define CRYPTO_IE (1 << 20)
+ #define AUTH_IE (1 << 19)
+ #define PCM_IE (1 << 18)
+ #define GPIO_DEFGHI_IE (1 << 17)
+ #define PCIBTMO_IE (1 << 16)
+
+#define GISR 0xBD012004
+ #define TC_IP (1 << 31)
+ #define USB_IP (1 << 30)
+ #define PCMICA_IP (1 << 29)
+ #define UART0_IP (1 << 28)
+ #define UART1_IP (1 << 27)
+ #define PCI_IP (1 << 26)
+ #define SWCORE_IP (1 << 25)
+ #define GPIO_ABC_IP (1 << 24)
+ #define EXT_IP (1 << 23)
+ #define LBCTMO_IP (1 << 21)
+ #define CRYPTO_IP (1 << 20)
+ #define AUTH_IP (1 << 19)
+ #define PCM_IP (1 << 18)
+ #define GPIO_DEFGHI_IP (1 << 17)
+ #define PCIBTMO_IP (1 << 16)
+
+#define IRR1 0xBD012008
+#define IRR1_SETTING (((TC_RS & 0x3) << 30) | \
+ ((USB_RS & 0x3) << 28) | \
+ ((PCMCIA_RS & 0x3) << 26) | \
+ ((UART0_RS & 0x3) << 24) | \
+ ((UART1_RS & 0x3) << 22) | \
+ ((PCI_RS & 0x3) << 20) | \
+ ((SWCORE_RS & 0x3) << 18) | \
+ ((GPIO_ABC_RS & 0x3) << 16) | \
+ ((EXT_RS & 0x3) << 14) | \
+ ((LBCTMO_RS & 0x3) << 12) | \
+ ((TC_RS & 0x4) >> 2 << 9) | \
+ ((USB_RS & 0x4) >> 2 << 8) | \
+ ((PCMCIA_RS & 0x4) >> 2 << 7) | \
+ ((UART0_RS & 0x4) >> 2 << 6) | \
+ ((UART1_RS & 0x4) >> 2 << 5) | \
+ ((PCI_RS & 0x4) >> 2 << 4) | \
+ ((SWCORE_RS & 0x4) >> 2 << 3) | \
+ ((GPIO_ABC_RS & 0x4) >> 2 << 2) | \
+ ((EXT_RS & 0x4) >> 2 << 1) | \
+ ((LBCTMO_RS & 0x4) >> 2 << 0) \
+ )
+
+#define IRR2 0xBD0120A0
+#define IRR2_SETTING (((CRYPTO_RS & 0x7) << 29) | \
+ ((AUTH_RS & 0x7) << 26) | \
+ ((PCM_RS & 0x7) << 23) | \
+ ((GPIO_DEFGHI_RS & 0x7) << 20) | \
+ ((PCIBTMO_RS & 0x7) << 17) \
+ )
+
+/*
+ * Timer/Counter
+ */
+#define TC_BASE 0xBD012020
+#define TC0DATA (TC_BASE + 0x00)
+#define TC1DATA (TC_BASE + 0x04)
+ #define TCD_OFFSET 8
+#define TC0CNT (TC_BASE + 0x08)
+#define TC1CNT (TC_BASE + 0x0C)
+#define TCCNR (TC_BASE + 0x10)
+ #define TC0EN (1 << 31)
+ #define TC0MODE_TIMER (1 << 30)
+ #define TC1EN (1 << 29)
+ #define TC1MODE_TIMER (1 << 28)
+#define TCIR (TC_BASE + 0x14)
+ #define TC0IE (1 << 31)
+ #define TC1IE (1 << 30)
+ #define TC0IP (1 << 29)
+ #define TC1IP (1 << 28)
+#define CDBR (TC_BASE + 0x18)
+ #define DIVF_OFFSET 16
+#define WDTCNR (TC_BASE + 0x1C)
+
+
+#endif /* _PLATFORM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl865xb/prom.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl865xb/prom.h new file mode 100644 index 000000000..84b360b1d --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl865xb/prom.h @@ -0,0 +1,8 @@ +#ifndef _PROM_H
+#define _PROM_H
+
+extern void prom_printf(char *fmt, ...);
+extern void prom_meminit(void);
+extern void prom_console_init(void);
+
+#endif /* _PROM_H */
diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_assert.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_assert.h new file mode 100644 index 000000000..dba893beb --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_assert.h @@ -0,0 +1,13 @@ + + +#ifndef RTL865X_DEBUG +#define assert(expr) do {} while (0) +#else +#define assert(expr) \ + if(!(expr)) { \ + rtlglue_printf( "\033[33;41m%s:%d: assert(%s)\033[m\n", \ + __FILE__,__LINE__,#expr); \ + } +#endif + + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_glue.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_glue.h new file mode 100644 index 000000000..9d1cdea79 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_glue.h @@ -0,0 +1,609 @@ +/* +* -------------------------------------------------------------------- +* Copyright c Realtek Semiconductor Corporation, 2002 +* All rights reserved. +* +* Program : rtl_glue.h +* Abstract :Header of porting layer +* Author : Edward Jin-Ru Chen +* +* $Id: rtl_glue.h,v 1.1.1.1 2007-11-12 13:27:50 alva_zhang Exp $ +* $Log: not supported by cvs2svn $ +* Revision 1.32 2007/04/09 14:14:01 michaelhuang +* +: added rtlglue_read() function +* +* Revision 1.31 2007/03/02 13:31:59 chenyl +* *: enable range based D-cache flush function. +* +* Revision 1.30 2007/01/09 02:36:08 michaelhuang +* *: Prepare implement test module for RTL8672 +* +* Revision 1.29 2006/12/21 06:57:00 yjlou +* -: remove the following usages: +* printk +* printfByPolling +* +* Revision 1.28 2006/11/28 02:15:14 hyking_liu +* *: Mofify function related with usrDefineTunnel +* +* Revision 1.27 2006/11/21 12:28:35 chenyl +* *: rearrange some code +* *: bug fix - Src VLAN decision +* *: bug fix - D-cache invalidation for FAST extension device forwarding +* *: bug fix - m_unused1 and ph_reserved are needed for FAST extension device forwarding +* +* Revision 1.26 2006/10/26 02:15:32 qy_wang +* *:remove the inculed file net_device.h in rtl8651_layer2fwd.c +* +* Revision 1.25 2006/10/25 07:10:15 qy_wang +* +:add a function to block extension device when link up +* +* Revision 1.24 2006/08/31 15:44:48 chenyl +* *: add some declarations of external APIs +* +* Revision 1.23 2006/07/13 15:55:49 chenyl +* *: modify code for RTL865XC driver compilation. +* *: dos2unix process +* +* Revision 1.22 2006/06/20 05:53:22 brian_bin +* +: brian_bin move open, write, close declaration into __RTL_GLUE__ define brace +* +* Revision 1.21 2006/01/12 08:32:37 brian_bin +* +: brian_bin add kernel system call of file operations +* +* Revision 1.20 2006/01/02 02:52:14 chenyl +* +: VLAN-tag support extension port forwarding and software Rome Driver forwarding. +* +* Revision 1.19 2005/09/16 11:34:48 tony +* *: bug fixed: support kernel space swNic model code for RTL865XC. +* +* Revision 1.18 2005/09/06 02:36:38 yjlou +* +: add random and time glue functions. +* +* Revision 1.17 2005/07/20 15:29:38 yjlou +* +: porting Model Code to Linux Kernel: check RTL865X_MODEL_KERNEL. +* +* Revision 1.16 2005/07/01 09:34:41 yjlou +* *: porting swNic2.c into model code. +* +* Revision 1.15 2005/06/19 05:41:19 yjlou +* *: merge ASIC driver into model code. +* +* Revision 1.14 2005/06/07 15:00:57 chenyl +* *: modify mutex Lock / Unlock code to check the balance of Lock/Unlock function call +* +* Revision 1.13 2004/11/29 07:35:44 chenyl +* *: fix bug : multiple-PPPoE MTU setting bug +* *: fix bug : Never add second session's ip into ASIC in multiple-PPPoE WAN type. +* *: fix bug : Tunekey abnormal behavior when multiple-PPPoE Dial-on-demand Dynamically turn ON/OFF +* *: in forwarding engine Init function, the parameter == 0xffffffff means user want to set as default value +* *: add Mutex-Lock/Unlock checking in testing code +* +* Revision 1.12 2004/11/05 09:54:08 yjlou +* +: support more precise timeUpdate() function. +* +: add EVENT_TRIGGER_TIMEUPDATE==2 +* *: modify #ifdef EVENT_TRIGGER_TIMEUPDATE +* +* Revision 1.11 2004/07/27 10:47:08 cfliu +* -: Remove RTL865x external loopback port related code for PPTP/L2TP/WLAN +* +* Revision 1.10 2004/06/23 08:11:55 yjlou +* *: change the declaration of rtlglue_getmstime() +* +* Revision 1.9 2004/05/03 14:56:18 cfliu +* Add 8650B extension port support. +* Revise all WLAN/extport related code. +* +* Revision 1.8 2004/05/03 02:53:03 chenyl +* *: swNic_getRingSize -> rtlglue_getRingSize and move it from swNic2.c to rtl_glue.c +* *: set default upstream ip to 0 if we config interface to dhcp +* +* Revision 1.7 2004/04/30 08:58:08 chenyl +* +: ip multicast/igmp proxy +* +* Revision 1.6 2004/04/08 12:11:20 cfliu +* Change extension port API.....define rtlglue_extDeviceSend() +* +* Revision 1.5 2004/03/31 09:37:01 cfliu +* Add WDS support +* +* Revision 1.4 2004/03/19 13:13:35 cfliu +* Reorganize ROME driver local header files. Put all private data structures into different .h file corrsponding to its layering +* Rename printf, printk, malloc, free with rtlglue_XXX prefix +* +* Revision 1.1 2004/03/10 11:42:36 cfliu +* Move rtl_glue.* from rtl865x/ +* +* Revision 1.2 2004/03/03 10:40:38 yjlou +* *: commit for mergence the difference in rtl86xx_tbl/ since 2004/02/26. +* +* Revision 1.1 2004/02/25 14:26:33 chhuang +* *** empty log message *** +* +* Revision 1.2 2004/02/25 14:24:52 chhuang +* *** empty log message *** +* +* Revision 1.7 2004/02/24 04:15:43 cfliu +* add API for WLAN acceleration +* +* Revision 1.6 2004/02/18 13:54:37 chhuang +* *** empty log message *** +* +* Revision 1.5 2003/12/26 09:27:50 orlando +* add rtl_glue.h +* +* Revision 1.3 2003/09/30 06:07:50 orlando +* check in RTL8651BLDRV_V20_20030930 +* +* Revision 1.4 2003/06/10 05:33:30 cfliu +* Remove rtl8651_tblDrvFwdSend registration. +* Add rtlglue_drvSend to replace rtl8651_tblDrvFwdSend function pointer +* +* Revision 1.3 2003/06/09 04:48:43 cfliu +* add 3 OS dependent glue functions to support mbuf external cluster allocation. +* Rewrite all help messages using Autoduck's syntax so documentation could generated automatically. +* +* Revision 1.2 2003/05/23 07:47:06 cfliu +* Extract porting function and fix compile warning. +* +* Revision 1.1 2003/05/23 04:55:25 jzchen +* Add rtl glue to solve porting issue +* +*/ + +#ifndef _RTL_GLUE_ +#define _RTL_GLUE_ + +#include "rtl_types.h" +#if defined(CONFIG_RTL865X) +#include "mbuf.h" +#endif + + +/* @doc RTLGLUE_API + + @module rtl_glue.h - Glue interface for Realtek 8651 Home gateway controller driver | + This guide documents the glue interface for porting 8651 driver to targeted operating system + @normal Chun-Feng Liu (cfliu@realtek.com.tw) <date> + + Copyright <cp>2003 Realtek<tm> Semiconductor Cooperation, All Rights Reserved. + + @head3 List of Symbols | + Here is the list of all functions and variables in this module. + + @index | RTLGLUE_API +*/ + + +extern int32 rtlglue_init(void); +/* +@func int32 | rtlglue_init | Initialize all OS dependent mutex, semaphore objects, etc. here +@rvalue SUCCESS | if initialization succeed +@rvalue FAILED | if initialization failed. This aborts system initialization. +@comm +All required OS supporting capabilities such as mutex, semaphore, and timer service are initialized here. + */ + +extern int32 rtlglue_registerTimerMs(uint32 *eventId,uint32 *eventSerialNumber, + int32 (* callback_func)(uint32 eventSerialNumber,void *), void *callback_func_arg, uint32 msec); +/* +@func int32 | rtlglue_registerTimerMs | OS dependent timer registration function. +@parm uint32 * | eventId | placeholder for saving registered timer event id. +@parm uint32 * | eventSerialNumber | placeholder for saving the unique serial number returned with event id. +@parm int32 (*)(uint32,void *) | callback_func | the registering callback function for execution +@parm void * | callback_func_arg | arguments for callback_func +@parm uint32 | msec | timeout in units of milli-seconds. + +@rvalue SUCCESS | if timer event registration failed. +@rvalue FAILED | if timer event successfully registered. +@comm +a) If the timer service provided by the ported OS is a kernel service(which guarantees atomic operation), +then return value of <p eventSerialNumber> MUST always be zero. + +b) If the timer service is provided by a "soft" timer, ie. a timer thread/task, then the return value of <p eventSerialNumber> must +NOT be zero and MUST be unique every time this glue function is called. This returned value would then be saved by caller and +checked by the callback function upon called-back to prevent race condition between running thread and timer thread. + */ + + +extern int32 rtlglue_cancelTimer(uint32 eventId,uint32 eventSerialNumber); +/* +@func int32 | rtlglue_cancelTimer |OS dependent timer deregistration function. +@parm uint32 | eventId | The identifier of timer event to be cancelled. +@parm uint32 | eventSerialNumber | The serial number of timer event identifier <p eventId>. + +@rvalue SUCCESS | Timer event successfully cancelled. If the OS timer is a kernel service, the registered callback function would NOT be called. If the OS timer is provided via timer thread, the registered callback function may still/may not be called. +@rvalue FAILED | Failed to cancel timer event <p eventId> + */ + +#ifndef RTL865X_TEST +extern int32 rtlglue_mbufMutexLock(void); +#endif +/* +@func int32 | rtlglue_mbufMutexLock | The mutex lock function for mbuf module to protect internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + + +#ifndef RTL865X_TEST +extern int32 rtlglue_mbufMutexUnlock(void); +#endif +/* +@func int32 | rtlglue_mbufMutexLock | The mutex unlock function for mbuf module to protect internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + + +extern int32 rtlglue_mbufTsleep(uint32 wait_channel); +/* +@func int32 | rtlglue_mbufTsleep | Used by mbuf module, to let calling thread blocking when requested resource not readily available. +@parm uint32 | wait_channel | Identifier of requesting resource. May be an memory address, resource handle, etc. +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +Ref FreeBSD's tsleep() or Steven's TCP/IP Vol2 pp456 + */ + + +extern int32 rtlglue_mbufTwakeup(uint32 wait_channel); +/* +@func int32 | rtlglue_mbufTwakeup | Used by mbuf module, to wakeup blocked waiting thread when requesed resource is available +@parm uint32 | wait_channel | Identifier of waiting channel to be waked up. +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +Ref FreeBSD's tsleep() or Steven's TCP/IP Vol2 pp456 + */ + +extern int32 rtlglue_mbufAllocCluster(void **buffer, uint32 size, uint32 *id); +/* +@func int32 | rtlglue_mbufAllocCluster | Used by mbuf module, to allocate a cluster externally from OS +@parm void ** | buffer | For output, address of allocated cluster. +@parm uint32 | size | number of bytes requested. +@parm uint32 * | id | For output, identifier of allocated cluster, up to OS memory allocator's interpretation. +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +each allocation must set returned buffer's reference count to 1. +But if you are sure you WON'T call any of mbuf's spliting(<p mBuf_split>), cloning(<p mBuf_clonePacket>, +<p mBuf_cloneMbufChain>) or trimming(<p mBuf_trimHead>, <p mBuf_trimTail>) APIs in your code, never mind about reference counts. + */ + +extern int32 rtlglue_mbufFreeCluster(void *buffer, uint32 size, uint32 id); +/* +@func int32 | rtlglue_mbufFreeCluster | Used by mbuf module, to free allocated cluster +@parm void * | buffer | buffer address to free +@parm uint32 | size | identifier of buffer to free +@parm uint32 | id | size of buffer to free +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +each buffer returned must has its reference count decremented to exactly 0. mbuf module would query buffer's reference count and make sure it's 1 before calling this function. +But if you are sure you WON'T call any of mbuf's spliting(<p mBuf_split>), cloning(<p mBuf_clonePacket>, +<p mBuf_cloneMbufChain>) or trimming(<p mBuf_trimHead>, <p mBuf_trimTail>) APIs in your code, never mind about reference counts. + */ + +extern int32 rtlglue_mbufClusterRefcnt(void *buffer, uint32 id, uint32 *count, int8 operation); +/* +@func int32 | rtlglue_mbufClusterRefcnt | Used by mbuf module, to free allocated cluster +@parm void * | buffer | buffer address to free +@parm uint32 | id | identifier of designated buffer +@parm uint32 * | count | For output. Placeholder for returned reference number *AFTER* <p operation> done. +@parm int8 | operation | 0: Query, 1: Increment, 2: Decrement +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +1) For parameter <p count>: <p count> is the reference count of designated cluster *AFTER* 'operation' done. MUST not be NULL for Query operation, MAY be NULL for Increment o Decrement operation. + +2) When clusters are allocated externally by OS, <p mBuf_data2Mbuf()>, <p mBuf_clusterIsWritable()> +become void. Also, since mbuf module no longer knows which mbuf is the first referee (which owns the write priviledge to +cluster). Design decision here simply grants write priviledge to ALL cluster referees. + +3) Porting Note: If you are sure you WON'T call any of mbuf's spliting(<p mBuf_split>), cloning(<p mBuf_clonePacket>, +<p mBuf_cloneMbufChain>), or trimming(<p mBuf_trimHead>, <p mBuf_trimTail>) APIs, you can always return +1 when operation=0(Query), and do nothing when operation=1(Increment) or 2(Decrement). +*/ + +extern void * rtlglue_mbufClusterToData(void *buffer); +/* +@parm void * | buffer | find mbuf cluster's m_data's position +@rvalue 0 | failed +@rvalue Non-0 | succeed +@comm +return mbuf cluster's m_data's position +*/ +#ifndef RTL865X_TEST +extern int32 rtlglue_drvMutexLock(void); +#endif +/* +@func int32 | rtlglue_drvMutexLock | Used by driver, to safeguard driver internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + +#ifndef RTL865X_TEST +extern int32 rtlglue_drvMutexUnlock(void); +#endif +/* +@func int32 | rtlglue_drvMutexLock | Used by driver, to safeguard driver internal data structure. + +@rvalue 0 | succeed +@rvalue Non-0 | failed + */ + + +extern void rtlglue_getMacAddress(ether_addr_t * macAddress, uint32 * number); +/* +@func void | rtlglue_getMacAddress | Used during board initialization, to read the total number of configured MAC addresses and their values in flash. +@parm ether_addr_t * | macAddress | For output. The base MAC address configured for this board. +@parm uint32 * | number | For output. Total (consecutive) number of MAC addresses starting from <p *macAddress>. + +@rvalue 0 | succeed +@rvalue Non-0 | failed +@comm +Read from the flash to get the base MAC address and total number of MAC addresses configured to the board. +If anything goes wrong, a default MAC address would be written back to the flash. + */ + +#if defined(CONFIG_RTL865X) +extern void rtlglue_drvSend(void * pkthdr);//void * assumed to be packet header +/* +@func void | rtlglue_drvSend | The OS dependent raw driver send function for high level driver to send pkt. +@parm void * | pkthdr | The pkthdr address of outgoing mbuf chain +@rdesc None +@comm +Implement this function to provide table driver and upper layer protocols such as PPPoE module to send packet to driver. +The sending packet must have already in mbuf chain format. + */ +#endif /* defined(CONFIG_RTL865X) */ + +#if defined(CONFIG_RTL865X) +/* +@func int32 | rtlglue_extPortMbufFastRecv | Fast Path for packet from Extension device to HW. +@parm struct rtl_pktHdr* | pkt | packet from extension device. +@parm uint16 | myvid | RX VID of this packet. +@parm uint32 | myportmask | RX Port mask of this packet. +@rvalue SUCCESS | Always return SUCCESS. +@comm + +Glue Interface for <p rtl8651_fwdEngineExtPortUcastFastRecv> + +Fast path for extension device to HW Accelerated forwarding. +Note that this function would NOT do + 1. SMAC learning. + 2. Extension Device Bridge. + +Therefore, if extension device would like to use Fast path, it would do these by itself. +*/ +int32 rtlglue_extPortMbufFastRecv( struct rtl_pktHdr *pkt, + uint16 myvid, + uint32 myportmask); +#endif /* defined(CONFIG_RTL865X) */ + +/* +@func int32 | rtlglue_regWlanSta | Register (LinkID<->Port Number) binding into Rome Driver +@parm uint32 | portNumber | Extension Port Number to bind. +@parm uint16 | defaultVID | Default VID of this extension device. +@parm uint32* | linkID_p | pointer to the LinkID of current extension device. +@parm void* | extDevice | extension device's own pointer ( can NOT be NULL ). +@rvalue FAILED | No free LinkID or extDevice == NULL. +@rvalue SUCCESS | Registration OK. +@comm + +Glue Interface for <p rtl8651_fwdEngineRegExtDevice> + +Register Extension Device into Rome Driver: + Extension device would need to provide it's binding <p portNumber> and <p extDevice>. + Rome Driver would fill the <p linkID> if registration success. + <p defaultVID> indicates the default VLAN ID of this extension device. It is used in TX vlan filtering + now. + + - Note: We don't support per-LinkID's untag set setting yet. +*/ + +int32 rtlglue_regWlanSta( uint32 portNumber, + uint16 defaultVID, + uint32 *linkID_p, + void *extDevice); + +/* +@func int32 | rtlglue_unregWlanSta | Un-Register (LinkID<->Port Number) binding. +@parm uint32 | linkID | pointer to the LinkID of current extension device. +@rvalue FAILED | LinkID is not found. +@rvalue SUCCESS | UnRegistration OK. +@comm + +Glue Interface for <p rtl8651_fwdEngineUnregExtDevice> + +UnRegister exist LinkID from Rome Driver. + Extension device would need to provide it's <p linkID> which gotten from registration function. + Rome Driver would remove the related information for this <p linkID>. + */ + +int32 rtlglue_unregWlanSta(uint32 linkID); + +#if defined(CONFIG_RTL865X) +void rtlglue_extDeviceSend(struct rtl_pktHdr *pktHdr, void *txExtDev); +// This function is called back by RTL8651 driver when it wants to send a pkt to WLAN interface. +//First input parameter represents the destination vlan ID, second parameter is the destination link ID +//which was given and learnt from rtl8651_fwdEngineExtPortRecv() during L2 SA learning process. +// It's WLAN driver's job to find out to which card or WDS link the pkt should be sent by maintaining a +//small database keeping linkId<-> device mapping. +// The 'linkId' was assigned by WLAN driver and is not interpreted by 8651 driver. However, linkId=0 +//has special usage reserved for "Broadcast to all vlan member ports" therefore linkId=0 can't be associated +//to any WLAN card or WDS link. +// ***This function is called by 8651 driver and MUST be implemented. +#endif /* defined(CONFIG_RTL865X) */ + +//#endif +#if defined(CONFIG_RTL865X) +int32 rtlglue_reclaimRxBD(uint32 rxDescIdx,struct rtl_pktHdr *pThisPkthdr, struct rtl_mBuf *pThisMbuf); +#endif /* defined(CONFIG_RTL865X) */ +#ifdef CONFIG_RTL865XC +void rtlglue_getRingSize(uint32 *rx, uint32 *tx,int whichDesc); +#else +void rtlglue_getRingSize(uint32 *rx, uint32 *tx); +#endif +uint32 rtlglue_getsectime(void) ; +uint32 rtlglue_getmstime( uint32* ); +void *rtlglue_malloc(uint32); +void rtlglue_free(void *APTR); + +uint32 rtl865x_getHZ(void); + +#if defined(RTL865X_TEST) || defined(RTL865X_MODEL_USER) || defined(RTL867X_MODEL_USER) || defined(RTL8389_MODEL_USER) +#include <stdio.h> +#include <stdlib.h> +#include <ctype.h> +#include <string.h> + + +int32 rtlglue_getDrvMutex(void); +int32 rtlglue_reinitDrvMutex(void); +int32 rtlglue_getMbufMutex(void); +int32 rtlglue_reinitMbufMutex(void); + +extern int test_drvMutex; +extern int test_mbufMutex; + +#define rtlglue_drvMutexLock() \ + do { \ + test_drvMutex ++;\ + } while (0) +#define rtlglue_drvMutexUnlock()\ + do {\ + test_drvMutex --;\ + if (test_drvMutex < 0)\ + {\ + printf("%s (%d) Error: Driver Mutex Lock/Unlcok is not balance (%d).\n", __FUNCTION__, __LINE__, test_drvMutex);\ + }\ + } while (0) + +#define rtlglue_mbufMutexLock() \ + do { \ + test_mbufMutex ++;\ + } while (0) +#define rtlglue_mbufMutexUnlock()\ + do {\ + test_mbufMutex --;\ + if (test_mbufMutex < 0)\ + {\ + printf("%s (%d) Error: Mbuffer Mutex Lock/Unlcok is not balance (%d).\n", __FUNCTION__, __LINE__, test_mbufMutex);\ + }\ + } while (0) + +#define wmb() do {} while(0) + +#define spin_lock(x) do {x=x;} while(0) +#define spin_unlock(x) do {x=x;} while(0) + +#ifdef RTL865X_TEST +int32 spin_lock_irqsave(spinlock_t *spinlock, int32 s); +int32 spin_unlock_irqrestore(spinlock_t *spinlock, int32 s); +#else +#define spin_lock_irqsave(sp,s) do { sp=sp; s=s; } while(0) +#define spin_unlock_irqrestore(sp,s) do { sp=sp; s=s; } while(0) +#endif/*RTL865X_TEST*/ + +#endif /* RTL865X_TEST || RTL865X_MODEL_USER || RTL867X_MODEL_USER || defined(RTL8389_MODEL_USER)*/ + +#define bzero( p, s ) memset( p, 0, s ) + + +/* +@func void | rtlglue_srandom | The OS dependent seed function for random. +@parm uint32 | seed | seed +@comm + */ +void rtlglue_srandom( uint32 seed ); + +/* +@func uint32 | rtlglue_random | The OS dependent random function. +@parm void | | +@comm + */ +uint32 rtlglue_random( void ); + +/* +@func uint32 | rtlglue_time | The OS dependent time function. +@parm uint32* | t | address to store time +@comm + */ +uint32 rtlglue_time( uint32* t ); + +/* +@func int | rtlglue_open | The OS dependent open function. +@parm const char* | path | filename or path +@parm int | flags | file attribute +@parm int | mode | file mode +@comm + */ +int rtlglue_open(const char *path, int flags, int mode ); + +/* +@func int | rtlglue_read | The OS dependent read function. +@parm int | fd | file descriptor +@parm void* | buf | read buffer +@parm int | nbytes | number of bytes to read in buffer +@comm + */ +int rtlglue_read(int fd, void* buf, int nbytes); + +/* +@func int | rtlglue_write | The OS dependent write function. +@parm int | fd | file descriptor +@parm void* | buf | write buffer +@parm int | nbytes | number of bytes to write in buffer +@comm + */ +int rtlglue_write(int fd, void* buf, int nbytes); + +/* +@func int | rtlglue_close | The OS dependent close function. +@parm int | fd | file descriptor +@comm + */ +int rtlglue_close(int fd); + +#if defined(CONFIG_RTL865X) +struct sk_buff *re865x_mbuf2skb(struct rtl_pktHdr* pPkt); +#endif /* defined(CONFIG_RTL865X) */ + +/* +@func void | rtl8651_extDevMakeBlocking | make extension device port STP blocking . +@parm void* | extDev | extension device +@comm + */ +int32 rtlglue_extDevMakeBlocking(void * extDev); + +/* +@func void | rtlglue_getExtDeviceName | Get device NAME of "device" +@parm void* | device | pointer of device to get name. +@parm void* | name | pointer of name to be filled by this API. +@comm + */ +int32 rtlglue_getExtDeviceName(void * device, char* name); + +/* +@func void | rtlglue_pktToProtocolStackPreprocess | Process before packet is trapped to protocol stack. +@comm + */ +inline int32 rtlglue_pktToProtocolStackPreprocess(void); + +/* +@func int32 | rtlglue_flushDCache | Flush D-cache. +@parm uint32 | start | start address to flush +@parm uint32 | size | total size to flush +@comm +Flush D-cache from <p start> with size being <p size>. +Set <p start> = 0 and <p size> = 0 if we need to flush ALL D-cache entries. + */ +inline int32 rtlglue_flushDCache(uint32 start, uint32 size); + +#endif/*#ifndef _RTL_GLUE_*/ + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_queue.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_queue.h new file mode 100644 index 000000000..515a19663 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_queue.h @@ -0,0 +1,940 @@ + +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: src/sys/sys/queue.h,v 1.32.2.4 2001/03/31 03:33:39 hsu Exp $ + */ + +#ifndef _RTL_QUEUE_H_ +#define _RTL_QUEUE_H_ + +////#include <machine/ansi.h> /* for __offsetof */ + +/* + * This file defines five types of data structures: singly-linked lists, + * singly-linked tail queues, lists, tail queues, and circular queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * A circle queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or after + * an existing element, at the head of the list, or at the end of the list. + * A circle queue may be traversed in either direction, but has a more + * complex end of list detection. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ CIRCLEQ + * _HEAD + + + + + + * _ENTRY + + + + + + * _INIT + + + + + + * _EMPTY + + + + + + * _FIRST + + + + + + * _NEXT + + + + + + * _PREV - - - + + + * _LAST - - + + + + * _FOREACH + + + + + + * _FOREACH_REVERSE - - - + + + * _INSERT_HEAD + + + + + + * _INSERT_BEFORE - + - + + + * _INSERT_AFTER + + + + + + * _INSERT_TAIL - - + + + + * _REMOVE_HEAD + - + - - + * _REMOVE + + + + + + * + */ + +#ifndef __offsetof +#define __offsetof(type, field) ((unsigned long)(&((type *)0)->field)) +#endif + +/* + * Singly-linked List definitions. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next) + +#define SLIST_INIT(head) { \ + (head)->slh_first = NULL; \ +} + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ +} while (0) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = (head)->slh_first; \ + while( curelm->field.sle_next != (elm) ) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = \ + curelm->field.sle_next->field.sle_next; \ + } \ +} while (0) + +/* + * Counting Singly-linked List definitions. + */ +#define CSLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ + int slh_count;\ +} + +#define CSLIST_HEAD_INITIALIZER(head) \ + {0, NULL } + +#define CSLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define CSLIST_EMPTY(head) ((head)->slh_first == NULL) +#define CSLIST_FIRST(head) ((head)->slh_first) +#define CSLIST_TOTAL(head) ((head)->slh_count) +#define CSLIST_FOREACH(var, head, field) \ + for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next) + +#define CSLIST_INIT(head) { \ + (head)->slh_count=0;\ + (head)->slh_first = NULL; \ +} + +#define CSLIST_INSERT_AFTER(head, slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ + (head)->slh_count++;\ +} while (0) + +#define CSLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ + (head)->slh_count++;\ +} while (0) + +#define CSLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define CSLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ + (head)->slh_count--;\ +} while (0) + +#define CSLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + CSLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = (head)->slh_first; \ + while( curelm->field.sle_next != (elm) ) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = curelm->field.sle_next->field.sle_next;\ + (head)->slh_count--;\ + }\ +} while (0) + +/* + * Singly-linked Tail queue definitions. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_INIT(head) do { \ + (head)->stqh_first = NULL; \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY(head) ? \ + NULL : \ + ((struct type *) \ + ((int8 *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = (head)->stqh_first; (var); (var) = (var)->field.stqe_next) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_first = (elm); \ +} while (0) + +/*if the header->stqh_first == NULL,we should modify it*/ +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + if((head)->stqh_first == NULL) \ + STAILQ_INSERT_HEAD(head, elm, field); \ + else { \ + (elm)->field.stqe_next = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + } \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if (((elm)->field.stqe_next = (tqelm)->field.stqe_next) == NULL)\ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (tqelm)->field.stqe_next = (elm); \ +} while (0) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if (((head)->stqh_first = \ + (head)->stqh_first->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \ + if (((head)->stqh_first = (elm)->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if ((head)->stqh_first == (elm)) { \ + STAILQ_REMOVE_HEAD(head, field); \ + } \ + else { \ + struct type *curelm = (head)->stqh_first; \ + while( curelm->field.stqe_next != (elm) ) \ + curelm = curelm->field.stqe_next; \ + if((curelm->field.stqe_next = \ + curelm->field.stqe_next->field.stqe_next) == NULL) \ + (head)->stqh_last = &(curelm)->field.stqe_next; \ + } \ +} while (0) + + +/* + * Counting Singly-linked Tail queue definitions. + */ +#define CSTAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ + int stqh_count;\ +} + +#define CSTAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first, 0 } + +#define CSTAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Counting Singly-linked Tail queue functions. + */ +#define CSTAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define CSTAILQ_INIT(head) do { \ + (head)->stqh_count=0;\ + (head)->stqh_first = NULL; \ + (head)->stqh_last = &(head)->stqh_first; \ +} while (0) + +#define CSTAILQ_FIRST(head) ((head)->stqh_first) +#define CSTAILQ_TOTAL(head) ((head)->stqh_count) +#define CSTAILQ_LAST(head, type, field) \ + (CSTAILQ_EMPTY(head) ? \ + NULL : \ + ((struct type *) \ + ((int8 *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define CSTAILQ_FOREACH(var, head, field) \ + for((var) = (head)->stqh_first; (var); (var) = (var)->field.stqe_next) + +#define CSTAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_first = (elm); \ + (head)->stqh_count++;\ +} while (0) + +#define CSTAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.stqe_next = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (head)->stqh_count++;\ +} while (0) + +#define CSTAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if (((elm)->field.stqe_next = (tqelm)->field.stqe_next) == NULL)\ + (head)->stqh_last = &(elm)->field.stqe_next; \ + (tqelm)->field.stqe_next = (elm); \ + (head)->stqh_count++;\ +} while (0) + +#define CSTAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define CSTAILQ_REMOVE_HEAD(head, field) do { \ + if (((head)->stqh_first = \ + (head)->stqh_first->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ + (head)->stqh_count--;\ +} while (0) + +#define CSTAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \ + if (((head)->stqh_first = (elm)->field.stqe_next) == NULL) \ + (head)->stqh_last = &(head)->stqh_first; \ + (head)->stqh_count--;\ +} while (0) + +#define CSTAILQ_REMOVE(head, elm, type, field) do { \ + if ((head)->stqh_first == (elm)) { \ + CSTAILQ_REMOVE_HEAD(head, field); \ + } \ + else { \ + struct type *curelm = (head)->stqh_first; \ + while( curelm->field.stqe_next != (elm) ) \ + curelm = curelm->field.stqe_next; \ + if((curelm->field.stqe_next = \ + curelm->field.stqe_next->field.stqe_next) == NULL) \ + (head)->stqh_last = &(curelm)->field.stqe_next; \ + (head)->stqh_count--;\ + } \ +} while (0) + +#ifndef __linux__ + +/* + * List definitions. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for((var) = (head)->lh_first; (var); (var) = (var)->field.le_next) + +#define LIST_INIT(head) do { \ + (head)->lh_first = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.le_next = (head)->lh_first) != NULL) \ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_REMOVE(elm, field) do { \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ +} while (0) + +#endif /* __linux__ */ + +/* + * Counting List definitions. + */ +#define CLIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ + int lh_count;\ +} + +#define CLIST_HEAD_INITIALIZER(head) \ + { 0, NULL } + +#define CLIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * Counting List functions. + */ + +#define CLIST_EMPTY(head) ((head)->lh_first == NULL) +#define CLIST_TOTAL(head) ((head)->lh_count) +#define CLIST_FIRST(head) ((head)->lh_first) + +#define CLIST_FOREACH(var, head, field) \ + for((var) = (head)->lh_first; (var); (var) = (var)->field.le_next) + +#define CLIST_INIT(head) do { \ + (head)->lh_count=0;\ + (head)->lh_first = NULL; \ +} while (0) + +#define CLIST_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ + (head)->lh_count++;\ +} while (0) + +#define CLIST_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ + (head)->lh_count++;\ +} while (0) + +#define CLIST_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.le_next = (head)->lh_first) != NULL) \ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ + (head)->lh_count++;\ +} while (0) + +#define CLIST_NEXT(elm, field) ((elm)->field.le_next) + +#define CLIST_REMOVE(head, elm, field) do { \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ + (head)->lh_count--;\ +} while (0) + + +/* + * Tail queue definitions. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ +} + +/* + * Tail queue functions. + */ +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FOREACH(var, head, field) \ + for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_INIT(head) do { \ + (head)->tqh_first = NULL; \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.tqe_next = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ +} while (0) + +#define TAILQ_REMOVE(head, elm, field) do { \ + if (((elm)->field.tqe_next) != NULL) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ +} while (0) + +/* + * Counting Tail queue definitions. + */ +#define CTAILQ_HEAD(name, type) \ +struct name {\ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + int tqh_count;\ +} + +#define CTAILQ_HEAD_INITIALIZER(head) \ + { 0, NULL, &(head).tqh_first } + +#define CTAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ +} + +/* + * Counting Tail queue functions. + */ +#define CTAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define CTAILQ_FOREACH(var, head, field) \ + for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) + +#define CTAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define CTAILQ_FIRST(head) ((head)->tqh_first) +#define CTAILQ_TOTAL(head) ((head)->tqh_count) +#define CTAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define CTAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define CTAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define CTAILQ_INIT(head) do { \ + (head)->tqh_count=0;\ + (head)->tqh_first = NULL; \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (0) + +#define CTAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ + (head)->tqh_count++;\ +} while (0) + +#define CTAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.tqe_next = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_count++;\ +} while (0) + +#define CTAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ + (head)->tqh_count++; \ +} while (0) + +#define CTAILQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ + (head)->tqh_count++;\ +} while (0) + +#define CTAILQ_REMOVE(head, elm, field) do { \ + if (((elm)->field.tqe_next) != NULL) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ + (head)->tqh_count--;\ +} while (0) + + + +/* + * Circular queue definitions. + */ +#define CIRCLEQ_HEAD(name, type) \ +struct name { \ + struct type *cqh_first; /* first element */ \ + struct type *cqh_last; /* last element */ \ +} + +#define CIRCLEQ_ENTRY(type) \ +struct { \ + struct type *cqe_next; /* next element */ \ + struct type *cqe_prev; /* previous element */ \ +} + +/* + * Circular queue functions. + */ +#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) + +#define CIRCLEQ_FIRST(head) ((head)->cqh_first) + +#define CIRCLEQ_FOREACH(var, head, field) \ + for((var) = (head)->cqh_first; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_next) + +#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \ + for((var) = (head)->cqh_last; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_prev) + +#define CIRCLEQ_INIT(head) do { \ + (head)->cqh_first = (void *)(head); \ + (head)->cqh_last = (void *)(head); \ +} while (0) + +#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm)->field.cqe_next; \ + (elm)->field.cqe_prev = (listelm); \ + if ((listelm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (listelm)->field.cqe_next->field.cqe_prev = (elm); \ + (listelm)->field.cqe_next = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm); \ + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ + if ((listelm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (listelm)->field.cqe_prev->field.cqe_next = (elm); \ + (listelm)->field.cqe_prev = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.cqe_next = (head)->cqh_first; \ + (elm)->field.cqe_prev = (void *)(head); \ + if ((head)->cqh_last == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (head)->cqh_first->field.cqe_prev = (elm); \ + (head)->cqh_first = (elm); \ +} while (0) + +#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.cqe_next = (void *)(head); \ + (elm)->field.cqe_prev = (head)->cqh_last; \ + if ((head)->cqh_first == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (head)->cqh_last->field.cqe_next = (elm); \ + (head)->cqh_last = (elm); \ +} while (0) + +#define CIRCLEQ_LAST(head) ((head)->cqh_last) + +#define CIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next) + +#define CIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev) + +#define CIRCLEQ_REMOVE(head, elm, field) do { \ + if ((elm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm)->field.cqe_prev; \ + else \ + (elm)->field.cqe_next->field.cqe_prev = \ + (elm)->field.cqe_prev; \ + if ((elm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm)->field.cqe_next; \ + else \ + (elm)->field.cqe_prev->field.cqe_next = \ + (elm)->field.cqe_next; \ +} while (0) + +/* + * Counting Circular queue definitions. + */ +#define CCIRCLEQ_HEAD(name, type) \ +struct name { \ + struct type *cqh_first; /* first element */ \ + struct type *cqh_last; /* last element */ \ +} + +#define CCIRCLEQ_ENTRY(type) \ +struct { \ + int cqe_count;\ + struct type *cqe_next; /* next element */ \ + struct type *cqe_prev; /* previous element */ \ +} + +/* + * Counting Circular queue functions. + */ +#define CCIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head)) +#define CCIRCLEQ_FIRST(head) ((head)->cqh_first) +#define CCIRCLEQ_TOTAL(head) ((head))->cqh_count) +#define CCIRCLEQ_FOREACH(var, head, field) \ + for((var) = (head)->cqh_first; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_next) + +#define CCIRCLEQ_FOREACH_REVERSE(var, head, field) \ + for((var) = (head)->cqh_last; \ + (var) != (void *)(head); \ + (var) = (var)->field.cqe_prev) + +#define CCIRCLEQ_INIT(head) do { \ + (head)->cqh_count=0;\ + (head)->cqh_first = (void *)(head); \ + (head)->cqh_last = (void *)(head); \ +} while (0) + +#define CCIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm)->field.cqe_next; \ + (elm)->field.cqe_prev = (listelm); \ + if ((listelm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (listelm)->field.cqe_next->field.cqe_prev = (elm); \ + (listelm)->field.cqe_next = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm); \ + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ + if ((listelm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (listelm)->field.cqe_prev->field.cqe_next = (elm); \ + (listelm)->field.cqe_prev = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.cqe_next = (head)->cqh_first; \ + (elm)->field.cqe_prev = (void *)(head); \ + if ((head)->cqh_last == (void *)(head)) \ + (head)->cqh_last = (elm); \ + else \ + (head)->cqh_first->field.cqe_prev = (elm); \ + (head)->cqh_first = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.cqe_next = (void *)(head); \ + (elm)->field.cqe_prev = (head)->cqh_last; \ + if ((head)->cqh_first == (void *)(head)) \ + (head)->cqh_first = (elm); \ + else \ + (head)->cqh_last->field.cqe_next = (elm); \ + (head)->cqh_last = (elm); \ + (head)->cqh_count++;\ +} while (0) + +#define CCIRCLEQ_LAST(head) ((head)->cqh_last) + +#define CCIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next) + +#define CCIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev) + +#define CCIRCLEQ_REMOVE(head, elm, field) do { \ + if ((elm)->field.cqe_next == (void *)(head)) \ + (head)->cqh_last = (elm)->field.cqe_prev; \ + else \ + (elm)->field.cqe_next->field.cqe_prev = \ + (elm)->field.cqe_prev; \ + if ((elm)->field.cqe_prev == (void *)(head)) \ + (head)->cqh_first = (elm)->field.cqe_next; \ + else \ + (elm)->field.cqe_prev->field.cqe_next = \ + (elm)->field.cqe_next; \ + (head)->cqh_count--;\ +} while (0) +#endif /* !_RTL_QUEUE_H_ */ diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_types.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_types.h new file mode 100644 index 000000000..24f1a2d29 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_types.h @@ -0,0 +1,541 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2002 +* All rights reserved. +* +* Program : The header file of realtek type definition +* Abstract : +* Author : +* $Id: rtl_types.h,v 1.1.1.1 2007-11-12 13:27:50 alva_zhang Exp $ +* $Log: not supported by cvs2svn $ +* Revision 1.20 2007/04/04 15:48:54 chenyl +* +: cleshell commend for asic register configuration : mmtu ( multicast mtu ) +* +* Revision 1.19 2006/08/29 13:00:00 chenyl +* *: New SWNIC driver for RTL865xC +* *: some rearrange in re_core.c for Bootstrap sequence being more readable. +* +* Revision 1.18 2006/02/27 07:47:06 ympan +* +: No change by ympan +* +* Revision 1.17 2005/09/27 05:59:44 chenyl +* *: modify IRAM / DRAM layout: +* IRAM/DRAM-FWD : external used, swNic ... blahblah +* IRAM/DRAM-L2-FWD : fwdengine internal used, L2 and below (ex. preprocess, postprocess) +* IRAM/DRAM-L34-FWD : fwdengine internal used, L3/L4 process only (ex. Routing, decision table...etc). +* +* => If L34 is used, we strongly suggest L2 must be used, too. +* +* Revision 1.16 2005/08/23 14:38:26 chenyl +* +: apply prioirty IRAM/DRAM usage +* +* Revision 1.15 2005/08/22 07:33:55 chenyl +* *: don't set DRAM/IRAM for other OSs yet. +* +* Revision 1.14 2005/08/18 09:14:08 chenyl +* *: add code to porting to other OSs +* +* Revision 1.13 2005/08/18 06:29:29 chenyl +* +: always define the rtlglue_printf in rtl_types.h +* +* Revision 1.12 2005/07/01 09:34:41 yjlou +* *: porting swNic2.c into model code. +* +* Revision 1.11 2005/06/19 05:29:37 yjlou +* *: use 'unsigned int' to replace 'size_t' +* *: define spinlock_t when RTL865X_MODEL_USER defined. +* +* Revision 1.10 2005/06/10 05:32:22 yjlou +* +: Porting CLE Shell to Linux user space for model test. +* See RTL865X_MODEL_USER compile flags. +* +* Revision 1.9 2005/01/10 03:21:43 yjlou +* *: always define __IRAM and __DRAM +* +* Revision 1.8 2004/07/23 13:42:45 tony +* *: remove all warning messages +* +* Revision 1.7 2004/07/05 08:25:32 chenyl +* +: define __IRAM, __DRAM for module test +* +* Revision 1.6 2004/07/04 15:04:55 cfliu +* +: add IRAM and DRAM +* +* Revision 1.5 2004/04/20 03:44:03 tony +* if disable define "RTL865X_OVER_KERNEL" and "RTL865X_OVER_LINUX", __KERNEL__ and __linux__ will be undefined. +* +* Revision 1.4 2004/03/19 13:13:35 cfliu +* Reorganize ROME driver local header files. Put all private data structures into different .h file corrsponding to its layering +* Rename printf, printk, malloc, free with rtlglue_XXX prefix +* +* Revision 1.3 2004/03/05 07:44:27 cfliu +* fix header file problem for ctype.h +* +* Revision 1.2 2004/03/03 10:40:38 yjlou +* *: commit for mergence the difference in rtl86xx_tbl/ since 2004/02/26. +* +* Revision 1.1 2004/02/25 14:26:33 chhuang +* *** empty log message *** +* +* Revision 1.3 2004/02/25 14:24:52 chhuang +* *** empty log message *** +* +* Revision 1.8 2003/12/10 06:30:12 tony +* add linux/config.h, disable define CONFIG_RTL865X_NICDRV2 in mbuf.c by default +* +* Revision 1.7 2003/12/03 14:25:43 cfliu +* change SIZE_T to _SIZE_T. Linux kernel seems to recognize _SIZE_T +* +* Revision 1.6 2003/10/01 12:29:02 tony +* #define DEBUG_P(args...) while(0); +* +* Revision 1.5 2003/10/01 10:31:47 tony +* solve all the compiler warnning messages in the board.c +* +* Revision 1.4 2003/09/30 06:07:50 orlando +* check in RTL8651BLDRV_V20_20030930 +* +* Revision 1.30 2003/07/21 06:27:49 cfliu +* no message +* +* Revision 1.29 2003/04/30 15:32:30 cfliu +* move macros to types.h +* +* Revision 1.28 2003/03/13 10:29:22 cfliu +* Remove unused symbols +* +* Revision 1.27 2003/03/06 05:00:04 cfliu +* Move '#pragma ghs inlineprologue' to rtl_depend.h since it is compiler dependent +* +* Revision 1.26 2003/03/06 03:41:46 danwu +* Prevent compiler from generating internal sub-routine call code at the +* function prologue and epilogue automatically +* +* Revision 1.25 2003/03/03 09:16:35 hiwu +* remove ip4a +* +* Revision 1.24 2003/02/18 10:04:06 jzchen +* Add ether_addr_t to compatable with protocol stack's ether_addr +* +* Revision 1.23 2003/01/21 05:59:51 cfliu +* add min, max, SETBITS, CLEARBITS, etc. +* +* Revision 1.22 2002/11/25 07:31:30 cfliu +* Remove _POSIX_SOURCE since it is cygwin specific +* +* Revision 1.21 2002/09/30 11:51:49 jzchen +* Add ASSERT_ISR for not print inside ISR +* +* Revision 1.20 2002/09/18 01:43:24 jzchen +* Add type limit definition +* +* Revision 1.19 2002/09/16 00:14:34 elvis +* remove struct posix_handle_t (change the handle type from +* structure to uint32) +* +* Revision 1.18 2002/08/20 01:40:40 danwu +* Add definitions of ipaddr_t & macaddr_t. +* +* Revision 1.17 2002/07/30 04:36:30 danwu +* Add ASSERT_CSP. +* +* Revision 1.16 2002/07/19 06:47:30 cfliu +* Add _POSIX_SOURCE symbol +* +* Revision 1.15 2002/07/05 02:10:39 elvis +* Add new types for OSK +* +* Revision 1.14 2002/07/03 12:36:21 orlando +* <rtl_depend.h> will use type definitions. Has to be moved to +* be after the type declaration lines. +* +* Revision 1.13 2002/07/03 09:19:00 cfliu +* Removed all standard header files from source code. They would be included by <core/types.h>-><rtl_depend.h> +* +* Revision 1.12 2002/07/03 09:16:48 cfliu +* Removed all standard header files from source code. They would be included by <core/types.h>-><rtl_depend.h> +* +* Revision 1.11 2002/07/03 07:14:47 orlando +* Add "struct posix_handle_t_", used by POSIX module. +* +* Revision 1.9 2002/06/21 03:15:36 cfliu +* Add time.h for struct timeval +* +* Revision 1.8 2002/06/14 01:58:03 cfliu +* Move sa_family_t to socket +* +* Revision 1.7 2002/06/13 09:37:42 cfliu +* Move byte order conversion routines to socket +* +* Revision 1.6 2002/05/23 04:24:37 hiwu +* change memaddr_t to calladdr_t +* +* Revision 1.5 2002/05/13 10:15:16 hiwu +* add new type definition +* +* Revision 1.4 2002/05/09 05:21:51 cfliu +* Add parenthesis around swaps16, swapl32 +* +* Revision 1.3 2002/04/30 03:07:34 orlando +* Remove UIxx_T definitions to conform with new +* naming conventions. +* +* Revision 1.2 2002/04/29 10:10:32 hiwu +* add NTOHS macro +* +* Revision 1.1.1.1 2002/04/26 08:53:53 orlando +* Initial source tree creation. +* +* Revision 1.9 2002/04/25 03:59:05 cfliu +* no message +* +* Revision 1.8 2002/04/08 08:08:04 hiwu +* initial version +* +*/ + + +#ifndef _RTL_TYPES_H +#define _RTL_TYPES_H + +/* + * Internal names for basic integral types. Omit the typedef if + * not possible for a machine/compiler combination. + */ +#ifdef __linux__ +#ifdef __KERNEL__ +#include <linux/version.h> +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) +#include <linux/config.h> +#endif +#include <linux/ctype.h> +#include <linux/module.h> +#include <linux/string.h> +#endif /*__KERNEL__*/ +#endif /*__linux__*/ + +/* =============================================================================== + IRAM / DRAM definition + =============================================================================== */ +#undef __DRAM_GEN +#undef __DRAM_FWD +#undef __DRAM_L2_FWD +#undef __DRAM_L34_FWD +#undef __DRAM_EXTDEV +#undef __DRAM_AIRGO +#undef __DRAM_RTKWLAN +#undef __DRAM_CRYPTO +#undef __DRAM_VOIP +#undef __DRAM_TX +#undef __DRAM + +#undef __IRAM_GEN +#undef __IRAM_FWD +#undef __IRAM_L2_FWD +#undef __IRAM_L34_FWD +#undef __IRAM_EXTDEV +#undef __IRAM_AIRGO +#undef __IRAM_RTKWLAN +#undef __IRAM_CRYPTO +#undef __IRAM_VOIP +#undef __IRAM_TX +#undef __IRAM + +#if defined(__linux__)&&defined(__KERNEL__)&&defined(CONFIG_RTL865X) + #define __DRAM_GEN __attribute__ ((section(".dram-gen"))) + #define __DRAM_FWD __attribute__ ((section(".dram-fwd"))) + #define __DRAM_L2_FWD __attribute__ ((section(".dram-l2-fwd"))) + #define __DRAM_L34_FWD __attribute__ ((section(".dram-l34-fwd"))) + #define __DRAM_EXTDEV __attribute__ ((section(".dram-extdev"))) + #define __DRAM_AIRGO __attribute__ ((section(".dram-airgo"))) + #define __DRAM_RTKWLAN __attribute__ ((section(".dram-rtkwlan"))) + #define __DRAM_CRYPTO __attribute__ ((section(".dram-crypto"))) + #define __DRAM_VOIP __attribute__ ((section(".dram-voip"))) + #define __DRAM_TX __attribute__ ((section(".dram-tx"))) + #define __DRAM __attribute__ ((section(".dram"))) + + #define __IRAM_GEN __attribute__ ((section(".iram-gen"))) + #define __IRAM_FWD __attribute__ ((section(".iram-fwd"))) + #define __IRAM_L2_FWD __attribute__ ((section(".iram-l2-fwd"))) + #define __IRAM_L34_FWD __attribute__ ((section(".iram-l34-fwd"))) + #define __IRAM_EXTDEV __attribute__ ((section(".iram-extdev"))) + #define __IRAM_AIRGO __attribute__ ((section(".iram-airgo"))) + #define __IRAM_RTKWLAN __attribute__ ((section(".iram-rtkwlan"))) + #define __IRAM_CRYPTO __attribute__ ((section(".iram-crypto"))) + #define __IRAM_VOIP __attribute__ ((section(".iram-voip"))) + #define __IRAM_TX __attribute__ ((section(".iram-tx"))) + #define __IRAM __attribute__ ((section(".iram"))) +#else + #define __DRAM_GEN + #define __DRAM_FWD + #define __DRAM_L2_FWD + #define __DRAM_L34_FWD + #define __DRAM_EXTDEV + #define __DRAM_AIRGO + #define __DRAM_RTKWLAN + #define __DRAM_CRYPTO + #define __DRAM_VOIP + #define __DRAM_TX + #define __DRAM + + #define __IRAM_GEN + #define __IRAM_FWD + #define __IRAM_L2_FWD + #define __IRAM_L34_FWD + #define __IRAM_EXTDEV + #define __IRAM_AIRGO + #define __IRAM_RTKWLAN + #define __IRAM_CRYPTO + #define __IRAM_VOIP + #define __IRAM_TX + #define __IRAM +#endif + +#if defined(CONFIG_RTL_DYNAMIC_IRAM_MAPPING_FOR_WAPI) + #define __IRAM_GEN_WAPI __attribute__ ((section(".iram-gen-wapi"))) + #define __IRAM_FWD_WAPI __attribute__ ((section(".iram-fwd-wapi"))) + #define __IRAM_L2_FWD_WAPI __attribute__ ((section(".iram-l2-fwd-wapi"))) + #define __IRAM_L34_FWD_WAPI __attribute__ ((section(".iram-l34-fwd-wapi"))) + #define __IRAM_RTKWLAN_WAPI __attribute__ ((section(".iram-rtkwlan-wapi"))) + #define __IRAM_TX_WAPI __attribute__ ((section(".iram-tx-wapi"))) + + #define FUNCTION_CHECK(x) do \ + { \ + if((x)==NULL) \ + printk("---%s %s(%d) function is NULL!!\n",__FILE__,__FUNCTION__,__LINE__); \ + } while(0) +#endif + +/* =============================================================================== + print macro + =============================================================================== */ +#if defined(__linux__)&&defined(__KERNEL__) + + #define rtlglue_printf printk + +#else /* defined(__linux__)&&defined(__KERNEL__) */ + +#ifdef RTL865X_TEST + #include <ctype.h> +#endif /* RTL865X_TEST */ + +#define rtlglue_printf printf + +#endif /* defined(__linux__)&&defined(__KERNEL__) */ + +/* =============================================================================== + Type definition + =============================================================================== */ + +typedef unsigned long long uint64; +typedef long long int64; +typedef unsigned int uint32; +typedef int int32; +typedef unsigned short uint16; +typedef short int16; +typedef unsigned char uint8; +typedef char int8; + + +typedef uint32 memaddr; +typedef uint32 ipaddr_t; +typedef struct { + uint16 mac47_32; + uint16 mac31_16; + uint16 mac15_0; +} macaddr_t; + +#define ETHER_ADDR_LEN 6 +typedef struct ether_addr_s { + uint8 octet[ETHER_ADDR_LEN]; +} ether_addr_t; + + + +#ifndef NULL +#define NULL 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef SUCCESS +#define SUCCESS 0 +#endif +#ifndef FAILED +#define FAILED -1 +#endif + + + +#define DEBUG_P(args...) while(0); +#ifndef OK +#define OK 0 +#endif +#ifndef NOT_OK +#define NOT_OK 1 +#endif + +#ifndef CLEARBITS +#define CLEARBITS(a,b) ((a) &= ~(b)) +#endif + +#ifndef SETBITS +#define SETBITS(a,b) ((a) |= (b)) +#endif + +#ifndef ISSET +#define ISSET(a,b) (((a) & (b))!=0) +#endif + +#ifndef ISCLEARED +#define ISCLEARED(a,b) (((a) & (b))==0) +#endif + +#ifndef max +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#endif /* max */ + +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif /* min */ + +//round down x to multiple of y. Ex: ROUNDDOWN(20, 7)=14 +#ifndef ROUNDDOWN +#define ROUNDDOWN(x, y) (((x)/(y))*(y)) +#endif + +//round up x to multiple of y. Ex: ROUNDUP(11, 7) = 14 +#ifndef ROUNDUP +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ +#endif + +#ifndef ROUNDUP2 +#define ROUNDUP2(x, y) (((x)+((y)-1))&(~((y)-1))) /* if y is powers of two */ +#endif + +#ifndef ROUNDUP4 +#define ROUNDUP4(x) ((1+(((x)-1)>>2))<<2) +#endif + +#ifndef IS4BYTEALIGNED +#define IS4BYTEALIGNED(x) ((((x) & 0x3)==0)? 1 : 0) +#endif + +#ifndef __offsetof +#define __offsetof(type, field) ((unsigned long)(&((type *)0)->field)) +#endif + +#ifndef offsetof +#define offsetof(type, field) __offsetof(type, field) +#endif + +#ifndef RTL_PROC_CHECK +#define RTL_PROC_CHECK(expr, success) \ + do {\ + int __retval; \ + if ((__retval = (expr)) != (success))\ + {\ + rtlglue_printf("ERROR >>> [%s]:[%d] failed -- return value: %d\n", __FUNCTION__,__LINE__, __retval);\ + return __retval; \ + }\ + }while(0) +#endif + +#ifndef RTL_STREAM_SAME +#define RTL_STREAM_SAME(s1, s2) \ + ((strlen(s1) == strlen(s2)) && (strcmp(s1, s2) == 0)) +#endif + +#define ASSERT_ISR(x) if(!(x)) {while(1);} +#define RTL_STATIC_INLINE static __inline__ + +#define ASSERT_CSP(x) if (!(x)) {rtlglue_printf("\nAssert Fail: %s %d", __FILE__, __LINE__); while(1);} + +#if defined(RTL865X_TEST) || defined(RTL865X_MODEL_USER) +/* Only model code needs to define the following code. */ +typedef struct { } spinlock_t; +typedef uint8 u8; +typedef uint16 u16; +typedef uint32 u32; +#endif + +#if defined(DRTL_TBLDRV)||defined(RTL865X_TEST) +//only ROME driver and module test code need to include this header file +#include "rtl_glue.h" +#endif + +#if defined(RTL865X_TEST)||defined(RTL865X_MODEL_USER) +#define UNCACHE_MASK 0 +#define UNCACHE(addr) (addr) +#define CACHED(addr) ((uint32)(addr)) +#else +#define UNCACHE_MASK 0x20000000 +#define UNCACHE(addr) ((UNCACHE_MASK)|(uint32)(addr)) +#define CACHED(addr) ((uint32)(addr) & ~(UNCACHE_MASK)) +#endif + + +#define swapl32(x)\ + ((((x) & 0xff000000U) >> 24) | \ + (((x) & 0x00ff0000U) >> 8) | \ + (((x) & 0x0000ff00U) << 8) | \ + (((x) & 0x000000ffU) << 24)) +#define swaps16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) + +#ifdef _LITTLE_ENDIAN + +/*#ifndef __linux__*/ + #define ntohs(x) (swaps16(x)) + #define ntohl(x) (swapl32(x)) + #define htons(x) (swaps16(x)) + #define htonl(x) (swapl32(x)) +/*#endif*/ + #define NTOHL(d) ((d) = ntohl((d))) + #define NTOHS(d) ((d) = ntohs((uint16)(d))) + #define HTONL(d) ((d) = htonl((d))) + #define HTONS(d) ((d) = htons((uint16)(d))) + + #define GET_UINT16_UNALIGNED( ptr ) GET_UINT16_LITTLE_ENDIAN_UNALIGNED(ptr) + #define SET_UINT16_UNALIGNED( u16value, ptr ) SET_UINT16_LITTLE_ENDIAN_UNALIGNED( u16value, ptr ) + #define GET_UINT32_UNALIGNED( ptr ) GET_UINT32_LITTLE_ENDIAN_UNALIGNED(ptr) + #define SET_UINT32_UNALIGNED( u32value, ptr ) SET_UINT32_LITTLE_ENDIAN_UNALIGNED( u32value,ptr) + #define PKTGET_UINT16_UNALIGNED( ptr ) GET_UINT16_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT16_UNALIGNED( u16value, ptr ) SET_UINT16_BIG_ENDIAN_UNALIGNED( u16value, ptr ) + #define PKTGET_UINT32_UNALIGNED( ptr ) GET_UINT32_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT32_UNALIGNED( u32value, ptr ) SET_UINT32_BIG_ENDIAN_UNALIGNED( u32value,ptr) + +#else /*Big endian system */ + +/* chhuang */ +#ifdef __linux__ + #undef ntohs + #undef ntohl + #undef htons + #undef htonl + #define ntohs(x) (x) + #define ntohl(x) (x) + #define htons(x) (x) + #define htonl(x) (x) + #define _LINUX_BYTEORDER_GENERIC_H +#endif /* __linux__ */ + #define NTOHL(d) ((d) = ntohl(d)) + #define NTOHS(d) ((d) = ntohs((uint16)(d))) + #define HTONL(d) ((d) = htonl(d)) + #define HTONS(d) ((d) = htons((uint16)(d))) + #define GET_UINT16_UNALIGNED( ptr ) GET_UINT16_BIG_ENDIAN_UNALIGNED(ptr) + #define SET_UINT16_UNALIGNED( u16value, ptr ) SET_UINT16_BIG_ENDIAN_UNALIGNED( u16value, ptr ) + #define GET_UINT32_UNALIGNED( ptr ) GET_UINT32_BIG_ENDIAN_UNALIGNED(ptr) + #define SET_UINT32_UNALIGNED( u32value, ptr ) SET_UINT32_BIG_ENDIAN_UNALIGNED( u32value,ptr) + #define PKTGET_UINT16_UNALIGNED( ptr ) GET_UINT16_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT16_UNALIGNED( u16value, ptr) SET_UINT16_BIG_ENDIAN_UNALIGNED( u16value, ptr ) + #define PKTGET_UINT32_UNALIGNED( ptr ) GET_UINT32_BIG_ENDIAN_UNALIGNED(ptr) + #define PKTSET_UINT32_UNALIGNED( u32value, ptr) SET_UINT32_BIG_ENDIAN_UNALIGNED( u32value,ptr) +#endif + +#endif/*_LITTLE_ENDIAN*/ + diff --git a/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_utils.h b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_utils.h new file mode 100644 index 000000000..767432f5f --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/mips/rtl_utils.h @@ -0,0 +1,80 @@ +/* +* Copyright c Realtek Semiconductor Corporation, 2002 +* All rights reserved. +* +* Program : Header File for RTL utilities +* Abstract : +* Author : +* $Id: rtl_utils.h,v 1.1.1.1 2007-11-12 13:27:50 alva_zhang Exp $ +*/ + +#ifndef __RTL_UTILS_H__ +#define __RTL_UTILS_H__ + +#include "rtl_types.h" + + + +void __strlowerncpy(char *dst, const char *src, int32 len); +int8 *_strncpy(int8 *dst0, const int8 *src0, int32 count); +int _strncasecmp(const char *s1, const char *s2, unsigned int n); +int32 _strncmp(const int8 *s1, const int8 *s2, int32 n); +void rtl8651_memcpy(void *dst,void*src,int32 len); +int32 isPowerOf2(uint32 number, uint32 *exponent); +int32 IpStrToAscii(const int8 *cp, uint32 *addr); +void IntToAscii(int32 n, int8 s[]); +int AsciiToInt( char **s); +uint8 charToInt(char c); +int32 ether_aton_r(int8 *a, ether_addr_t *eth); +int32 ether_ntoa_r(ether_addr_t *n, uint8 *a); +int8 *inet_ntoa_r(ipaddr_t ipaddr, int8 *p); +void memDump (void *start, uint32 size, int8 * strHeader); +int32 memComp( void* _p1, void *_p2, int32 len, uint8* strHeader ); +uint8* strtomac(ether_addr_t *mac, int8 *str); + +#define PROFILING_START(x) do{}while(0) +#define PROFILING_END(x) do{}while(0) + + + +/*=================================================================== + * ONE's COMPLEMENT OPERATION + * All the operands and return value are 'host-order'. + * Please notice the endian problem. + *===================================================================*/ +/* One's Complement ADD */ +inline static uint16 OCADD( uint16 a, uint16 b ) +{ + uint32 t; /* temp */ + t = ((a)&0xffff)+((b)&0xffff); + t = (t&0xffff)+(t>>16); + return (uint16)t; +} + +/* One's Complement NEGtive */ +inline static uint16 OCNEG( uint16 a ) +{ + return (~a)&0xffff; +} + +/* One's Complement SUBtract */ +inline static uint16 OCSUB( uint16 a, uint16 b ) +{ + return OCADD( a, OCNEG(b) ); +} + +ipaddr_t convPrefix(int prefixLen); + + +#if defined(RTL8389_MODEL_USER) + /* User mode, compiler use STDINC, said that, bezro is defined. */ +#else + /* Not user mode, we need define. */ + #ifndef bzero + #define bzero( p, s ) memset( p, 0, s ) + #endif +#endif + + +#endif /* __RTL_UTILS_H__ */ + diff --git a/target/linux/realtek/files/arch/mips/include/asm/rlxregs.h b/target/linux/realtek/files/arch/mips/include/asm/rlxregs.h new file mode 100644 index 000000000..32ef8bec5 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/include/asm/rlxregs.h @@ -0,0 +1,1563 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * Copyright (C) 2003, 2004 Maciej W. Rozycki + */ +#ifndef _ASM_MIPSREGS_H +#define _ASM_MIPSREGS_H + +#include <linux/linkage.h> +#include <asm/hazards.h> +#include <asm/war.h> + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 +#define CP0_DESAVE $31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * Values for PageMask register + */ +#ifdef CONFIG_CPU_VR41XX + +/* Why doesn't stupidity hurt ... */ + +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 + +#else + +#define PM_4K 0x00000000 +#define PM_8K 0x00002000 +#define PM_16K 0x00006000 +#define PM_32K 0x0000e000 +#define PM_64K 0x0001e000 +#define PM_128K 0x0003e000 +#define PM_256K 0x0007e000 +#define PM_512K 0x000fe000 +#define PM_1M 0x001fe000 +#define PM_2M 0x003fe000 +#define PM_4M 0x007fe000 +#define PM_8M 0x00ffe000 +#define PM_16M 0x01ffe000 +#define PM_32M 0x03ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 +#define PM_1G 0x7fffe000 + +#endif + +/* + * Default page size for a given kernel configuration + */ +#ifdef CONFIG_PAGE_SIZE_4KB +#define PM_DEFAULT_MASK PM_4K +#elif defined(CONFIG_PAGE_SIZE_8KB) +#define PM_DEFAULT_MASK PM_8K +#elif defined(CONFIG_PAGE_SIZE_16KB) +#define PM_DEFAULT_MASK PM_16K +#elif defined(CONFIG_PAGE_SIZE_32KB) +#define PM_DEFAULT_MASK PM_32K +#elif defined(CONFIG_PAGE_SIZE_64KB) +#define PM_DEFAULT_MASK PM_64K +#else +#error Bad page size configuration! +#endif + + +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate + * cacheops in userspace. This bit exists only on RM7000 and RM9000 + * processors. + */ +#define ST0_CO 0x08000000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Enable the MIPS MDMX and DSP ASEs + */ +#define ST0_MX 0x01000000 + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_P4K (_ULCAST_(1) << 13) +#define VR41_CONF_BP (_ULCAST_(1) << 16) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. + */ +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS (_ULCAST_(7) << 22) +#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) + +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) +#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) +#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) +#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF2_TU (_ULCAST_(7) << 28) + +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) + +#define MIPS_CONF7_WII (_ULCAST_(1) << 31) + +#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) + + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. + */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) + +#ifndef __ASSEMBLY__ + +/* + * Functions to access the R10000 performance counters. These are basically + * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit + * performance counter number encoded into bits 1 ... 5 of the instruction. + * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware + * disassembler these will look like an access to sel 0 or 1. + */ +#define read_r10k_perf_cntr(counter) \ +({ \ + unsigned int __res; \ + __asm__ __volatile__( \ + "mfpc\t%0, %1" \ + : "=r" (__res) \ + : "i" (counter)); \ + \ + __res; \ +}) + +#define write_r10k_perf_cntr(counter,val) \ +do { \ + __asm__ __volatile__( \ + "mtpc\t%0, %1" \ + : \ + : "r" (val), "i" (counter)); \ +} while (0) + +#define read_r10k_perf_event(counter) \ +({ \ + unsigned int __res; \ + __asm__ __volatile__( \ + "mfps\t%0, %1" \ + : "=r" (__res) \ + : "i" (counter)); \ + \ + __res; \ +}) + +#define write_r10k_perf_cntl(counter,val) \ +do { \ + __asm__ __volatile__( \ + "mtps\t%0, %1" \ + : \ + : "r" (val), "i" (counter)); \ +} while (0) + + +/* + * Macros to access the system control coprocessor + */ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long long __res; \ + if (sizeof(unsigned long) == 4) \ + __res = __read_64bit_c0_split(source, sel); \ + else if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_64bit_c0_split(register, sel, value); \ + else if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ +} while (0) + +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + (unsigned long) __read_32bit_c0_register(reg, sel) : \ + (unsigned long) __read_64bit_c0_register(reg, sel)) + +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ +} while (0) + +/* + * On RM7000/RM9000 these are uses to access cop0 set 1 registers + */ +#define __read_32bit_c0_ctrl_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + "cfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_ctrl_register(register, value) \ +do { \ + __asm__ __volatile__( \ + "ctc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +/* + * These versions are only needed for systems with more than 38 bits of + * physical address space running the 32-bit kernel. That's none atm :-) + */ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long __val; \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (__val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (__val)); \ + local_irq_restore(__flags); \ + \ + __val; \ +}) + +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long __flags; \ + \ + local_irq_save(__flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(__flags); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) + +#define read_c0_userlocal() __read_ulong_c0_register($4, 2) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) +#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ +#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) + +#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ +#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) + +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ +#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) + +#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ +#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#ifdef CONFIG_MIPS_MT_SMTC +#define write_c0_status(val) \ +do { \ + __write_32bit_c0_register($12, 0, val); \ + __ehb(); \ +} while (0) +#else +/* + * Legacy non-SMTC code, which may be hazardous + * but which might not support EHB + */ +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#endif /* CONFIG_MIPS_MT_SMTC */ + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define read_c0_config4() __read_32bit_c0_register($16, 4) +#define read_c0_config5() __read_32bit_c0_register($16, 5) +#define read_c0_config6() __read_32bit_c0_register($16, 6) +#define read_c0_config7() __read_32bit_c0_register($16, 7) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) + +/* + * The WatchLo register. There may be upto 8 of them. + */ +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) + +/* + * The WatchHi register. There may be upto 8 of them. + */ +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) + +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) + +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) + +#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) +#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) + +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) + +/* RM9000 PerfControl performance counter control register */ +#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) +#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_diag1() __read_32bit_c0_register($22, 1) +#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_diag2() __read_32bit_c0_register($22, 2) +#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_diag3() __read_32bit_c0_register($22, 3) +#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_diag4() __read_32bit_c0_register($22, 4) +#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_diag5() __read_32bit_c0_register($22, 5) +#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) + +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) + +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) + +/* + * MIPS32 / MIPS64 performance counters + */ +#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) +#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) +#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) +#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) +#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) +#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) +#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) +#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) +#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) +#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) +#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) +#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) +#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) +#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) +#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) +#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) + +/* RM9000 PerfCount performance counter register */ +#define read_c0_perfcount() __read_64bit_c0_register($25, 0) +#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) + +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) + +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) + +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) + +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) + +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) + +#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) +#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) + +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) + +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) + +/* MIPSR2 */ +#define read_c0_hwrena() __read_32bit_c0_register($7, 0) +#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_intctl() __read_32bit_c0_register($12, 1) +#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) + +#define read_c0_srsctl() __read_32bit_c0_register($12, 2) +#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) + +#define read_c0_srsmap() __read_32bit_c0_register($12, 3) +#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) + +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + + +/* Cavium OCTEON (cnMIPS) */ +#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) +#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) + +#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) +#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) + +#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) +#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) +/* + * The cacheerr registers are not standardized. On OCTEON, they are + * 64 bits wide. + */ +#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) +#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) + +#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) +#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) + +/* + * Macros to access the floating point coprocessor control registers + */ +#define read_32bit_cp1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + /* gas fails to assemble cfc1 for some archs (octeon).*/ \ + ".set\tmips1\n\t" \ + "cfc1\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define rddsp(mask) \ +({ \ + unsigned int __res; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # rddsp $1, %x1 \n" \ + " .word 0x7c000cb8 | (%x1 << 16) \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__res) \ + : "i" (mask)); \ + __res; \ +}) + +#define wrdsp(val, mask) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # wrdsp $1, %x1 \n" \ + " .word 0x7c2004f8 | (%x1 << 11) \n" \ + " .set pop \n" \ + : \ + : "r" (val), "i" (mask)); \ +} while (0) + +#if 0 /* Need DSP ASE capable assembler ... */ +#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) +#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) +#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) +#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) + +#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) +#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) +#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) +#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) + +#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) +#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) +#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) +#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) + +#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) +#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) +#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) +#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) + +#else + +#define mfhi0() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac0 \n" \ + " .word 0x00000810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi1() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac1 \n" \ + " .word 0x00200810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi2() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac2 \n" \ + " .word 0x00400810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mfhi3() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mfhi %0, $ac3 \n" \ + " .word 0x00600810 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo0() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac0 \n" \ + " .word 0x00000812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo1() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac1 \n" \ + " .word 0x00200812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo2() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac2 \n" \ + " .word 0x00400812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mflo3() \ +({ \ + unsigned long __treg; \ + \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " # mflo %0, $ac3 \n" \ + " .word 0x00600812 \n" \ + " move %0, $1 \n" \ + " .set pop \n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mthi0(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac0 \n" \ + " .word 0x00200011 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi1(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac1 \n" \ + " .word 0x00200811 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi2(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac2 \n" \ + " .word 0x00201011 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mthi3(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mthi $1, $ac3 \n" \ + " .word 0x00201811 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo0(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac0 \n" \ + " .word 0x00200013 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo1(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac1 \n" \ + " .word 0x00200813 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo2(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac2 \n" \ + " .word 0x00201013 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#define mtlo3(x) \ +do { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " move $1, %0 \n" \ + " # mtlo $1, $ac3 \n" \ + " .word 0x00201813 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +} while (0) + +#endif + +/* + * TLB operations. + * + * It is responsibility of the caller to take care of any TLB hazards. + */ +static inline void tlb_probe(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); +} + +static inline void tlb_read(void) +{ +#if MIPS34K_MISSED_ITLB_WAR + int res = 0; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41610001 # dvpe $1 \n" + " move %0, $1 \n" + " ehb \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); +#endif + + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); + +#if MIPS34K_MISSED_ITLB_WAR + if ((res & _ULCAST_(1))) + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41600021 # evpe \n" + " ehb \n" + " .set pop \n"); +#endif +} + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); +} + +static inline void tlb_write_random(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); +} + +/* + * Manipulate bits in a c0 register. + */ +#ifndef CONFIG_MIPS_MT_SMTC +/* + * SMTC Linux requires shutting-down microthread scheduling + * during CP0 register read-modify-write sequences. + */ +#define __BUILD_SET_C0(name) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res, new; \ + \ + res = read_c0_##name(); \ + new = res | set; \ + write_c0_##name(new); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res, new; \ + \ + res = read_c0_##name(); \ + new = res & ~clear; \ + write_c0_##name(new); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int val) \ +{ \ + unsigned int res, new; \ + \ + res = read_c0_##name(); \ + new = res & ~change; \ + new |= (val & change); \ + write_c0_##name(new); \ + \ + return res; \ +} + +#else /* SMTC versions that manage MT scheduling */ + +#include <linux/irqflags.h> + +/* + * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with + * header file recursion. + */ +static inline unsigned int __dmt(void) +{ + int res; + + __asm__ __volatile__( + " .set push \n" + " .set mips32r2 \n" + " .set noat \n" + " .word 0x41610BC1 # dmt $1 \n" + " ehb \n" + " move %0, $1 \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); + + return res; +} + +#define __VPECONTROL_TE_SHIFT 15 +#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) + +#define __EMT_ENABLE __VPECONTROL_TE + +static inline void __emt(unsigned int previous) +{ + if ((previous & __EMT_ENABLE)) + __asm__ __volatile__( + " .set mips32r2 \n" + " .word 0x41600be1 # emt \n" + " ehb \n" + " .set mips0 \n"); +} + +static inline void __ehb(void) +{ + __asm__ __volatile__( + " .set mips32r2 \n" + " ehb \n" " .set mips0 \n"); +} + +/* + * Note that local_irq_save/restore affect TC-specific IXMT state, + * not Status.IE as in non-SMTC kernel. + */ + +#define __BUILD_SET_C0(name) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + unsigned int new; \ + unsigned int omt; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + omt = __dmt(); \ + res = read_c0_##name(); \ + new = res | set; \ + write_c0_##name(new); \ + __emt(omt); \ + local_irq_restore(flags); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + unsigned int new; \ + unsigned int omt; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + omt = __dmt(); \ + res = read_c0_##name(); \ + new = res & ~clear; \ + write_c0_##name(new); \ + __emt(omt); \ + local_irq_restore(flags); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int newbits) \ +{ \ + unsigned int res; \ + unsigned int new; \ + unsigned int omt; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + \ + omt = __dmt(); \ + res = read_c0_##name(); \ + new = res & ~change; \ + new |= (newbits & change); \ + write_c0_##name(new); \ + __emt(omt); \ + local_irq_restore(flags); \ + \ + return res; \ +} +#endif + +__BUILD_SET_C0(status) +__BUILD_SET_C0(cause) +__BUILD_SET_C0(config) +__BUILD_SET_C0(intcontrol) +__BUILD_SET_C0(intctl) +__BUILD_SET_C0(srsmap) + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_MIPSREGS_H */ diff --git a/target/linux/realtek/files/arch/mips/kernel/cevt-rtl819x.c b/target/linux/realtek/files/arch/mips/kernel/cevt-rtl819x.c new file mode 100644 index 000000000..102eb6dbd --- /dev/null +++ b/target/linux/realtek/files/arch/mips/kernel/cevt-rtl819x.c @@ -0,0 +1,187 @@ +#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/time.h>
+#include <platform.h>
+
+#if defined(CONFIG_RTL_WTDOG)
+ int is_fault=0; // kernel fault flag
+#endif
+
+#ifdef CONFIG_RTL_TIMER_ADJUSTMENT
+#define TIMER0_ADJUSTMENT_THRESHOLD 20
+
+
+//static unsigned long tuRemainder=0; /* unit is the same as TC0DATA, say "timer unit". */
+static unsigned long tuRemainder=0;
+static unsigned long previousTC1CNT=0xFFFFFF00; /* Previous value of Timer 1 */
+static u64 timer0AccJiffies=0;
+static u64 timer1AccJiffies=0; /* accumulated jiffies, unit is the same as jiffies, 1/HZ. */
+static unsigned int timer0IntCnt=0;
+#define TICK_SIZE (tick_nsec / 1000)
+
+unsigned long rtl865x_getTimer1PassedJiffies(void)
+{
+ unsigned long jifPassed=0;
+ unsigned long currTC1CNT;
+ unsigned long tc0data;
+
+ //tc0data = READ_MEM32(TC0DATA)>>TCD_OFFSET;
+ tc0data =((MHZ * 250) / HZ);
+ /* compute passed time since last time executed this function */
+ currTC1CNT = READ_MEM32(TC1CNT);
+
+#if defined(CONFIG_RTL_819X)
+ /*
+ In RTL865xC, timer / counter is incremental
+ */
+ if ( previousTC1CNT <= currTC1CNT )
+ {
+ /* No wrap happend. */
+ tuRemainder += (currTC1CNT-previousTC1CNT)>>TCD_OFFSET; /* how many units are passed since last check? */
+ }
+ else
+ {
+ /* Timer1 wrapped!! */
+ tuRemainder += (currTC1CNT+(0xffffff00-previousTC1CNT)+(0x1<<TCD_OFFSET))>>TCD_OFFSET; /* how many units are passed since last check? */
+ }
+#endif
+ previousTC1CNT = currTC1CNT; /* keep TC1CNT value for next time check */
+
+ /* If tc0data is zero, it means 'time is frozen.' */
+ if ( tc0data == 0 )
+ {
+ jifPassed = 0;
+ }
+ else
+ {
+ jifPassed = tuRemainder / tc0data;
+ tuRemainder = tuRemainder % tc0data;
+ }
+
+ timer1AccJiffies += jifPassed;
+ return jifPassed;
+}
+#endif
+
+int rlx_timer_state(void)
+{
+ return 0;
+}
+
+int rlx_timer_set_base_clock(unsigned int hz)
+{
+ return 0;
+}
+
+static int rtl_timer_set_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+{
+ return -EINVAL;
+}
+
+static void rtl_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ return;
+}
+
+static void rtl_timer_event_handler(struct clock_event_device *dev)
+{
+}
+
+static void rtl_timer_ack(void)
+{ + REG32(TCIR) |= TC0IP; +}
+
+static struct clock_event_device rtl819x_clockevent = {
+ .name = "rtl819x timer",
+ .features = CLOCK_EVT_FEAT_PERIODIC,
+ .set_next_event = rtl_timer_set_next_event,
+ .set_mode = rtl_timer_set_mode,
+ .event_handler = rtl_timer_event_handler,
+};
+
+static irqreturn_t rtl_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *cd = &rtl819x_clockevent;
+
+#if defined(CONFIG_RTL_WTDOG)
+ if (!is_fault) {
+ #ifdef CONFIG_RTK_VOIP
+ extern int bBspWatchdog;
+
+ if( bBspWatchdog )
+ *(volatile unsigned long *)(0xB800311c) |= 1 << 23;
+ else
+ *(volatile unsigned long *)(0xB800311c) |= ( ( 1 << 23 ) | ( 0xA5 << 24 ) );
+ #else
+ *(volatile unsigned long *)(0xB800311c) |= 1 << 23;
+ #endif
+ } else {
+ // quick fix for warn reboot fail issue
+ local_irq_disable();
+ *(volatile unsigned long *)(0xB800311c)=0; /*this is to enable 865xc watch dog reset*/
+ for(;;);
+ }
+#endif
+
+#if defined(CONFIG_RTL_TIMER_ADJUSTMENT)
+ timer0AccJiffies++;
+ timer0IntCnt++;
+ if((timer0IntCnt%TIMER0_ADJUSTMENT_THRESHOLD)==0)
+ {
+ rtl865x_getTimer1PassedJiffies();
+ if(timer1AccJiffies>timer0AccJiffies)
+ {
+ /*to compensate system jiffied, because timer0's interrupt may be disabled by nic driver*/
+ do_timer((timer1AccJiffies-timer0AccJiffies)+1);
+ timer0AccJiffies=timer1AccJiffies;
+ }
+ else
+ {
+ /*for timer1 start later than timer0*/
+ if(timer1AccJiffies<timer0AccJiffies)
+ {
+ timer1AccJiffies=timer0AccJiffies;
+ }
+ do_timer(1);
+ }
+ }
+ else
+ {
+ do_timer(1);
+ }
+#endif
+
+ /* Ack the RTC interrupt. */
+//printk("====%s(%d),jiffes(%lu)\n",__FUNCTION__,__LINE__,jiffies);
+ rtl_timer_ack();
+ cd->event_handler(cd);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction rtl_irqaction = {
+ .handler = rtl_timer_interrupt,
+ .flags = IRQF_DISABLED | IRQF_PERCPU,
+ .name = "rtl timer",
+};
+
+int __init rtl_clockevent_init(int irq)
+{
+ struct clock_event_device *cd;
+
+ cd = &rtl819x_clockevent;
+ cd->rating = 100;
+ cd->irq = irq;
+ clockevent_set_clock(cd, 32768);
+ cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
+ cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
+ cd->cpumask = cpumask_of(0);
+
+ clockevents_register_device(&rtl819x_clockevent);
+
+ return setup_irq(irq, &rtl_irqaction);
+}
diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/Makefile b/target/linux/realtek/files/arch/mips/rtl8196b/Makefile new file mode 100644 index 000000000..f7e8766ca --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the RTL8652 specific parts of the kernel +# +DIR_RTLASIC = $(DIR_LINUX)/drivers/net/rtl819x/ + +obj-y := setup.o printf.o int.o mem.o +obj-$(CONFIG_PCI) += pci.o +EXTRA_AFLAGS := $(CFLAGS) +EXTRA_CFLAGS += -I$(DIR_RTLASIC) diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/int.c b/target/linux/realtek/files/arch/mips/rtl8196b/int.c new file mode 100644 index 000000000..fd8699a23 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/int.c @@ -0,0 +1,281 @@ +#include <linux/config.h>
+#include <linux/irq.h>
+
+#include <asm/irq_cpu.h>
+#include <prom.h>
+#include <platform.h>
+#include <linux/hardirq.h>
+#if defined(CONFIG_RTL_819X)
+#include <common/rtl_types.h>
+#endif
+
+spinlock_t irq_lock = SPIN_LOCK_UNLOCKED;
+
+static void rtl8196_enable_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ REG32(GIMR) = REG32(GIMR) | (1 << irq);
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static unsigned int rtl8196_startup_irq(unsigned int irq)
+{
+ rtl8196_enable_irq(irq);
+
+ return 0;
+}
+
+static void rtl8196_disable_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ REG32(GIMR) = REG32(GIMR) & (~(1 << irq));
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static void rtl8196_end_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ REG32(GIMR) = REG32(GIMR) | (1 << irq);
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+#define rtl8196_shutdown_irq rtl8196_disable_irq
+#define rtl8196_mask_and_ack_irq rtl8196_disable_irq
+
+static struct irq_chip irq_type = {
+ .typename = "RTL8196",
+ .startup = rtl8196_startup_irq,
+ .shutdown = rtl8196_shutdown_irq,
+ .enable = rtl8196_enable_irq,
+ .disable = rtl8196_disable_irq,
+ .ack = rtl8196_mask_and_ack_irq,
+ .end = rtl8196_end_irq,
+ .mask = rtl8196_disable_irq,
+ .mask_ack = rtl8196_mask_and_ack_irq,
+ .unmask = rtl8196_enable_irq,
+};
+
+
+/*
+ * RTL8196b Interrupt Scheme (Subject to change)
+ *
+ * Source EXT_INT IRQ CPU INT
+ * -------- ------- ------ -------
+ * PCIB0TO 0 0 2
+ * PCIB1TO 1 1 2
+ * LBCTMOm0 2 2 2
+ * LBCTMOm1 3 3 2
+ * LBCTMOs 4 4 2
+ * TIMER0 8 8 7
+ * TIMER1 9 9 2
+ * USB 10 10 4
+ * UART0 12 12 3
+ * UART1 13 13 2
+ * PCI 14 14 5
+ * SWCORE 15 15 6
+ * GPIO_ABCD 16 16 2
+ * GPIO_EFGH 17 17 2
+ * HCI 18 18 2
+ * PCM 19 19 2
+ * CRYPTO 20 20 2
+ * GDMA 21 21 2
+ */
+
+void __init arch_init_irq(void)
+{
+ int i;
+
+ /* Initialize for IRQ: 0~31 */
+ for (i = 0; i < 32; i++) {
+ //irq_desc[i].chip = &irq_type;
+ set_irq_chip_and_handler(i, &irq_type, handle_level_irq);
+ }
+
+ /* Enable all interrupt mask of CPU */
+ write_c0_status(read_c0_status() | ST0_IM);
+
+ /* Set GIMR, IRR */
+ REG32(GIMR) = TC0_IE | UART0_IE |SW_IE ;
+
+ REG32(IRR0) = IRR0_SETTING;
+ REG32(IRR1) = IRR1_SETTING;
+ REG32(IRR2) = IRR2_SETTING;
+ REG32(IRR3) = IRR3_SETTING;
+}
+
+#define ST0_USED_IM (_ULCAST_(0xfc00)) /* interrupt 2/3/4/5/6/7 */
+#define ST0_REENTRY_IM (_ULCAST_(0xe000)) /* interrupt 5/6/7 */
+
+__IRAM_GEN asmlinkage void plat_irq_dispatch(void)
+{
+#if 0
+ unsigned int cpuint_ip;
+ unsigned int cpuint_mask;
+ unsigned int extint_ip;
+
+ cpuint_mask = read_c0_status() & ST0_IM;
+ cpuint_ip = read_c0_cause() & read_c0_status() & ST0_IM;
+
+#if 1
+ write_c0_status(read_c0_status()&(~ST0_IM));
+#else
+ write_c0_status((read_c0_status()&(~ST0_IM))|(cpuint_mask&(~(STATUSF_IP6|STATUSF_IP5))));
+#endif
+
+ do
+ {
+ if (cpuint_ip & CAUSEF_IP7)
+ {
+ /* Timer 0 */
+ do_IRQ(TC0_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP5)
+ {
+ /* PCIE */
+ do_IRQ(PCIE_IRQ);
+ }
+ if (cpuint_ip & CAUSEF_IP6)
+ {
+ /* switch core*/
+ do_IRQ(SWCORE_IRQ);
+
+ }
+ else if (cpuint_ip & CAUSEF_IP3)
+ {
+ /* pci */
+ do_IRQ(PCI_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP4)
+ {
+ /*USB*/
+ do_IRQ(USB_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP2)
+ {
+ /* For shared interrupts */
+ unsigned int extint_ip = REG32(GIMR) & REG32(GISR);
+
+ if (extint_ip & UART0_IP)
+ {
+ /* UART 0 */
+ do_IRQ(UART0_IRQ);
+ }
+ else if (extint_ip & TC1_IP)
+ {
+ do_IRQ(TC1_IRQ);
+ }
+#if 0
+ /* currently we do not use uart1 */
+ else if (extint_ip & UART1_IP)
+ {
+ do_IRQ(UART1_IRQ);
+ }
+#endif
+ else
+ {
+ prom_printf("Unknown Interrupt2:%x\n",extint_ip);
+ REG32(GISR) = extint_ip;
+ }
+ }
+
+ cpuint_ip = read_c0_cause() & (STATUSF_IP6|STATUSF_IP5|STATUSF_IP7);
+ } while(cpuint_ip);
+
+#if 0 /* patch for wds+wep hang up issue */
+ write_c0_status((read_c0_status()&(~ST0_IM))|(cpuint_mask));
+#else
+ write_c0_status((read_c0_status()|(ST0_IM)));
+#endif
+#else
+ unsigned int cpuint_ip;
+ unsigned int extint_ip;
+
+ cpuint_ip = read_c0_cause() & ST0_USED_IM;
+ write_c0_status(read_c0_status()&(~ST0_IM));
+
+#if 0
+ if ( ST0_REENTRY_IM & cpuint_ip )
+ {
+ do
+ {
+ if (cpuint_ip & CAUSEF_IP7)
+ {
+ /* Timer 0 */
+ do_IRQ(TC0_IRQ);
+ }
+ if (cpuint_ip & CAUSEF_IP6)
+ {
+ /* switch core*/
+ do_IRQ(SWCORE_IRQ);
+ }
+ if (cpuint_ip & CAUSEF_IP5)
+ {
+ /* PCIE */
+ do_IRQ(PCIE_IRQ);
+ }
+ cpuint_ip = read_c0_cause() & ST0_REENTRY_IM;
+ } while(cpuint_ip);
+ }
+#else
+ if (cpuint_ip & CAUSEF_IP6)
+ {
+ /* switch core*/
+ do_IRQ(SWCORE_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP5)
+ {
+ /* PCIE */
+ do_IRQ(PCIE_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP7)
+ {
+ /* Timer 0 */
+ do_IRQ(TC0_IRQ);
+ }
+#endif
+ else if(cpuint_ip & CAUSEF_IP3)
+ {
+ /* pci */
+ do_IRQ(PCI_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP4)
+ {
+ /*USB*/
+ do_IRQ(USB_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP2)
+ {
+ /* For shared interrupts */
+ extint_ip = REG32(GIMR) & REG32(GISR);
+
+ if (extint_ip & UART0_IP)
+ {
+ /* UART 0 */
+ do_IRQ(UART0_IRQ);
+ }
+#if 0
+ else if (extint_ip & TC1_IP)
+ {
+ do_IRQ(TC1_IRQ);
+ }
+ /* currently we do not use uart1 */
+ else if (extint_ip & UART1_IP)
+ {
+ do_IRQ(UART1_IRQ);
+ }
+ else
+ {
+ prom_printf("Unknown Interrupt2:%x\n",extint_ip);
+ REG32(GISR) = extint_ip;
+ }
+#endif
+ }
+ write_c0_status((read_c0_status()|(ST0_USED_IM)));
+#endif
+}
diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/mem.c b/target/linux/realtek/files/arch/mips/rtl8196b/mem.c new file mode 100644 index 000000000..98644d98b --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/mem.c @@ -0,0 +1,133 @@ +#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+
+#include <prom.h>
+#include <platform.h>
+
+#define DCR 0xb8001004
+
+void __init prom_meminit(void)
+{
+ //char *ptr;
+ unsigned int memsize;
+
+ memsize = 0x02000000; /* Default to 32MB */
+ /* Check the command line first for a memsize directive */
+ //ptr = strstr(arcs_cmdline, "mem=");
+#if 1
+ /*now: alway believe DRAM configuration register*/
+ {
+ unsigned int DCRvalue = 0;
+ unsigned int bus_width = 0, chip_sel = 0, row_cnt = 0, col_cnt = 0,bank_cnt = 0;
+
+ DCRvalue = ( (*(volatile unsigned int *)DCR));
+
+ /*bit 19,0:2 bank; 1: 4 bank*/
+ switch(DCRvalue & 0x080000)
+ {
+ case 0x0:
+ bank_cnt = 2;
+ break;
+ case 0x080000:
+ bank_cnt = 4;
+ break;
+ default:
+ bank_cnt = 0;
+ break;
+ }
+
+ /*bit 22~24: colomn count*/
+ switch(DCRvalue & 0x01C00000)
+ {
+ case 0x00000000:
+ col_cnt = 256;
+ break;
+ case 0x00400000:
+ col_cnt = 512;
+ break;
+ case 0x00800000:
+ col_cnt = 1024;
+ break;
+ case 0x00C00000:
+ col_cnt = 2048;
+ break;
+ case 0x01000000:
+ col_cnt = 4096;
+ break;
+ default:
+ printk("unknow colomn count(0x%x)\n",DCRvalue & 0x01C00000);
+ break;
+ }
+
+ /*bit 25~26: row count*/
+ switch(DCRvalue & 0x06000000)
+ {
+ case 0x00000000:
+ row_cnt = 2048;
+ break;
+ case 0x02000000:
+ row_cnt = 4096;
+ break;
+ case 0x04000000:
+ row_cnt = 8192;
+ break;
+ case 0x06000000:
+ row_cnt = 16384;
+ break;
+ }
+
+ /*bit 27: chip select*/
+ switch(DCRvalue & 0x08000000)
+ {
+ case 0x0:
+ chip_sel = 1;
+ break;
+ case 0x08000000:
+ chip_sel = 2;
+ break;
+ }
+
+ /*bit 28~29: bus width*/
+ switch(DCRvalue & 0x30000000)
+ {
+ case 0x0:
+ bus_width = 8;
+ break;
+ case 0x10000000:
+ bus_width = 16;
+ break;
+ case 0x20000000:
+ bus_width = 32;
+ break;
+ default:
+ printk("bus width is reseved!\n");
+ break;
+ }
+
+ /*total size(Byte)*/
+ memsize = (row_cnt * col_cnt *bank_cnt) * (bus_width >> 3) * chip_sel;
+
+ }
+#endif
+
+ /*
+ * call <add_memory_region> to register boot_mem_map
+ * add_memory_region(base, size, type);
+ * type: BOOT_MEM_RAM, BOOT_MEM_ROM_DATA or BOOT_MEM_RESERVED
+ */
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+//unsigned long __init prom_free_prom_memory(void)
+void prom_free_prom_memory(void)
+{
+ //unsigned long freed = 0;
+
+ return;// freed;
+}
diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/pci-rtl8196.c b/target/linux/realtek/files/arch/mips/rtl8196b/pci-rtl8196.c new file mode 100644 index 000000000..fffd6d58f --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/pci-rtl8196.c @@ -0,0 +1,526 @@ +/* + * RTL8196B PCIE Host Controller Glue Driver + * Author: ghhuang@realtek.com.tw + * + * Notes: + * - Two host controllers available. + * - Each host direcly connects to one device + * - Supports PCI devices through PCIE-to-PCI bridges + * - If no PCI devices are connected to RC. Timeout monitor shall be + * enabled to prevent bus hanging. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/delay.h> + +#include <asm/mipsregs.h> + +#include <platform.h> + + +#define PCI_8BIT_ACCESS 1 +#define PCI_16BIT_ACCESS 2 +#define PCI_32BIT_ACCESS 4 +#define PCI_ACCESS_READ 8 +#define PCI_ACCESS_WRITE 16 + +#define MAX_NUM_DEV 4 + +#define DEBUG_PRINTK 0 + + +static int pci0_bus_number = 0xff; +static int pci1_bus_number = 0xff; + + +static struct resource rtl8196b_pci0_io_resource = { + .name = "RTL8196B PCI0 IO", + .flags = IORESOURCE_IO, + .start = PADDR(PCIE0_D_IO), + .end = PADDR(PCIE0_D_IO + 0x1FFFFF) +}; + +static struct resource rtl8196b_pci0_mem_resource = { + .name = "RTL8196B PCI0 MEM", + .flags = IORESOURCE_MEM, + .start = PADDR(PCIE0_D_MEM), + .end = PADDR(PCIE0_D_MEM + 0xFFFFFF) +}; + +static struct resource rtl8196b_pci1_io_resource = { + .name = "RTL8196B PCI1 IO", + .flags = IORESOURCE_IO, + .start = PADDR(PCIE1_D_IO), + .end = PADDR(PCIE1_D_IO + 0x1FFFFFF) +}; + +static struct resource rtl8196b_pci1_mem_resource = { + .name = "RTL8196B PCI1 MEM", + .flags = IORESOURCE_MEM, + .start = PADDR(PCIE1_D_MEM), + .end = PADDR(PCIE1_D_MEM + 0xFFFFFF) +}; +//#define PIN_208 +#define DEMO_8196 +static int rtl8196b_pci_reset(void) +{ + cli(); + /* If PCI needs to be reset, put code here. + * Note: + * Software may need to do hot reset for a period of time, say ~100us. + * Here we put 2ms. + */ +#if 1 +#ifdef PIN_208 +WRITE_MEM32(0xb8000044, 0x358);//Disable PCIE EX-PLL +#else +//#ifdef DEMO_8196 +//WRITE_MEM32(0xb8000044, 0x358);//Disable PCIE EX-PLL +//#else +//Modified for PHY parameter for RD center 12292008 +WRITE_MEM32(0xb8000044, 0x9);//Enable PCIE IN-PLL +//#endif +#endif +mdelay(100); +WRITE_MEM32(0xb8000010, 0x00FFFFD6);//Active LX & PCIE Clock in 8196B system register +mdelay(100); +WRITE_MEM32(0xb800003C, 0x1);//PORT0 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb800003C, 0x3);//PORT0 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb8000040, 0x1);//PORT1 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb8000040, 0x3);//PORT1 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb8b01008, 0x1);// PCIE PHY Reset Close:Port 0 +mdelay(100); +WRITE_MEM32(0xb8b01008, 0x81);// PCIE PHY Reset On:Port 0 +mdelay(100); +#ifdef PIN_208 +WRITE_MEM32(0xb8b21008, 0x1);// PCIE PHY Reset Close:Port 1 +mdelay(100); +WRITE_MEM32(0xb8b21008, 0x81);// PCIE PHY Reset On:Port 1 +mdelay(100); +#endif +#if 0//1//1// 1//def OUT_CYSTALL +WRITE_MEM32(0xb8b01000, 0xcc011901);// PCIE Close Port 0 +mdelay(10); +#ifdef PIN_208 +WRITE_MEM32(0xb8b21000, 0xcc011901);// PCIE Close Port 1 +mdelay(10); +#endif +#endif +WRITE_MEM32(0xb8000010, 0x01FFFFD6);// PCIE PHY Reset On:Port 1 +mdelay(100); +#endif + WRITE_MEM32(PCIE0_H_PWRCR, READ_MEM32(PCIE0_H_PWRCR) & 0xFFFFFF7F); +#ifdef PIN_208 + WRITE_MEM32(PCIE1_H_PWRCR, READ_MEM32(PCIE1_H_PWRCR) & 0xFFFFFF7F); +#endif + mdelay(100); + WRITE_MEM32(PCIE0_H_PWRCR, READ_MEM32(PCIE0_H_PWRCR) | 0x00000080); +#ifdef PIN_208 + WRITE_MEM32(PCIE1_H_PWRCR, READ_MEM32(PCIE1_H_PWRCR) | 0x00000080); +#endif + sti(); + return 0; +} + + +static int rtl8196b_pcibios_config_access(unsigned char access_type, + unsigned int addr, unsigned int *data) +{ + /* Do 8bit/16bit/32bit access */ + if (access_type & PCI_ACCESS_WRITE) + { + if (access_type & PCI_8BIT_ACCESS) + WRITE_MEM8(addr, *data); + else if (access_type & PCI_16BIT_ACCESS) + WRITE_MEM16(addr, *data); + else + WRITE_MEM32(addr, *data); + } + else if (access_type & PCI_ACCESS_READ) + { + if (access_type & PCI_8BIT_ACCESS) + *data = READ_MEM8(addr); + else if (access_type & PCI_16BIT_ACCESS) + *data = READ_MEM16(addr); + else + *data = READ_MEM32(addr); + } + + /* If need to check for PCIE access timeout, put code here */ + /* ... */ + + return 0; +} + + + +/* + * RTL8196b supports config word read access for 8/16/32 bit + * + * FIXME: currently only utilize 32bit access + */ +static int rtl8196b_pcibios0_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int *val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + if (pci0_bus_number == 0xff) + pci0_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + if (bus->number == pci0_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci0_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE0_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Read Value: 0x%08X\n", *val); + #endif + + return PCIBIOS_SUCCESSFUL; +} + + +static int rtl8196b_pcibios0_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + static int pci0_bus_number = 0xff; + + if (pci0_bus_number == 0xff) + pci0_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + if (bus->number == pci0_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else + data = val; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE, addr, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci0_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE0_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; +} + + +/* + * RTL8196b supports config word read access for 8/16/32 bit + * + * FIXME: currently only utilize 32bit access + */ +static int rtl8196b_pcibios1_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int *val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + if (pci1_bus_number == 0xff) + pci1_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + if (bus->number == pci1_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci1_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE1_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Read Value: 0x%08X\n", *val); + #endif + + return PCIBIOS_SUCCESSFUL; +} + + +static int rtl8196b_pcibios1_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + static int pci1_bus_number = 0xff; + + if (pci1_bus_number == 0xff) + pci1_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + + if (bus->number == pci1_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else + data = val; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE, addr, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci1_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE1_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops rtl8196b_pci0_ops = { + .read = rtl8196b_pcibios0_read, + .write = rtl8196b_pcibios0_write +}; + +struct pci_ops rtl8196b_pci1_ops = { + .read = rtl8196b_pcibios1_read, + .write = rtl8196b_pcibios1_write +}; + + +static struct pci_controller rtl8196b_pci0_controller = { + .pci_ops = &rtl8196b_pci0_ops, + .mem_resource = &rtl8196b_pci0_mem_resource, + .io_resource = &rtl8196b_pci0_io_resource, +}; + +static struct pci_controller rtl8196b_pci1_controller = { + .pci_ops = &rtl8196b_pci1_ops, + .mem_resource = &rtl8196b_pci1_mem_resource, + .io_resource = &rtl8196b_pci1_io_resource, +}; + + +int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("**Slot: %d\n", slot); + printk("**Pin: %d\n", pin); + printk("**Dev->BUS->Number: %d\n", dev->bus->number); + #endif + + if (dev->bus->number < pci1_bus_number) + return PCIE_IRQ; + else + return PCIE2_IRQ; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + #endif + + return 0; +} + + +static __init int rtl8196b_pci_init(void) +{ + rtl8196b_pci_reset(); + + set_io_port_base(KSEG1); + ioport_resource.end = 0xFFFFFFFF; + + #if DEBUG_PRINTK + printk("<<<<<Register 1st PCI Controller>>>>>\n"); + printk("<<<<<Register 2nd PCI Controller>>>>>\n"); + #endif + + register_pci_controller(&rtl8196b_pci0_controller); +#ifdef PIN_208 + register_pci_controller(&rtl8196b_pci1_controller); +#endif + return 0; +} + +arch_initcall(rtl8196b_pci_init); diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/pci.h b/target/linux/realtek/files/arch/mips/rtl8196b/pci.h new file mode 100644 index 000000000..1c8dca8b9 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/pci.h @@ -0,0 +1,75 @@ +#ifndef PCI_H +#define PCI_H + + + +struct pci_slot_baseaddr_s { + u32 slotNum; + u32 addr; +}; + +#ifdef CONFIG_RTL865XC + +#define PCI_SLOT0_CONFIG_BASE 0xB8B40000 +#define PCI_SLOT1_CONFIG_BASE 0xB8B80000 +#define PCI_SLOT2_CONFIG_BASE 0xB8B10000 +#define PCI_SLOT3_CONFIG_BASE 0xB8B20000 + +#define PCI_SLOT_MEM_BASE0 0xB9000000 +#define PCI_SLOT_IO_BASE0 0xB8C00000 +#define PCI_MEM_SPACE_SIZE0 0x01000000 +#define PCI_IO_SPACE_SIZE0 0x00200000 + +#define PCI_SLOT_MEM_BASE1 0xBA000000 +#define PCI_SLOT_IO_BASE1 0xB8E00000 +#define PCI_MEM_SPACE_SIZE1 0x01000000 +#define PCI_IO_SPACE_SIZE1 0x00200000 + + +#else + +#define PCI_SLOT0_CONFIG_BASE 0xBBD40000 +#define PCI_SLOT1_CONFIG_BASE 0xBBD80000 +#define PCI_SLOT2_CONFIG_BASE 0xBBD10000 +#define PCI_SLOT3_CONFIG_BASE 0xBBD20000 + +#define PCI_SLOT_MEM_BASE 0xBBF00000 +#define PCI_SLOT_IO_BASE 0xBBE00000 +#define PCI_MEM_SPACE_SIZE 0x00100000 +#define PCI_IO_SPACE_SIZE 0x00100000 +#endif + + +//PCI configuration space +#define PCI_CONFIG_VENDER_DEV 0x0000 +#define PCI_CONFIG_COMMAND 0x0004 +#define PCI_CONFIG_STATUS 0x0006 +#define PCI_CONFIG_CLASS_REVISION 0x0008 +#define PCI_CONFIG_CACHE 0x000c +#define PCI_CONFIG_LATENCY 0x000d +#define PCI_CONFIG_HEADER_TYPE 0x000e +#define PCI_CONFIG_BASE0 0x0010 +#define PCI_CONFIG_BASE1 0x0014 +#define PCI_CONFIG_BASE2 0x0018 +#define PCI_CONFIG_BASE3 0x001c +#define PCI_CONFIG_BASE4 0x0020 +#define PCI_CONFIG_BASE5 0x0024 +#define PCI_CONFIG_SUBSYSTEMVENDOR 0x002c +#define PCI_CONFIG_INT_LINE 0x003c +#define PCI_CONFIG_INT_PIN 0x003d +#define PCI_CONFIG_MAXLAN 0x003f +#define PCI_CONFIG_MINGNT 0x003e + +//PCI command register flag +#define CMD_FAST_BACK_TO_BACK (1<<9) +#define CMD_SERR (1<<8) +#define CMD_STEP_CONTROL (1<<7) +#define CMD_PARITY_ERROR_RESPONSE (1<<6) +#define CMD_VGA_PALLETE_SNOOP (1<<5) +#define CMD_WRITE_AND_INVALIDATE (1<<4) +#define CMD_SPECIAL_CYCLE (1<<3) +#define CMD_BUS_MASTER (1<<2) +#define CMD_MEM_SPACE (1<<1) +#define CMD_IO_SPACE (1<<0) + +#endif diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/printf.c b/target/linux/realtek/files/arch/mips/rtl8196b/printf.c new file mode 100644 index 000000000..650f46d27 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/printf.c @@ -0,0 +1,51 @@ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <asm/io.h> +#include <asm/system.h> + +#include <prom.h> +#include <platform.h> + +void __init prom_console_init(void) +{ + /* 8 bits, 1 stop bit, no parity. */ + REG8(UART0_LCR) = CHAR_LEN_8 | ONE_STOP | PARITY_DISABLE; + + /* Reset/Enable the FIFO */ + REG8(UART0_FCR) = FCR_EN | RXRST | TXRST | CHAR_TRIGGER_14; + + /* Disable All Interrupts */ + REG8(UART0_IER) = 0x00000000; + + /* Enable Divisor Latch */ + REG8(UART0_LCR) |= DLAB; + + /* Set Divisor */ + REG8(UART0_DLL) = (SYSCLK / (BAUDRATE * 16) - 1) & 0x00FF; + REG8(UART0_DLM) = ((SYSCLK / (BAUDRATE * 16) - 1) & 0xFF00) >> 8; + + /* Disable Divisor Latch */ + REG8(UART0_LCR) &= (~DLAB); +} + +int prom_putchar(char c) +{ + unsigned int busy_cnt = 0; + + do + { + /* Prevent Hanging */ + if (busy_cnt++ >= 30000) + { + /* Reset Tx FIFO */ + REG8(UART0_FCR) = TXRST | CHAR_TRIGGER_14; + return 0; + } + } while ((REG8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL); + + /* Send Character */ + REG8(UART0_THR) = c; + + return 1; +} diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/setup.c b/target/linux/realtek/files/arch/mips/rtl8196b/setup.c new file mode 100644 index 000000000..7a2598495 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/setup.c @@ -0,0 +1,191 @@ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/serial.h> +#include <asm/io.h> +#include <asm/time.h> + +#include <prom.h> +#include <platform.h> + +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/percpu.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <linux/notifier.h> +#include <linux/thread_info.h> +#include <linux/time.h> +#include <linux/jiffies.h> +#include <linux/posix-timers.h> +#include <linux/cpu.h> +#include <linux/syscalls.h> +#include <linux/delay.h> + +#include <asm/uaccess.h> +#include <asm/unistd.h> +#include <asm/div64.h> +#include <asm/timex.h> +#include <asm/io.h> + +static void __init serial_init(void); +#if 0 +static void __init rtl8652_time_init(void); +static void rtl8652_timer_ack(void); + +/* + * Called from the timer interrupt handler to charge one tick to the current + * process. user_tick is 1 if the tick is user time, 0 for system. + */ + +void local_timer_interrupt(int irq, void *dev_id) +{ +// profile_tick(CPU_PROFILING); + account_process_tick(current, user_mode(get_irq_regs())); +} +/* + * High-level timer interrupt service routines. This function + * is set as irqaction->handler and is invoked through do_IRQ. + */ + +irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + write_seqlock(&xtime_lock); + +//Add for update flash check + + rtl8652_timer_ack(); + + /* + * call the generic timer interrupt handling + */ + do_timer(1); + + + write_sequnlock(&xtime_lock); + + /* + * In UP mode, we call local_timer_interrupt() to do profiling + * and process accouting. + * + * In SMP mode, local_timer_interrupt() is invoked by appropriate + * low-level local timer interrupt handler. + */ + local_timer_interrupt(irq, dev_id); + + return IRQ_HANDLED; +} +#endif +const char *get_system_type(void) +{ + return "RTL8652"; +} + +void __init prom_init(void) +{ + prom_console_init(); + prom_meminit(); +} + +void __init plat_mem_setup(void) +{ + /* Platform Specific Setup */ + /* define io/mem region */ + ioport_resource.start = 0x18000000; + ioport_resource.end = 0x1fffffff; + + iomem_resource.start = 0x18000000; + iomem_resource.end = 0x1fffffff; + + serial_init(); + +// board_time_init = rtl8652_time_init; +// mips_timer_ack = rtl8652_timer_ack; +} + +#if 0 +static void rtl8652_timer_ack(void) +{ + REG32(TCIR) |= TC0IP; +} + +static void __init rtl8652_time_init(void) +{ + +} +#endif + +extern int rtl_clockevent_init(int irq); +//void __init plat_time_init(struct irqaction *irq) +void __init plat_time_init(void) +{ + /* Setup Timer0 */ + + /* Clear Timer IP status */ + if (REG32(TCIR) & TC0IP) + REG32(TCIR) |= TC0IP; + + /* Here irq->handler is passed from outside */ + // irq->handler = timer_interrupt; + //setup_irq(TC0_IRQ, irq); + + REG32(TCCNR) = 0; /* disable timer before setting CDBR */ + /* extend timer base to 4 times for wireless init process */ +#if 0 + REG32(CDBR) = (DIVISOR) << DIVF_OFFSET; + REG32(TC0DATA) = (MHZ * (1000 / HZ)) << TCD_OFFSET; +#else + REG32(CDBR)=(DIVISOR*4) << DIVF_OFFSET; + REG32(TC0DATA) = ((MHZ * 250) / HZ) << TCD_OFFSET; +#endif + + rtl_clockevent_init(TC0_IRQ); + /* enable timer */ + REG32(TCCNR) = TC0EN | TC0MODE_TIMER; + REG32(TCIR) = TC0IE; + #ifdef CONFIG_RTL865X_WTDOG + *(volatile unsigned long *)(0xb800311C)=0x00600000; + #endif +} + +extern int __init early_serial_setup(struct uart_port *port); +static void __init serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct uart_port s; + + memset(&s, 0, sizeof(s)); + + s.line = 0; + s.type = PORT_16550A; + //s.membase = (unsigned char *) UART0_BASE; + s.mapbase = UART0_MAP_BASE; + s.membase = ioremap_nocache(s.mapbase, 0x20); + s.irq = UART0_IRQ; + //s.uartclk = SYSCLK - BAUDRATE * 24; + s.uartclk = 200000000; + //s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_SPD_CUST; + s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY; + s.iotype = UPIO_MEM; + s.regshift = 2; + //s.fifosize = 1; + s.fifosize = 16; + // s.custom_divisor = SYSCLK / (BAUDRATE * 16) - 1; + + /* Call early_serial_setup() here, to set up 8250 console driver */ + if (early_serial_setup(&s) != 0) { + panic("Serial setup failed!\n"); + } +#endif +} diff --git a/target/linux/realtek/files/arch/mips/rtl8196b/timer.c b/target/linux/realtek/files/arch/mips/rtl8196b/timer.c new file mode 100644 index 000000000..e8d58ebf8 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196b/timer.c @@ -0,0 +1,80 @@ +/* + * linux/arch/rlx/rlxocp/time.c + * + * Copyright (C) 1999 Harald Koerfgen + * Copyright (C) 2000 Pavel Machek (pavel@suse.cz) + * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Time handling functinos for Philips Nino. + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <linux/interrupt.h> +#include <linux/timex.h> +#include <linux/delay.h> + +#include <asm/time.h> +#include <asm/rlxbsp.h> + +#include "bspchip.h" + +#ifdef CONFIG_RTL_TIMER_ADJUSTMENT +#include <rtl_types.h> +#include <rtl865xc_asicregs.h> + +void rtl865x_setupTimer1(void) +{ + WRITE_MEM32( TCCNR, READ_MEM32(TCCNR) & ~TC1EN );/* Disable timer1 */ + WRITE_MEM32( TC1DATA, 0xffffff00); + WRITE_MEM32( TCCNR, ( READ_MEM32(TCCNR) | TC1EN ) | TC1MODE_TIMER );/* Enable timer1 - timer mode */ + WRITE_MEM32( TCIR, READ_MEM32(TCIR) & ~TC1IE ); /* Disable timer1 interrupt */ +} +#endif + +void inline bsp_timer_ack(void) +{ + REG32(BSP_TCIR) |= BSP_TC0IP; +} + +void __init bsp_timer_init(void) +{ + unsigned int sys_clock_rate; + + sys_clock_rate = BSP_SYS_CLK_RATE; + + /* Clear Timer IP status */ + if (REG32(BSP_TCIR) & BSP_TC0IP) + REG32(BSP_TCIR) |= BSP_TC0IP; + + /* disable timer */ + REG32(BSP_TCCNR) = 0; /* disable timer before setting CDBR */ + + /* initialize timer registers */ + REG32(BSP_CDBR)=(BSP_DIVISOR) << BSP_DIVF_OFFSET; + REG32(BSP_TC0DATA) = (((sys_clock_rate/BSP_DIVISOR)/HZ)) << BSP_TCD_OFFSET; + // extend timer base to 4 times + //REG32(BSP_CDBR)=(BSP_DIVISOR*4) << BSP_DIVF_OFFSET; + //REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*4))/HZ)) << BSP_TCD_OFFSET; +#ifdef CONFIG_RTL_TIMER_ADJUSTMENT + rtl865x_setupTimer1(); +#endif +#if defined(CONFIG_RTK_WTDOG) + REG32(BSP_WDTCNR) = 0x00600000; +#endif + + /* hook up timer interrupt handler */ + rlx_clockevent_init(BSP_TC0_IRQ); + + /* enable timer */ + REG32(BSP_TCCNR) = BSP_TC0EN | BSP_TC0MODE_TIMER; + REG32(BSP_TCIR) = BSP_TC0IE; +} diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/Makefile b/target/linux/realtek/files/arch/mips/rtl8196c/Makefile new file mode 100644 index 000000000..f7e8766ca --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the RTL8652 specific parts of the kernel +# +DIR_RTLASIC = $(DIR_LINUX)/drivers/net/rtl819x/ + +obj-y := setup.o printf.o int.o mem.o +obj-$(CONFIG_PCI) += pci.o +EXTRA_AFLAGS := $(CFLAGS) +EXTRA_CFLAGS += -I$(DIR_RTLASIC) diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/int.c b/target/linux/realtek/files/arch/mips/rtl8196c/int.c new file mode 100644 index 000000000..4d00494dc --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/int.c @@ -0,0 +1,262 @@ +#include <linux/config.h>
+#include <linux/irq.h>
+
+#include <asm/irq_cpu.h>
+#include <prom.h>
+#include <platform.h>
+#include <linux/hardirq.h>
+
+spinlock_t irq_lock = SPIN_LOCK_UNLOCKED;
+
+static void rtl8196_enable_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ REG32(GIMR) = REG32(GIMR) | (1 << irq);
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static unsigned int rtl8196_startup_irq(unsigned int irq)
+{
+ rtl8196_enable_irq(irq);
+
+ return 0;
+}
+
+static void rtl8196_disable_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ REG32(GIMR) = REG32(GIMR) & (~(1 << irq));
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static void rtl8196_end_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ REG32(GIMR) = REG32(GIMR) | (1 << irq);
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+#define rtl8196_shutdown_irq rtl8196_disable_irq
+#define rtl8196_mask_and_ack_irq rtl8196_disable_irq
+
+static struct irq_chip irq_type = {
+ .typename = "RTL8196",
+ .startup = rtl8196_startup_irq,
+ .shutdown = rtl8196_shutdown_irq,
+ .enable = rtl8196_enable_irq,
+ .disable = rtl8196_disable_irq,
+ .ack = rtl8196_mask_and_ack_irq,
+ .end = rtl8196_end_irq,
+ .mask = rtl8196_disable_irq,
+ .mask_ack = rtl8196_mask_and_ack_irq,
+ .unmask = rtl8196_enable_irq,
+};
+
+
+/*
+ * RTL8196b Interrupt Scheme (Subject to change)
+ *
+ * Source EXT_INT IRQ CPU INT
+ * -------- ------- ------ -------
+ * PCIB0TO 0 0 2
+ * PCIB1TO 1 1 2
+ * LBCTMOm0 2 2 2
+ * LBCTMOm1 3 3 2
+ * LBCTMOs 4 4 2
+ * TIMER0 8 8 7
+ * TIMER1 9 9 2
+ * USB 10 10 4
+ * UART0 12 12 3
+ * UART1 13 13 2
+ * PCI 14 14 5
+ * SWCORE 15 15 6
+ * GPIO_ABCD 16 16 2
+ * GPIO_EFGH 17 17 2
+ * HCI 18 18 2
+ * PCM 19 19 2
+ * CRYPTO 20 20 2
+ * GDMA 21 21 2
+ */
+
+void __init arch_init_irq(void)
+{
+ int i;
+
+ /* Initialize for IRQ: 0~31 */
+ for (i = 0; i < 32; i++) {
+ //irq_desc[i].chip = &irq_type;
+ set_irq_chip_and_handler(i, &irq_type, handle_level_irq);
+ }
+
+ /* Enable all interrupt mask of CPU */
+ write_c0_status(read_c0_status() | ST0_IM);
+
+ /* Set GIMR, IRR */
+ REG32(GIMR) = TC0_IE | UART0_IE ;
+
+ REG32(IRR0) = IRR0_SETTING;
+ REG32(IRR1) = IRR1_SETTING;
+ REG32(IRR2) = IRR2_SETTING;
+ REG32(IRR3) = IRR3_SETTING;
+}
+
+#define ST0_USED_IM (_ULCAST_(0xfc00)) /* interrupt 2/3/4/5/6/7 */
+#define ST0_REENTRY_IM (_ULCAST_(0xe000)) /* interrupt 5/6/7 */
+
+#define __IRAM_GEN __attribute__ ((section(".iram-gen")))
+
+__IRAM_GEN asmlinkage void plat_irq_dispatch(void)
+{
+#if 0
+ unsigned int cpuint_ip;
+ unsigned int cpuint_mask;
+ unsigned int extint_ip;
+
+ cpuint_mask = read_c0_status() & ST0_IM;
+ cpuint_ip = read_c0_cause() & read_c0_status() & ST0_IM;
+
+#if 1
+ write_c0_status(read_c0_status()&(~ST0_IM));
+#else
+ write_c0_status((read_c0_status()&(~ST0_IM))|(cpuint_mask&(~(STATUSF_IP6|STATUSF_IP5))));
+#endif
+
+ do
+ {
+ if (cpuint_ip & CAUSEF_IP7)
+ {
+ /* Timer 0 */
+ do_IRQ(TC0_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP5)
+ {
+ /* PCIE */
+ do_IRQ(PCIE_IRQ);
+ }
+ if (cpuint_ip & CAUSEF_IP6)
+ {
+ /* switch core*/
+ do_IRQ(SWCORE_IRQ);
+
+ }
+ else if (cpuint_ip & CAUSEF_IP3)
+ {
+ /* pci */
+ do_IRQ(PCI_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP4)
+ {
+ /*USB*/
+ do_IRQ(USB_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP2)
+ {
+ /* For shared interrupts */
+ unsigned int extint_ip = REG32(GIMR) & REG32(GISR);
+
+ if (extint_ip & UART0_IP)
+ {
+ /* UART 0 */
+ do_IRQ(UART0_IRQ);
+ }
+ else if (extint_ip & TC1_IP)
+ {
+ do_IRQ(TC1_IRQ);
+ }
+#if 0
+ /* currently we do not use uart1 */
+ else if (extint_ip & UART1_IP)
+ {
+ do_IRQ(UART1_IRQ);
+ }
+#endif
+ else
+ {
+ prom_printf("Unknown Interrupt2:%x\n",extint_ip);
+ REG32(GISR) = extint_ip;
+ }
+ }
+
+ cpuint_ip = read_c0_cause() & (STATUSF_IP6|STATUSF_IP5|STATUSF_IP7);
+ } while(cpuint_ip);
+
+#if 0 /* patch for wds+wep hang up issue */
+ write_c0_status((read_c0_status()&(~ST0_IM))|(cpuint_mask));
+#else
+ write_c0_status((read_c0_status()|(ST0_IM)));
+#endif
+#else
+ unsigned int cpuint_ip;
+ unsigned int extint_ip;
+
+ cpuint_ip = read_c0_cause() & ST0_USED_IM;
+ write_c0_status(read_c0_status()&(~ST0_IM));
+ if ( ST0_REENTRY_IM & cpuint_ip )
+ {
+ do
+ {
+ if (cpuint_ip & CAUSEF_IP7)
+ {
+ /* Timer 0 */
+ do_IRQ(TC0_IRQ);
+ }
+ if (cpuint_ip & CAUSEF_IP6)
+ {
+ /* switch core*/
+ do_IRQ(SWCORE_IRQ);
+ }
+ if (cpuint_ip & CAUSEF_IP5)
+ {
+ /* PCIE */
+ do_IRQ(PCIE_IRQ);
+ }
+ cpuint_ip = read_c0_cause() & ST0_REENTRY_IM;
+
+ } while(cpuint_ip);
+ }
+ else if(cpuint_ip & CAUSEF_IP3)
+ {
+ /* pci */
+ do_IRQ(PCI_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP4)
+ {
+ /*USB*/
+ do_IRQ(USB_IRQ);
+ }
+ else if (cpuint_ip & CAUSEF_IP2)
+ {
+ /* For shared interrupts */
+ extint_ip = REG32(GIMR) & REG32(GISR);
+
+ if (extint_ip & UART0_IP)
+ {
+ /* UART 0 */
+ do_IRQ(UART0_IRQ);
+ }
+#if 0
+ else if (extint_ip & TC1_IP)
+ {
+ do_IRQ(TC1_IRQ);
+ }
+ /* currently we do not use uart1 */
+ else if (extint_ip & UART1_IP)
+ {
+ do_IRQ(UART1_IRQ);
+ }
+ else
+ {
+ prom_printf("Unknown Interrupt2:%x\n",extint_ip);
+ REG32(GISR) = extint_ip;
+ }
+#endif
+ }
+ write_c0_status((read_c0_status()|(ST0_USED_IM)));
+#endif
+}
diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/mem.c b/target/linux/realtek/files/arch/mips/rtl8196c/mem.c new file mode 100644 index 000000000..98644d98b --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/mem.c @@ -0,0 +1,133 @@ +#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+
+#include <prom.h>
+#include <platform.h>
+
+#define DCR 0xb8001004
+
+void __init prom_meminit(void)
+{
+ //char *ptr;
+ unsigned int memsize;
+
+ memsize = 0x02000000; /* Default to 32MB */
+ /* Check the command line first for a memsize directive */
+ //ptr = strstr(arcs_cmdline, "mem=");
+#if 1
+ /*now: alway believe DRAM configuration register*/
+ {
+ unsigned int DCRvalue = 0;
+ unsigned int bus_width = 0, chip_sel = 0, row_cnt = 0, col_cnt = 0,bank_cnt = 0;
+
+ DCRvalue = ( (*(volatile unsigned int *)DCR));
+
+ /*bit 19,0:2 bank; 1: 4 bank*/
+ switch(DCRvalue & 0x080000)
+ {
+ case 0x0:
+ bank_cnt = 2;
+ break;
+ case 0x080000:
+ bank_cnt = 4;
+ break;
+ default:
+ bank_cnt = 0;
+ break;
+ }
+
+ /*bit 22~24: colomn count*/
+ switch(DCRvalue & 0x01C00000)
+ {
+ case 0x00000000:
+ col_cnt = 256;
+ break;
+ case 0x00400000:
+ col_cnt = 512;
+ break;
+ case 0x00800000:
+ col_cnt = 1024;
+ break;
+ case 0x00C00000:
+ col_cnt = 2048;
+ break;
+ case 0x01000000:
+ col_cnt = 4096;
+ break;
+ default:
+ printk("unknow colomn count(0x%x)\n",DCRvalue & 0x01C00000);
+ break;
+ }
+
+ /*bit 25~26: row count*/
+ switch(DCRvalue & 0x06000000)
+ {
+ case 0x00000000:
+ row_cnt = 2048;
+ break;
+ case 0x02000000:
+ row_cnt = 4096;
+ break;
+ case 0x04000000:
+ row_cnt = 8192;
+ break;
+ case 0x06000000:
+ row_cnt = 16384;
+ break;
+ }
+
+ /*bit 27: chip select*/
+ switch(DCRvalue & 0x08000000)
+ {
+ case 0x0:
+ chip_sel = 1;
+ break;
+ case 0x08000000:
+ chip_sel = 2;
+ break;
+ }
+
+ /*bit 28~29: bus width*/
+ switch(DCRvalue & 0x30000000)
+ {
+ case 0x0:
+ bus_width = 8;
+ break;
+ case 0x10000000:
+ bus_width = 16;
+ break;
+ case 0x20000000:
+ bus_width = 32;
+ break;
+ default:
+ printk("bus width is reseved!\n");
+ break;
+ }
+
+ /*total size(Byte)*/
+ memsize = (row_cnt * col_cnt *bank_cnt) * (bus_width >> 3) * chip_sel;
+
+ }
+#endif
+
+ /*
+ * call <add_memory_region> to register boot_mem_map
+ * add_memory_region(base, size, type);
+ * type: BOOT_MEM_RAM, BOOT_MEM_ROM_DATA or BOOT_MEM_RESERVED
+ */
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+//unsigned long __init prom_free_prom_memory(void)
+void prom_free_prom_memory(void)
+{
+ //unsigned long freed = 0;
+
+ return;// freed;
+}
diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/pci-rtl8196.c b/target/linux/realtek/files/arch/mips/rtl8196c/pci-rtl8196.c new file mode 100644 index 000000000..fffd6d58f --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/pci-rtl8196.c @@ -0,0 +1,526 @@ +/* + * RTL8196B PCIE Host Controller Glue Driver + * Author: ghhuang@realtek.com.tw + * + * Notes: + * - Two host controllers available. + * - Each host direcly connects to one device + * - Supports PCI devices through PCIE-to-PCI bridges + * - If no PCI devices are connected to RC. Timeout monitor shall be + * enabled to prevent bus hanging. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/delay.h> + +#include <asm/mipsregs.h> + +#include <platform.h> + + +#define PCI_8BIT_ACCESS 1 +#define PCI_16BIT_ACCESS 2 +#define PCI_32BIT_ACCESS 4 +#define PCI_ACCESS_READ 8 +#define PCI_ACCESS_WRITE 16 + +#define MAX_NUM_DEV 4 + +#define DEBUG_PRINTK 0 + + +static int pci0_bus_number = 0xff; +static int pci1_bus_number = 0xff; + + +static struct resource rtl8196b_pci0_io_resource = { + .name = "RTL8196B PCI0 IO", + .flags = IORESOURCE_IO, + .start = PADDR(PCIE0_D_IO), + .end = PADDR(PCIE0_D_IO + 0x1FFFFF) +}; + +static struct resource rtl8196b_pci0_mem_resource = { + .name = "RTL8196B PCI0 MEM", + .flags = IORESOURCE_MEM, + .start = PADDR(PCIE0_D_MEM), + .end = PADDR(PCIE0_D_MEM + 0xFFFFFF) +}; + +static struct resource rtl8196b_pci1_io_resource = { + .name = "RTL8196B PCI1 IO", + .flags = IORESOURCE_IO, + .start = PADDR(PCIE1_D_IO), + .end = PADDR(PCIE1_D_IO + 0x1FFFFFF) +}; + +static struct resource rtl8196b_pci1_mem_resource = { + .name = "RTL8196B PCI1 MEM", + .flags = IORESOURCE_MEM, + .start = PADDR(PCIE1_D_MEM), + .end = PADDR(PCIE1_D_MEM + 0xFFFFFF) +}; +//#define PIN_208 +#define DEMO_8196 +static int rtl8196b_pci_reset(void) +{ + cli(); + /* If PCI needs to be reset, put code here. + * Note: + * Software may need to do hot reset for a period of time, say ~100us. + * Here we put 2ms. + */ +#if 1 +#ifdef PIN_208 +WRITE_MEM32(0xb8000044, 0x358);//Disable PCIE EX-PLL +#else +//#ifdef DEMO_8196 +//WRITE_MEM32(0xb8000044, 0x358);//Disable PCIE EX-PLL +//#else +//Modified for PHY parameter for RD center 12292008 +WRITE_MEM32(0xb8000044, 0x9);//Enable PCIE IN-PLL +//#endif +#endif +mdelay(100); +WRITE_MEM32(0xb8000010, 0x00FFFFD6);//Active LX & PCIE Clock in 8196B system register +mdelay(100); +WRITE_MEM32(0xb800003C, 0x1);//PORT0 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb800003C, 0x3);//PORT0 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb8000040, 0x1);//PORT1 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb8000040, 0x3);//PORT1 PCIE PHY MDIO Reset +mdelay(100); +WRITE_MEM32(0xb8b01008, 0x1);// PCIE PHY Reset Close:Port 0 +mdelay(100); +WRITE_MEM32(0xb8b01008, 0x81);// PCIE PHY Reset On:Port 0 +mdelay(100); +#ifdef PIN_208 +WRITE_MEM32(0xb8b21008, 0x1);// PCIE PHY Reset Close:Port 1 +mdelay(100); +WRITE_MEM32(0xb8b21008, 0x81);// PCIE PHY Reset On:Port 1 +mdelay(100); +#endif +#if 0//1//1// 1//def OUT_CYSTALL +WRITE_MEM32(0xb8b01000, 0xcc011901);// PCIE Close Port 0 +mdelay(10); +#ifdef PIN_208 +WRITE_MEM32(0xb8b21000, 0xcc011901);// PCIE Close Port 1 +mdelay(10); +#endif +#endif +WRITE_MEM32(0xb8000010, 0x01FFFFD6);// PCIE PHY Reset On:Port 1 +mdelay(100); +#endif + WRITE_MEM32(PCIE0_H_PWRCR, READ_MEM32(PCIE0_H_PWRCR) & 0xFFFFFF7F); +#ifdef PIN_208 + WRITE_MEM32(PCIE1_H_PWRCR, READ_MEM32(PCIE1_H_PWRCR) & 0xFFFFFF7F); +#endif + mdelay(100); + WRITE_MEM32(PCIE0_H_PWRCR, READ_MEM32(PCIE0_H_PWRCR) | 0x00000080); +#ifdef PIN_208 + WRITE_MEM32(PCIE1_H_PWRCR, READ_MEM32(PCIE1_H_PWRCR) | 0x00000080); +#endif + sti(); + return 0; +} + + +static int rtl8196b_pcibios_config_access(unsigned char access_type, + unsigned int addr, unsigned int *data) +{ + /* Do 8bit/16bit/32bit access */ + if (access_type & PCI_ACCESS_WRITE) + { + if (access_type & PCI_8BIT_ACCESS) + WRITE_MEM8(addr, *data); + else if (access_type & PCI_16BIT_ACCESS) + WRITE_MEM16(addr, *data); + else + WRITE_MEM32(addr, *data); + } + else if (access_type & PCI_ACCESS_READ) + { + if (access_type & PCI_8BIT_ACCESS) + *data = READ_MEM8(addr); + else if (access_type & PCI_16BIT_ACCESS) + *data = READ_MEM16(addr); + else + *data = READ_MEM32(addr); + } + + /* If need to check for PCIE access timeout, put code here */ + /* ... */ + + return 0; +} + + + +/* + * RTL8196b supports config word read access for 8/16/32 bit + * + * FIXME: currently only utilize 32bit access + */ +static int rtl8196b_pcibios0_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int *val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + if (pci0_bus_number == 0xff) + pci0_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + if (bus->number == pci0_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci0_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE0_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Read Value: 0x%08X\n", *val); + #endif + + return PCIBIOS_SUCCESSFUL; +} + + +static int rtl8196b_pcibios0_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + static int pci0_bus_number = 0xff; + + if (pci0_bus_number == 0xff) + pci0_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + if (bus->number == pci0_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else + data = val; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE, addr, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci0_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE0_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE0_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE0_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; +} + + +/* + * RTL8196b supports config word read access for 8/16/32 bit + * + * FIXME: currently only utilize 32bit access + */ +static int rtl8196b_pcibios1_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int *val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + if (pci1_bus_number == 0xff) + pci1_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + if (bus->number == pci1_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci1_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE1_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | size, addr, val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Read Value: 0x%08X\n", *val); + #endif + + return PCIBIOS_SUCCESSFUL; +} + + +static int rtl8196b_pcibios1_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, unsigned int val) +{ + unsigned int data = 0; + unsigned int addr = 0; + + static int pci1_bus_number = 0xff; + + if (pci1_bus_number == 0xff) + pci1_bus_number = bus->number; + + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("Bus: %d, Slot: %d, Func: %d, Where: %d, Size: %d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + #endif + + + if (bus->number == pci1_bus_number) + { + /* PCIE host controller */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_H_CFG + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_READ | PCI_32BIT_ACCESS, addr & ~(0x3), &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); + else + data = val; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE, addr, &data)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else if (bus->number == (pci1_bus_number + 1)) + { + /* PCIE devices directly connected */ + if (PCI_SLOT(devfn) == 0) + { + addr = PCIE1_D_CFG0 + (PCI_FUNC(devfn) << 12) + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + { + /* Devices connected through bridge */ + if (PCI_SLOT(devfn) < MAX_NUM_DEV) + { + WRITE_MEM32(PCIE1_H_IPCFG, ((bus->number) << 8) | (PCI_SLOT(devfn) << 3) | PCI_FUNC(devfn)); + addr = PCIE1_D_CFG1 + where; + + if (rtl8196b_pcibios_config_access(PCI_ACCESS_WRITE | size, addr, &val)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + else + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops rtl8196b_pci0_ops = { + .read = rtl8196b_pcibios0_read, + .write = rtl8196b_pcibios0_write +}; + +struct pci_ops rtl8196b_pci1_ops = { + .read = rtl8196b_pcibios1_read, + .write = rtl8196b_pcibios1_write +}; + + +static struct pci_controller rtl8196b_pci0_controller = { + .pci_ops = &rtl8196b_pci0_ops, + .mem_resource = &rtl8196b_pci0_mem_resource, + .io_resource = &rtl8196b_pci0_io_resource, +}; + +static struct pci_controller rtl8196b_pci1_controller = { + .pci_ops = &rtl8196b_pci1_ops, + .mem_resource = &rtl8196b_pci1_mem_resource, + .io_resource = &rtl8196b_pci1_io_resource, +}; + + +int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + printk("**Slot: %d\n", slot); + printk("**Pin: %d\n", pin); + printk("**Dev->BUS->Number: %d\n", dev->bus->number); + #endif + + if (dev->bus->number < pci1_bus_number) + return PCIE_IRQ; + else + return PCIE2_IRQ; +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + #if DEBUG_PRINTK + printk("File: %s, Function: %s, Line: %d\n", __FILE__, __FUNCTION__, __LINE__); + #endif + + return 0; +} + + +static __init int rtl8196b_pci_init(void) +{ + rtl8196b_pci_reset(); + + set_io_port_base(KSEG1); + ioport_resource.end = 0xFFFFFFFF; + + #if DEBUG_PRINTK + printk("<<<<<Register 1st PCI Controller>>>>>\n"); + printk("<<<<<Register 2nd PCI Controller>>>>>\n"); + #endif + + register_pci_controller(&rtl8196b_pci0_controller); +#ifdef PIN_208 + register_pci_controller(&rtl8196b_pci1_controller); +#endif + return 0; +} + +arch_initcall(rtl8196b_pci_init); diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/pci.h b/target/linux/realtek/files/arch/mips/rtl8196c/pci.h new file mode 100644 index 000000000..1c8dca8b9 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/pci.h @@ -0,0 +1,75 @@ +#ifndef PCI_H +#define PCI_H + + + +struct pci_slot_baseaddr_s { + u32 slotNum; + u32 addr; +}; + +#ifdef CONFIG_RTL865XC + +#define PCI_SLOT0_CONFIG_BASE 0xB8B40000 +#define PCI_SLOT1_CONFIG_BASE 0xB8B80000 +#define PCI_SLOT2_CONFIG_BASE 0xB8B10000 +#define PCI_SLOT3_CONFIG_BASE 0xB8B20000 + +#define PCI_SLOT_MEM_BASE0 0xB9000000 +#define PCI_SLOT_IO_BASE0 0xB8C00000 +#define PCI_MEM_SPACE_SIZE0 0x01000000 +#define PCI_IO_SPACE_SIZE0 0x00200000 + +#define PCI_SLOT_MEM_BASE1 0xBA000000 +#define PCI_SLOT_IO_BASE1 0xB8E00000 +#define PCI_MEM_SPACE_SIZE1 0x01000000 +#define PCI_IO_SPACE_SIZE1 0x00200000 + + +#else + +#define PCI_SLOT0_CONFIG_BASE 0xBBD40000 +#define PCI_SLOT1_CONFIG_BASE 0xBBD80000 +#define PCI_SLOT2_CONFIG_BASE 0xBBD10000 +#define PCI_SLOT3_CONFIG_BASE 0xBBD20000 + +#define PCI_SLOT_MEM_BASE 0xBBF00000 +#define PCI_SLOT_IO_BASE 0xBBE00000 +#define PCI_MEM_SPACE_SIZE 0x00100000 +#define PCI_IO_SPACE_SIZE 0x00100000 +#endif + + +//PCI configuration space +#define PCI_CONFIG_VENDER_DEV 0x0000 +#define PCI_CONFIG_COMMAND 0x0004 +#define PCI_CONFIG_STATUS 0x0006 +#define PCI_CONFIG_CLASS_REVISION 0x0008 +#define PCI_CONFIG_CACHE 0x000c +#define PCI_CONFIG_LATENCY 0x000d +#define PCI_CONFIG_HEADER_TYPE 0x000e +#define PCI_CONFIG_BASE0 0x0010 +#define PCI_CONFIG_BASE1 0x0014 +#define PCI_CONFIG_BASE2 0x0018 +#define PCI_CONFIG_BASE3 0x001c +#define PCI_CONFIG_BASE4 0x0020 +#define PCI_CONFIG_BASE5 0x0024 +#define PCI_CONFIG_SUBSYSTEMVENDOR 0x002c +#define PCI_CONFIG_INT_LINE 0x003c +#define PCI_CONFIG_INT_PIN 0x003d +#define PCI_CONFIG_MAXLAN 0x003f +#define PCI_CONFIG_MINGNT 0x003e + +//PCI command register flag +#define CMD_FAST_BACK_TO_BACK (1<<9) +#define CMD_SERR (1<<8) +#define CMD_STEP_CONTROL (1<<7) +#define CMD_PARITY_ERROR_RESPONSE (1<<6) +#define CMD_VGA_PALLETE_SNOOP (1<<5) +#define CMD_WRITE_AND_INVALIDATE (1<<4) +#define CMD_SPECIAL_CYCLE (1<<3) +#define CMD_BUS_MASTER (1<<2) +#define CMD_MEM_SPACE (1<<1) +#define CMD_IO_SPACE (1<<0) + +#endif diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/printf.c b/target/linux/realtek/files/arch/mips/rtl8196c/printf.c new file mode 100644 index 000000000..650f46d27 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/printf.c @@ -0,0 +1,51 @@ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <asm/io.h> +#include <asm/system.h> + +#include <prom.h> +#include <platform.h> + +void __init prom_console_init(void) +{ + /* 8 bits, 1 stop bit, no parity. */ + REG8(UART0_LCR) = CHAR_LEN_8 | ONE_STOP | PARITY_DISABLE; + + /* Reset/Enable the FIFO */ + REG8(UART0_FCR) = FCR_EN | RXRST | TXRST | CHAR_TRIGGER_14; + + /* Disable All Interrupts */ + REG8(UART0_IER) = 0x00000000; + + /* Enable Divisor Latch */ + REG8(UART0_LCR) |= DLAB; + + /* Set Divisor */ + REG8(UART0_DLL) = (SYSCLK / (BAUDRATE * 16) - 1) & 0x00FF; + REG8(UART0_DLM) = ((SYSCLK / (BAUDRATE * 16) - 1) & 0xFF00) >> 8; + + /* Disable Divisor Latch */ + REG8(UART0_LCR) &= (~DLAB); +} + +int prom_putchar(char c) +{ + unsigned int busy_cnt = 0; + + do + { + /* Prevent Hanging */ + if (busy_cnt++ >= 30000) + { + /* Reset Tx FIFO */ + REG8(UART0_FCR) = TXRST | CHAR_TRIGGER_14; + return 0; + } + } while ((REG8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL); + + /* Send Character */ + REG8(UART0_THR) = c; + + return 1; +} diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/setup.c b/target/linux/realtek/files/arch/mips/rtl8196c/setup.c new file mode 100644 index 000000000..7a2598495 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/setup.c @@ -0,0 +1,191 @@ +#include <linux/config.h> +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/serial.h> +#include <asm/io.h> +#include <asm/time.h> + +#include <prom.h> +#include <platform.h> + +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/percpu.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <linux/notifier.h> +#include <linux/thread_info.h> +#include <linux/time.h> +#include <linux/jiffies.h> +#include <linux/posix-timers.h> +#include <linux/cpu.h> +#include <linux/syscalls.h> +#include <linux/delay.h> + +#include <asm/uaccess.h> +#include <asm/unistd.h> +#include <asm/div64.h> +#include <asm/timex.h> +#include <asm/io.h> + +static void __init serial_init(void); +#if 0 +static void __init rtl8652_time_init(void); +static void rtl8652_timer_ack(void); + +/* + * Called from the timer interrupt handler to charge one tick to the current + * process. user_tick is 1 if the tick is user time, 0 for system. + */ + +void local_timer_interrupt(int irq, void *dev_id) +{ +// profile_tick(CPU_PROFILING); + account_process_tick(current, user_mode(get_irq_regs())); +} +/* + * High-level timer interrupt service routines. This function + * is set as irqaction->handler and is invoked through do_IRQ. + */ + +irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + write_seqlock(&xtime_lock); + +//Add for update flash check + + rtl8652_timer_ack(); + + /* + * call the generic timer interrupt handling + */ + do_timer(1); + + + write_sequnlock(&xtime_lock); + + /* + * In UP mode, we call local_timer_interrupt() to do profiling + * and process accouting. + * + * In SMP mode, local_timer_interrupt() is invoked by appropriate + * low-level local timer interrupt handler. + */ + local_timer_interrupt(irq, dev_id); + + return IRQ_HANDLED; +} +#endif +const char *get_system_type(void) +{ + return "RTL8652"; +} + +void __init prom_init(void) +{ + prom_console_init(); + prom_meminit(); +} + +void __init plat_mem_setup(void) +{ + /* Platform Specific Setup */ + /* define io/mem region */ + ioport_resource.start = 0x18000000; + ioport_resource.end = 0x1fffffff; + + iomem_resource.start = 0x18000000; + iomem_resource.end = 0x1fffffff; + + serial_init(); + +// board_time_init = rtl8652_time_init; +// mips_timer_ack = rtl8652_timer_ack; +} + +#if 0 +static void rtl8652_timer_ack(void) +{ + REG32(TCIR) |= TC0IP; +} + +static void __init rtl8652_time_init(void) +{ + +} +#endif + +extern int rtl_clockevent_init(int irq); +//void __init plat_time_init(struct irqaction *irq) +void __init plat_time_init(void) +{ + /* Setup Timer0 */ + + /* Clear Timer IP status */ + if (REG32(TCIR) & TC0IP) + REG32(TCIR) |= TC0IP; + + /* Here irq->handler is passed from outside */ + // irq->handler = timer_interrupt; + //setup_irq(TC0_IRQ, irq); + + REG32(TCCNR) = 0; /* disable timer before setting CDBR */ + /* extend timer base to 4 times for wireless init process */ +#if 0 + REG32(CDBR) = (DIVISOR) << DIVF_OFFSET; + REG32(TC0DATA) = (MHZ * (1000 / HZ)) << TCD_OFFSET; +#else + REG32(CDBR)=(DIVISOR*4) << DIVF_OFFSET; + REG32(TC0DATA) = ((MHZ * 250) / HZ) << TCD_OFFSET; +#endif + + rtl_clockevent_init(TC0_IRQ); + /* enable timer */ + REG32(TCCNR) = TC0EN | TC0MODE_TIMER; + REG32(TCIR) = TC0IE; + #ifdef CONFIG_RTL865X_WTDOG + *(volatile unsigned long *)(0xb800311C)=0x00600000; + #endif +} + +extern int __init early_serial_setup(struct uart_port *port); +static void __init serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct uart_port s; + + memset(&s, 0, sizeof(s)); + + s.line = 0; + s.type = PORT_16550A; + //s.membase = (unsigned char *) UART0_BASE; + s.mapbase = UART0_MAP_BASE; + s.membase = ioremap_nocache(s.mapbase, 0x20); + s.irq = UART0_IRQ; + //s.uartclk = SYSCLK - BAUDRATE * 24; + s.uartclk = 200000000; + //s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_SPD_CUST; + s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY; + s.iotype = UPIO_MEM; + s.regshift = 2; + //s.fifosize = 1; + s.fifosize = 16; + // s.custom_divisor = SYSCLK / (BAUDRATE * 16) - 1; + + /* Call early_serial_setup() here, to set up 8250 console driver */ + if (early_serial_setup(&s) != 0) { + panic("Serial setup failed!\n"); + } +#endif +} diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/timer.c b/target/linux/realtek/files/arch/mips/rtl8196c/timer.c new file mode 100644 index 000000000..e8d58ebf8 --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/timer.c @@ -0,0 +1,80 @@ +/* + * linux/arch/rlx/rlxocp/time.c + * + * Copyright (C) 1999 Harald Koerfgen + * Copyright (C) 2000 Pavel Machek (pavel@suse.cz) + * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Time handling functinos for Philips Nino. + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <linux/interrupt.h> +#include <linux/timex.h> +#include <linux/delay.h> + +#include <asm/time.h> +#include <asm/rlxbsp.h> + +#include "bspchip.h" + +#ifdef CONFIG_RTL_TIMER_ADJUSTMENT +#include <rtl_types.h> +#include <rtl865xc_asicregs.h> + +void rtl865x_setupTimer1(void) +{ + WRITE_MEM32( TCCNR, READ_MEM32(TCCNR) & ~TC1EN );/* Disable timer1 */ + WRITE_MEM32( TC1DATA, 0xffffff00); + WRITE_MEM32( TCCNR, ( READ_MEM32(TCCNR) | TC1EN ) | TC1MODE_TIMER );/* Enable timer1 - timer mode */ + WRITE_MEM32( TCIR, READ_MEM32(TCIR) & ~TC1IE ); /* Disable timer1 interrupt */ +} +#endif + +void inline bsp_timer_ack(void) +{ + REG32(BSP_TCIR) |= BSP_TC0IP; +} + +void __init bsp_timer_init(void) +{ + unsigned int sys_clock_rate; + + sys_clock_rate = BSP_SYS_CLK_RATE; + + /* Clear Timer IP status */ + if (REG32(BSP_TCIR) & BSP_TC0IP) + REG32(BSP_TCIR) |= BSP_TC0IP; + + /* disable timer */ + REG32(BSP_TCCNR) = 0; /* disable timer before setting CDBR */ + + /* initialize timer registers */ + REG32(BSP_CDBR)=(BSP_DIVISOR) << BSP_DIVF_OFFSET; + REG32(BSP_TC0DATA) = (((sys_clock_rate/BSP_DIVISOR)/HZ)) << BSP_TCD_OFFSET; + // extend timer base to 4 times + //REG32(BSP_CDBR)=(BSP_DIVISOR*4) << BSP_DIVF_OFFSET; + //REG32(BSP_TC0DATA) = (((sys_clock_rate/(BSP_DIVISOR*4))/HZ)) << BSP_TCD_OFFSET; +#ifdef CONFIG_RTL_TIMER_ADJUSTMENT + rtl865x_setupTimer1(); +#endif +#if defined(CONFIG_RTK_WTDOG) + REG32(BSP_WDTCNR) = 0x00600000; +#endif + + /* hook up timer interrupt handler */ + rlx_clockevent_init(BSP_TC0_IRQ); + + /* enable timer */ + REG32(BSP_TCCNR) = BSP_TC0EN | BSP_TC0MODE_TIMER; + REG32(BSP_TCIR) = BSP_TC0IE; +} |