diff options
| author | Roman Yeryomin <roman@advem.lv> | 2012-09-13 00:40:35 +0300 |
|---|---|---|
| committer | Roman Yeryomin <roman@advem.lv> | 2012-12-03 00:13:21 +0200 |
| commit | 5deb3317cb51ac52de922bb55f8492624018906d (patch) | |
| tree | c2fbe6346699d9bb0f2100490c3029519bb8fde8 /target/linux/realtek/files/arch/mips/rtl8196c/mem.c | |
| parent | 0239d37124f9184b478a42de8a7fa1bc85a6a6fe (diff) | |
Add realtek target files
Signed-off-by: Roman Yeryomin <roman@advem.lv>
Diffstat (limited to 'target/linux/realtek/files/arch/mips/rtl8196c/mem.c')
| -rw-r--r-- | target/linux/realtek/files/arch/mips/rtl8196c/mem.c | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/target/linux/realtek/files/arch/mips/rtl8196c/mem.c b/target/linux/realtek/files/arch/mips/rtl8196c/mem.c new file mode 100644 index 000000000..98644d98b --- /dev/null +++ b/target/linux/realtek/files/arch/mips/rtl8196c/mem.c @@ -0,0 +1,133 @@ +#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+
+#include <prom.h>
+#include <platform.h>
+
+#define DCR 0xb8001004
+
+void __init prom_meminit(void)
+{
+ //char *ptr;
+ unsigned int memsize;
+
+ memsize = 0x02000000; /* Default to 32MB */
+ /* Check the command line first for a memsize directive */
+ //ptr = strstr(arcs_cmdline, "mem=");
+#if 1
+ /*now: alway believe DRAM configuration register*/
+ {
+ unsigned int DCRvalue = 0;
+ unsigned int bus_width = 0, chip_sel = 0, row_cnt = 0, col_cnt = 0,bank_cnt = 0;
+
+ DCRvalue = ( (*(volatile unsigned int *)DCR));
+
+ /*bit 19,0:2 bank; 1: 4 bank*/
+ switch(DCRvalue & 0x080000)
+ {
+ case 0x0:
+ bank_cnt = 2;
+ break;
+ case 0x080000:
+ bank_cnt = 4;
+ break;
+ default:
+ bank_cnt = 0;
+ break;
+ }
+
+ /*bit 22~24: colomn count*/
+ switch(DCRvalue & 0x01C00000)
+ {
+ case 0x00000000:
+ col_cnt = 256;
+ break;
+ case 0x00400000:
+ col_cnt = 512;
+ break;
+ case 0x00800000:
+ col_cnt = 1024;
+ break;
+ case 0x00C00000:
+ col_cnt = 2048;
+ break;
+ case 0x01000000:
+ col_cnt = 4096;
+ break;
+ default:
+ printk("unknow colomn count(0x%x)\n",DCRvalue & 0x01C00000);
+ break;
+ }
+
+ /*bit 25~26: row count*/
+ switch(DCRvalue & 0x06000000)
+ {
+ case 0x00000000:
+ row_cnt = 2048;
+ break;
+ case 0x02000000:
+ row_cnt = 4096;
+ break;
+ case 0x04000000:
+ row_cnt = 8192;
+ break;
+ case 0x06000000:
+ row_cnt = 16384;
+ break;
+ }
+
+ /*bit 27: chip select*/
+ switch(DCRvalue & 0x08000000)
+ {
+ case 0x0:
+ chip_sel = 1;
+ break;
+ case 0x08000000:
+ chip_sel = 2;
+ break;
+ }
+
+ /*bit 28~29: bus width*/
+ switch(DCRvalue & 0x30000000)
+ {
+ case 0x0:
+ bus_width = 8;
+ break;
+ case 0x10000000:
+ bus_width = 16;
+ break;
+ case 0x20000000:
+ bus_width = 32;
+ break;
+ default:
+ printk("bus width is reseved!\n");
+ break;
+ }
+
+ /*total size(Byte)*/
+ memsize = (row_cnt * col_cnt *bank_cnt) * (bus_width >> 3) * chip_sel;
+
+ }
+#endif
+
+ /*
+ * call <add_memory_region> to register boot_mem_map
+ * add_memory_region(base, size, type);
+ * type: BOOT_MEM_RAM, BOOT_MEM_ROM_DATA or BOOT_MEM_RESERVED
+ */
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+//unsigned long __init prom_free_prom_memory(void)
+void prom_free_prom_memory(void)
+{
+ //unsigned long freed = 0;
+
+ return;// freed;
+}
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