[ramips] add GPIO configuration feature

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17512 3c298f89-4303-0410-b956-a3cf2f4a3e73

5 files changed, 89 insertions, 1 deletions

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h
index 9e0fdeca6..4fd732432 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h
@@ -17,6 +17,7 @@ void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
 u32 ramips_intc_get_status(void);
 
 void __init ramips_soc_setup(void);
+void __init ramips_gpio_init(void);
 void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq,
 				      unsigned irq);
 
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
index 445bafa3d..a804488f0 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -1,7 +1,7 @@
 /*
  * Ralink RT288x SoC specific definitions
  *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  * Parts of this file are based on Ralink's 2.6.21 BSP
@@ -68,4 +68,6 @@ static inline u32 rt288x_memc_rr(unsigned reg)
 	return __raw_readl(rt288x_memc_base + reg);
 }
 
+void rt288x_gpio_init(u32 mode) __init;
+
 #endif /* _RT228X_H_ */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
index 98308ffe0..d29880611 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
@@ -46,6 +46,7 @@
 #define SYSC_REG_SYSTEM_CONFIG	0x010	/* System Configuration */
 #define SYSC_REG_RESET_CTRL	0x034	/* Reset Control*/
 #define SYSC_REG_RESET_STATUS	0x038	/* Reset Status*/
+#define SYSC_REG_GPIO_MODE	0x060	/* GPIO Purpose Select */
 #define SYSC_REG_IA_ADDRESS	0x310	/* Illegal Access Address */
 #define SYSC_REG_IA_TYPE	0x314	/* Illegal Access Type */
 
@@ -75,6 +76,15 @@
 #define RT2880_RESET_FE		BIT(18)
 #define RT2880_RESET_PCM	BIT(19)
 
+#define RT2880_GPIO_MODE_I2C	BIT(0)
+#define RT2880_GPIO_MODE_UART0	BIT(1)
+#define RT2880_GPIO_MODE_SPI	BIT(2)
+#define RT2880_GPIO_MODE_UART1	BIT(3)
+#define RT2880_GPIO_MODE_JTAG	BIT(4)
+#define RT2880_GPIO_MODE_MDIO	BIT(5)
+#define RT2880_GPIO_MODE_SDRAM	BIT(6)
+#define RT2880_GPIO_MODE_PCI	BIT(7)
+
 #define RT2880_INTC_INT_TIMER0	BIT(0)
 #define RT2880_INTC_INT_TIMER1	BIT(1)
 #define RT2880_INTC_INT_UART0	BIT(2)
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
index c9d5b4458..195bfbe51 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -73,4 +73,59 @@ static inline u32 rt305x_memc_rr(unsigned reg)
 	return __raw_readl(rt305x_memc_base + reg);
 }
 
+#define RT305X_GPIO_I2C_SD	1
+#define RT305X_GPIO_I2C_SCLK	2
+#define RT305X_GPIO_SPI_EN	3
+#define RT305X_GPIO_SPI_CLK	4
+#define RT305X_GPIO_SPI_DOUT	5
+#define RT305X_GPIO_SPI_DIN	6
+/* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
+#define RT305X_GPIO_7		7
+#define RT305X_GPIO_8		8
+#define RT305X_GPIO_9		9
+#define RT305X_GPIO_10		10
+#define RT305X_GPIO_11		11
+#define RT305X_GPIO_12		12
+#define RT305X_GPIO_13		13
+#define RT305X_GPIO_14		14
+#define RT305X_GPIO_UART1_TXD	15
+#define RT305X_GPIO_UART1_RXD	16
+#define RT305X_GPIO_JTAG_TDO	17
+#define RT305X_GPIO_JTAG_TDI	18
+#define RT305X_GPIO_JTAG_TMS	19
+#define RT305X_GPIO_JTAG_TCLK	20
+#define RT305X_GPIO_JTAG_TRST_N	21
+#define RT305X_GPIO_MDIO_MDC	22
+#define RT305X_GPIO_MDIO_MDIO	23
+#define RT305X_GPIO_SDRAM_MD16	24
+#define RT305X_GPIO_SDRAM_MD17	25
+#define RT305X_GPIO_SDRAM_MD18	26
+#define RT305X_GPIO_SDRAM_MD19	27
+#define RT305X_GPIO_SDRAM_MD20	28
+#define RT305X_GPIO_SDRAM_MD21	29
+#define RT305X_GPIO_SDRAM_MD22	30
+#define RT305X_GPIO_SDRAM_MD23	31
+#define RT305X_GPIO_SDRAM_MD24	32
+#define RT305X_GPIO_SDRAM_MD25	33
+#define RT305X_GPIO_SDRAM_MD26	34
+#define RT305X_GPIO_SDRAM_MD27	35
+#define RT305X_GPIO_SDRAM_MD28	36
+#define RT305X_GPIO_SDRAM_MD29	37
+#define RT305X_GPIO_SDRAM_MD30	38
+#define RT305X_GPIO_SDRAM_MD31	39
+#define RT305X_GPIO_GE0_TXD0	40
+#define RT305X_GPIO_GE0_TXD1	41
+#define RT305X_GPIO_GE0_TXD2	42
+#define RT305X_GPIO_GE0_TXD3	43
+#define RT305X_GPIO_GE0_TXEN	44
+#define RT305X_GPIO_GE0_TXCLK	45
+#define RT305X_GPIO_GE0_RXD0	46
+#define RT305X_GPIO_GE0_RXD1	47
+#define RT305X_GPIO_GE0_RXD2	48
+#define RT305X_GPIO_GE0_RXD3	49
+#define RT305X_GPIO_GE0_RXDV	50
+#define RT305X_GPIO_GE0_RXCLK	51
+
+void rt305x_gpio_init(u32 mode) __init;
+
 #endif /* _RT305X_H_ */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index d4a192063..7f0666d5b 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -49,6 +49,7 @@
 #define SYSC_REG_SYSTEM_CONFIG	0x010	/* System Configuration */
 #define SYSC_REG_RESET_CTRL	0x034	/* Reset Control*/
 #define SYSC_REG_RESET_STATUS	0x038	/* Reset Status*/
+#define SYSC_REG_GPIO_MODE	0x060	/* GPIO Purpose Select */
 #define SYSC_REG_IA_ADDRESS	0x310	/* Illegal Access Address */
 #define SYSC_REG_IA_TYPE	0x314	/* Illegal Access Type */
 
@@ -61,6 +62,25 @@
 #define SYSTEM_CONFIG_CPUCLK_320	0x0
 #define SYSTEM_CONFIG_CPUCLK_384	0x1
 
+#define RT305X_GPIO_MODE_I2C		BIT(0)
+#define RT305X_GPIO_MODE_SPI		BIT(1)
+#define RT305X_GPIO_MODE_UART0_SHIFT	2
+#define RT305X_GPIO_MODE_UART0_MASK	0x7
+#define RT305X_GPIO_MODE_UART0(x)	((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+#define RT305X_GPIO_MODE_UARTF		0x0
+#define RT305X_GPIO_MODE_PCM_UARTF	0x1
+#define RT305X_GPIO_MODE_PCM_I2S	0x2
+#define RT305X_GPIO_MODE_I2S_UARTF	0x3
+#define RT305X_GPIO_MODE_PCM_GPIO	0x4
+#define RT305X_GPIO_MODE_GPIO_UARTF	0x5
+#define RT305X_GPIO_MODE_GPIO_I2S	0x6
+#define RT305X_GPIO_MODE_GPIO		0x7
+#define RT305X_GPIO_MODE_UART1		BIT(5)
+#define RT305X_GPIO_MODE_JTAG		BIT(6)
+#define RT305X_GPIO_MODE_MDIO		BIT(7)
+#define RT305X_GPIO_MODE_SDRAM		BIT(8)
+#define RT305X_GPIO_MODE_RGMII		BIT(9)
+
 #define RT305X_RESET_SYSTEM	BIT(0)
 #define RT305X_RESET_TIMER	BIT(8)
 #define RT305X_RESET_INTC	BIT(9)