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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2009-09-04 15:08:26 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2009-09-04 15:08:26 +0000
commit2f3b768d56c443c04e57ada7ac6893ef7c8ab7bc (patch)
treeccf6a5b81e9dc2421a4387d63ac2735067130ab1 /target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
parent3ff4f7ce16ee4fa844ab699d64c1b8f8f8065c07 (diff)
[ramips] add GPIO configuration feature
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17512 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h')
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index d4a192063..7f0666d5b 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -49,6 +49,7 @@
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
+#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
@@ -61,6 +62,25 @@
#define SYSTEM_CONFIG_CPUCLK_320 0x0
#define SYSTEM_CONFIG_CPUCLK_384 0x1
+#define RT305X_GPIO_MODE_I2C BIT(0)
+#define RT305X_GPIO_MODE_SPI BIT(1)
+#define RT305X_GPIO_MODE_UART0_SHIFT 2
+#define RT305X_GPIO_MODE_UART0_MASK 0x7
+#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+#define RT305X_GPIO_MODE_UARTF 0x0
+#define RT305X_GPIO_MODE_PCM_UARTF 0x1
+#define RT305X_GPIO_MODE_PCM_I2S 0x2
+#define RT305X_GPIO_MODE_I2S_UARTF 0x3
+#define RT305X_GPIO_MODE_PCM_GPIO 0x4
+#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
+#define RT305X_GPIO_MODE_GPIO_I2S 0x6
+#define RT305X_GPIO_MODE_GPIO 0x7
+#define RT305X_GPIO_MODE_UART1 BIT(5)
+#define RT305X_GPIO_MODE_JTAG BIT(6)
+#define RT305X_GPIO_MODE_MDIO BIT(7)
+#define RT305X_GPIO_MODE_SDRAM BIT(8)
+#define RT305X_GPIO_MODE_RGMII BIT(9)
+
#define RT305X_RESET_SYSTEM BIT(0)
#define RT305X_RESET_TIMER BIT(8)
#define RT305X_RESET_INTC BIT(9)