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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-09-12 19:03:12 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-09-12 19:03:12 +0000
commitde071d14f78fc086180e69333194467bd32787ed (patch)
treeeb44f761ca9bbb580c94b1cb48bea748c1e3523a /target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
parent95cfc6ea8c36cfccd312e5a90583faf263e7d29d (diff)
ramips/rt305x: add initial support for Rt5350 SoC
Somehow detecting the RAM size in common/setup.c doesn't work here, it always detects 64M and then crashes on devices with less RAM. Probably using MEMC_REG_SDRAM_CFG1 to know the RAM size is how it could be, for now I use the mem=32M kernel parameter to get stuff working. Signed-off-by: Daniel Golle <dgolle@allnet.de> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33381 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h')
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index db037a583..930b3337b 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -76,6 +76,9 @@
#define RT3352_CHIP_NAME0 0x33335452
#define RT3352_CHIP_NAME1 0x20203235
+#define RT5350_CHIP_NAME0 0x33355452
+#define RT5350_CHIP_NAME1 0x20203035
+
#define CHIP_ID_ID_MASK 0xff
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
@@ -95,6 +98,12 @@
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
+#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
+#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
+#define RT5350_SYSCFG0_CPUCLK_360 0x0
+#define RT5350_SYSCFG0_CPUCLK_320 0x2
+#define RT5350_SYSCFG0_CPUCLK_300 0x3
+
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)