diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-08-30 19:15:51 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-08-30 19:15:51 +0000 |
commit | b887a6d197170b719028f31085876d8deaed35b6 (patch) | |
tree | 36b5045e64065dcb96b8da4d93ffe20fc286a711 /target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h | |
parent | 237a5a2c34824a249326c1cb58c495ab4629baae (diff) |
[ramips] initial support for RT288x/RT305x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17439 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h')
-rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h new file mode 100644 index 000000000..9b218de02 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h @@ -0,0 +1,89 @@ +/* + * Ralink RT288x SoC specific definitions + * + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RT288X_H_ +#define _RT288X_H_ + +#include <linux/init.h> +#include <linux/io.h> + +void rt288x_detect_sys_type(void) __init; + +#define RT288X_SYS_TYPE_LEN 64 +extern unsigned char rt288x_sys_type[RT288X_SYS_TYPE_LEN]; + +void rt288x_detect_sys_freq(void) __init; + +extern unsigned long rt288x_cpu_freq; +extern unsigned long rt288x_sys_freq; + +extern unsigned long rt288x_mach_type; +#define RT288X_MACH_GENERIC 0 + +#define RT288X_CPU_IRQ_BASE 0 +#define RT288X_INTC_IRQ_BASE 8 +#define RT288X_INTC_IRQ_COUNT 32 +#define RT288X_GPIO_IRQ_BASE 40 + +#define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2) +#define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4) +#define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5) +#define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6) +#define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7) + +#define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0) +#define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1) +#define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2) +#define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3) +#define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4) +#define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8) +#define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23) + +#define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x)) +#define RT288X_GPIO_COUNT 32 + +extern void __iomem *rt288x_sysc_base; +extern void __iomem *rt288x_intc_base; +extern void __iomem *rt288x_memc_base; + +static inline void rt288x_sysc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_sysc_base + reg); +} + +static inline u32 rt288x_sysc_rr(unsigned reg) +{ + return __raw_readl(rt288x_sysc_base + reg); +} + +static inline void rt288x_intc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_intc_base + reg); +} + +static inline u32 rt288x_intc_rr(unsigned reg) +{ + return __raw_readl(rt288x_intc_base + reg); +} + +static inline void rt288x_memc_wr(u32 val, unsigned reg) +{ + __raw_writel(val, rt288x_memc_base + reg); +} + +static inline u32 rt288x_memc_rr(unsigned reg) +{ + return __raw_readl(rt288x_memc_base + reg); +} + +#endif /* _RT228X_H_ */ |