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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-30 17:38:08 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-30 17:38:08 +0000
commitf39cd042512614edfbed8b4ea22023c1f75145b2 (patch)
treec6f85a18f1e5ea9e15a4649f8956c53b33f3726d /target/linux/olpc/files/drivers
parent25040fe2c0cc788e36c2f4a4d82e84ddea8a71a1 (diff)
cleaning up olpc patch 1
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10060 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/olpc/files/drivers')
-rw-r--r--target/linux/olpc/files/drivers/input/mouse/olpc.c554
-rw-r--r--target/linux/olpc/files/drivers/input/mouse/olpc.h49
-rw-r--r--target/linux/olpc/files/drivers/media/video/cafe_ccic-regs.h166
-rw-r--r--target/linux/olpc/files/drivers/media/video/cafe_ccic.c2319
-rw-r--r--target/linux/olpc/files/drivers/mtd/mtdcore.h11
-rw-r--r--target/linux/olpc/files/drivers/mtd/mtdoops.c365
-rw-r--r--target/linux/olpc/files/drivers/mtd/onenand/onenand_sim.c495
-rw-r--r--target/linux/olpc/files/drivers/video/geode/geode_regs.h242
-rw-r--r--target/linux/olpc/files/drivers/video/geode/suspend_gx.c272
-rw-r--r--target/linux/olpc/files/drivers/video/olpc_dcon.c824
-rw-r--r--target/linux/olpc/files/drivers/video/olpc_dcon.h75
11 files changed, 5372 insertions, 0 deletions
diff --git a/target/linux/olpc/files/drivers/input/mouse/olpc.c b/target/linux/olpc/files/drivers/input/mouse/olpc.c
new file mode 100644
index 000000000..dc575ac06
--- /dev/null
+++ b/target/linux/olpc/files/drivers/input/mouse/olpc.c
@@ -0,0 +1,554 @@
+/*
+ * OLPC touchpad PS/2 mouse driver
+ *
+ * Copyright (c) 2006 One Laptop Per Child, inc.
+ * Authors Zephaniah E. Hull and Andres Salomon <dilinger@laptop.org>
+ *
+ * This driver is partly based on the ALPS driver, which is:
+ *
+ * Copyright (c) 2003 Neil Brown <neilb@cse.unsw.edu.au>
+ * Copyright (c) 2003-2005 Peter Osterlund <petero2@telia.com>
+ * Copyright (c) 2004 Dmitry Torokhov <dtor@mail.ru>
+ * Copyright (c) 2005 Vojtech Pavlik <vojtech@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The touchpad on the OLPC is fairly wide, with the entire area usable
+ * as a tablet ("PT mode"), and the center 1/3rd also usable as a touchpad
+ * ("GS mode").
+ *
+ * Earlier version of the device had simultaneous reporting; however, that
+ * was removed. Instead, the device now reports packets in one mode, and
+ * tells the driver when a mode switch needs to happen.
+ */
+
+#include <linux/input.h>
+#include <linux/serio.h>
+#include <linux/libps2.h>
+#include <linux/delay.h>
+#include <asm/olpc.h>
+
+#include "psmouse.h"
+#include "olpc.h"
+
+static int tpdebug;
+module_param(tpdebug, int, 0644);
+
+#define OLPC_GS 1 /* The GS sensor. */
+#define OLPC_PT 2 /* The PT sensor. */
+
+static struct olpc_model_info olpc_model_data[] = {
+ { { 0x67, 0x00, 0x00 }, OLPC_GS | OLPC_PT }, /* unknown ID */
+ { { 0x67, 0x00, 0x0a }, OLPC_GS | OLPC_PT }, /* pre-B1 */
+ { { 0x67, 0x00, 0x14 }, OLPC_GS }, /* B1.*/
+ { { 0x67, 0x00, 0x28 }, OLPC_GS | OLPC_PT }, /* B2 */
+ { { 0x67, 0x00, 0x3c }, OLPC_GS | OLPC_PT }, /* B2-2 */
+ { { 0x67, 0x00, 0x50 }, OLPC_GS | OLPC_PT }, /* C1 */
+};
+
+#define OLPC_PKT_PT 0xcf
+#define OLPC_PKT_GS 0xff
+
+static int olpc_absolute_mode(struct psmouse *psmouse, int mode);
+
+/*
+ * OLPC absolute Mode - single-mode format
+ *
+ * byte 0: 1 1 0 0 1 1 1 1
+ * byte 1: 0 x6 x5 x4 x3 x2 x1 x0
+ * byte 2(PT): 0 0 x9 x8 x7 ? pt-dsw gs-dsw
+ * byte 2(GS): 0 x10 x9 x8 x7 ? gs-dsw pt-dsw
+ * byte 3: 0 y9 y8 y7 1 0 swr swl
+ * byte 4: 0 y6 y5 y4 y3 y2 y1 y0
+ * byte 5: 0 z6 z5 z4 z3 z2 z1 z0
+ *
+ * ?'s are not defined in the protocol spec, may vary between models.
+ *
+ * swr/swl are the left/right buttons.
+ *
+ * pt-dsw/gs-dsw indicate that the pt/gs sensor is detecting a
+ * pen/finger
+ */
+
+static void olpc_process_packet_gspt(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+ unsigned char *packet = psmouse->packet;
+ struct input_dev *dev = psmouse->dev;
+ struct input_dev *dev2 = priv->dev2;
+ int x, y, z, gs_down = 0, pt_down = 0, left, right;
+ struct timeval now_tv;
+ s64 now_ns;
+
+ left = packet[3] & 1;
+ right = packet[3] & 2;
+ x = packet[1] | ((packet[2] & 0x78) << 4);
+ y = packet[4] | ((packet[3] & 0x70) << 3);
+ z = packet[5];
+
+ if (psmouse->packet[0] == OLPC_PKT_GS) {
+ pt_down = !!(packet[2] & 1);
+ gs_down = !!(packet[2] & 2);
+ } else if (psmouse->packet[0] == OLPC_PKT_PT) {
+ gs_down = !!(packet[2] & 1);
+ pt_down = !!(packet[2] & 2);
+ }
+
+ /*
+ * XXX: Kludge.
+ * If it's been more than 30ms since the last packet,
+ * assume that there was a lift we were never told about.
+ */
+ do_gettimeofday(&now_tv);
+ now_ns = timeval_to_ns (&now_tv);
+ if (now_ns >= priv->late) {
+ input_report_key(dev, BTN_TOUCH, 0);
+ input_report_key(dev, BTN_TOOL_PEN, 0);
+ input_report_key(dev2, BTN_TOUCH, 0);
+ input_report_key(dev2, BTN_TOOL_FINGER, 0);
+
+ input_sync(dev);
+ input_sync(dev2);
+ }
+
+ priv->late = now_ns + (30 * NSEC_PER_MSEC);
+
+
+ if (tpdebug) {
+ printk(KERN_DEBUG "%s %02x %02x %02x %02x %02x %02x\n",
+ __FUNCTION__, psmouse->packet[0], psmouse->packet[1],
+ psmouse->packet[2], psmouse->packet[3], psmouse->packet[4],
+ psmouse->packet[5]);
+ printk(KERN_DEBUG "l=%d r=%d p=%d g=%d x=%d y=%d z=%d\n",
+ left, right, pt_down, gs_down, x, y, z);
+ }
+
+ if (psmouse->packet[0] == OLPC_PKT_PT) {
+ input_report_key(dev, BTN_LEFT, left);
+ input_report_key(dev, BTN_RIGHT, right);
+ } else if (psmouse->packet[0] == OLPC_PKT_GS) {
+ input_report_key(dev, BTN_LEFT, left);
+ input_report_key(dev, BTN_RIGHT, right);
+ input_report_key(dev2, BTN_LEFT, left);
+ input_report_key(dev2, BTN_RIGHT, right);
+ }
+
+ input_report_key(dev, BTN_TOUCH, pt_down);
+ input_report_key(dev, BTN_TOOL_PEN, pt_down);
+ input_report_key(dev2, BTN_TOUCH, gs_down);
+ input_report_key(dev2, BTN_TOOL_FINGER, gs_down);
+
+ input_report_abs(dev2, ABS_PRESSURE, z);
+
+ if (psmouse->packet[0] == OLPC_PKT_PT && pt_down) {
+ input_report_abs(dev, ABS_X, x);
+ input_report_abs(dev, ABS_Y, y);
+ } else if (psmouse->packet[0] == OLPC_PKT_GS && gs_down) {
+ input_report_abs(dev2, ABS_X, x);
+ input_report_abs(dev2, ABS_Y, y);
+ }
+
+ input_sync(dev);
+ input_sync(dev2);
+
+ if (priv->pending_mode == OLPC_GS &&
+ psmouse->packet[0] == OLPC_PKT_PT && pt_down) {
+ priv->pending_mode = 0;
+ cancel_delayed_work(&priv->mode_switch);
+ }
+
+ if (priv->i->flags & (OLPC_PT|OLPC_GS)) {
+ int pending = 0;
+ if (psmouse->packet[0] == OLPC_PKT_PT && !pt_down)
+ pending = OLPC_GS;
+ else if (psmouse->packet[0] == OLPC_PKT_GS && pt_down)
+ pending = OLPC_PT;
+
+ if (priv->current_mode == pending) {
+ priv->pending_mode = 0;
+ pending = priv->current_mode;
+ }
+ else if (priv->pending_mode != pending) {
+ priv->pending_mode = pending;
+ if (tpdebug)
+ printk(KERN_WARNING "Scheduling mode switch to %s.\n",
+ pending == OLPC_GS ? "GS" : "PT");
+
+ /*
+ * Apply a de-bounce when switching from PT to GS, to allow for
+ * spurious PT-up packets.
+ */
+ if (priv->pending_mode == OLPC_GS)
+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, msecs_to_jiffies(50));
+ else
+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, 0);
+ }
+ }
+}
+
+static psmouse_ret_t olpc_process_byte(struct psmouse *psmouse)
+{
+ psmouse_ret_t ret = PSMOUSE_BAD_DATA;
+
+ if (psmouse->packet[0] != OLPC_PKT_PT &&
+ psmouse->packet[0] != OLPC_PKT_GS)
+ goto out;
+
+ /* Bytes 2 - 6 should have 0 in the highest bit */
+ if (psmouse->pktcnt >= 2 && psmouse->pktcnt <= 6 &&
+ (psmouse->packet[psmouse->pktcnt - 1] & 0x80))
+ goto out;
+
+ if (psmouse->pktcnt == 6) {
+ olpc_process_packet_gspt(psmouse);
+ ret = PSMOUSE_FULL_PACKET;
+ goto out;
+ }
+
+ ret = PSMOUSE_GOOD_DATA;
+out:
+ if (ret != PSMOUSE_GOOD_DATA && ret != PSMOUSE_FULL_PACKET)
+ printk(KERN_DEBUG "%s: (%d) %02x %02x %02x %02x %02x %02x\n",
+ __FUNCTION__, psmouse->pktcnt, psmouse->packet[0],
+ psmouse->packet[1], psmouse->packet[2],
+ psmouse->packet[3], psmouse->packet[4],
+ psmouse->packet[5]);
+ return ret;
+}
+
+static struct olpc_model_info *olpc_get_model(struct psmouse *psmouse)
+{
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+ unsigned char param[4];
+ int i;
+
+ /*
+ * Now try "E7 report". Allowed responses are in
+ * olpc_model_data[].signature
+ */
+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21))
+ return NULL;
+
+ param[0] = param[1] = param[2] = 0xff;
+ if (ps2_command(ps2dev, param, PSMOUSE_CMD_GETINFO))
+ return NULL;
+
+ pr_debug("olpc.c(%d): E7 report: %2.2x %2.2x %2.2x",
+ __LINE__, param[0], param[1], param[2]);
+
+ for (i = 0; i < ARRAY_SIZE(olpc_model_data); i++) {
+ if (!memcmp(param, olpc_model_data[i].signature,
+ sizeof(olpc_model_data[i].signature))) {
+ printk(KERN_INFO __FILE__ ": OLPC touchpad revision 0x%x.\n", param[2]);
+ return olpc_model_data + i;
+ }
+ }
+
+ /*
+ * ALPS creates new IDs pretty frequently; rather than listing them
+ * all, just assume they support the defaults. We've set aside the
+ * first entry of olpc_model_data as the catch-all.
+ */
+ if (!memcmp(param, olpc_model_data[0].signature, 2)) {
+ printk(KERN_INFO __FILE__ ": unknown ALPS revision %x, assuming default flags.\n", param[2]);
+ return &olpc_model_data[0];
+ }
+
+ return NULL;
+}
+
+static int olpc_find_mode(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+ int mode = priv->i->flags;
+
+ if (mode & OLPC_GS)
+ mode = OLPC_GS;
+ else if (mode & OLPC_PT)
+ mode = OLPC_PT;
+ else
+ mode = -1;
+
+ return mode;
+}
+
+/*
+ * Touchpad should be disabled before calling this!
+ */
+static int olpc_new_mode(struct psmouse *psmouse, int mode)
+{
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+ struct olpc_data *priv = psmouse->private;
+ unsigned char param;
+ int ret;
+
+ if (tpdebug)
+ printk(KERN_WARNING __FILE__ ": Switching to %d. [%lu]\n", mode, jiffies);
+
+ if ((ret = ps2_command(ps2dev, &param, 0x01F2)))
+ goto failed;
+ if ((ret = ps2_command(ps2dev, &param, 0x01F2)))
+ goto failed;
+ if ((ret = ps2_command(ps2dev, &param, 0x01F2)))
+ goto failed;
+
+ switch (mode) {
+ default:
+ printk(KERN_WARNING __FILE__ ": Invalid mode %d. Defaulting to OLPC_GS.\n", mode);
+ case OLPC_GS:
+ ret = ps2_command(ps2dev, NULL, 0xE6);
+ break;
+ case OLPC_PT:
+ ret = ps2_command(ps2dev, NULL, 0xE7);
+ break;
+ }
+ if (ret)
+ goto failed;
+
+ /* XXX: This is a bit hacky, make sure this isn't screwing stuff up. */
+ psmouse->pktcnt = psmouse->out_of_sync = 0;
+ psmouse->last = jiffies;
+ psmouse->state = PSMOUSE_ACTIVATED;
+
+ if ((ret = ps2_command(ps2dev, NULL, PSMOUSE_CMD_ENABLE)))
+ goto failed;
+
+ priv->current_mode = mode;
+ priv->pending_mode = 0;
+ if (tpdebug)
+ printk(KERN_WARNING __FILE__ ": Switched to mode %d successful.\n", mode);
+
+failed:
+ if (ret)
+ printk(KERN_WARNING __FILE__ ": Mode switch to %d failed! (%d) [%lu]\n", mode, ret, jiffies);
+ return ret;
+}
+
+static int olpc_absolute_mode(struct psmouse *psmouse, int mode)
+{
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+
+ /* Switch to 'Advanced mode.', four disables in a row. */
+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE))
+ return -1;
+
+ return olpc_new_mode(psmouse, mode);
+}
+
+/*
+ * olpc_poll() - poll the touchpad for current motion packet.
+ * Used in resync.
+ * Note: We can't poll, so always return failure.
+ */
+static int olpc_poll(struct psmouse *psmouse)
+{
+ return -1;
+}
+
+static int olpc_reconnect(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+ int mode;
+
+ if (olpc_rev_after(OLPC_REV_B2))
+ if (psmouse->ps2dev.serio->dev.power.power_state.event != PM_EVENT_ON)
+ return 0;
+
+ psmouse_reset(psmouse);
+
+ if (!(priv->i = olpc_get_model(psmouse)))
+ return -1;
+
+ mode = olpc_find_mode(psmouse);
+ if (mode < 0)
+ return -1;
+
+ if (olpc_absolute_mode(psmouse, mode)) {
+ printk(KERN_ERR __FILE__ ": Failed to reenable absolute mode.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static void olpc_disconnect(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+
+ psmouse_reset(psmouse);
+ input_unregister_device(priv->dev2);
+ kfree(priv);
+}
+
+static void olpc_mode_switch(struct work_struct *w)
+{
+ struct delayed_work *work = container_of(w, struct delayed_work, work);
+ struct olpc_data *priv = container_of(work, struct olpc_data, mode_switch);
+ struct psmouse *psmouse = priv->psmouse;
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+ int pending_mode, ret;
+
+ if (priv->pending_mode == priv->current_mode) {
+ priv->pending_mode = 0;
+ printk (KERN_DEBUG __FILE__ ": In switch_mode, no target mode.\n");
+ return;
+ }
+
+ if (tpdebug)
+ printk(KERN_WARNING __FILE__ ": Disable for switch to %d. [%lu]\n", priv->pending_mode, jiffies);
+
+ /* XXX: This is a bit hacky, make sure this isn't screwing stuff up. */
+ psmouse->state = PSMOUSE_INITIALIZING;
+
+ ret = ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE);
+ if (ret) {
+ /* XXX: if this ever fails, we need to do a full reset! */
+ printk(KERN_WARNING __FILE__ ": Disable failed for switch to %d. (%d) [%lu]\n", priv->pending_mode, ret, jiffies);
+ return;
+ }
+
+ /*
+ * ALPS tells us that it may take up to 20msec for the disable to
+ * take effect; however, ps2_command() will wait up to 200msec for
+ * the ACK to come back (and I'm assuming that by the time the
+ * hardware sends back its ACK, it has stopped sending bytes).
+ */
+ pending_mode = priv->pending_mode;
+
+ if (olpc_new_mode(psmouse, priv->pending_mode))
+ goto bad;
+
+ /*
+ * Deal with a potential race condition.
+ *
+ * If there is a brief tap of a stylus or a fingernail that
+ * triggers a mode switch to PT mode, and the stylus/fingernail is
+ * lifted after the DISABLE above, but before we reenable in the new mode,
+ * then we can get stuck in PT mode.
+ */
+ if (pending_mode == OLPC_PT) {
+ priv->pending_mode = OLPC_GS;
+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, msecs_to_jiffies(50));
+ }
+
+ return;
+
+bad:
+ printk(KERN_WARNING __FILE__ ": Failure to switch modes, resetting device...\n");
+ olpc_reconnect(psmouse);
+}
+
+int olpc_init(struct psmouse *psmouse)
+{
+ struct olpc_data *priv;
+ struct input_dev *dev = psmouse->dev;
+ struct input_dev *dev2;
+ int mode;
+
+ priv = kzalloc(sizeof(struct olpc_data), GFP_KERNEL);
+ dev2 = input_allocate_device();
+ if (!priv || !dev2)
+ goto init_fail;
+
+ psmouse->private = priv;
+ priv->dev2 = dev2;
+ priv->psmouse = psmouse;
+
+ psmouse_reset(psmouse);
+ if (!(priv->i = olpc_get_model(psmouse)))
+ goto init_fail;
+
+ mode = olpc_find_mode(psmouse);
+ if (mode < 0) {
+ printk(KERN_ERR __FILE__ ": Failed to identify proper mode\n");
+ goto init_fail;
+ }
+
+ if (olpc_absolute_mode(psmouse, mode)) {
+ printk(KERN_ERR __FILE__ ": Failed to enable absolute mode\n");
+ goto init_fail;
+ }
+
+ /*
+ * Unset some of the default bits for things we don't have.
+ */
+ dev->evbit[LONG(EV_REL)] &= ~BIT(EV_REL);
+ dev->relbit[LONG(REL_X)] &= ~(BIT(REL_X) | BIT(REL_Y));
+ dev->keybit[LONG(BTN_MIDDLE)] &= ~BIT(BTN_MIDDLE);
+
+ dev->evbit[LONG(EV_KEY)] |= BIT(EV_KEY);
+ dev->keybit[LONG(BTN_TOUCH)] |= BIT(BTN_TOUCH);
+ dev->keybit[LONG(BTN_TOOL_PEN)] |= BIT(BTN_TOOL_PEN);
+ dev->keybit[LONG(BTN_LEFT)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT);
+
+ dev->evbit[LONG(EV_ABS)] |= BIT(EV_ABS);
+ input_set_abs_params(dev, ABS_X, 2, 1000, 0, 0);
+ input_set_abs_params(dev, ABS_Y, 0, 717, 0, 0);
+
+ snprintf(priv->phys, sizeof(priv->phys),
+ "%s/input1", psmouse->ps2dev.serio->phys);
+ dev2->phys = priv->phys;
+ dev2->name = "OLPC ALPS GlideSensor";
+ dev2->id.bustype = BUS_I8042;
+ dev2->id.vendor = 0x0002;
+ dev2->id.product = PSMOUSE_OLPC;
+ dev2->id.version = 0x0000;
+
+ dev2->evbit[LONG(EV_KEY)] |= BIT(EV_KEY);
+ dev2->keybit[LONG(BTN_TOUCH)] |= BIT(BTN_TOUCH);
+ dev2->keybit[LONG(BTN_TOOL_FINGER)] |= BIT(BTN_TOOL_FINGER);
+ dev2->keybit[LONG(BTN_LEFT)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT);
+
+ dev2->evbit[LONG(EV_ABS)] |= BIT(EV_ABS);
+ input_set_abs_params(dev2, ABS_X, 350, 512, 0, 0);
+ input_set_abs_params(dev2, ABS_Y, 70, 325, 0, 0);
+ input_set_abs_params(dev2, ABS_PRESSURE, 0, 63, 0, 0);
+
+ if (input_register_device(dev2)) {
+ printk(KERN_ERR __FILE__ ": Failed to register GlideSensor\n");
+ goto init_fail;
+ }
+
+ psmouse->protocol_handler = olpc_process_byte;
+ psmouse->poll = olpc_poll;
+ psmouse->disconnect = olpc_disconnect;
+ psmouse->reconnect = olpc_reconnect;
+ psmouse->pktsize = 6;
+
+ /* Disable the idle resync. */
+ psmouse->resync_time = 0;
+ /* Reset after a lot of bad bytes. */
+ psmouse->resetafter = 1024;
+
+ INIT_DELAYED_WORK(&priv->mode_switch, olpc_mode_switch);
+
+ return 0;
+
+init_fail:
+ input_free_device(dev2);
+ kfree(priv);
+ return -1;
+}
+
+int olpc_detect(struct psmouse *psmouse, int set_properties)
+{
+ if (!olpc_get_model(psmouse))
+ return -1;
+
+ if (set_properties) {
+ psmouse->vendor = "ALPS";
+ psmouse->name = "PenTablet";
+ psmouse->model = 0;
+ }
+ return 0;
+}
+
diff --git a/target/linux/olpc/files/drivers/input/mouse/olpc.h b/target/linux/olpc/files/drivers/input/mouse/olpc.h
new file mode 100644
index 000000000..426f8b4ea
--- /dev/null
+++ b/target/linux/olpc/files/drivers/input/mouse/olpc.h
@@ -0,0 +1,49 @@
+/*
+ * OLPC touchpad PS/2 mouse driver
+ *
+ * Copyright (c) 2006 One Laptop Per Child, inc.
+ *
+ * This driver is partly based on the ALPS driver.
+ * Copyright (c) 2003 Peter Osterlund <petero2@telia.com>
+ * Copyright (c) 2005 Vojtech Pavlik <vojtech@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef _OLPC_H
+#define _OLPC_H
+
+struct olpc_model_info {
+ unsigned char signature[3];
+ unsigned char flags;
+};
+
+struct olpc_data {
+ struct input_dev *dev2; /* Relative device */
+ struct psmouse *psmouse;
+ char name[32]; /* Name */
+ char phys[32]; /* Phys */
+ struct olpc_model_info *i; /* Info */
+ int pending_mode;
+ int current_mode;
+ s64 late;
+ struct delayed_work mode_switch;
+};
+
+#ifdef CONFIG_MOUSE_PS2_OLPC
+int olpc_detect(struct psmouse *psmouse, int set_properties);
+int olpc_init(struct psmouse *psmouse);
+#else
+inline int olpc_detect(struct psmouse *psmouse, int set_properties)
+{
+ return -ENOSYS;
+}
+inline int olpc_init(struct psmouse *psmouse)
+{
+ return -ENOSYS;
+}
+#endif
+
+#endif
diff --git a/target/linux/olpc/files/drivers/media/video/cafe_ccic-regs.h b/target/linux/olpc/files/drivers/media/video/cafe_ccic-regs.h
new file mode 100644
index 000000000..8e2a87cdc
--- /dev/null
+++ b/target/linux/olpc/files/drivers/media/video/cafe_ccic-regs.h
@@ -0,0 +1,166 @@
+/*
+ * Register definitions for the m88alp01 camera interface. Offsets in bytes
+ * as given in the spec.
+ *
+ * Copyright 2006 One Laptop Per Child Association, Inc.
+ *
+ * Written by Jonathan Corbet, corbet@lwn.net.
+ *
+ * This file may be distributed under the terms of the GNU General
+ * Public License, version 2.
+ */
+#define REG_Y0BAR 0x00
+#define REG_Y1BAR 0x04
+#define REG_Y2BAR 0x08
+/* ... */
+
+#define REG_IMGPITCH 0x24 /* Image pitch register */
+#define IMGP_YP_SHFT 2 /* Y pitch params */
+#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
+#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
+#define IMGP_UVP_MASK 0x3ffc0000
+#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
+#define IRQ_EOF0 0x00000001 /* End of frame 0 */
+#define IRQ_EOF1 0x00000002 /* End of frame 1 */
+#define IRQ_EOF2 0x00000004 /* End of frame 2 */
+#define IRQ_SOF0 0x00000008 /* Start of frame 0 */
+#define IRQ_SOF1 0x00000010 /* Start of frame 1 */
+#define IRQ_SOF2 0x00000020 /* Start of frame 2 */
+#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
+#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
+#define IRQ_TWSIR 0x00020000 /* TWSI read */
+#define IRQ_TWSIE 0x00040000 /* TWSI error */
+#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
+#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
+#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
+#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
+#define REG_IRQSTAT 0x30 /* IRQ status / clear */
+
+#define REG_IMGSIZE 0x34 /* Image size */
+#define IMGSZ_V_MASK 0x1fff0000
+#define IMGSZ_V_SHIFT 16
+#define IMGSZ_H_MASK 0x00003fff
+#define REG_IMGOFFSET 0x38 /* IMage offset */
+
+#define REG_CTRL0 0x3c /* Control 0 */
+#define C0_ENABLE 0x00000001 /* Makes the whole thing go */
+
+/* Mask for all the format bits */
+#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
+
+/* RGB ordering */
+#define C0_RGB4_RGBX 0x00000000
+#define C0_RGB4_XRGB 0x00000004
+#define C0_RGB4_BGRX 0x00000008
+#define C0_RGB4_XBGR 0x0000000c
+#define C0_RGB5_RGGB 0x00000000
+#define C0_RGB5_GRBG 0x00000004
+#define C0_RGB5_GBRG 0x00000008
+#define C0_RGB5_BGGR 0x0000000c
+
+/* Spec has two fields for DIN and DOUT, but they must match, so
+ combine them here. */
+#define C0_DF_YUV 0x00000000 /* Data is YUV */
+#define C0_DF_RGB 0x000000a0 /* ... RGB */
+#define C0_DF_BAYER 0x00000140 /* ... Bayer */
+/* 8-8-8 must be missing from the below - ask */
+#define C0_RGBF_565 0x00000000
+#define C0_RGBF_444 0x00000800
+#define C0_RGB_BGR 0x00001000 /* Blue comes first */
+#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
+#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
+#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
+/* Think that 420 packed must be 111 - ask */
+#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
+#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
+#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
+#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
+#define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
+#define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
+#define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
+#define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
+/* Bayer bits 18,19 if needed */
+#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
+#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
+#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
+#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
+#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
+#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
+#define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
+
+
+#define REG_CTRL1 0x40 /* Control 1 */
+#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
+#define C1_ALPHA_SHFT 20
+#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
+#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
+#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
+#define C1_DMAB_MASK 0x06000000
+#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
+#define C1_PWRDWN 0x10000000 /* Power down */
+
+#define REG_CLKCTRL 0x88 /* Clock control */
+#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
+
+#define REG_GPR 0xb4 /* General purpose register. This
+ controls inputs to the power and reset
+ pins on the OV7670 used with OLPC;
+ other deployments could differ. */
+#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
+#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
+#define GPR_C1 0x00000002 /* Control 1 value */
+/*
+ * Control 0 is wired to reset on OLPC machines. For ov7x sensors,
+ * it is active low, for 0v6x, instead, it's active high. What
+ * fun.
+ */
+#define GPR_C0 0x00000001 /* Control 0 value */
+
+#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
+#define TWSIC0_EN 0x00000001 /* TWSI enable */
+#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
+#define TWSIC0_SID 0x000003fc /* Slave ID */
+#define TWSIC0_SID_SHIFT 2
+#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
+#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
+#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
+
+#define REG_TWSIC1 0xbc /* TWSI control 1 */
+#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
+#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
+#define TWSIC1_ADDR_SHIFT 16
+#define TWSIC1_READ 0x01000000 /* Set for read op */
+#define TWSIC1_WSTAT 0x02000000 /* Write status */
+#define TWSIC1_RVALID 0x04000000 /* Read data valid */
+#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
+
+
+#define REG_UBAR 0xc4 /* Upper base address register */
+
+/*
+ * Here's the weird global control registers which are said to live
+ * way up here.
+ */
+#define REG_GL_CSR 0x3004 /* Control/status register */
+#define GCSR_SRS 0x00000001 /* SW Reset set */
+#define GCSR_SRC 0x00000002 /* SW Reset clear */
+#define GCSR_MRS 0x00000004 /* Master reset set */
+#define GCSR_MRC 0x00000008 /* HW Reset clear */
+#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
+#define REG_GL_IMASK 0x300c /* Interrupt mask register */
+#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
+
+#define REG_GL_FCR 0x3038 /* GPIO functional control register */
+#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
+#define REG_GL_GPIOR 0x315c /* GPIO register */
+#define GGPIO_OUT 0x80000 /* GPIO output */
+#define GGPIO_VAL 0x00008 /* Output pin value */
+
+#define REG_LEN REG_GL_IMASK + 4
+
+
+/*
+ * Useful stuff that probably belongs somewhere global.
+ */
+#define VGA_WIDTH 640
+#define VGA_HEIGHT 480
diff --git a/target/linux/olpc/files/drivers/media/video/cafe_ccic.c b/target/linux/olpc/files/drivers/media/video/cafe_ccic.c
new file mode 100644
index 000000000..61b4bf6b1
--- /dev/null
+++ b/target/linux/olpc/files/drivers/media/video/cafe_ccic.c
@@ -0,0 +1,2319 @@
+/*
+ * A driver for the CMOS camera controller in the Marvell 88ALP01 "cafe"
+ * multifunction chip. Currently works with the Omnivision OV7670
+ * sensor.
+ *
+ * Copyright 2006 One Laptop Per Child Association, Inc.
+ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
+ *
+ * Written by Jonathan Corbet, corbet@lwn.net.
+ *
+ * This file may be distributed under the terms of the GNU General
+ * Public License, version 2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/pci.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-chip-ident.h>
+#include <linux/device.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/debugfs.h>
+#include <linux/jiffies.h>
+#include <linux/vmalloc.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include "cafe_ccic-regs.h"
+
+#define CAFE_VERSION 0x000002
+
+
+/*
+ * Parameters.
+ */
+MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
+MODULE_DESCRIPTION("Marvell 88ALP01 CMOS Camera Controller driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("Video");
+
+/*
+ * Internal DMA buffer management. Since the controller cannot do S/G I/O,
+ * we must have physically contiguous buffers to bring frames into.
+ * These parameters control how many buffers we use, whether we
+ * allocate them at load time (better chance of success, but nails down
+ * memory) or when somebody tries to use the camera (riskier), and,
+ * for load-time allocation, how big they should be.
+ *
+ * The controller can cycle through three buffers. We could use
+ * more by flipping pointers around, but it probably makes little
+ * sense.
+ */
+
+#define MAX_DMA_BUFS 3
+static int alloc_bufs_at_read = 0;
+module_param(alloc_bufs_at_read, bool, 0444);
+MODULE_PARM_DESC(alloc_bufs_at_read,
+ "Non-zero value causes DMA buffers to be allocated when the "
+ "video capture device is read, rather than at module load "
+ "time. This saves memory, but decreases the chances of "
+ "successfully getting those buffers.");
+
+static int n_dma_bufs = 3;
+module_param(n_dma_bufs, uint, 0644);
+MODULE_PARM_DESC(n_dma_bufs,
+ "The number of DMA buffers to allocate. Can be either two "
+ "(saves memory, makes timing tighter) or three.");
+
+static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
+module_param(dma_buf_size, uint, 0444);
+MODULE_PARM_DESC(dma_buf_size,
+ "The size of the allocated DMA buffers. If actual operating "
+ "parameters require larger buffers, an attempt to reallocate "
+ "will be made.");
+
+static int min_buffers = 1;
+module_param(min_buffers, uint, 0644);
+MODULE_PARM_DESC(min_buffers,
+ "The minimum number of streaming I/O buffers we are willing "
+ "to work with.");
+
+static int max_buffers = 10;
+module_param(max_buffers, uint, 0644);
+MODULE_PARM_DESC(max_buffers,
+ "The maximum number of streaming I/O buffers an application "
+ "will be allowed to allocate. These buffers are big and live "
+ "in vmalloc space.");
+
+static int flip = 0;
+module_param(flip, bool, 0444);
+MODULE_PARM_DESC(flip,
+ "If set, the sensor will be instructed to flip the image "
+ "vertically.");
+
+
+enum cafe_state {
+ S_NOTREADY, /* Not yet initialized */
+ S_IDLE, /* Just hanging around */
+ S_FLAKED, /* Some sort of problem */
+ S_SINGLEREAD, /* In read() */
+ S_SPECREAD, /* Speculative read (for future read()) */
+ S_STREAMING /* Streaming data */
+};
+
+/*
+ * Tracking of streaming I/O buffers.
+ */
+struct cafe_sio_buffer {
+ struct list_head list;
+ struct v4l2_buffer v4lbuf;
+ char *buffer; /* Where it lives in kernel space */
+ int mapcount;
+ struct cafe_camera *cam;
+};
+
+/*
+ * A description of one of our devices.
+ * Locking: controlled by s_mutex. Certain fields, however, require
+ * the dev_lock spinlock; they are marked as such by comments.
+ * dev_lock is also required for access to device registers.
+ */
+struct cafe_camera
+{
+ enum cafe_state state;
+ unsigned long flags; /* Buffer status, mainly (dev_lock) */
+ int users; /* How many open FDs */
+ struct file *owner; /* Who has data access (v4l2) */
+
+ /*
+ * Subsystem structures.
+ */
+ struct pci_dev *pdev;
+ struct video_device v4ldev;
+ struct i2c_adapter i2c_adapter;
+ struct i2c_client *sensor;
+
+ unsigned char __iomem *regs;
+ struct list_head dev_list; /* link to other devices */
+
+ /* DMA buffers */
+ unsigned int nbufs; /* How many are alloc'd */
+ int next_buf; /* Next to consume (dev_lock) */
+ unsigned int dma_buf_size; /* allocated size */
+ void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */
+ dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
+ unsigned int specframes; /* Unconsumed spec frames (dev_lock) */
+ unsigned int sequence; /* Frame sequence number */
+ unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual buffers */
+
+ /* Streaming buffers */
+ unsigned int n_sbufs; /* How many we have */
+ struct cafe_sio_buffer *sb_bufs; /* The array of housekeeping structs */
+ struct list_head sb_avail; /* Available for data (we own) (dev_lock) */
+ struct list_head sb_full; /* With data (user space owns) (dev_lock) */
+ struct tasklet_struct s_tasklet;
+
+ /* Current operating parameters */
+ u32 sensor_type; /* Currently ov7670 only */
+ struct v4l2_pix_format pix_format;
+
+ /* Locks */
+ struct mutex s_mutex; /* Access to this structure */
+ spinlock_t dev_lock; /* Access to device */
+
+ /* Misc */
+ wait_queue_head_t smbus_wait; /* Waiting on i2c events */
+ wait_queue_head_t iowait; /* Waiting on frame data */
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ struct dentry *dfs_regs;
+ struct dentry *dfs_cam_regs;
+#endif
+};
+
+/*
+ * Status flags. Always manipulated with bit operations.
+ */
+#define CF_BUF0_VALID 0 /* Buffers valid - first three */
+#define CF_BUF1_VALID 1
+#define CF_BUF2_VALID 2
+#define CF_DMA_ACTIVE 3 /* A frame is incoming */
+#define CF_CONFIG_NEEDED 4 /* Must configure hardware */
+
+
+
+/*
+ * Start over with DMA buffers - dev_lock needed.
+ */
+static void cafe_reset_buffers(struct cafe_camera *cam)
+{
+ int i;
+
+ cam->next_buf = -1;
+ for (i = 0; i < cam->nbufs; i++)
+ clear_bit(i, &cam->flags);
+ cam->specframes = 0;
+}
+
+static inline int cafe_needs_config(struct cafe_camera *cam)
+{
+ return test_bit(CF_CONFIG_NEEDED, &cam->flags);
+}
+
+static void cafe_set_config_needed(struct cafe_camera *cam, int needed)
+{
+ if (needed)
+ set_bit(CF_CONFIG_NEEDED, &cam->flags);
+ else
+ clear_bit(CF_CONFIG_NEEDED, &cam->flags);
+}
+
+
+
+
+/*
+ * Debugging and related.
+ */
+#define cam_err(cam, fmt, arg...) \
+ dev_err(&(cam)->pdev->dev, fmt, ##arg);
+#define cam_warn(cam, fmt, arg...) \
+ dev_warn(&(cam)->pdev->dev, fmt, ##arg);
+#define cam_dbg(cam, fmt, arg...) \
+ dev_dbg(&(cam)->pdev->dev, fmt, ##arg);
+
+
+/* ---------------------------------------------------------------------*/
+/*
+ * We keep a simple list of known devices to search at open time.
+ */
+static LIST_HEAD(cafe_dev_list);
+static DEFINE_MUTEX(cafe_dev_list_lock);
+
+static void cafe_add_dev(struct cafe_camera *cam)
+{
+ mutex_lock(&cafe_dev_list_lock);
+ list_add_tail(&cam->dev_list, &cafe_dev_list);
+ mutex_unlock(&cafe_dev_list_lock);
+}
+
+static void cafe_remove_dev(struct cafe_camera *cam)
+{
+ mutex_lock(&cafe_dev_list_lock);
+ list_del(&cam->dev_list);
+ mutex_unlock(&cafe_dev_list_lock);
+}
+
+static struct cafe_camera *cafe_find_dev(int minor)
+{
+ struct cafe_camera *cam;
+
+ mutex_lock(&cafe_dev_list_lock);
+ list_for_each_entry(cam, &cafe_dev_list, dev_list) {
+ if (cam->v4ldev.minor == minor)
+ goto done;
+ }
+ cam = NULL;
+ done:
+ mutex_unlock(&cafe_dev_list_lock);
+ return cam;
+}
+
+
+static struct cafe_camera *cafe_find_by_pdev(struct pci_dev *pdev)
+{
+ struct cafe_camera *cam;
+
+ mutex_lock(&cafe_dev_list_lock);
+ list_for_each_entry(cam, &cafe_dev_list, dev_list) {
+ if (cam->pdev == pdev)
+ goto done;
+ }
+ cam = NULL;
+ done:
+ mutex_unlock(&cafe_dev_list_lock);
+ return cam;
+}
+
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Device register I/O
+ */
+static inline void cafe_reg_write(struct cafe_camera *cam, unsigned int reg,
+ unsigned int val)
+{
+ iowrite32(val, cam->regs + reg);
+}
+
+static inline unsigned int cafe_reg_read(struct cafe_camera *cam,
+ unsigned int reg)
+{
+ return ioread32(cam->regs + reg);
+}
+
+
+static inline void cafe_reg_write_mask(struct cafe_camera *cam, unsigned int reg,
+ unsigned int val, unsigned int mask)
+{
+ unsigned int v = cafe_reg_read(cam, reg);
+
+ v = (v & ~mask) | (val & mask);
+ cafe_reg_write(cam, reg, v);
+}
+
+static inline void cafe_reg_clear_bit(struct cafe_camera *cam,
+ unsigned int reg, unsigned int val)
+{
+ cafe_reg_write_mask(cam, reg, 0, val);
+}
+
+static inline void cafe_reg_set_bit(struct cafe_camera *cam,
+ unsigned int reg, unsigned int val)
+{
+ cafe_reg_write_mask(cam, reg, val, val);
+}
+
+
+
+/* -------------------------------------------------------------------- */
+/*
+ * The I2C/SMBUS interface to the camera itself starts here. The
+ * controller handles SMBUS itself, presenting a relatively simple register
+ * interface; all we have to do is to tell it where to route the data.
+ */
+#define CAFE_SMBUS_TIMEOUT (HZ) /* generous */
+
+static int cafe_smbus_write_done(struct cafe_camera *cam)
+{
+ unsigned long flags;
+ int c1;
+
+ /*
+ * We must delay after the interrupt, or the controller gets confused
+ * and never does give us good status. Fortunately, we don't do this
+ * often.
+ */
+ udelay(20);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ c1 = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return (c1 & (TWSIC1_WSTAT|TWSIC1_ERROR)) != TWSIC1_WSTAT;
+}
+
+static int cafe_smbus_write_data(struct cafe_camera *cam,
+ u16 addr, u8 command, u8 value)
+{
+ unsigned int rval;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
+ rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
+ /*
+ * Marvell sez set clkdiv to all 1's for now.
+ */
+ rval |= TWSIC0_CLKDIV;
+ cafe_reg_write(cam, REG_TWSIC0, rval);
+ (void) cafe_reg_read(cam, REG_TWSIC1); /* force write */
+ rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
+ cafe_reg_write(cam, REG_TWSIC1, rval);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ mdelay(2); /* It'll probably take about 900µs anyway, and the
+ CAFÉ is apparently quite sensitive to being poked
+ at this point. If we can work out precisely what's
+ going on and reduce this delay, it would be nice. */
+
+ wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(cam),
+ CAFE_SMBUS_TIMEOUT);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ if (rval & TWSIC1_WSTAT) {
+ cam_err(cam, "SMBUS write (%02x/%02x/%02x) timed out\n", addr,
+ command, value);
+ return -EIO;
+ }
+ if (rval & TWSIC1_ERROR) {
+ cam_err(cam, "SMBUS write (%02x/%02x/%02x) error\n", addr,
+ command, value);
+ return -EIO;
+ }
+ return 0;
+}
+
+
+
+static int cafe_smbus_read_done(struct cafe_camera *cam)
+{
+ unsigned long flags;
+ int c1;
+
+ /*
+ * We must delay after the interrupt, or the controller gets confused
+ * and never does give us good status. Fortunately, we don't do this
+ * often.
+ */
+ udelay(20);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ c1 = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return c1 & (TWSIC1_RVALID|TWSIC1_ERROR);
+}
+
+
+
+static int cafe_smbus_read_data(struct cafe_camera *cam,
+ u16 addr, u8 command, u8 *value)
+{
+ unsigned int rval;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
+ rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
+ /*
+ * Marvel sez set clkdiv to all 1's for now.
+ */
+ rval |= TWSIC0_CLKDIV;
+ cafe_reg_write(cam, REG_TWSIC0, rval);
+ (void) cafe_reg_read(cam, REG_TWSIC1); /* force write */
+ rval = TWSIC1_READ | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
+ cafe_reg_write(cam, REG_TWSIC1, rval);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ wait_event_timeout(cam->smbus_wait,
+ cafe_smbus_read_done(cam), CAFE_SMBUS_TIMEOUT);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ if (rval & TWSIC1_ERROR) {
+ cam_err(cam, "SMBUS read (%02x/%02x) error\n", addr, command);
+ return -EIO;
+ }
+ if (! (rval & TWSIC1_RVALID)) {
+ cam_err(cam, "SMBUS read (%02x/%02x) timed out\n", addr,
+ command);
+ return -EIO;
+ }
+ *value = rval & 0xff;
+ return 0;
+}
+
+/*
+ * Perform a transfer over SMBUS. This thing is called under
+ * the i2c bus lock, so we shouldn't race with ourselves...
+ */
+static int cafe_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
+ unsigned short flags, char rw, u8 command,
+ int size, union i2c_smbus_data *data)
+{
+ struct cafe_camera *cam = i2c_get_adapdata(adapter);
+ int ret = -EINVAL;
+
+ /*
+ * Refuse to talk to anything but OV cam chips. We should
+ * never even see an attempt to do so, but one never knows.
+ */
+ if (cam->sensor && addr != cam->sensor->addr) {
+ cam_err(cam, "funky smbus addr %d\n", addr);
+ return -EINVAL;
+ }
+ /*
+ * This interface would appear to only do byte data ops. OK
+ * it can do word too, but the cam chip has no use for that.
+ */
+ if (size != I2C_SMBUS_BYTE_DATA) {
+ cam_err(cam, "funky xfer size %d\n", size);
+ return -EINVAL;
+ }
+
+ if (rw == I2C_SMBUS_WRITE)
+ ret = cafe_smbus_write_data(cam, addr, command, data->byte);
+ else if (rw == I2C_SMBUS_READ)
+ ret = cafe_smbus_read_data(cam, addr, command, &data->byte);
+ return ret;
+}
+
+
+static void cafe_smbus_enable_irq(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reg_set_bit(cam, REG_IRQMASK, TWSIIRQS);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+static u32 cafe_smbus_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_SMBUS_READ_BYTE_DATA |
+ I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
+}
+
+static struct i2c_algorithm cafe_smbus_algo = {
+ .smbus_xfer = cafe_smbus_xfer,
+ .functionality = cafe_smbus_func
+};
+
+/* Somebody is on the bus */
+static int cafe_cam_init(struct cafe_camera *cam);
+static void cafe_ctlr_stop_dma(struct cafe_camera *cam);
+static void cafe_ctlr_power_down(struct cafe_camera *cam);
+
+static int cafe_smbus_attach(struct i2c_client *client)
+{
+ struct cafe_camera *cam = i2c_get_adapdata(client->adapter);
+
+ /*
+ * Don't talk to chips we don't recognize.
+ */
+ if (client->driver->id == I2C_DRIVERID_OV7670) {
+ cam->sensor = client;
+ return cafe_cam_init(cam);
+ }
+ return -EINVAL;
+}
+
+static int cafe_smbus_detach(struct i2c_client *client)
+{
+ struct cafe_camera *cam = i2c_get_adapdata(client->adapter);
+
+ if (cam->sensor == client) {
+ cafe_ctlr_stop_dma(cam);
+ cafe_ctlr_power_down(cam);
+ cam_err(cam, "lost the sensor!\n");
+ cam->sensor = NULL; /* Bummer, no camera */
+ cam->state = S_NOTREADY;
+ }
+ return 0;
+}
+
+static int cafe_smbus_setup(struct cafe_camera *cam)
+{
+ struct i2c_adapter *adap = &cam->i2c_adapter;
+ int ret;
+
+ cafe_smbus_enable_irq(cam);
+ adap->id = I2C_HW_SMBUS_CAFE;
+ adap->class = I2C_CLASS_CAM_DIGITAL;
+ adap->owner = THIS_MODULE;
+ adap->client_register = cafe_smbus_attach;
+ adap->client_unregister = cafe_smbus_detach;
+ adap->algo = &cafe_smbus_algo;
+ strcpy(adap->name, "cafe_ccic");
+ adap->dev.parent = &cam->pdev->dev;
+ i2c_set_adapdata(adap, cam);
+ ret = i2c_add_adapter(adap);
+ if (ret)
+ printk(KERN_ERR "Unable to register cafe i2c adapter\n");
+ return ret;
+}
+
+static void cafe_smbus_shutdown(struct cafe_camera *cam)
+{
+ i2c_del_adapter(&cam->i2c_adapter);
+}
+
+
+/* ------------------------------------------------------------------- */
+/*
+ * Deal with the controller.
+ */
+
+/*
+ * Do everything we think we need to have the interface operating
+ * according to the desired format.
+ */
+static void cafe_ctlr_dma(struct cafe_camera *cam)
+{
+ /*
+ * Store the first two Y buffers (we aren't supporting
+ * planar formats for now, so no UV bufs). Then either
+ * set the third if it exists, or tell the controller
+ * to just use two.
+ */
+ cafe_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]);
+ cafe_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]);
+ if (cam->nbufs > 2) {
+ cafe_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]);
+ cafe_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
+ }
+ else
+ cafe_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
+ cafe_reg_write(cam, REG_UBAR, 0); /* 32 bits only for now */
+}
+
+static void cafe_ctlr_image(struct cafe_camera *cam)
+{
+ int imgsz;
+ struct v4l2_pix_format *fmt = &cam->pix_format;
+
+ imgsz = ((fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK) |
+ (fmt->bytesperline & IMGSZ_H_MASK);
+ cafe_reg_write(cam, REG_IMGSIZE, imgsz);
+ cafe_reg_write(cam, REG_IMGOFFSET, 0);
+ /* YPITCH just drops the last two bits */
+ cafe_reg_write_mask(cam, REG_IMGPITCH, fmt->bytesperline,
+ IMGP_YP_MASK);
+ /*
+ * Tell the controller about the image format we are using.
+ */
+ switch (cam->pix_format.pixelformat) {
+ case V4L2_PIX_FMT_YUYV:
+ cafe_reg_write_mask(cam, REG_CTRL0,
+ C0_DF_YUV|C0_YUV_PACKED|C0_YUVE_YUYV,
+ C0_DF_MASK);
+ break;
+
+ case V4L2_PIX_FMT_RGB444:
+ cafe_reg_write_mask(cam, REG_CTRL0,
+ C0_DF_RGB|C0_RGBF_444|C0_RGB4_XRGB,
+ C0_DF_MASK);
+ /* Alpha value? */
+ break;
+
+ case V4L2_PIX_FMT_RGB565:
+ cafe_reg_write_mask(cam, REG_CTRL0,
+ C0_DF_RGB|C0_RGBF_565|C0_RGB5_BGGR,
+ C0_DF_MASK);
+ break;
+
+ default:
+ cam_err(cam, "Unknown format %x\n", cam->pix_format.pixelformat);
+ break;
+ }
+ /*
+ * Make sure it knows we want to use hsync/vsync.
+ */
+ cafe_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC,
+ C0_SIFM_MASK);
+}
+
+
+/*
+ * Configure the controller for operation; caller holds the
+ * device mutex.
+ */
+static int cafe_ctlr_configure(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_ctlr_dma(cam);
+ cafe_ctlr_image(cam);
+ cafe_set_config_needed(cam, 0);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return 0;
+}
+
+static void cafe_ctlr_irq_enable(struct cafe_camera *cam)
+{
+ /*
+ * Clear any pending interrupts, since we do not
+ * expect to have I/O active prior to enabling.
+ */
+ cafe_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
+ cafe_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
+}
+
+static void cafe_ctlr_irq_disable(struct cafe_camera *cam)
+{
+ cafe_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
+}
+
+/*
+ * Make the controller start grabbing images. Everything must
+ * be set up before doing this.
+ */
+static void cafe_ctlr_start(struct cafe_camera *cam)
+{
+ /* set_bit performs a read, so no other barrier should be
+ needed here */
+ cafe_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
+}
+
+static void cafe_ctlr_stop(struct cafe_camera *cam)
+{
+ cafe_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
+}
+
+static void cafe_ctlr_init(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ /*
+ * Added magic to bring up the hardware on the B-Test board
+ */
+ cafe_reg_write(cam, 0x3038, 0x8);
+ cafe_reg_write(cam, 0x315c, 0x80008);
+ /*
+ * Go through the dance needed to wake the device up.
+ * Note that these registers are global and shared
+ * with the NAND and SD devices. Interaction between the
+ * three still needs to be examined.
+ */
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_SRS|GCSR_MRS); /* Needed? */
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_SRC|GCSR_MRC);
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_SRC|GCSR_MRS);
+ /*
+ * Here we must wait a bit for the controller to come around.
+ */
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ mdelay(5); /* FIXME revisit this */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_CCIC_EN|GCSR_SRC|GCSR_MRC);
+ cafe_reg_set_bit(cam, REG_GL_IMASK, GIMSK_CCIC_EN);
+ /*
+ * Make sure it's not powered down.
+ */
+ cafe_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
+ /*
+ * Turn off the enable bit. It sure should be off anyway,
+ * but it's good to be sure.
+ */
+ cafe_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
+ /*
+ * Mask all interrupts.
+ */
+ cafe_reg_write(cam, REG_IRQMASK, 0);
+ /*
+ * Clock the sensor appropriately. Controller clock should
+ * be 48MHz, sensor "typical" value is half that.
+ */
+ cafe_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+
+/*
+ * Stop the controller, and don't return until we're really sure that no
+ * further DMA is going on.
+ */
+static void cafe_ctlr_stop_dma(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ /*
+ * Theory: stop the camera controller (whether it is operating
+ * or not). Delay briefly just in case we race with the SOF
+ * interrupt, then wait until no DMA is active.
+ */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_ctlr_stop(cam);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ mdelay(1);
+ wait_event_timeout(cam->iowait,
+ !test_bit(CF_DMA_ACTIVE, &cam->flags), HZ);
+ if (test_bit(CF_DMA_ACTIVE, &cam->flags))
+ cam_err(cam, "Timeout waiting for DMA to end\n");
+ /* This would be bad news - what now? */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cam->state = S_IDLE;
+ cafe_ctlr_irq_disable(cam);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+/*
+ * Power up and down.
+ */
+static void cafe_ctlr_power_up(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
+ /*
+ * Part one of the sensor dance: turn the global
+ * GPIO signal on.
+ */
+ cafe_reg_write(cam, REG_GL_FCR, GFCR_GPIO_ON);
+ cafe_reg_write(cam, REG_GL_GPIOR, GGPIO_OUT|GGPIO_VAL);
+ /*
+ * Put the sensor into operational mode (assumes OLPC-style
+ * wiring). Control 0 is reset - set to 1 to operate.
+ * Control 1 is power down, set to 0 to operate.
+ */
+ cafe_reg_write(cam, REG_GPR, GPR_C1EN|GPR_C0EN); /* pwr up, reset */
+// mdelay(1); /* Marvell says 1ms will do it */
+ cafe_reg_write(cam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C0);
+// mdelay(1); /* Enough? */
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ msleep(5); /* Just to be sure */
+}
+
+static void cafe_ctlr_power_down(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reg_write(cam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C1);
+ cafe_reg_write(cam, REG_GL_FCR, GFCR_GPIO_ON);
+ cafe_reg_write(cam, REG_GL_GPIOR, GGPIO_OUT);
+ cafe_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+/* -------------------------------------------------------------------- */
+/*
+ * Communications with the sensor.
+ */
+
+static int __cafe_cam_cmd(struct cafe_camera *cam, int cmd, void *arg)
+{
+ struct i2c_client *sc = cam->sensor;
+ int ret;
+
+ if (sc == NULL || sc->driver == NULL || sc->driver->command == NULL)
+ return -EINVAL;
+ ret = sc->driver->command(sc, cmd, arg);
+ if (ret == -EPERM) /* Unsupported command */
+ return 0;
+ return ret;
+}
+
+static int __cafe_cam_reset(struct cafe_camera *cam)
+{
+ int zero = 0;
+ return __cafe_cam_cmd(cam, VIDIOC_INT_RESET, &zero);
+}
+
+/*
+ * We have found the sensor on the i2c. Let's try to have a
+ * conversation.
+ */
+static int cafe_cam_init(struct cafe_camera *cam)
+{
+ struct v4l2_chip_ident chip = { V4L2_CHIP_MATCH_I2C_ADDR, 0, 0, 0 };
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ if (cam->state != S_NOTREADY)
+ cam_warn(cam, "Cam init with device in funky state %d",
+ cam->state);
+ ret = __cafe_cam_reset(cam);
+ if (ret)
+ goto out;
+ chip.match_chip = cam->sensor->addr;
+ ret = __cafe_cam_cmd(cam, VIDIOC_G_CHIP_IDENT, &chip);
+ if (ret)
+ goto out;
+ cam->sensor_type = chip.ident;
+// if (cam->sensor->addr != OV7xx0_SID) {
+ if (cam->sensor_type != V4L2_IDENT_OV7670) {
+ cam_err(cam, "Unsupported sensor type %d", cam->sensor->addr);
+ ret = -EINVAL;
+ goto out;
+ }
+/* Get/set parameters? */
+ ret = 0;
+ cam->state = S_IDLE;
+ out:
+ cafe_ctlr_power_down(cam);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+/*
+ * Configure the sensor to match the parameters we have. Caller should
+ * hold s_mutex
+ */
+static int cafe_cam_set_flip(struct cafe_camera *cam)
+{
+ struct v4l2_control ctrl;
+
+ memset(&ctrl, 0, sizeof(ctrl));
+ ctrl.id = V4L2_CID_VFLIP;
+ ctrl.value = flip;
+ return __cafe_cam_cmd(cam, VIDIOC_S_CTRL, &ctrl);
+}
+
+
+static int cafe_cam_configure(struct cafe_camera *cam)
+{
+ struct v4l2_format fmt;
+ int ret, zero = 0;
+
+ fmt.fmt.pix = cam->pix_format;
+ ret = __cafe_cam_cmd(cam, VIDIOC_INT_INIT, &zero);
+ if (ret == 0)
+ ret = __cafe_cam_cmd(cam, VIDIOC_S_FMT, &fmt);
+ /*
+ * OV7670 does weird things if flip is set *before* format...
+ */
+ ret += cafe_cam_set_flip(cam);
+ return ret;
+}
+
+/* -------------------------------------------------------------------- */
+/*
+ * DMA buffer management. These functions need s_mutex held.
+ */
+
+/* FIXME: this is inefficient as hell, since dma_alloc_coherent just
+ * does a get_free_pages() call, and we waste a good chunk of an orderN
+ * allocation. Should try to allocate the whole set in one chunk.
+ */
+static int cafe_alloc_dma_bufs(struct cafe_camera *cam, int loadtime)
+{
+ int i;
+
+ cafe_set_config_needed(cam, 1);
+ if (loadtime)
+ cam->dma_buf_size = dma_buf_size;
+ else
+ cam->dma_buf_size = cam->pix_format.sizeimage;
+ if (n_dma_bufs > 3)
+ n_dma_bufs = 3;
+
+ cam->nbufs = 0;
+ for (i = 0; i < n_dma_bufs; i++) {
+ cam->dma_bufs[i] = dma_alloc_coherent(&cam->pdev->dev,
+ cam->dma_buf_size, cam->dma_handles + i,
+ GFP_KERNEL);
+ if (cam->dma_bufs[i] == NULL) {
+ cam_warn(cam, "Failed to allocate DMA buffer\n");
+ break;
+ }
+ /* For debug, remove eventually */
+ memset(cam->dma_bufs[i], 0xcc, cam->dma_buf_size);
+ (cam->nbufs)++;
+ }
+
+ switch (cam->nbufs) {
+ case 1:
+ dma_free_coherent(&cam->pdev->dev, cam->dma_buf_size,
+ cam->dma_bufs[0], cam->dma_handles[0]);
+ cam->nbufs = 0;
+ case 0:
+ cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
+ return -ENOMEM;
+
+ case 2:
+ if (n_dma_bufs > 2)
+ cam_warn(cam, "Will limp along with only 2 buffers\n");
+ break;
+ }
+ return 0;
+}
+
+static void cafe_free_dma_bufs(struct cafe_camera *cam)
+{
+ int i;
+
+ for (i = 0; i < cam->nbufs; i++) {
+ dma_free_coherent(&cam->pdev->dev, cam->dma_buf_size,
+ cam->dma_bufs[i], cam->dma_handles[i]);
+ cam->dma_bufs[i] = NULL;
+ }
+ cam->nbufs = 0;
+}
+
+
+
+
+
+/* ----------------------------------------------------------------------- */
+/*
+ * Here starts the V4L2 interface code.
+ */
+
+/*
+ * Read an image from the device.
+ */
+static ssize_t cafe_deliver_buffer(struct cafe_camera *cam,
+ char __user *buffer, size_t len, loff_t *pos)
+{
+ int bufno;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ if (cam->next_buf < 0) {
+ cam_err(cam, "deliver_buffer: No next buffer\n");
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return -EIO;
+ }
+ bufno = cam->next_buf;
+ clear_bit(bufno, &cam->flags);
+ if (++(cam->next_buf) >= cam->nbufs)
+ cam->next_buf = 0;
+ if (! test_bit(cam->next_buf, &cam->flags))
+ cam->next_buf = -1;
+ cam->specframes = 0;
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ if (len > cam->pix_format.sizeimage)
+ len = cam->pix_format.sizeimage;
+ if (copy_to_user(buffer, cam->dma_bufs[bufno], len))
+ return -EFAULT;
+ (*pos) += len;
+ return len;
+}
+
+/*
+ * Get everything ready, and start grabbing frames.
+ */
+static int cafe_read_setup(struct cafe_camera *cam, enum cafe_state state)
+{
+ int ret;
+ unsigned long flags;
+
+ /*
+ * Configuration. If we still don't have DMA buffers,
+ * make one last, desperate attempt.
+ */
+ if (cam->nbufs == 0)
+ if (cafe_alloc_dma_bufs(cam, 0))
+ return -ENOMEM;
+
+ if (cafe_needs_config(cam)) {
+ cafe_cam_configure(cam);
+ ret = cafe_ctlr_configure(cam);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * Turn it loose.
+ */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reset_buffers(cam);
+ cafe_ctlr_irq_enable(cam);
+ cam->state = state;
+ cafe_ctlr_start(cam);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return 0;
+}
+
+
+static ssize_t cafe_v4l_read(struct file *filp,
+ char __user *buffer, size_t len, loff_t *pos)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = 0;
+
+ /*
+ * Perhaps we're in speculative read mode and already
+ * have data?
+ */
+ mutex_lock(&cam->s_mutex);
+ if (cam->state == S_SPECREAD) {
+ if (cam->next_buf >= 0) {
+ ret = cafe_deliver_buffer(cam, buffer, len, pos);
+ if (ret != 0)
+ goto out_unlock;
+ }
+ } else if (cam->state == S_FLAKED || cam->state == S_NOTREADY) {
+ ret = -EIO;
+ goto out_unlock;
+ } else if (cam->state != S_IDLE) {
+ ret = -EBUSY;
+ goto out_unlock;
+ }
+
+ /*
+ * v4l2: multiple processes can open the device, but only
+ * one gets to grab data from it.
+ */
+ if (cam->owner && cam->owner != filp) {
+ ret = -EBUSY;
+ goto out_unlock;
+ }
+ cam->owner = filp;
+
+ /*
+ * Do setup if need be.
+ */
+ if (cam->state != S_SPECREAD) {
+ ret = cafe_read_setup(cam, S_SINGLEREAD);
+ if (ret)
+ goto out_unlock;
+ }
+ /*
+ * Wait for something to happen. This should probably
+ * be interruptible (FIXME).
+ */
+ wait_event_timeout(cam->iowait, cam->next_buf >= 0, HZ);
+ if (cam->next_buf < 0) {
+ cam_err(cam, "read() operation timed out\n");
+ cafe_ctlr_stop_dma(cam);
+ ret = -EIO;
+ goto out_unlock;
+ }
+ /*
+ * Give them their data and we should be done.
+ */
+ ret = cafe_deliver_buffer(cam, buffer, len, pos);
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+
+
+
+
+
+
+/*
+ * Streaming I/O support.
+ */
+
+
+
+static int cafe_vidioc_streamon(struct file *filp, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = -EINVAL;
+
+ if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ mutex_lock(&cam->s_mutex);
+ if (cam->state != S_IDLE || cam->n_sbufs == 0)
+ goto out_unlock;
+
+ cam->sequence = 0;
+ ret = cafe_read_setup(cam, S_STREAMING);
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ out:
+ return ret;
+}
+
+
+static int cafe_vidioc_streamoff(struct file *filp, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = -EINVAL;
+
+ if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ mutex_lock(&cam->s_mutex);
+ if (cam->state != S_STREAMING)
+ goto out_unlock;
+
+ cafe_ctlr_stop_dma(cam);
+ ret = 0;
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ out:
+ return ret;
+}
+
+
+
+static int cafe_setup_siobuf(struct cafe_camera *cam, int index)
+{
+ struct cafe_sio_buffer *buf = cam->sb_bufs + index;
+
+ INIT_LIST_HEAD(&buf->list);
+ buf->v4lbuf.length = PAGE_ALIGN(cam->pix_format.sizeimage);
+ buf->buffer = vmalloc_user(buf->v4lbuf.length);
+ if (buf->buffer == NULL)
+ return -ENOMEM;
+ buf->mapcount = 0;
+ buf->cam = cam;
+
+ buf->v4lbuf.index = index;
+ buf->v4lbuf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ buf->v4lbuf.field = V4L2_FIELD_NONE;
+ buf->v4lbuf.memory = V4L2_MEMORY_MMAP;
+ /*
+ * Offset: must be 32-bit even on a 64-bit system. video-buf
+ * just uses the length times the index, but the spec warns
+ * against doing just that - vma merging problems. So we
+ * leave a gap between each pair of buffers.
+ */
+ buf->v4lbuf.m.offset = 2*index*buf->v4lbuf.length;
+ return 0;
+}
+
+static int cafe_free_sio_buffers(struct cafe_camera *cam)
+{
+ int i;
+
+ /*
+ * If any buffers are mapped, we cannot free them at all.
+ */
+ for (i = 0; i < cam->n_sbufs; i++)
+ if (cam->sb_bufs[i].mapcount > 0)
+ return -EBUSY;
+ /*
+ * OK, let's do it.
+ */
+ for (i = 0; i < cam->n_sbufs; i++)
+ vfree(cam->sb_bufs[i].buffer);
+ cam->n_sbufs = 0;
+ kfree(cam->sb_bufs);
+ cam->sb_bufs = NULL;
+ INIT_LIST_HEAD(&cam->sb_avail);
+ INIT_LIST_HEAD(&cam->sb_full);
+ return 0;
+}
+
+
+
+static int cafe_vidioc_reqbufs(struct file *filp, void *priv,
+ struct v4l2_requestbuffers *req)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = 0; /* Silence warning */
+
+ /*
+ * Make sure it's something we can do. User pointers could be
+ * implemented without great pain, but that's not been done yet.
+ */
+ if (req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ if (req->memory != V4L2_MEMORY_MMAP)
+ return -EINVAL;
+ /*
+ * If they ask for zero buffers, they really want us to stop streaming
+ * (if it's happening) and free everything. Should we check owner?
+ */
+ mutex_lock(&cam->s_mutex);
+ if (req->count == 0) {
+ if (cam->state == S_STREAMING)
+ cafe_ctlr_stop_dma(cam);
+ ret = cafe_free_sio_buffers (cam);
+ goto out;
+ }
+ /*
+ * Device needs to be idle and working. We *could* try to do the
+ * right thing in S_SPECREAD by shutting things down, but it
+ * probably doesn't matter.
+ */
+ if (cam->state != S_IDLE || (cam->owner && cam->owner != filp)) {
+ ret = -EBUSY;
+ goto out;
+ }
+ cam->owner = filp;
+
+ if (req->count < min_buffers)
+ req->count = min_buffers;
+ else if (req->count > max_buffers)
+ req->count = max_buffers;
+ if (cam->n_sbufs > 0) {
+ ret = cafe_free_sio_buffers(cam);
+ if (ret)
+ goto out;
+ }
+
+ cam->sb_bufs = kzalloc(req->count*sizeof(struct cafe_sio_buffer),
+ GFP_KERNEL);
+ if (cam->sb_bufs == NULL) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ for (cam->n_sbufs = 0; cam->n_sbufs < req->count; (cam->n_sbufs++)) {
+ ret = cafe_setup_siobuf(cam, cam->n_sbufs);
+ if (ret)
+ break;
+ }
+
+ if (cam->n_sbufs == 0) /* no luck at all - ret already set */
+ kfree(cam->sb_bufs);
+ req->count = cam->n_sbufs; /* In case of partial success */
+
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_querybuf(struct file *filp, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = -EINVAL;
+
+ mutex_lock(&cam->s_mutex);
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ if (buf->index < 0 || buf->index >= cam->n_sbufs)
+ goto out;
+ *buf = cam->sb_bufs[buf->index].v4lbuf;
+ ret = 0;
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+static int cafe_vidioc_qbuf(struct file *filp, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct cafe_camera *cam = filp->private_data;
+ struct cafe_sio_buffer *sbuf;
+ int ret = -EINVAL;
+ unsigned long flags;
+
+ mutex_lock(&cam->s_mutex);
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ if (buf->index < 0 || buf->index >= cam->n_sbufs)
+ goto out;
+ sbuf = cam->sb_bufs + buf->index;
+ if (sbuf->v4lbuf.flags & V4L2_BUF_FLAG_QUEUED) {
+ ret = 0; /* Already queued?? */
+ goto out;
+ }
+ if (sbuf->v4lbuf.flags & V4L2_BUF_FLAG_DONE) {
+ /* Spec doesn't say anything, seems appropriate tho */
+ ret = -EBUSY;
+ goto out;
+ }
+ sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_QUEUED;
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ list_add(&sbuf->list, &cam->sb_avail);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ ret = 0;
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+static int cafe_vidioc_dqbuf(struct file *filp, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct cafe_camera *cam = filp->private_data;
+ struct cafe_sio_buffer *sbuf;
+ int ret = -EINVAL;
+ unsigned long flags;
+
+ mutex_lock(&cam->s_mutex);
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out_unlock;
+ if (cam->state != S_STREAMING)
+ goto out_unlock;
+ if (list_empty(&cam->sb_full) && filp->f_flags & O_NONBLOCK) {
+ ret = -EAGAIN;
+ goto out_unlock;
+ }
+
+ while (list_empty(&cam->sb_full) && cam->state == S_STREAMING) {
+ mutex_unlock(&cam->s_mutex);
+ if (wait_event_interruptible(cam->iowait,
+ !list_empty(&cam->sb_full))) {
+ ret = -ERESTARTSYS;
+ goto out;
+ }
+ mutex_lock(&cam->s_mutex);
+ }
+
+ if (cam->state != S_STREAMING)
+ ret = -EINTR;
+ else {
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ /* Should probably recheck !list_empty() here */
+ sbuf = list_entry(cam->sb_full.next,
+ struct cafe_sio_buffer, list);
+ list_del_init(&sbuf->list);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_DONE;
+ *buf = sbuf->v4lbuf;
+ ret = 0;
+ }
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ out:
+ return ret;
+}
+
+
+
+static void cafe_v4l_vm_open(struct vm_area_struct *vma)
+{
+ struct cafe_sio_buffer *sbuf = vma->vm_private_data;
+ /*
+ * Locking: done under mmap_sem, so we don't need to
+ * go back to the camera lock here.
+ */
+ sbuf->mapcount++;
+}
+
+
+static void cafe_v4l_vm_close(struct vm_area_struct *vma)
+{
+ struct cafe_sio_buffer *sbuf = vma->vm_private_data;
+
+ mutex_lock(&sbuf->cam->s_mutex);
+ sbuf->mapcount--;
+ /* Docs say we should stop I/O too... */
+ if (sbuf->mapcount == 0)
+ sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_MAPPED;
+ mutex_unlock(&sbuf->cam->s_mutex);
+}
+
+static struct vm_operations_struct cafe_v4l_vm_ops = {
+ .open = cafe_v4l_vm_open,
+ .close = cafe_v4l_vm_close
+};
+
+
+static int cafe_v4l_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ struct cafe_camera *cam = filp->private_data;
+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+ int ret = -EINVAL;
+ int i;
+ struct cafe_sio_buffer *sbuf = NULL;
+
+ if (! (vma->vm_flags & VM_WRITE) || ! (vma->vm_flags & VM_SHARED))
+ return -EINVAL;
+ /*
+ * Find the buffer they are looking for.
+ */
+ mutex_lock(&cam->s_mutex);
+ for (i = 0; i < cam->n_sbufs; i++)
+ if (cam->sb_bufs[i].v4lbuf.m.offset == offset) {
+ sbuf = cam->sb_bufs + i;
+ break;
+ }
+ if (sbuf == NULL)
+ goto out;
+
+ ret = remap_vmalloc_range(vma, sbuf->buffer, 0);
+ if (ret)
+ goto out;
+ vma->vm_flags |= VM_DONTEXPAND;
+ vma->vm_private_data = sbuf;
+ vma->vm_ops = &cafe_v4l_vm_ops;
+ sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_MAPPED;
+ cafe_v4l_vm_open(vma);
+ ret = 0;
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+
+static int cafe_v4l_open(struct inode *inode, struct file *filp)
+{
+ struct cafe_camera *cam;
+
+ cam = cafe_find_dev(iminor(inode));
+ if (cam == NULL)
+ return -ENODEV;
+ filp->private_data = cam;
+
+ mutex_lock(&cam->s_mutex);
+ if (cam->users == 0) {
+ cafe_ctlr_power_up(cam);
+ __cafe_cam_reset(cam);
+ cafe_set_config_needed(cam, 1);
+ /* FIXME make sure this is complete */
+ }
+ (cam->users)++;
+ mutex_unlock(&cam->s_mutex);
+ return 0;
+}
+
+
+static int cafe_v4l_release(struct inode *inode, struct file *filp)
+{
+ struct cafe_camera *cam = filp->private_data;
+
+ mutex_lock(&cam->s_mutex);
+ (cam->users)--;
+ if (filp == cam->owner) {
+ cafe_ctlr_stop_dma(cam);
+ cafe_free_sio_buffers(cam);
+ cam->owner = NULL;
+ }
+ if (cam->users == 0) {
+ cafe_ctlr_power_down(cam);
+ if (alloc_bufs_at_read)
+ cafe_free_dma_bufs(cam);
+ }
+ mutex_unlock(&cam->s_mutex);
+ return 0;
+}
+
+
+
+static unsigned int cafe_v4l_poll(struct file *filp,
+ struct poll_table_struct *pt)
+{
+ struct cafe_camera *cam = filp->private_data;
+
+ poll_wait(filp, &cam->iowait, pt);
+ if (cam->next_buf >= 0)
+ return POLLIN | POLLRDNORM;
+ return 0;
+}
+
+
+
+static int cafe_vidioc_queryctrl(struct file *filp, void *priv,
+ struct v4l2_queryctrl *qc)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_QUERYCTRL, qc);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_g_ctrl(struct file *filp, void *priv,
+ struct v4l2_control *ctrl)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_G_CTRL, ctrl);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_s_ctrl(struct file *filp, void *priv,
+ struct v4l2_control *ctrl)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_S_CTRL, ctrl);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+
+
+
+static int cafe_vidioc_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strcpy(cap->driver, "cafe_ccic");
+ strcpy(cap->card, "cafe_ccic");
+ cap->version = CAFE_VERSION;
+ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
+ V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
+ return 0;
+}
+
+
+/*
+ * The default format we use until somebody says otherwise.
+ */
+static struct v4l2_pix_format cafe_def_pix_format = {
+ .width = VGA_WIDTH,
+ .height = VGA_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .field = V4L2_FIELD_NONE,
+ .bytesperline = VGA_WIDTH*2,
+ .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
+};
+
+static int cafe_vidioc_enum_fmt_cap(struct file *filp,
+ void *priv, struct v4l2_fmtdesc *fmt)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_ENUM_FMT, fmt);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_try_fmt_cap (struct file *filp, void *priv,
+ struct v4l2_format *fmt)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_TRY_FMT, fmt);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+static int cafe_vidioc_s_fmt_cap(struct file *filp, void *priv,
+ struct v4l2_format *fmt)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ /*
+ * Can't do anything if the device is not idle
+ * Also can't if there are streaming buffers in place.
+ */
+ if (cam->state != S_IDLE || cam->n_sbufs > 0)
+ return -EBUSY;
+ /*
+ * See if the formatting works in principle.
+ */
+ ret = cafe_vidioc_try_fmt_cap(filp, priv, fmt);
+ if (ret)
+ return ret;
+ /*
+ * Now we start to change things for real, so let's do it
+ * under lock.
+ */
+ mutex_lock(&cam->s_mutex);
+ cam->pix_format = fmt->fmt.pix;
+ /*
+ * Make sure we have appropriate DMA buffers.
+ */
+ ret = -ENOMEM;
+ if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
+ cafe_free_dma_bufs(cam);
+ if (cam->nbufs == 0) {
+ if (cafe_alloc_dma_bufs(cam, 0))
+ goto out;
+ }
+ /*
+ * It looks like this might work, so let's program the sensor.
+ */
+ ret = cafe_cam_configure(cam);
+ if (! ret)
+ ret = cafe_ctlr_configure(cam);
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+/*
+ * Return our stored notion of how the camera is/should be configured.
+ * The V4l2 spec wants us to be smarter, and actually get this from
+ * the camera (and not mess with it at open time). Someday.
+ */
+static int cafe_vidioc_g_fmt_cap(struct file *filp, void *priv,
+ struct v4l2_format *f)
+{
+ struct cafe_camera *cam = priv;
+
+ f->fmt.pix = cam->pix_format;
+ return 0;
+}
+
+/*
+ * We only have one input - the sensor - so minimize the nonsense here.
+ */
+static int cafe_vidioc_enum_input(struct file *filp, void *priv,
+ struct v4l2_input *input)
+{
+ if (input->index != 0)
+ return -EINVAL;
+
+ input->type = V4L2_INPUT_TYPE_CAMERA;
+ input->std = V4L2_STD_ALL; /* Not sure what should go here */
+ strcpy(input->name, "Camera");
+ return 0;
+}
+
+static int cafe_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
+{
+ *i = 0;
+ return 0;
+}
+
+static int cafe_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
+{
+ if (i != 0)
+ return -EINVAL;
+ return 0;
+}
+
+/* from vivi.c */
+static int cafe_vidioc_s_std(struct file *filp, void *priv, v4l2_std_id *a)
+{
+ return 0;
+}
+
+/*
+ * G/S_PARM. Most of this is done by the sensor, but we are
+ * the level which controls the number of read buffers.
+ */
+static int cafe_vidioc_g_parm(struct file *filp, void *priv,
+ struct v4l2_streamparm *parms)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_G_PARM, parms);
+ mutex_unlock(&cam->s_mutex);
+ parms->parm.capture.readbuffers = n_dma_bufs;
+ return ret;
+}
+
+static int cafe_vidioc_s_parm(struct file *filp, void *priv,
+ struct v4l2_streamparm *parms)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_S_PARM, parms);
+ mutex_unlock(&cam->s_mutex);
+ parms->parm.capture.readbuffers = n_dma_bufs;
+ return ret;
+}
+
+
+static void cafe_v4l_dev_release(struct video_device *vd)
+{
+ struct cafe_camera *cam = container_of(vd, struct cafe_camera, v4ldev);
+
+ kfree(cam);
+}
+
+
+/*
+ * This template device holds all of those v4l2 methods; we
+ * clone it for specific real devices.
+ */
+
+static const struct file_operations cafe_v4l_fops = {
+ .owner = THIS_MODULE,
+ .open = cafe_v4l_open,
+ .release = cafe_v4l_release,
+ .read = cafe_v4l_read,
+ .poll = cafe_v4l_poll,
+ .mmap = cafe_v4l_mmap,
+ .ioctl = video_ioctl2,
+ .llseek = no_llseek,
+};
+
+static struct video_device cafe_v4l_template = {
+ .name = "cafe",
+ .type = VFL_TYPE_GRABBER,
+ .type2 = VID_TYPE_CAPTURE,
+ .minor = -1, /* Get one dynamically */
+ .tvnorms = V4L2_STD_NTSC_M,
+ .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */
+
+ .fops = &cafe_v4l_fops,
+ .release = cafe_v4l_dev_release,
+
+ .vidioc_querycap = cafe_vidioc_querycap,
+ .vidioc_enum_fmt_cap = cafe_vidioc_enum_fmt_cap,
+ .vidioc_try_fmt_cap = cafe_vidioc_try_fmt_cap,
+ .vidioc_s_fmt_cap = cafe_vidioc_s_fmt_cap,
+ .vidioc_g_fmt_cap = cafe_vidioc_g_fmt_cap,
+ .vidioc_enum_input = cafe_vidioc_enum_input,
+ .vidioc_g_input = cafe_vidioc_g_input,
+ .vidioc_s_input = cafe_vidioc_s_input,
+ .vidioc_s_std = cafe_vidioc_s_std,
+ .vidioc_reqbufs = cafe_vidioc_reqbufs,
+ .vidioc_querybuf = cafe_vidioc_querybuf,
+ .vidioc_qbuf = cafe_vidioc_qbuf,
+ .vidioc_dqbuf = cafe_vidioc_dqbuf,
+ .vidioc_streamon = cafe_vidioc_streamon,
+ .vidioc_streamoff = cafe_vidioc_streamoff,
+ .vidioc_queryctrl = cafe_vidioc_queryctrl,
+ .vidioc_g_ctrl = cafe_vidioc_g_ctrl,
+ .vidioc_s_ctrl = cafe_vidioc_s_ctrl,
+ .vidioc_g_parm = cafe_vidioc_g_parm,
+ .vidioc_s_parm = cafe_vidioc_s_parm,
+};
+
+
+
+
+
+
+
+/* ---------------------------------------------------------------------- */
+/*
+ * Interrupt handler stuff
+ */
+
+
+
+static void cafe_frame_tasklet(unsigned long data)
+{
+ struct cafe_camera *cam = (struct cafe_camera *) data;
+ int i;
+ unsigned long flags;
+ struct cafe_sio_buffer *sbuf;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ for (i = 0; i < cam->nbufs; i++) {
+ int bufno = cam->next_buf;
+ if (bufno < 0) { /* "will never happen" */
+ cam_err(cam, "No valid bufs in tasklet!\n");
+ break;
+ }
+ if (++(cam->next_buf) >= cam->nbufs)
+ cam->next_buf = 0;
+ if (! test_bit(bufno, &cam->flags))
+ continue;
+ if (list_empty(&cam->sb_avail))
+ break; /* Leave it valid, hope for better later */
+ clear_bit(bufno, &cam->flags);
+ sbuf = list_entry(cam->sb_avail.next,
+ struct cafe_sio_buffer, list);
+ /*
+ * Drop the lock during the big copy. This *should* be safe...
+ */
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ memcpy(sbuf->buffer, cam->dma_bufs[bufno],
+ cam->pix_format.sizeimage);
+ sbuf->v4lbuf.bytesused = cam->pix_format.sizeimage;
+ sbuf->v4lbuf.sequence = cam->buf_seq[bufno];
+ sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_QUEUED;
+ sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_DONE;
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ list_move_tail(&sbuf->list, &cam->sb_full);
+ }
+ if (! list_empty(&cam->sb_full))
+ wake_up(&cam->iowait);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+
+
+static void cafe_frame_complete(struct cafe_camera *cam, int frame)
+{
+ /*
+ * Basic frame housekeeping.
+ */
+ if (test_bit(frame, &cam->flags) && printk_ratelimit())
+ cam_err(cam, "Frame overrun on %d, frames lost\n", frame);
+ set_bit(frame, &cam->flags);
+ clear_bit(CF_DMA_ACTIVE, &cam->flags);
+ if (cam->next_buf < 0)
+ cam->next_buf = frame;
+ cam->buf_seq[frame] = ++(cam->sequence);
+
+ switch (cam->state) {
+ /*
+ * If in single read mode, try going speculative.
+ */
+ case S_SINGLEREAD:
+ cam->state = S_SPECREAD;
+ cam->specframes = 0;
+ wake_up(&cam->iowait);
+ break;
+
+ /*
+ * If we are already doing speculative reads, and nobody is
+ * reading them, just stop.
+ */
+ case S_SPECREAD:
+ if (++(cam->specframes) >= cam->nbufs) {
+ cafe_ctlr_stop(cam);
+ cafe_ctlr_irq_disable(cam);
+ cam->state = S_IDLE;
+ }
+ wake_up(&cam->iowait);
+ break;
+ /*
+ * For the streaming case, we defer the real work to the
+ * camera tasklet.
+ *
+ * FIXME: if the application is not consuming the buffers,
+ * we should eventually put things on hold and restart in
+ * vidioc_dqbuf().
+ */
+ case S_STREAMING:
+ tasklet_schedule(&cam->s_tasklet);
+ break;
+
+ default:
+ cam_err(cam, "Frame interrupt in non-operational state\n");
+ break;
+ }
+}
+
+
+
+
+static void cafe_frame_irq(struct cafe_camera *cam, unsigned int irqs)
+{
+ unsigned int frame;
+
+ cafe_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
+ /*
+ * Handle any frame completions. There really should
+ * not be more than one of these, or we have fallen
+ * far behind.
+ */
+ for (frame = 0; frame < cam->nbufs; frame++)
+ if (irqs & (IRQ_EOF0 << frame))
+ cafe_frame_complete(cam, frame);
+ /*
+ * If a frame starts, note that we have DMA active. This
+ * code assumes that we won't get multiple frame interrupts
+ * at once; may want to rethink that.
+ */
+ if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2))
+ set_bit(CF_DMA_ACTIVE, &cam->flags);
+}
+
+
+
+static irqreturn_t cafe_irq(int irq, void *data)
+{
+ struct cafe_camera *cam = data;
+ unsigned int irqs;
+
+ spin_lock(&cam->dev_lock);
+ irqs = cafe_reg_read(cam, REG_IRQSTAT);
+ if ((irqs & ALLIRQS) == 0) {
+ spin_unlock(&cam->dev_lock);
+ return IRQ_NONE;
+ }
+ if (irqs & FRAMEIRQS)
+ cafe_frame_irq(cam, irqs);
+ if (irqs & TWSIIRQS) {
+ cafe_reg_write(cam, REG_IRQSTAT, TWSIIRQS);
+ wake_up(&cam->smbus_wait);
+ }
+ spin_unlock(&cam->dev_lock);
+ return IRQ_HANDLED;
+}
+
+
+/* -------------------------------------------------------------------------- */
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+/*
+ * Debugfs stuff.
+ */
+
+static char cafe_debug_buf[1024];
+static struct dentry *cafe_dfs_root;
+
+static void cafe_dfs_setup(void)
+{
+ cafe_dfs_root = debugfs_create_dir("cafe_ccic", NULL);
+ if (IS_ERR(cafe_dfs_root)) {
+ cafe_dfs_root = NULL; /* Never mind */
+ printk(KERN_NOTICE "cafe_ccic unable to set up debugfs\n");
+ }
+}
+
+static void cafe_dfs_shutdown(void)
+{
+ if (cafe_dfs_root)
+ debugfs_remove(cafe_dfs_root);
+}
+
+static int cafe_dfs_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t cafe_dfs_read_regs(struct file *file,
+ char __user *buf, size_t count, loff_t *ppos)
+{
+ struct cafe_camera *cam = file->private_data;
+ char *s = cafe_debug_buf;
+ int offset;
+
+ for (offset = 0; offset < 0x44; offset += 4)
+ s += sprintf(s, "%02x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ for (offset = 0x88; offset <= 0x90; offset += 4)
+ s += sprintf(s, "%02x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ for (offset = 0xb4; offset <= 0xbc; offset += 4)
+ s += sprintf(s, "%02x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ for (offset = 0x3000; offset <= 0x300c; offset += 4)
+ s += sprintf(s, "%04x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ return simple_read_from_buffer(buf, count, ppos, cafe_debug_buf,
+ s - cafe_debug_buf);
+}
+
+static const struct file_operations cafe_dfs_reg_ops = {
+ .owner = THIS_MODULE,
+ .read = cafe_dfs_read_regs,
+ .open = cafe_dfs_open
+};
+
+static ssize_t cafe_dfs_read_cam(struct file *file,
+ char __user *buf, size_t count, loff_t *ppos)
+{
+ struct cafe_camera *cam = file->private_data;
+ char *s = cafe_debug_buf;
+ int offset;
+
+ if (! cam->sensor)
+ return -EINVAL;
+ for (offset = 0x0; offset < 0x8a; offset++)
+ {
+ u8 v;
+
+ cafe_smbus_read_data(cam, cam->sensor->addr, offset, &v);
+ s += sprintf(s, "%02x: %02x\n", offset, v);
+ }
+ return simple_read_from_buffer(buf, count, ppos, cafe_debug_buf,
+ s - cafe_debug_buf);
+}
+
+static const struct file_operations cafe_dfs_cam_ops = {
+ .owner = THIS_MODULE,
+ .read = cafe_dfs_read_cam,
+ .open = cafe_dfs_open
+};
+
+
+
+static void cafe_dfs_cam_setup(struct cafe_camera *cam)
+{
+ char fname[40];
+
+ if (!cafe_dfs_root)
+ return;
+ sprintf(fname, "regs-%d", cam->v4ldev.minor);
+ cam->dfs_regs = debugfs_create_file(fname, 0444, cafe_dfs_root,
+ cam, &cafe_dfs_reg_ops);
+ sprintf(fname, "cam-%d", cam->v4ldev.minor);
+ cam->dfs_cam_regs = debugfs_create_file(fname, 0444, cafe_dfs_root,
+ cam, &cafe_dfs_cam_ops);
+}
+
+
+static void cafe_dfs_cam_shutdown(struct cafe_camera *cam)
+{
+ if (! IS_ERR(cam->dfs_regs))
+ debugfs_remove(cam->dfs_regs);
+ if (! IS_ERR(cam->dfs_cam_regs))
+ debugfs_remove(cam->dfs_cam_regs);
+}
+
+#else
+
+#define cafe_dfs_setup()
+#define cafe_dfs_shutdown()
+#define cafe_dfs_cam_setup(cam)
+#define cafe_dfs_cam_shutdown(cam)
+#endif /* CONFIG_VIDEO_ADV_DEBUG */
+
+
+
+
+/* ------------------------------------------------------------------------*/
+/*
+ * PCI interface stuff.
+ */
+
+static int cafe_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int ret;
+ u16 classword;
+ struct cafe_camera *cam;
+ /*
+ * Make sure we have a camera here - we'll get calls for
+ * the other cafe devices as well.
+ */
+ pci_read_config_word(pdev, PCI_CLASS_DEVICE, &classword);
+ if (classword != PCI_CLASS_MULTIMEDIA_VIDEO)
+ return -ENODEV;
+ /*
+ * Start putting together one of our big camera structures.
+ */
+ ret = -ENOMEM;
+ cam = kzalloc(sizeof(struct cafe_camera), GFP_KERNEL);
+ if (cam == NULL)
+ goto out;
+ mutex_init(&cam->s_mutex);
+ mutex_lock(&cam->s_mutex);
+ spin_lock_init(&cam->dev_lock);
+ cam->state = S_NOTREADY;
+ cafe_set_config_needed(cam, 1);
+ init_waitqueue_head(&cam->smbus_wait);
+ init_waitqueue_head(&cam->iowait);
+ cam->pdev = pdev;
+ cam->pix_format = cafe_def_pix_format;
+ INIT_LIST_HEAD(&cam->dev_list);
+ INIT_LIST_HEAD(&cam->sb_avail);
+ INIT_LIST_HEAD(&cam->sb_full);
+ tasklet_init(&cam->s_tasklet, cafe_frame_tasklet, (unsigned long) cam);
+ /*
+ * Get set up on the PCI bus.
+ */
+ ret = pci_enable_device(pdev);
+ if (ret)
+ goto out_free;
+ pci_set_master(pdev);
+
+ ret = -EIO;
+ cam->regs = pci_iomap(pdev, 0, 0);
+ if (! cam->regs) {
+ printk(KERN_ERR "Unable to ioremap cafe-ccic regs\n");
+ goto out_free;
+ }
+ ret = request_irq(pdev->irq, cafe_irq, IRQF_SHARED, "cafe-ccic", cam);
+ if (ret)
+ goto out_iounmap;
+ /*
+ * Initialize the controller and leave it powered up. It will
+ * stay that way until the sensor driver shows up.
+ */
+ cafe_ctlr_init(cam);
+ cafe_ctlr_power_up(cam);
+ /*
+ * Set up I2C/SMBUS communications. We have to drop the mutex here
+ * because the sensor could attach in this call chain, leading to
+ * unsightly deadlocks.
+ */
+ mutex_unlock(&cam->s_mutex); /* attach can deadlock */
+ ret = cafe_smbus_setup(cam);
+ if (ret)
+ goto out_freeirq;
+ /*
+ * Get the v4l2 setup done.
+ */
+ mutex_lock(&cam->s_mutex);
+ cam->v4ldev = cafe_v4l_template;
+ cam->v4ldev.debug = 0;
+// cam->v4ldev.debug = V4L2_DEBUG_IOCTL_ARG;
+ cam->v4ldev.dev = &pdev->dev;
+ ret = video_register_device(&cam->v4ldev, VFL_TYPE_GRABBER, -1);
+ if (ret)
+ goto out_smbus;
+ /*
+ * If so requested, try to get our DMA buffers now.
+ */
+ if (!alloc_bufs_at_read) {
+ if (cafe_alloc_dma_bufs(cam, 1))
+ cam_warn(cam, "Unable to alloc DMA buffers at load"
+ " will try again later.");
+ }
+
+ cafe_dfs_cam_setup(cam);
+ mutex_unlock(&cam->s_mutex);
+ cafe_add_dev(cam);
+ return 0;
+
+ out_smbus:
+ cafe_smbus_shutdown(cam);
+ out_freeirq:
+ cafe_ctlr_power_down(cam);
+ free_irq(pdev->irq, cam);
+ out_iounmap:
+ pci_iounmap(pdev, cam->regs);
+ out_free:
+ kfree(cam);
+ out:
+ return ret;
+}
+
+
+/*
+ * Shut down an initialized device
+ */
+static void cafe_shutdown(struct cafe_camera *cam)
+{
+/* FIXME: Make sure we take care of everything here */
+ cafe_dfs_cam_shutdown(cam);
+ if (cam->n_sbufs > 0)
+ /* What if they are still mapped? Shouldn't be, but... */
+ cafe_free_sio_buffers(cam);
+ cafe_remove_dev(cam);
+ cafe_ctlr_stop_dma(cam);
+ cafe_ctlr_power_down(cam);
+ cafe_smbus_shutdown(cam);
+ cafe_free_dma_bufs(cam);
+ free_irq(cam->pdev->irq, cam);
+ pci_iounmap(cam->pdev, cam->regs);
+ video_unregister_device(&cam->v4ldev);
+ /* kfree(cam); done in v4l_release () */
+}
+
+
+static void cafe_pci_remove(struct pci_dev *pdev)
+{
+ struct cafe_camera *cam = cafe_find_by_pdev(pdev);
+
+ if (cam == NULL) {
+ printk(KERN_WARNING "pci_remove on unknown pdev %p\n", pdev);
+ return;
+ }
+ mutex_lock(&cam->s_mutex);
+ if (cam->users > 0)
+ cam_warn(cam, "Removing a device with users!\n");
+ cafe_shutdown(cam);
+/* No unlock - it no longer exists */
+}
+
+
+#ifdef CONFIG_PM
+/*
+ * Basic power management.
+ */
+static int cafe_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct cafe_camera *cam = cafe_find_by_pdev(pdev);
+ int ret;
+ enum cafe_state cstate;
+
+ mutex_lock(&cam->s_mutex);
+ ret = pci_save_state(pdev);
+ if (ret) {
+ cam_warn(cam, "Unable to save PCI state\n");
+ return ret;
+ }
+ cstate = cam->state; /* HACK - stop_dma sets to idle */
+ cafe_ctlr_stop_dma(cam);
+ cafe_ctlr_power_down(cam);
+ pci_disable_device(pdev);
+ cam->state = cstate;
+ /* hold mutex until restore */
+ return 0;
+}
+
+
+static int cafe_pci_resume(struct pci_dev *pdev)
+{
+ struct cafe_camera *cam = cafe_find_by_pdev(pdev);
+ int ret = 0;
+
+ ret = pci_restore_state(pdev);
+ if (ret)
+ return ret;
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ cam_warn(cam, "Unable to re-enable device on resume!\n");
+ return ret;
+ }
+ /* we're still holding mutex from suspend */
+ cafe_ctlr_init(cam);
+
+ if (cam->users > 0) {
+ cafe_ctlr_power_up(cam);
+ __cafe_cam_reset(cam);
+ }
+ else
+ cafe_ctlr_power_down(cam);
+ mutex_unlock(&cam->s_mutex);
+
+ set_bit(CF_CONFIG_NEEDED, &cam->flags);
+ if (cam->state == S_SPECREAD)
+ cam->state = S_IDLE; /* Don't bother restarting */
+ else if (cam->state == S_SINGLEREAD || cam->state == S_STREAMING)
+ ret = cafe_read_setup(cam, cam->state);
+ return ret;
+}
+
+#endif /* CONFIG_PM */
+
+
+static struct pci_device_id cafe_ids[] = {
+ { PCI_DEVICE(0x11ab, 0x4100) }, /* Eventual real ID */
+ { PCI_DEVICE(0x11ab, 0x4102) }, /* Really eventual real ID */
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, cafe_ids);
+
+static struct pci_driver cafe_pci_driver = {
+ .name = "cafe1000-ccic",
+ .id_table = cafe_ids,
+ .probe = cafe_pci_probe,
+ .remove = cafe_pci_remove,
+#ifdef CONFIG_PM
+ .suspend = cafe_pci_suspend,
+ .resume = cafe_pci_resume,
+#endif
+};
+
+
+
+
+static int __init cafe_init(void)
+{
+ int ret;
+
+ printk(KERN_NOTICE "Marvell M88ALP01 'CAFE' Camera Controller version %d\n",
+ CAFE_VERSION);
+ cafe_dfs_setup();
+ ret = pci_register_driver(&cafe_pci_driver);
+ if (ret) {
+ printk(KERN_ERR "Unable to register cafe_ccic driver\n");
+ goto out;
+ }
+ request_module("ov7670"); /* FIXME want something more general */
+ ret = 0;
+
+ out:
+ return ret;
+}
+
+
+static void __exit cafe_exit(void)
+{
+ pci_unregister_driver(&cafe_pci_driver);
+ cafe_dfs_shutdown();
+}
+
+module_init(cafe_init);
+module_exit(cafe_exit);
diff --git a/target/linux/olpc/files/drivers/mtd/mtdcore.h b/target/linux/olpc/files/drivers/mtd/mtdcore.h
new file mode 100644
index 000000000..a33251f4b
--- /dev/null
+++ b/target/linux/olpc/files/drivers/mtd/mtdcore.h
@@ -0,0 +1,11 @@
+/* linux/drivers/mtd/mtdcore.h
+ *
+ * Header file for driver private mtdcore exports
+ *
+ */
+
+/* These are exported solely for the purpose of mtd_blkdevs.c. You
+ should not use them for _anything_ else */
+
+extern struct mutex mtd_table_mutex;
+extern struct mtd_info *mtd_table[MAX_MTD_DEVICES];
diff --git a/target/linux/olpc/files/drivers/mtd/mtdoops.c b/target/linux/olpc/files/drivers/mtd/mtdoops.c
new file mode 100644
index 000000000..cfc28ab4a
--- /dev/null
+++ b/target/linux/olpc/files/drivers/mtd/mtdoops.c
@@ -0,0 +1,365 @@
+/*
+ * MTD Oops/Panic logger
+ *
+ * Copyright (C) 2007 Nokia Corporation. All rights reserved.
+ *
+ * Author: Richard Purdie <rpurdie@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/mtd/mtd.h>
+
+#define OOPS_PAGE_SIZE 4096
+
+static struct mtdoops_context {
+ int mtd_index;
+ struct work_struct work;
+ struct mtd_info *mtd;
+ int oops_pages;
+ int nextpage;
+ int nextcount;
+
+ void *oops_buf;
+ int ready;
+ int writecount;
+} oops_cxt;
+
+static void mtdoops_erase_callback(struct erase_info *done)
+{
+ wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
+ wake_up(wait_q);
+}
+
+static int mtdoops_erase_block(struct mtd_info *mtd, int offset)
+{
+ struct erase_info erase;
+ DECLARE_WAITQUEUE(wait, current);
+ wait_queue_head_t wait_q;
+ int ret;
+
+ init_waitqueue_head(&wait_q);
+ erase.mtd = mtd;
+ erase.callback = mtdoops_erase_callback;
+ erase.addr = offset;
+ if (mtd->erasesize < OOPS_PAGE_SIZE)
+ erase.len = OOPS_PAGE_SIZE;
+ else
+ erase.len = mtd->erasesize;
+ erase.priv = (u_long)&wait_q;
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ add_wait_queue(&wait_q, &wait);
+
+ ret = mtd->erase(mtd, &erase);
+ if (ret) {
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&wait_q, &wait);
+ printk (KERN_WARNING "mtdoops: erase of region [0x%x, 0x%x] "
+ "on \"%s\" failed\n",
+ erase.addr, erase.len, mtd->name);
+ return ret;
+ }
+
+ schedule(); /* Wait for erase to finish. */
+ remove_wait_queue(&wait_q, &wait);
+
+ return 0;
+}
+
+static int mtdoops_inc_counter(struct mtdoops_context *cxt)
+{
+ struct mtd_info *mtd = cxt->mtd;
+ size_t retlen;
+ u32 count;
+ int ret;
+
+ cxt->nextpage++;
+ if (cxt->nextpage > cxt->oops_pages)
+ cxt->nextpage = 0;
+ cxt->nextcount++;
+ if (cxt->nextcount == 0xffffffff)
+ cxt->nextcount = 0;
+
+ ret = mtd->read(mtd, cxt->nextpage * OOPS_PAGE_SIZE, 4,
+ &retlen, (u_char *) &count);
+ if ((retlen != 4) || (ret < 0)) {
+ printk(KERN_ERR "mtdoops: Read failure at %d (%d of 4 read)"
+ ", err %d.\n", cxt->nextpage * OOPS_PAGE_SIZE,
+ retlen, ret);
+ return 1;
+ }
+
+ /* See if we need to erase the next block */
+ if (count != 0xffffffff)
+ return 1;
+
+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (no erase)\n",
+ cxt->nextpage, cxt->nextcount);
+ cxt->ready = 1;
+ return 0;
+}
+
+static void mtdoops_prepare(struct mtdoops_context *cxt)
+{
+ struct mtd_info *mtd = cxt->mtd;
+ int i = 0, j, ret, mod;
+
+ /* We were unregistered */
+ if (!mtd)
+ return;
+
+ mod = (cxt->nextpage * OOPS_PAGE_SIZE) % mtd->erasesize;
+ if (mod != 0) {
+ cxt->nextpage = cxt->nextpage + ((mtd->erasesize - mod) / OOPS_PAGE_SIZE);
+ if (cxt->nextpage > cxt->oops_pages)
+ cxt->nextpage = 0;
+ }
+
+ while (mtd->block_isbad &&
+ mtd->block_isbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE)) {
+badblock:
+ printk(KERN_WARNING "mtdoops: Bad block at %08x\n",
+ cxt->nextpage * OOPS_PAGE_SIZE);
+ i++;
+ cxt->nextpage = cxt->nextpage + (mtd->erasesize / OOPS_PAGE_SIZE);
+ if (cxt->nextpage > cxt->oops_pages)
+ cxt->nextpage = 0;
+ if (i == (cxt->oops_pages / (mtd->erasesize / OOPS_PAGE_SIZE))) {
+ printk(KERN_ERR "mtdoops: All blocks bad!\n");
+ return;
+ }
+ }
+
+ for (j = 0, ret = -1; (j < 3) && (ret < 0); j++)
+ ret = mtdoops_erase_block(mtd, cxt->nextpage * OOPS_PAGE_SIZE);
+
+ if (ret < 0) {
+ if (mtd->block_markbad)
+ mtd->block_markbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE);
+ goto badblock;
+ }
+
+ printk(KERN_DEBUG "mtdoops: Ready %d, %d \n", cxt->nextpage, cxt->nextcount);
+
+ cxt->ready = 1;
+}
+
+static void mtdoops_workfunc(struct work_struct *work)
+{
+ struct mtdoops_context *cxt =
+ container_of(work, struct mtdoops_context, work);
+
+ mtdoops_prepare(cxt);
+}
+
+static int find_next_position(struct mtdoops_context *cxt)
+{
+ struct mtd_info *mtd = cxt->mtd;
+ int page, maxpos = 0;
+ u32 count, maxcount = 0xffffffff;
+ size_t retlen;
+
+ for (page = 0; page < cxt->oops_pages; page++) {
+ mtd->read(mtd, page * OOPS_PAGE_SIZE, 4, &retlen, (u_char *) &count);
+ if (count == 0xffffffff)
+ continue;
+ if (maxcount == 0xffffffff) {
+ maxcount = count;
+ maxpos = page;
+ } else if ((count < 0x40000000) && (maxcount > 0xc0000000)) {
+ maxcount = count;
+ maxpos = page;
+ } else if ((count > maxcount) && (count < 0xc0000000)) {
+ maxcount = count;
+ maxpos = page;
+ } else if ((count > maxcount) && (count > 0xc0000000)
+ && (maxcount > 0x80000000)) {
+ maxcount = count;
+ maxpos = page;
+ }
+ }
+ if (maxcount == 0xffffffff) {
+ cxt->nextpage = 0;
+ cxt->nextcount = 1;
+ cxt->ready = 1;
+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (first init)\n",
+ cxt->nextpage, cxt->nextcount);
+ return 0;
+ }
+
+ cxt->nextpage = maxpos;
+ cxt->nextcount = maxcount;
+
+ return mtdoops_inc_counter(cxt);
+}
+
+
+static void mtdoops_notify_add(struct mtd_info *mtd)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+ int ret;
+
+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0)
+ return;
+
+ if (mtd->size < (mtd->erasesize * 2)) {
+ printk(KERN_ERR "MTD partition %d not big enough for mtdoops\n",
+ mtd->index);
+ return;
+ }
+
+ cxt->mtd = mtd;
+ cxt->oops_pages = mtd->size / OOPS_PAGE_SIZE;
+
+ ret = find_next_position(cxt);
+ if (ret == 1)
+ mtdoops_prepare(cxt);
+
+ printk(KERN_DEBUG "mtdoops: Attached to MTD device %d\n", mtd->index);
+}
+
+static void mtdoops_notify_remove(struct mtd_info *mtd)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+
+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0)
+ return;
+
+ cxt->mtd = NULL;
+ flush_scheduled_work();
+}
+
+
+static void
+mtdoops_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct mtdoops_context *cxt = co->data;
+ struct mtd_info *mtd = cxt->mtd;
+ int i, ret;
+
+ if (!cxt->ready || !mtd)
+ return;
+
+ if (!oops_in_progress && cxt->writecount != 0) {
+ size_t retlen;
+ if (cxt->writecount < OOPS_PAGE_SIZE)
+ memset(cxt->oops_buf + cxt->writecount, 0xff,
+ OOPS_PAGE_SIZE - cxt->writecount);
+
+ ret = mtd->write(mtd, cxt->nextpage * OOPS_PAGE_SIZE,
+ OOPS_PAGE_SIZE, &retlen, cxt->oops_buf);
+ cxt->ready = 0;
+ cxt->writecount = 0;
+
+ if ((retlen != OOPS_PAGE_SIZE) || (ret < 0))
+ printk(KERN_ERR "mtdoops: Write failure at %d (%d of %d"
+ " written), err %d.\n",
+ cxt->nextpage * OOPS_PAGE_SIZE, retlen,
+ OOPS_PAGE_SIZE, ret);
+
+ ret = mtdoops_inc_counter(cxt);
+ if (ret == 1)
+ schedule_work(&cxt->work);
+ }
+
+ if (!oops_in_progress)
+ return;
+
+ if (cxt->writecount == 0) {
+ u32 *stamp = cxt->oops_buf;
+ *stamp = cxt->nextcount;
+ cxt->writecount = 4;
+ }
+
+ if ((count + cxt->writecount) > OOPS_PAGE_SIZE)
+ count = OOPS_PAGE_SIZE - cxt->writecount;
+
+ for (i = 0; i < count; i++, s++)
+ *((char *)(cxt->oops_buf) + cxt->writecount + i) = *s;
+
+ cxt->writecount = cxt->writecount + count;
+}
+
+static int __init mtdoops_console_setup(struct console *co, char *options)
+{
+ struct mtdoops_context *cxt = co->data;
+
+ if (cxt->mtd_index != -1)
+ return -EBUSY;
+ if (co->index == -1)
+ return -EINVAL;
+
+ cxt->mtd_index = co->index;
+ return 0;
+}
+
+static struct mtd_notifier mtdoops_notifier = {
+ .add = mtdoops_notify_add,
+ .remove = mtdoops_notify_remove,
+};
+
+static struct console mtdoops_console = {
+ .name = "ttyMTD",
+ .write = mtdoops_console_write,
+ .setup = mtdoops_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &oops_cxt,
+};
+
+static int __init mtdoops_console_init(void)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+
+ cxt->mtd_index = -1;
+ cxt->oops_buf = vmalloc(OOPS_PAGE_SIZE);
+
+ if (!cxt->oops_buf) {
+ printk(KERN_ERR "Failed to allocate oops buffer workspace\n");
+ return -ENOMEM;
+ }
+
+ INIT_WORK(&cxt->work, mtdoops_workfunc);
+
+ register_console(&mtdoops_console);
+ register_mtd_user(&mtdoops_notifier);
+ return 0;
+}
+
+static void __exit mtdoops_console_exit(void)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+
+ unregister_mtd_user(&mtdoops_notifier);
+ unregister_console(&mtdoops_console);
+ vfree(cxt->oops_buf);
+}
+
+
+subsys_initcall(mtdoops_console_init);
+module_exit(mtdoops_console_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Richard Purdie <rpurdie@openedhand.com>");
+MODULE_DESCRIPTION("MTD Oops/Panic console logger/driver");
diff --git a/target/linux/olpc/files/drivers/mtd/onenand/onenand_sim.c b/target/linux/olpc/files/drivers/mtd/onenand/onenand_sim.c
new file mode 100644
index 000000000..b80667309
--- /dev/null
+++ b/target/linux/olpc/files/drivers/mtd/onenand/onenand_sim.c
@@ -0,0 +1,495 @@
+/*
+ * linux/drivers/mtd/onenand/onenand_sim.c
+ *
+ * The OneNAND simulator
+ *
+ * Copyright © 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
+
+#include <linux/io.h>
+
+#ifndef CONFIG_ONENAND_SIM_MANUFACTURER
+#define CONFIG_ONENAND_SIM_MANUFACTURER 0xec
+#endif
+#ifndef CONFIG_ONENAND_SIM_DEVICE_ID
+#define CONFIG_ONENAND_SIM_DEVICE_ID 0x04
+#endif
+#ifndef CONFIG_ONENAND_SIM_VERSION_ID
+#define CONFIG_ONENAND_SIM_VERSION_ID 0x1e
+#endif
+
+static int manuf_id = CONFIG_ONENAND_SIM_MANUFACTURER;
+static int device_id = CONFIG_ONENAND_SIM_DEVICE_ID;
+static int version_id = CONFIG_ONENAND_SIM_VERSION_ID;
+
+struct onenand_flash {
+ void __iomem *base;
+ void __iomem *data;
+};
+
+#define ONENAND_CORE(flash) (flash->data)
+#define ONENAND_CORE_SPARE(flash, this, offset) \
+ ((flash->data) + (this->chipsize) + (offset >> 5))
+
+#define ONENAND_MAIN_AREA(this, offset) \
+ (this->base + ONENAND_DATARAM + offset)
+
+#define ONENAND_SPARE_AREA(this, offset) \
+ (this->base + ONENAND_SPARERAM + offset)
+
+#define ONENAND_GET_WP_STATUS(this) \
+ (readw(this->base + ONENAND_REG_WP_STATUS))
+
+#define ONENAND_SET_WP_STATUS(v, this) \
+ (writew(v, this->base + ONENAND_REG_WP_STATUS))
+
+/* It has all 0xff chars */
+#define MAX_ONENAND_PAGESIZE (2048 + 64)
+static unsigned char *ffchars;
+
+static struct mtd_partition os_partitions[] = {
+ {
+ .name = "OneNAND simulator partition",
+ .offset = 0,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+/*
+ * OneNAND simulator mtd
+ */
+struct onenand_info {
+ struct mtd_info mtd;
+ struct mtd_partition *parts;
+ struct onenand_chip onenand;
+ struct onenand_flash flash;
+};
+
+struct onenand_info *info;
+
+#define DPRINTK(format, args...) \
+do { \
+ printk(KERN_DEBUG "%s[%d]: " format "\n", __func__, \
+ __LINE__, ##args); \
+} while (0)
+
+/**
+ * onenand_lock_handle - Handle Lock scheme
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Send lock command to OneNAND device.
+ * The lock scheme is depends on chip type.
+ */
+static void onenand_lock_handle(struct onenand_chip *this, int cmd)
+{
+ int block_lock_scheme;
+ int status;
+
+ status = ONENAND_GET_WP_STATUS(this);
+ block_lock_scheme = !(this->options & ONENAND_HAS_CONT_LOCK);
+
+ switch (cmd) {
+ case ONENAND_CMD_UNLOCK:
+ if (block_lock_scheme)
+ ONENAND_SET_WP_STATUS(ONENAND_WP_US, this);
+ else
+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_US, this);
+ break;
+
+ case ONENAND_CMD_LOCK:
+ if (block_lock_scheme)
+ ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this);
+ else
+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LS, this);
+ break;
+
+ case ONENAND_CMD_LOCK_TIGHT:
+ if (block_lock_scheme)
+ ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this);
+ else
+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LTS, this);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * onenand_bootram_handle - Handle BootRAM area
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Emulate BootRAM area. It is possible to do basic operation using BootRAM.
+ */
+static void onenand_bootram_handle(struct onenand_chip *this, int cmd)
+{
+ switch (cmd) {
+ case ONENAND_CMD_READID:
+ writew(manuf_id, this->base);
+ writew(device_id, this->base + 2);
+ writew(version_id, this->base + 4);
+ break;
+
+ default:
+ /* REVIST: Handle other commands */
+ break;
+ }
+}
+
+/**
+ * onenand_update_interrupt - Set interrupt register
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Update interrupt register. The status is depends on command.
+ */
+static void onenand_update_interrupt(struct onenand_chip *this, int cmd)
+{
+ int interrupt = ONENAND_INT_MASTER;
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ case ONENAND_CMD_READOOB:
+ interrupt |= ONENAND_INT_READ;
+ break;
+
+ case ONENAND_CMD_PROG:
+ case ONENAND_CMD_PROGOOB:
+ interrupt |= ONENAND_INT_WRITE;
+ break;
+
+ case ONENAND_CMD_ERASE:
+ interrupt |= ONENAND_INT_ERASE;
+ break;
+
+ case ONENAND_CMD_RESET:
+ interrupt |= ONENAND_INT_RESET;
+ break;
+
+ default:
+ break;
+ }
+
+ writew(interrupt, this->base + ONENAND_REG_INTERRUPT);
+}
+
+/**
+ * onenand_check_overwrite - Check over-write if happend
+ * @param dest The destination pointer
+ * @param src The source pointer
+ * @param count The length to be check
+ * @return 0 on same, otherwise 1
+ *
+ * Compare the source with destination
+ */
+static int onenand_check_overwrite(void *dest, void *src, size_t count)
+{
+ unsigned int *s = (unsigned int *) src;
+ unsigned int *d = (unsigned int *) dest;
+ int i;
+
+ count >>= 2;
+ for (i = 0; i < count; i++)
+ if ((*s++ ^ *d++) != 0)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * onenand_data_handle - Handle OneNAND Core and DataRAM
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ * @param dataram Which dataram used
+ * @param offset The offset to OneNAND Core
+ *
+ * Copy data from OneNAND Core to DataRAM (read)
+ * Copy data from DataRAM to OneNAND Core (write)
+ * Erase the OneNAND Core (erase)
+ */
+static void onenand_data_handle(struct onenand_chip *this, int cmd,
+ int dataram, unsigned int offset)
+{
+ struct mtd_info *mtd = &info->mtd;
+ struct onenand_flash *flash = this->priv;
+ int main_offset, spare_offset;
+ void __iomem *src;
+ void __iomem *dest;
+ unsigned int i;
+
+ if (dataram) {
+ main_offset = mtd->writesize;
+ spare_offset = mtd->oobsize;
+ } else {
+ main_offset = 0;
+ spare_offset = 0;
+ }
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ src = ONENAND_CORE(flash) + offset;
+ dest = ONENAND_MAIN_AREA(this, main_offset);
+ memcpy(dest, src, mtd->writesize);
+ /* Fall through */
+
+ case ONENAND_CMD_READOOB:
+ src = ONENAND_CORE_SPARE(flash, this, offset);
+ dest = ONENAND_SPARE_AREA(this, spare_offset);
+ memcpy(dest, src, mtd->oobsize);
+ break;
+
+ case ONENAND_CMD_PROG:
+ src = ONENAND_MAIN_AREA(this, main_offset);
+ dest = ONENAND_CORE(flash) + offset;
+ /* To handle partial write */
+ for (i = 0; i < (1 << mtd->subpage_sft); i++) {
+ int off = i * this->subpagesize;
+ if (!memcmp(src + off, ffchars, this->subpagesize))
+ continue;
+ if (memcmp(dest + off, ffchars, this->subpagesize) &&
+ onenand_check_overwrite(dest + off, src + off, this->subpagesize))
+ printk(KERN_ERR "over-write happend at 0x%08x\n", offset);
+ memcpy(dest + off, src + off, this->subpagesize);
+ }
+ /* Fall through */
+
+ case ONENAND_CMD_PROGOOB:
+ src = ONENAND_SPARE_AREA(this, spare_offset);
+ /* Check all data is 0xff chars */
+ if (!memcmp(src, ffchars, mtd->oobsize))
+ break;
+
+ dest = ONENAND_CORE_SPARE(flash, this, offset);
+ if (memcmp(dest, ffchars, mtd->oobsize) &&
+ onenand_check_overwrite(dest, src, mtd->oobsize))
+ printk(KERN_ERR "OOB: over-write happend at 0x%08x\n",
+ offset);
+ memcpy(dest, src, mtd->oobsize);
+ break;
+
+ case ONENAND_CMD_ERASE:
+ memset(ONENAND_CORE(flash) + offset, 0xff, mtd->erasesize);
+ memset(ONENAND_CORE_SPARE(flash, this, offset), 0xff,
+ (mtd->erasesize >> 5));
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * onenand_command_handle - Handle command
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Emulate OneNAND command.
+ */
+static void onenand_command_handle(struct onenand_chip *this, int cmd)
+{
+ unsigned long offset = 0;
+ int block = -1, page = -1, bufferram = -1;
+ int dataram = 0;
+
+ switch (cmd) {
+ case ONENAND_CMD_UNLOCK:
+ case ONENAND_CMD_LOCK:
+ case ONENAND_CMD_LOCK_TIGHT:
+ case ONENAND_CMD_UNLOCK_ALL:
+ onenand_lock_handle(this, cmd);
+ break;
+
+ case ONENAND_CMD_BUFFERRAM:
+ /* Do nothing */
+ return;
+
+ default:
+ block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1);
+ if (block & (1 << ONENAND_DDP_SHIFT)) {
+ block &= ~(1 << ONENAND_DDP_SHIFT);
+ /* The half of chip block */
+ block += this->chipsize >> (this->erase_shift + 1);
+ }
+ if (cmd == ONENAND_CMD_ERASE)
+ break;
+
+ page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
+ page = (page >> ONENAND_FPA_SHIFT);
+ bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER);
+ bufferram >>= ONENAND_BSA_SHIFT;
+ bufferram &= ONENAND_BSA_DATARAM1;
+ dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0;
+ break;
+ }
+
+ if (block != -1)
+ offset += block << this->erase_shift;
+
+ if (page != -1)
+ offset += page << this->page_shift;
+
+ onenand_data_handle(this, cmd, dataram, offset);
+
+ onenand_update_interrupt(this, cmd);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Emulate write operation
+ * @param value value to write
+ * @param addr address to write
+ *
+ * Write OneNAND register with value
+ */
+static void onenand_writew(unsigned short value, void __iomem * addr)
+{
+ struct onenand_chip *this = info->mtd.priv;
+
+ /* BootRAM handling */
+ if (addr < this->base + ONENAND_DATARAM) {
+ onenand_bootram_handle(this, value);
+ return;
+ }
+ /* Command handling */
+ if (addr == this->base + ONENAND_REG_COMMAND)
+ onenand_command_handle(this, value);
+
+ writew(value, addr);
+}
+
+/**
+ * flash_init - Initialize OneNAND simulator
+ * @param flash OneNAND simulaotr data strucutres
+ *
+ * Initialize OneNAND simulator.
+ */
+static int __init flash_init(struct onenand_flash *flash)
+{
+ int density, size;
+ int buffer_size;
+
+ flash->base = kzalloc(131072, GFP_KERNEL);
+ if (!flash->base) {
+ printk(KERN_ERR "Unable to allocate base address.\n");
+ return -ENOMEM;
+ }
+
+ density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+ size = ((16 << 20) << density);
+
+ ONENAND_CORE(flash) = vmalloc(size + (size >> 5));
+ if (!ONENAND_CORE(flash)) {
+ printk(KERN_ERR "Unable to allocate nand core address.\n");
+ kfree(flash->base);
+ return -ENOMEM;
+ }
+
+ memset(ONENAND_CORE(flash), 0xff, size + (size >> 5));
+
+ /* Setup registers */
+ writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID);
+ writew(device_id, flash->base + ONENAND_REG_DEVICE_ID);
+ writew(version_id, flash->base + ONENAND_REG_VERSION_ID);
+
+ if (density < 2)
+ buffer_size = 0x0400; /* 1KiB page */
+ else
+ buffer_size = 0x0800; /* 2KiB page */
+ writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE);
+
+ return 0;
+}
+
+/**
+ * flash_exit - Clean up OneNAND simulator
+ * @param flash OneNAND simulaotr data strucutres
+ *
+ * Clean up OneNAND simulator.
+ */
+static void flash_exit(struct onenand_flash *flash)
+{
+ vfree(ONENAND_CORE(flash));
+ kfree(flash->base);
+ kfree(flash);
+}
+
+static int __init onenand_sim_init(void)
+{
+ /* Allocate all 0xff chars pointer */
+ ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL);
+ if (!ffchars) {
+ printk(KERN_ERR "Unable to allocate ff chars.\n");
+ return -ENOMEM;
+ }
+ memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE);
+
+ /* Allocate OneNAND simulator mtd pointer */
+ info = kzalloc(sizeof(struct onenand_info), GFP_KERNEL);
+ if (!info) {
+ printk(KERN_ERR "Unable to allocate core structures.\n");
+ kfree(ffchars);
+ return -ENOMEM;
+ }
+
+ /* Override write_word function */
+ info->onenand.write_word = onenand_writew;
+
+ if (flash_init(&info->flash)) {
+ printk(KERN_ERR "Unable to allocat flash.\n");
+ kfree(ffchars);
+ kfree(info);
+ return -ENOMEM;
+ }
+
+ info->parts = os_partitions;
+
+ info->onenand.base = info->flash.base;
+ info->onenand.priv = &info->flash;
+
+ info->mtd.name = "OneNAND simulator";
+ info->mtd.priv = &info->onenand;
+ info->mtd.owner = THIS_MODULE;
+
+ if (onenand_scan(&info->mtd, 1)) {
+ flash_exit(&info->flash);
+ kfree(ffchars);
+ kfree(info);
+ return -ENXIO;
+ }
+
+ add_mtd_partitions(&info->mtd, info->parts, ARRAY_SIZE(os_partitions));
+
+ return 0;
+}
+
+static void __exit onenand_sim_exit(void)
+{
+ struct onenand_chip *this = info->mtd.priv;
+ struct onenand_flash *flash = this->priv;
+
+ onenand_release(&info->mtd);
+ flash_exit(flash);
+ kfree(ffchars);
+ kfree(info);
+}
+
+module_init(onenand_sim_init);
+module_exit(onenand_sim_exit);
+
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("The OneNAND flash simulator");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/olpc/files/drivers/video/geode/geode_regs.h b/target/linux/olpc/files/drivers/video/geode/geode_regs.h
new file mode 100644
index 000000000..9e75505a8
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/geode/geode_regs.h
@@ -0,0 +1,242 @@
+/* This header file defines the registers and suspend/resume
+ structures for the Geode GX and LX. The lxfb driver defines
+ _GEODELX_ before including this file, which will unlock the
+ extra registers that are only valid for LX.
+*/
+
+#ifndef _GEODE_REGS_H_
+#define _GEODE_REGS_H_
+
+/* MSRs */
+
+#define GX_VP_MSR_PAD_SELECT 0xC0002011
+#define LX_VP_MSR_PAD_SELECT 0x48000011
+
+#define GEODE_MSR_GLCP_DOTPLL 0x4c000015
+
+#define GLCP_DOTPLL_RESET (1 << 0)
+#define GLCP_DOTPLL_BYPASS (1 << 15)
+#define GLCP_DOTPLL_HALFPIX (1 << 24)
+#define GLCP_DOTPLL_LOCK (1 << 25)
+
+/* Registers */
+#define VP_FP_START 0x400
+
+
+#ifdef _GEODELX_
+
+#define GP_REG_SIZE 0x7C
+#define DC_REG_SIZE 0xF0
+#define VP_REG_SIZE 0x158
+#define FP_REG_SIZE 0x70
+
+#else
+
+#define GP_REG_SIZE 0x50
+#define DC_REG_SIZE 0x90
+#define VP_REG_SIZE 0x138
+#define FP_REG_SIZE 0x70
+
+#endif
+
+#define DC_PAL_SIZE 0x105
+
+struct geoderegs {
+
+ struct {
+ u64 padsel;
+ u64 dotpll;
+
+#ifdef _GEODELX_
+ u64 dfglcfg;
+ u64 dcspare;
+#else
+ u64 rstpll;
+#endif
+ } msr;
+
+ union {
+ unsigned char b[GP_REG_SIZE];
+ struct {
+ u32 dst_offset; /* 0x00 */
+ u32 src_offset; /* 0x04 */
+ u32 stride; /* 0x08 */
+ u32 wid_height; /* 0x0C */
+ u32 src_color_fg; /* 0x10 */
+ u32 src_color_bg; /* 0x14 */
+ u32 pat_color_0; /* 0x18 */
+ u32 pat_color_1; /* 0x1C */
+ u32 pat_color_2; /* 0x20 */
+ u32 pat_color_3; /* 0x24 */
+ u32 pat_color_4; /* 0x28 */
+ u32 pat_color_5; /* 0x2C */
+ u32 pat_data_0; /* 0x30 */
+ u32 pat_data_1; /* 0x34 */
+ u32 raster_mode; /* 0x38 */
+ u32 vector_mode; /* 0x3C */
+ u32 blt_mode; /* 0x40 */
+ u32 blit_status; /* 0x4C */
+ u32 hst_src; /* 0x48 */
+ u32 base_offset; /* 0x4C */
+
+#ifdef _GEODELX_
+ u32 cmd_top; /* 0x50 */
+ u32 cmd_bot; /* 0x54 */
+ u32 cmd_read; /* 0x58 */
+ u32 cmd_write; /* 0x5C */
+ u32 ch3_offset; /* 0x60 */
+ u32 ch3_mode_str; /* 0x64 */
+ u32 ch3_width; /* 0x68 */
+ u32 ch3_hsrc; /* 0x6C */
+ u32 lut_index; /* 0x70 */
+ u32 lut_data; /* 0x74 */
+ u32 int_cntrl; /* 0x78 */
+#endif
+ } r;
+ } gp;
+
+ union {
+ unsigned char b[DC_REG_SIZE];
+
+ struct {
+ u32 unlock; /* 0x00 */
+ u32 gcfg; /* 0x04 */
+ u32 dcfg; /* 0x08 */
+ u32 arb; /* 0x0C */
+ u32 fb_st_offset; /* 0x10 */
+ u32 cb_st_offset; /* 0x14 */
+ u32 curs_st_offset; /* 0x18 */
+ u32 icon_st_offset; /* 0x1C */
+ u32 vid_y_st_offset; /* 0x20 */
+ u32 vid_u_st_offset; /* 0x24 */
+ u32 vid_v_st_offset; /* 0x28 */
+ u32 dctop; /* 0x2c */
+ u32 line_size; /* 0x30 */
+ u32 gfx_pitch; /* 0x34 */
+ u32 vid_yuv_pitch; /* 0x38 */
+ u32 rsvd2; /* 0x3C */
+ u32 h_active_timing; /* 0x40 */
+ u32 h_blank_timing; /* 0x44 */
+ u32 h_sync_timing; /* 0x48 */
+ u32 rsvd3; /* 0x4C */
+ u32 v_active_timing; /* 0x50 */
+ u32 v_blank_timing; /* 0x54 */
+ u32 v_sync_timing; /* 0x58 */
+ u32 fbactive; /* 0x5C */
+ u32 dc_cursor_x; /* 0x60 */
+ u32 dc_cursor_y; /* 0x64 */
+ u32 dc_icon_x; /* 0x68 */
+ u32 dc_line_cnt; /* 0x6C */
+ u32 rsvd5; /* 0x70 - palette address */
+ u32 rsvd6; /* 0x74 - palette data */
+ u32 dfifo_diag; /* 0x78 */
+ u32 cfifo_diag; /* 0x7C */
+ u32 dc_vid_ds_delta; /* 0x80 */
+ u32 gliu0_mem_offset; /* 0x84 */
+ u32 dv_ctl; /* 0x88 - added by LX */
+ u32 dv_acc; /* 0x8C */
+
+#ifdef _GEODELX_
+ u32 gfx_scale;
+ u32 irq_filt_ctl;
+ u32 filt_coeff1;
+ u32 filt_coeff2;
+ u32 vbi_event_ctl;
+ u32 vbi_odd_ctl;
+ u32 vbi_hor;
+ u32 vbi_ln_odd;
+ u32 vbi_ln_event;
+ u32 vbi_pitch;
+ u32 clr_key;
+ u32 clr_key_mask;
+ u32 clr_key_x;
+ u32 clr_key_y;
+ u32 irq;
+ u32 rsvd8;
+ u32 genlk_ctrl;
+ u32 vid_even_y_st_offset; /* 0xD8 */
+ u32 vid_even_u_st_offset; /* 0xDC */
+ u32 vid_even_v_st_offset; /* 0xE0 */
+ u32 v_active_even_timing; /* 0xE4 */
+ u32 v_blank_even_timing; /* 0xE8 */
+ u32 v_sync_even_timing; /* 0xEC */
+#endif
+ } r;
+ } dc;
+
+ union {
+ unsigned char b[VP_REG_SIZE];
+
+ struct {
+ u64 vcfg; /* 0x00 */
+ u64 dcfg; /* 0x08 */
+ u64 vx; /* 0x10 */
+ u64 vy; /* 0x18 */
+ u64 vs; /* 0x20 */
+ u64 vck; /* 0x28 */
+ u64 vcm; /* 0x30 */
+ u64 rsvd1; /* 0x38 - Gamma address*/
+ u64 rsvd2; /* 0x40 - Gamma data*/
+ u64 rsvd3; /* 0x48 */
+ u64 misc; /* 0x50 */
+ u64 ccs; /* 0x58 */
+ u64 rsvd4[3]; /* 0x60-0x70 */
+ u64 vdc; /* 0x78 */
+ u64 vco; /* 0x80 */
+ u64 crc; /* 0x88 */
+ u64 crc32; /* 0x90 */
+ u64 vde; /* 0x98 */
+ u64 cck; /* 0xA0 */
+ u64 ccm; /* 0xA8 */
+ u64 cc1; /* 0xB0 */
+ u64 cc2; /* 0xB8 */
+ u64 a1x; /* 0xC0 */
+ u64 a1y; /* 0xC8 */
+ u64 a1c; /* 0xD0 */
+ u64 a1t; /* 0xD8 */
+ u64 a2x; /* 0xE0 */
+ u64 a2y; /* 0xE8 */
+ u64 a2c; /* 0xF0 */
+ u64 a2t; /* 0xF8 */
+ u64 a3x; /* 0x100 */
+ u64 a3y; /* 0x108 */
+ u64 a3c; /* 0x110 */
+ u64 a3t; /* 0x118 */
+ u64 vrr; /* 0x120 */
+ u64 awt; /* 0x128 */
+ u64 vtm; /* 0x130 */
+#ifdef _GEODELX_
+ u64 vye; /* 0x138 */
+ u64 a1ye; /* 0x140 */
+ u32 a2ye; /* 0x148 */
+ u32 a3ye; /* 0x150 */
+#endif
+ } r;
+ } vp;
+
+ union {
+ unsigned char b[FP_REG_SIZE];
+
+ struct {
+ u64 pt1; /* 0x400 */
+ u64 pt2; /* 0x408 */
+ u64 pm; /* 0x410 */
+ u64 dfc; /* 0x418 */
+ u64 blfsr; /* 0x420 */
+ u64 rlfsr; /* 0x428 */
+ u64 fmi; /* 0x430 */
+ u64 fmd; /* 0x438 */
+ u64 rsvd; /* 0x440 */
+ u64 dca; /* 0x448 */
+ u64 dmd; /* 0x450 */
+ u64 crc; /* 0x458 */
+ u64 fbb; /* 0x460 */
+ u64 crc32; /* 0x468 */
+ } r;
+ } fp;
+
+ u32 pal[DC_PAL_SIZE];
+ u32 gamma[256];
+};
+
+#endif
diff --git a/target/linux/olpc/files/drivers/video/geode/suspend_gx.c b/target/linux/olpc/files/drivers/video/geode/suspend_gx.c
new file mode 100644
index 000000000..43c25bea5
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/geode/suspend_gx.c
@@ -0,0 +1,272 @@
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+
+#include "geodefb.h"
+#include "video_gx.h"
+
+void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs)
+{
+ int timeout = 1000;
+
+ u64 rstpll, dotpll;
+
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ dotpll &= 0x00000000ffffffffull;
+ dotpll |= regs->msr.dotpll & 0xffffffff00000000ull;
+
+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
+
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ rstpll |= (regs->msr.rstpll &
+ ( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 |
+ MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 |
+ MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3));
+
+ wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ do {
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
+}
+
+/* FIXME: Make sure nothing is read to clear */
+
+void gx_save_regs(struct fb_info *info, struct geoderegs *regs)
+{
+ struct geodefb_par *par = info->par;
+ int i;
+
+ /* Wait for the BLT engine to stop being busy */
+ while(readl(par->gp_regs + 0x44) & 0x05);
+
+ rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
+ rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll);
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll);
+
+ writel(0x4758, par->dc_regs + 0x00);
+
+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE);
+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE);
+ memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE);
+ memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE);
+
+ /* Save the palettes */
+ writel(0, par->dc_regs + 0x70);
+
+ for(i = 0; i < DC_PAL_SIZE; i++)
+ regs->pal[i] = readl(par->dc_regs + 0x74);
+
+ writel(0, par->vid_regs + 0x38);
+
+ for(i = 0; i < 0xFF; i++)
+ regs->gamma[i] = readl(par->vid_regs + 0x40);
+}
+
+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs)
+{
+ struct geodefb_par *par = info->par;
+ u32 val, i;
+
+ /* DOTPLL */
+ gx_set_dotpll(info, regs);
+
+ /* GP */
+
+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00);
+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04);
+ writel(regs->gp.r.stride, par->gp_regs + 0x08);
+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C);
+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10);
+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14);
+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18);
+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C);
+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20);
+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24);
+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28);
+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C);
+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30);
+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34);
+
+ /* Don't write the raster / vector / blt mode regs */
+ /* status register is read only */
+
+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48);
+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c);
+
+ /* DC */
+
+ /* Write the unlock value */
+ writel(0x4758, par->dc_regs + 0x00);
+
+ writel(0, par->dc_regs + 0x70);
+
+ for(i = 0; i < DC_PAL_SIZE; i++)
+ writel(regs->pal[i], par->dc_regs + 0x74);
+
+ /* Write the gcfg register without the enables */
+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04);
+
+ /* Write the vcfg register without the enables */
+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08);
+
+ /* Write the rest of the active registers */
+
+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10);
+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14);
+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18);
+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C);
+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20);
+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24);
+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28);
+ writel(regs->dc.r.line_size, par->dc_regs + 0x30);
+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34);
+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38);
+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40);
+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44);
+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48);
+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50);
+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54);
+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58);
+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60);
+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64);
+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68);
+
+ /* Don't write the line_cnt or diag registers */
+
+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80);
+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84);
+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C);
+
+ /* VP */
+
+ /* MSR */
+ wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
+
+ writel(0, par->vid_regs + 0x38);
+
+ for(i = 0; i < 0xFF; i++)
+ writel((u32) regs->gamma[i], par->vid_regs + 0x40);
+
+ /* Don't enable video yet */
+ writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00);
+
+ /* Don't enable the CRT yet */
+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08);
+
+ /* Write the rest of the VP registers */
+
+ writel((u32) regs->vp.r.vx, par->vid_regs + 0x10);
+ writel((u32) regs->vp.r.vy, par->vid_regs + 0x18);
+ writel((u32) regs->vp.r.vs, par->vid_regs + 0x20);
+ writel((u32) regs->vp.r.vck, par->vid_regs + 0x28);
+ writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30);
+ writel((u32) regs->vp.r.misc, par->vid_regs + 0x50);
+ writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58);
+ writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78);
+ writel((u32) regs->vp.r.vco, par->vid_regs + 0x80);
+ writel((u32) regs->vp.r.crc, par->vid_regs + 0x88);
+ writel((u32) regs->vp.r.vde, par->vid_regs + 0x98);
+ writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0);
+ writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8);
+ writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0);
+ writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8);
+ writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0);
+ writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8);
+ writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0);
+ writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8);
+ writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0);
+ writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8);
+ writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0);
+ writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8);
+ writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100);
+ writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108);
+ writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110);
+ writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118);
+ writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120);
+
+
+ /* FP registers */
+
+ writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400);
+ writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408);
+
+ writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418);
+ writel(regs->fp.r.blfsr, par->vid_regs + 0x420);
+ writel(regs->fp.r.rlfsr, par->vid_regs + 0x428);
+ writel(regs->fp.r.fmi, par->vid_regs + 0x430);
+ writel(regs->fp.r.fmd, par->vid_regs + 0x438);
+ writel(regs->fp.r.dca, par->vid_regs + 0x448);
+ writel(regs->fp.r.dmd, par->vid_regs + 0x450);
+ writel(regs->fp.r.crc, par->vid_regs + 0x458);
+ writel(regs->fp.r.fbb, par->vid_regs + 0x460);
+
+ /* Final enables */
+
+ val = readl(par->vid_regs + 0x410);
+
+ /* Control the panel */
+ if (regs->fp.r.pm & (1 << 24)) {
+
+ if (!(val & 0x09))
+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
+ }
+ else {
+ if (!(val & 0x05))
+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
+ }
+
+ /* Turn everything on */
+
+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04);
+ writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00);
+ writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08);
+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08);
+}
+
+
+#ifdef DEBUG
+
+void dump_regs(struct fb_info *info, int mode) {
+
+ struct geodefb_par *par = info->par;
+ u32 val;
+ int i;
+
+ if (mode == 0) {
+ for(i = 0; i < GP_REG_SIZE; i += 4) {
+ val = readl(par->gp_regs + i);
+ }
+ }
+
+ if (mode == 1) {
+ writel(0x4758, par->dc_regs + 0x00);
+
+ for(i = 0; i < DC_REG_SIZE; i += 4) {
+ val = readl(par->dc_regs + i);
+ printk("DC%x: %x\n", i, val);
+ }
+ }
+
+ if (mode == 2) {
+ for(i = 0; i < VP_REG_SIZE; i += 8) {
+ val = readl(par->vid_regs + i);
+ printk("VP%x: %x\n", i, val);
+ }
+ }
+
+ if (mode == 3) {
+ for(i = 0; i < FP_REG_SIZE; i += 8) {
+ val = readl(par->vid_regs + 0x400 + i);
+ printk("FP%x: %x\n", i, val);
+ }
+ }
+}
+
+#endif
diff --git a/target/linux/olpc/files/drivers/video/olpc_dcon.c b/target/linux/olpc/files/drivers/video/olpc_dcon.c
new file mode 100644
index 000000000..d4ef13867
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/olpc_dcon.c
@@ -0,0 +1,824 @@
+/*
+ * Mainly by David Woodhouse, somewhat modified by Jordan Crouse
+ *
+ * Copyright © 2006-2007 Red Hat, Inc.
+ * Copyright © 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software. You can redistribute it and/or
+ * modify it under the terms of version 2 of the GNU General Public
+ * License as published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/fb.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-id.h>
+#include <linux/pci.h>
+#include <linux/vt_kern.h>
+#include <linux/pci_ids.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/backlight.h>
+#include <linux/device.h>
+#include <asm/uaccess.h>
+#include <linux/ctype.h>
+#include <linux/reboot.h>
+#include <asm/tsc.h>
+#include <asm/olpc.h>
+
+#include "olpc_dcon.h"
+
+/* Module definitions */
+
+static int resumeline = 898;
+module_param(resumeline, int, 0444);
+
+static int noinit;
+module_param(noinit, int, 0444);
+
+/* Default off since it doesn't work on DCON ASIC in B-test OLPC board */
+static int useaa = 1;
+module_param(useaa, int, 0444);
+
+/* I2C structures */
+
+static struct i2c_driver dcon_driver;
+static struct i2c_client *dcon_client;
+
+/* Platform devices */
+static struct platform_device *dcon_device;
+
+/* Backlight device */
+static struct backlight_device *dcon_bl_dev;
+
+/* Base address of the GPIO registers */
+static unsigned long gpio_base;
+
+static struct fb_info *fbinfo;
+
+/* Current source, initialized at probe time */
+static int dcon_source;
+
+/* Desired source */
+static int dcon_pending;
+
+/* Current output type */
+static int dcon_output = DCON_OUTPUT_COLOR;
+
+/* Current sleep status (not yet implemented) */
+static int dcon_sleep_val = DCON_ACTIVE;
+
+/* Shadow register for the DCON_REG_MODE register */
+static unsigned short dcon_disp_mode;
+
+/* Variables used during switches */
+static int dcon_switched;
+
+static DECLARE_WAIT_QUEUE_HEAD(dcon_wait_queue);
+
+static unsigned short normal_i2c[] = { 0x0D, I2C_CLIENT_END };
+I2C_CLIENT_INSMOD;
+
+#define dcon_write(reg,val) i2c_smbus_write_word_data(dcon_client,reg,val)
+#define dcon_read(reg) i2c_smbus_read_word_data(dcon_client,reg)
+
+/* The current backlight value - this saves us some smbus traffic */
+static int bl_val = -1;
+
+/* ===== API functions - these are called by a variety of users ==== */
+
+/* Backlight notes - turning off the backlight enable bit in the DCON
+ * doesn't save us any power over just pushing the BL to zero, so we
+ * don't use that bit in this code.
+ */
+
+static int dcon_get_backlight(void)
+{
+ if (dcon_client == NULL)
+ return 0;
+
+ if (bl_val == -1)
+ bl_val = dcon_read(DCON_REG_BRIGHT) & 0x0F;
+
+ return bl_val;
+}
+
+static void dcon_set_backlight(int level)
+{
+ if (dcon_client == NULL)
+ return;
+
+ if (bl_val == (level & 0x0F))
+ return;
+
+ bl_val = level & 0x0F;
+ dcon_write(DCON_REG_BRIGHT, bl_val);
+
+ /* Purposely turn off the backlight when we go to level 0 */
+
+ if (bl_val == 0) {
+ dcon_disp_mode &= ~MODE_BL_ENABLE;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ }
+ else if (!(dcon_disp_mode & MODE_BL_ENABLE)) {
+ dcon_disp_mode |= MODE_BL_ENABLE;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ }
+}
+
+/* Set the output type to either color or mono */
+
+static int dcon_set_output(int arg)
+{
+ if (dcon_output == arg)
+ return 0;
+
+ dcon_output = arg;
+
+ if (arg == DCON_OUTPUT_MONO) {
+ dcon_disp_mode &= ~(MODE_CSWIZZLE | MODE_COL_AA);
+ dcon_disp_mode |= MODE_MONO_LUMA;
+ }
+ else {
+ dcon_disp_mode &= ~(MODE_MONO_LUMA);
+ dcon_disp_mode |= MODE_CSWIZZLE;
+ if (useaa)
+ dcon_disp_mode |= MODE_COL_AA;
+ }
+
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ return 0;
+}
+
+/* For now, this will be really stupid - we need to address how
+ * DCONLOAD works in a sleep and account for it accordingly
+ */
+
+static void dcon_sleep(int state)
+{
+ /* Turn off the backlight and put the DCON to sleep */
+
+ if (state == dcon_sleep_val)
+ return;
+
+ if (state == DCON_SLEEP) {
+ dcon_disp_mode &= ~MODE_BL_ENABLE;
+ dcon_disp_mode |= MODE_SLEEP;
+ }
+ else {
+ /* Only re-enable the backlight if the backlight value is set */
+
+ if (bl_val != 0)
+ dcon_disp_mode |= MODE_BL_ENABLE;
+
+ dcon_disp_mode &= ~MODE_SLEEP;
+ }
+
+ dcon_sleep_val = state;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+
+ /* We should turn off some stuff in the framebuffer - but what? */
+}
+
+/* Set the source of the display (CPU or DCON) */
+
+static void dcon_source_switch(struct work_struct *work)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ int source = dcon_pending;
+
+ if (dcon_source == source)
+ return;
+
+ dcon_switched = 0;
+
+ switch (source) {
+ case DCON_SOURCE_CPU:
+
+ /* Enable the scanline interrupt bit */
+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode | MODE_SCAN_INT))
+ printk(KERN_ERR "olpc-dcon: couldn't enable scanline interrupt!\n");
+ else {
+ /* Wait up to one second for the scanline interrupt */
+ wait_event_timeout(dcon_wait_queue, dcon_switched == 1, HZ);
+ }
+
+ if (!dcon_switched)
+ printk(KERN_ERR "olpc-dcon: Timeout entering CPU mode; expect a screen glitch.\n");
+
+ /*
+ * Ideally we'd like to disable interrupts here so that the
+ * fb_powerup and DCON turn on happen at a known time value;
+ * however, we can't do that right now with fb_set_suspend
+ * messing with semaphores.
+ *
+ * For now, we just hope..
+ */
+ if (fb_powerup(fbinfo)) {
+ printk(KERN_ERR "olpc-dcon: Failed to enter CPU mode\n");
+ dcon_pending = DCON_SOURCE_DCON;
+ return;
+ }
+
+ /* And turn off the DCON */
+ outl(1<<11, gpio_base + GPIOx_OUT_VAL);
+
+ /* Turn off the scanline interrupt */
+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode))
+ printk(KERN_ERR "olpc-dcon: couldn't disable scanline interrupt!\n");
+
+ printk(KERN_INFO "olpc-dcon: The CPU has control\n");
+ break;
+ case DCON_SOURCE_DCON:
+ {
+ int t;
+
+ add_wait_queue(&dcon_wait_queue, &wait);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+
+ /* Clear GPIO11 (DCONLOAD) - this implies that the DCON is in
+ control */
+
+ outl(1 << (11 + 16), gpio_base + GPIOx_OUT_VAL);
+
+ t = schedule_timeout(HZ/2);
+ remove_wait_queue(&dcon_wait_queue, &wait);
+ set_current_state(TASK_RUNNING);
+
+ if (!dcon_switched)
+ printk(KERN_ERR "olpc-dcon: Timeout entering DCON mode; expect a screen glitch.\n");
+
+ /* Turn off the graphics engine completely */
+ fb_powerdown(fbinfo);
+
+ printk(KERN_INFO "olpc-dcon: The DCON has control\n");
+ break;
+ }
+ default:
+ BUG();
+ }
+
+ dcon_source = source;
+}
+
+static DECLARE_WORK(dcon_work, dcon_source_switch);
+
+static int dcon_set_source(int arg)
+{
+ if (arg != DCON_SOURCE_CPU && arg != DCON_SOURCE_DCON)
+ return -EINVAL;
+
+ if (dcon_pending == arg)
+ return 0;
+
+ dcon_pending = arg;
+ if ((dcon_source != arg) && !work_pending(&dcon_work))
+ schedule_work(&dcon_work);
+
+ return 0;
+}
+
+static int dcon_set_source_sync(int arg)
+{
+ int ret = dcon_set_source(arg);
+ if (!ret)
+ flush_scheduled_work();
+ return ret;
+}
+
+static int dconbl_set(struct backlight_device *dev) {
+
+ int level = dev->props.brightness;
+
+ if (dev->props.power != FB_BLANK_UNBLANK)
+ level = 0;
+
+ dcon_set_backlight(level);
+ return 0;
+}
+
+static int dconbl_get(struct backlight_device *dev) {
+ return dcon_get_backlight();
+}
+
+static ssize_t dcon_mode_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%4.4X\n", dcon_disp_mode);
+}
+
+static ssize_t dcon_sleep_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_sleep_val);
+}
+
+static ssize_t /* __deprecated */ dcon_source_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n");
+ return sprintf(buf, "%d\n", dcon_source);
+}
+
+static ssize_t dcon_freeze_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_source == DCON_SOURCE_DCON ? 1 : 0);
+}
+
+static ssize_t dcon_output_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_output);
+}
+
+static ssize_t dcon_resumeline_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", resumeline);
+}
+
+static int _strtoul(const char *buf, int len, unsigned int *val)
+{
+
+ char *endp;
+ unsigned int output = simple_strtoul(buf, &endp, 0);
+ int size = endp - buf;
+
+ if (*endp && isspace(*endp))
+ size++;
+
+ if (size != len)
+ return -EINVAL;
+
+ *val = output;
+ return 0;
+}
+
+static ssize_t dcon_output_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ if (output == DCON_OUTPUT_COLOR || output == DCON_OUTPUT_MONO) {
+ dcon_set_output(output);
+ rc = count;
+ }
+
+ return rc;
+}
+
+static ssize_t /* __deprecated */ dcon_source_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n");
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ dcon_set_source(output);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_freeze_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &output))
+ return rc;
+
+ dcon_set_source(output ? DCON_SOURCE_DCON : DCON_SOURCE_CPU);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_resumeline_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int rl;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &rl))
+ return rc;
+
+ resumeline = rl;
+ dcon_write(DCON_REG_SCAN_INT, resumeline);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_sleep_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ dcon_sleep(output ? DCON_SLEEP : DCON_ACTIVE);
+ return count;
+}
+
+static struct device_attribute dcon_device_files[] = {
+ __ATTR(mode, 0444, dcon_mode_show, NULL),
+ __ATTR(sleep, 0644, dcon_sleep_show, dcon_sleep_store),
+ __ATTR(source, 0644, dcon_source_show, dcon_source_store),
+ __ATTR(freeze, 0644, dcon_freeze_show, dcon_freeze_store),
+ __ATTR(output, 0644, dcon_output_show, dcon_output_store),
+ __ATTR(resumeline, 0644, dcon_resumeline_show, dcon_resumeline_store),
+};
+
+static struct backlight_ops dcon_bl_ops = {
+ .get_brightness = dconbl_get,
+ .update_status = dconbl_set
+};
+
+/* List of GPIOs that we care about:
+ (in) GPIO12 -- DCONBLNK
+ (in) GPIO[56] -- DCONSTAT[01]
+ (out) GPIO11 -- DCONLOAD
+*/
+
+#define IN_GPIOS ((1<<5) | (1<<6) | (1<<7) | (1<<12))
+#define OUT_GPIOS (1<<11)
+
+static irqreturn_t dcon_interrupt(int, void *);
+
+static int dcon_request_irq(void)
+{
+ unsigned long lo, hi;
+ unsigned char lob;
+
+ rdmsr(MSR_LBAR_GPIO, lo, hi);
+
+ /* Check the mask and whether GPIO is enabled (sanity check) */
+ if (hi != 0x0000f001) {
+ printk(KERN_ERR "GPIO not enabled -- cannot use DCON\n");
+ return -ENODEV;
+ }
+
+ /* Mask off the IO base address */
+ gpio_base = lo & 0x0000ff00;
+
+ /* Turn off the event enable for GPIO7 just to be safe */
+ outl(1 << (16+7), gpio_base + GPIOx_EVNT_EN);
+
+ /* Set the directions for the GPIO pins */
+ outl(OUT_GPIOS | (IN_GPIOS << 16), gpio_base + GPIOx_OUT_EN);
+ outl(IN_GPIOS | (OUT_GPIOS << 16), gpio_base + GPIOx_IN_EN);
+
+ /* Set up the interrupt mappings */
+
+ /* Set the IRQ to pair 2 */
+ geode_gpio_event_irq(OLPC_GPIO_DCON_IRQ, 2);
+
+ /* Enable group 2 to trigger the DCON interrupt */
+ geode_gpio_set_irq(2, DCON_IRQ);
+
+ /* Select edge level for interrupt (in PIC) */
+
+ lob = inb(0x4d0);
+ lob &= ~(1 << DCON_IRQ);
+ outb(lob, 0x4d0);
+
+ /* Register the interupt handler */
+ if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", &dcon_driver))
+ return -EIO;
+
+ /* Clear INV_EN for GPIO7 (DCONIRQ) */
+ outl((1<<(16+7)), gpio_base + GPIOx_INV_EN);
+
+ /* Enable filter for GPIO12 (DCONBLANK) */
+ outl(1<<(12), gpio_base + GPIOx_IN_FLTR_EN);
+
+ /* Disable filter for GPIO7 */
+ outl(1<<(16+7), gpio_base + GPIOx_IN_FLTR_EN);
+
+ /* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+
+ outl(1<<(16+7), gpio_base + GPIOx_EVNTCNT_EN);
+ outl(1<<(16+12), gpio_base + GPIOx_EVNTCNT_EN);
+
+ /* Add GPIO12 to the Filter Event Pair #7 */
+ outb(12, gpio_base + GPIO_FE7_SEL);
+
+ /* Turn off negative Edge Enable for GPIO12 */
+ outl(1<<(16+12), gpio_base + GPIOx_NEGEDGE_EN);
+
+ /* Enable negative Edge Enable for GPIO7 */
+ outl(1<<7, gpio_base + GPIOx_NEGEDGE_EN);
+
+ /* Zero the filter amount for Filter Event Pair #7 */
+ outw(0, gpio_base + GPIO_FLT7_AMNT);
+
+ /* Clear the negative edge status for GPIO7 and GPIO12 */
+ outl((1<<7) | (1<<12), gpio_base+0x4c);
+
+ /* FIXME: Clear the posiitive status as well, just to be sure */
+ outl((1<<7) | (1<<12), gpio_base+0x48);
+
+ /* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+ outl((1<<(7))|(1<<12), gpio_base + GPIOx_EVNT_EN);
+
+ /* Determine the current state by reading the GPIO bit */
+ /* Earlier stages of the boot process have established the state */
+ dcon_source = inl(gpio_base + GPIOx_OUT_VAL) & (1<<11)
+ ? DCON_SOURCE_CPU
+ : DCON_SOURCE_DCON;
+ dcon_pending = dcon_source;
+
+ return 0;
+}
+
+static int dcon_reboot_notify(struct notifier_block *nb, unsigned long foo, void *bar)
+{
+ if (dcon_client == NULL)
+ return 0;
+
+ /* Turn off the DCON. Entirely. */
+ dcon_write(DCON_REG_MODE, 0x39);
+ dcon_write(DCON_REG_MODE, 0x32);
+ return 0;
+}
+
+static int dcon_conswitch_notify(struct notifier_block *nb,
+ unsigned long mode, void *dummy)
+{
+ if (mode == CONSOLE_EVENT_SWITCH_TEXT)
+ dcon_sleep(DCON_ACTIVE);
+
+ return 0;
+}
+
+static struct notifier_block dcon_nb = {
+ .notifier_call = dcon_reboot_notify,
+ .priority = -1,
+};
+
+static struct notifier_block dcon_console_nb = {
+ .notifier_call = dcon_conswitch_notify,
+ .priority = -1,
+};
+
+static int dcon_probe(struct i2c_adapter *adap, int addr, int kind)
+{
+ struct i2c_client *client;
+ uint16_t ver;
+ int rc, i;
+
+ if (!olpc_has_dcon()) {
+ printk("olpc-dcon: No DCON is attached.\n");
+ return -ENODEV;
+ }
+
+ if (num_registered_fb >= 1)
+ fbinfo = registered_fb[0];
+
+ if (adap->id != I2C_HW_SMBUS_SCX200) {
+ printk(KERN_ERR "olpc-dcon: Invalid I2C bus (%d not %d)\n",
+ adap->id, I2C_HW_SMBUS_SCX200);
+ return -ENXIO;
+ }
+
+ client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
+ if (client == NULL)
+ return -ENOMEM;
+
+ strncpy(client->name, "OLPC-DCON", I2C_NAME_SIZE);
+ client->addr = addr;
+ client->adapter = adap;
+ client->driver = &dcon_driver;
+
+ if ((rc = i2c_attach_client(client)) != 0) {
+ printk(KERN_ERR "olpc-dcon: Unable to attach the I2C client.\n");
+ goto eclient;
+ }
+
+ ver = i2c_smbus_read_word_data(client, DCON_REG_ID);
+
+ if ((ver >> 8) != 0xDC) {
+ printk(KERN_ERR "olpc-dcon: DCON ID not 0xDCxx: 0x%04x instead.\n", ver);
+ rc = -ENXIO;
+ goto ei2c;
+ }
+
+ if ((rc = dcon_request_irq())) {
+ printk(KERN_ERR "olpc-dcon: Unable to grab IRQ.\n");
+ goto ei2c;
+ }
+
+ if (ver < 0xdc02 && !noinit) {
+ /* Initialize the DCON registers */
+
+ /* Start with work-arounds for DCON ASIC */
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x0b, 0x007a);
+ i2c_smbus_write_word_data(client, 0x36, 0x025c);
+ i2c_smbus_write_word_data(client, 0x37, 0x025e);
+
+ /* Initialise SDRAM */
+
+ i2c_smbus_write_word_data(client, 0x3b, 0x002b);
+ i2c_smbus_write_word_data(client, 0x41, 0x0101);
+ i2c_smbus_write_word_data(client, 0x42, 0x0101);
+ }
+
+ /* Colour swizzle, AA, no passthrough, backlight */
+
+ dcon_disp_mode = MODE_PASSTHRU | MODE_BL_ENABLE | MODE_CSWIZZLE;
+ if (useaa)
+ dcon_disp_mode |= MODE_COL_AA;
+ i2c_smbus_write_word_data(client, DCON_REG_MODE, dcon_disp_mode);
+
+
+ /* Set the scanline to interrupt on during resume */
+
+ i2c_smbus_write_word_data(client, DCON_REG_SCAN_INT, resumeline);
+
+ /* Add the DCON device */
+
+ dcon_device = platform_device_alloc("dcon", -1);
+
+ if (dcon_device == NULL) {
+ printk(KERN_ERR "dcon: Unable to create the DCON device\n");
+ rc = -ENOMEM;
+ goto eirq;
+ }
+
+ if ((rc = platform_device_add(dcon_device))) {
+ printk(KERN_ERR "dcon: Unable to add the DCON device\n");
+ goto edev;
+ }
+
+ for(i = 0; i < ARRAY_SIZE(dcon_device_files); i++)
+ device_create_file(&dcon_device->dev, &dcon_device_files[i]);
+
+ /* Add the backlight device for the DCON */
+
+ dcon_client = client;
+
+ dcon_bl_dev = backlight_device_register("dcon-bl", &dcon_device->dev,
+ NULL, &dcon_bl_ops);
+
+ if (IS_ERR(dcon_bl_dev)) {
+ printk(KERN_INFO "Could not register the backlight device for the DCON (%ld)\n", PTR_ERR(dcon_bl_dev));
+ dcon_bl_dev = NULL;
+ }
+ else {
+ dcon_bl_dev->props.max_brightness = 15;
+ dcon_bl_dev->props.power = FB_BLANK_UNBLANK;
+ dcon_bl_dev->props.brightness = dcon_get_backlight();
+
+ backlight_update_status(dcon_bl_dev);
+ }
+
+ register_reboot_notifier(&dcon_nb);
+ console_event_register(&dcon_console_nb);
+
+ printk(KERN_INFO "olpc-dcon: Discovered DCON version %x\n", ver & 0xFF);
+
+ return 0;
+
+ edev:
+ platform_device_unregister(dcon_device);
+ dcon_device = NULL;
+ eirq:
+ free_irq(DCON_IRQ, &dcon_driver);
+ ei2c:
+ i2c_detach_client(client);
+ eclient:
+ kfree(client);
+
+ return rc;
+}
+
+static int dcon_attach(struct i2c_adapter *adap)
+{
+ int ret;
+
+ ret = i2c_probe(adap, &addr_data, dcon_probe);
+
+ if (dcon_client == NULL)
+ printk(KERN_ERR "olpc-dcon: No DCON found on SMBus\n");
+
+ return ret;
+}
+
+static int dcon_detach(struct i2c_client *client)
+{
+ int rc;
+ dcon_client = NULL;
+
+ unregister_reboot_notifier(&dcon_nb);
+ console_event_unregister(&dcon_console_nb);
+
+ free_irq(DCON_IRQ, &dcon_driver);
+
+ if ((rc = i2c_detach_client(client)) == 0)
+ kfree(i2c_get_clientdata(client));
+
+ if (dcon_bl_dev != NULL)
+ backlight_device_unregister(dcon_bl_dev);
+
+ if (dcon_device != NULL)
+ platform_device_unregister(dcon_device);
+ cancel_work_sync(&dcon_work);
+
+ return rc;
+}
+
+
+#ifdef CONFIG_PM
+static int dcon_suspend(struct i2c_client *client, pm_message_t state)
+{
+ if (dcon_sleep_val != DCON_ACTIVE)
+ return 0;
+
+ /* Set up the DCON to have the source */
+ return dcon_set_source_sync(DCON_SOURCE_DCON);
+}
+
+static int dcon_resume(struct i2c_client *client)
+{
+ int x;
+ if (dcon_sleep_val != DCON_ACTIVE)
+ return 0;
+
+ /* HACK: ensure the bus is stable */
+ do {
+ x = dcon_read(DCON_REG_ID);
+ } while (x < 0);
+
+ return dcon_set_source(DCON_SOURCE_CPU);
+}
+
+#endif
+
+static irqreturn_t dcon_interrupt(int irq, void *id)
+{
+ int status = inl(gpio_base + GPIOx_READ_BACK) >> 5;
+
+ /* Clear the negative edge status for GPIO7 */
+ outl(1 << 7, gpio_base + GPIOx_NEGEDGE_STS);
+
+ switch (status & 3) {
+ case 3:
+ printk(KERN_DEBUG "olpc-dcon: DCONLOAD_MISSED interrupt\n");
+ break;
+ case 2: /* switch to DCON mode */
+ case 1: /* switch to CPU mode */
+ dcon_switched = 1;
+ wake_up(&dcon_wait_queue);
+ break;
+ case 0:
+ printk(KERN_DEBUG "olpc-dcon: scanline interrupt w/CPU\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct i2c_driver dcon_driver = {
+ .driver = {
+ .name = "OLPC-DCON",
+ },
+ .id = I2C_DRIVERID_DCON,
+ .attach_adapter = dcon_attach,
+ .detach_client = dcon_detach,
+#ifdef CONFIG_PM
+ .suspend = dcon_suspend,
+ .resume = dcon_resume,
+#endif
+};
+
+
+static int __init olpc_dcon_init(void)
+{
+ i2c_add_driver(&dcon_driver);
+ return 0;
+}
+
+static void __exit olpc_dcon_exit(void)
+{
+ i2c_del_driver(&dcon_driver);
+}
+
+module_init(olpc_dcon_init);
+module_exit(olpc_dcon_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/target/linux/olpc/files/drivers/video/olpc_dcon.h b/target/linux/olpc/files/drivers/video/olpc_dcon.h
new file mode 100644
index 000000000..6453ca4ba
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/olpc_dcon.h
@@ -0,0 +1,75 @@
+#ifndef OLPC_DCON_H_
+#define OLPC_DCON_H_
+
+/* DCON registers */
+
+#define DCON_REG_ID 0
+#define DCON_REG_MODE 1
+
+#define MODE_PASSTHRU (1<<0)
+#define MODE_SLEEP (1<<1)
+#define MODE_SLEEP_AUTO (1<<2)
+#define MODE_BL_ENABLE (1<<3)
+#define MODE_BLANK (1<<4)
+#define MODE_CSWIZZLE (1<<5)
+#define MODE_COL_AA (1<<6)
+#define MODE_MONO_LUMA (1<<7)
+#define MODE_SCAN_INT (1<<8)
+#define MODE_CLOCKDIV (1<<9)
+#define MODE_DEBUG (1<<14)
+#define MODE_SELFTEST (1<<15)
+
+#define DCON_REG_HRES 2
+#define DCON_REG_HTOTAL 3
+#define DCON_REG_HSYNC_WIDTH 4
+#define DCON_REG_VRES 5
+#define DCON_REG_VTOTAL 6
+#define DCON_REG_VSYNC_WIDTH 7
+#define DCON_REG_TIMEOUT 8
+#define DCON_REG_SCAN_INT 9
+#define DCON_REG_BRIGHT 10
+
+/* GPIO registers (CS5536) */
+
+#define MSR_LBAR_GPIO 0x5140000C
+
+#define GPIOx_OUT_VAL 0x00
+#define GPIOx_OUT_EN 0x04
+#define GPIOx_IN_EN 0x20
+#define GPIOx_INV_EN 0x24
+#define GPIOx_IN_FLTR_EN 0x28
+#define GPIOx_EVNTCNT_EN 0x2C
+#define GPIOx_READ_BACK 0x30
+#define GPIOx_EVNT_EN 0x38
+#define GPIOx_NEGEDGE_EN 0x44
+#define GPIOx_NEGEDGE_STS 0x4C
+#define GPIO_FLT7_AMNT 0xD8
+#define GPIO_MAP_X 0xE0
+#define GPIO_MAP_Y 0xE4
+#define GPIO_FE7_SEL 0xF7
+
+
+/* Status values */
+
+#define DCONSTAT_SCANINT 0
+#define DCONSTAT_SCANINT_DCON 1
+#define DCONSTAT_DISPLAYLOAD 2
+#define DCONSTAT_MISSED 3
+
+/* Source values */
+
+#define DCON_SOURCE_DCON 0
+#define DCON_SOURCE_CPU 1
+
+/* Output values */
+#define DCON_OUTPUT_COLOR 0
+#define DCON_OUTPUT_MONO 1
+
+/* Sleep values */
+#define DCON_ACTIVE 0
+#define DCON_SLEEP 1
+
+/* Interrupt */
+#define DCON_IRQ 6
+
+#endif