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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-30 17:38:08 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-30 17:38:08 +0000
commitf39cd042512614edfbed8b4ea22023c1f75145b2 (patch)
treec6f85a18f1e5ea9e15a4649f8956c53b33f3726d /target/linux/olpc/files/drivers/video
parent25040fe2c0cc788e36c2f4a4d82e84ddea8a71a1 (diff)
cleaning up olpc patch 1
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10060 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/olpc/files/drivers/video')
-rw-r--r--target/linux/olpc/files/drivers/video/geode/geode_regs.h242
-rw-r--r--target/linux/olpc/files/drivers/video/geode/suspend_gx.c272
-rw-r--r--target/linux/olpc/files/drivers/video/olpc_dcon.c824
-rw-r--r--target/linux/olpc/files/drivers/video/olpc_dcon.h75
4 files changed, 1413 insertions, 0 deletions
diff --git a/target/linux/olpc/files/drivers/video/geode/geode_regs.h b/target/linux/olpc/files/drivers/video/geode/geode_regs.h
new file mode 100644
index 000000000..9e75505a8
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/geode/geode_regs.h
@@ -0,0 +1,242 @@
+/* This header file defines the registers and suspend/resume
+ structures for the Geode GX and LX. The lxfb driver defines
+ _GEODELX_ before including this file, which will unlock the
+ extra registers that are only valid for LX.
+*/
+
+#ifndef _GEODE_REGS_H_
+#define _GEODE_REGS_H_
+
+/* MSRs */
+
+#define GX_VP_MSR_PAD_SELECT 0xC0002011
+#define LX_VP_MSR_PAD_SELECT 0x48000011
+
+#define GEODE_MSR_GLCP_DOTPLL 0x4c000015
+
+#define GLCP_DOTPLL_RESET (1 << 0)
+#define GLCP_DOTPLL_BYPASS (1 << 15)
+#define GLCP_DOTPLL_HALFPIX (1 << 24)
+#define GLCP_DOTPLL_LOCK (1 << 25)
+
+/* Registers */
+#define VP_FP_START 0x400
+
+
+#ifdef _GEODELX_
+
+#define GP_REG_SIZE 0x7C
+#define DC_REG_SIZE 0xF0
+#define VP_REG_SIZE 0x158
+#define FP_REG_SIZE 0x70
+
+#else
+
+#define GP_REG_SIZE 0x50
+#define DC_REG_SIZE 0x90
+#define VP_REG_SIZE 0x138
+#define FP_REG_SIZE 0x70
+
+#endif
+
+#define DC_PAL_SIZE 0x105
+
+struct geoderegs {
+
+ struct {
+ u64 padsel;
+ u64 dotpll;
+
+#ifdef _GEODELX_
+ u64 dfglcfg;
+ u64 dcspare;
+#else
+ u64 rstpll;
+#endif
+ } msr;
+
+ union {
+ unsigned char b[GP_REG_SIZE];
+ struct {
+ u32 dst_offset; /* 0x00 */
+ u32 src_offset; /* 0x04 */
+ u32 stride; /* 0x08 */
+ u32 wid_height; /* 0x0C */
+ u32 src_color_fg; /* 0x10 */
+ u32 src_color_bg; /* 0x14 */
+ u32 pat_color_0; /* 0x18 */
+ u32 pat_color_1; /* 0x1C */
+ u32 pat_color_2; /* 0x20 */
+ u32 pat_color_3; /* 0x24 */
+ u32 pat_color_4; /* 0x28 */
+ u32 pat_color_5; /* 0x2C */
+ u32 pat_data_0; /* 0x30 */
+ u32 pat_data_1; /* 0x34 */
+ u32 raster_mode; /* 0x38 */
+ u32 vector_mode; /* 0x3C */
+ u32 blt_mode; /* 0x40 */
+ u32 blit_status; /* 0x4C */
+ u32 hst_src; /* 0x48 */
+ u32 base_offset; /* 0x4C */
+
+#ifdef _GEODELX_
+ u32 cmd_top; /* 0x50 */
+ u32 cmd_bot; /* 0x54 */
+ u32 cmd_read; /* 0x58 */
+ u32 cmd_write; /* 0x5C */
+ u32 ch3_offset; /* 0x60 */
+ u32 ch3_mode_str; /* 0x64 */
+ u32 ch3_width; /* 0x68 */
+ u32 ch3_hsrc; /* 0x6C */
+ u32 lut_index; /* 0x70 */
+ u32 lut_data; /* 0x74 */
+ u32 int_cntrl; /* 0x78 */
+#endif
+ } r;
+ } gp;
+
+ union {
+ unsigned char b[DC_REG_SIZE];
+
+ struct {
+ u32 unlock; /* 0x00 */
+ u32 gcfg; /* 0x04 */
+ u32 dcfg; /* 0x08 */
+ u32 arb; /* 0x0C */
+ u32 fb_st_offset; /* 0x10 */
+ u32 cb_st_offset; /* 0x14 */
+ u32 curs_st_offset; /* 0x18 */
+ u32 icon_st_offset; /* 0x1C */
+ u32 vid_y_st_offset; /* 0x20 */
+ u32 vid_u_st_offset; /* 0x24 */
+ u32 vid_v_st_offset; /* 0x28 */
+ u32 dctop; /* 0x2c */
+ u32 line_size; /* 0x30 */
+ u32 gfx_pitch; /* 0x34 */
+ u32 vid_yuv_pitch; /* 0x38 */
+ u32 rsvd2; /* 0x3C */
+ u32 h_active_timing; /* 0x40 */
+ u32 h_blank_timing; /* 0x44 */
+ u32 h_sync_timing; /* 0x48 */
+ u32 rsvd3; /* 0x4C */
+ u32 v_active_timing; /* 0x50 */
+ u32 v_blank_timing; /* 0x54 */
+ u32 v_sync_timing; /* 0x58 */
+ u32 fbactive; /* 0x5C */
+ u32 dc_cursor_x; /* 0x60 */
+ u32 dc_cursor_y; /* 0x64 */
+ u32 dc_icon_x; /* 0x68 */
+ u32 dc_line_cnt; /* 0x6C */
+ u32 rsvd5; /* 0x70 - palette address */
+ u32 rsvd6; /* 0x74 - palette data */
+ u32 dfifo_diag; /* 0x78 */
+ u32 cfifo_diag; /* 0x7C */
+ u32 dc_vid_ds_delta; /* 0x80 */
+ u32 gliu0_mem_offset; /* 0x84 */
+ u32 dv_ctl; /* 0x88 - added by LX */
+ u32 dv_acc; /* 0x8C */
+
+#ifdef _GEODELX_
+ u32 gfx_scale;
+ u32 irq_filt_ctl;
+ u32 filt_coeff1;
+ u32 filt_coeff2;
+ u32 vbi_event_ctl;
+ u32 vbi_odd_ctl;
+ u32 vbi_hor;
+ u32 vbi_ln_odd;
+ u32 vbi_ln_event;
+ u32 vbi_pitch;
+ u32 clr_key;
+ u32 clr_key_mask;
+ u32 clr_key_x;
+ u32 clr_key_y;
+ u32 irq;
+ u32 rsvd8;
+ u32 genlk_ctrl;
+ u32 vid_even_y_st_offset; /* 0xD8 */
+ u32 vid_even_u_st_offset; /* 0xDC */
+ u32 vid_even_v_st_offset; /* 0xE0 */
+ u32 v_active_even_timing; /* 0xE4 */
+ u32 v_blank_even_timing; /* 0xE8 */
+ u32 v_sync_even_timing; /* 0xEC */
+#endif
+ } r;
+ } dc;
+
+ union {
+ unsigned char b[VP_REG_SIZE];
+
+ struct {
+ u64 vcfg; /* 0x00 */
+ u64 dcfg; /* 0x08 */
+ u64 vx; /* 0x10 */
+ u64 vy; /* 0x18 */
+ u64 vs; /* 0x20 */
+ u64 vck; /* 0x28 */
+ u64 vcm; /* 0x30 */
+ u64 rsvd1; /* 0x38 - Gamma address*/
+ u64 rsvd2; /* 0x40 - Gamma data*/
+ u64 rsvd3; /* 0x48 */
+ u64 misc; /* 0x50 */
+ u64 ccs; /* 0x58 */
+ u64 rsvd4[3]; /* 0x60-0x70 */
+ u64 vdc; /* 0x78 */
+ u64 vco; /* 0x80 */
+ u64 crc; /* 0x88 */
+ u64 crc32; /* 0x90 */
+ u64 vde; /* 0x98 */
+ u64 cck; /* 0xA0 */
+ u64 ccm; /* 0xA8 */
+ u64 cc1; /* 0xB0 */
+ u64 cc2; /* 0xB8 */
+ u64 a1x; /* 0xC0 */
+ u64 a1y; /* 0xC8 */
+ u64 a1c; /* 0xD0 */
+ u64 a1t; /* 0xD8 */
+ u64 a2x; /* 0xE0 */
+ u64 a2y; /* 0xE8 */
+ u64 a2c; /* 0xF0 */
+ u64 a2t; /* 0xF8 */
+ u64 a3x; /* 0x100 */
+ u64 a3y; /* 0x108 */
+ u64 a3c; /* 0x110 */
+ u64 a3t; /* 0x118 */
+ u64 vrr; /* 0x120 */
+ u64 awt; /* 0x128 */
+ u64 vtm; /* 0x130 */
+#ifdef _GEODELX_
+ u64 vye; /* 0x138 */
+ u64 a1ye; /* 0x140 */
+ u32 a2ye; /* 0x148 */
+ u32 a3ye; /* 0x150 */
+#endif
+ } r;
+ } vp;
+
+ union {
+ unsigned char b[FP_REG_SIZE];
+
+ struct {
+ u64 pt1; /* 0x400 */
+ u64 pt2; /* 0x408 */
+ u64 pm; /* 0x410 */
+ u64 dfc; /* 0x418 */
+ u64 blfsr; /* 0x420 */
+ u64 rlfsr; /* 0x428 */
+ u64 fmi; /* 0x430 */
+ u64 fmd; /* 0x438 */
+ u64 rsvd; /* 0x440 */
+ u64 dca; /* 0x448 */
+ u64 dmd; /* 0x450 */
+ u64 crc; /* 0x458 */
+ u64 fbb; /* 0x460 */
+ u64 crc32; /* 0x468 */
+ } r;
+ } fp;
+
+ u32 pal[DC_PAL_SIZE];
+ u32 gamma[256];
+};
+
+#endif
diff --git a/target/linux/olpc/files/drivers/video/geode/suspend_gx.c b/target/linux/olpc/files/drivers/video/geode/suspend_gx.c
new file mode 100644
index 000000000..43c25bea5
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/geode/suspend_gx.c
@@ -0,0 +1,272 @@
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+
+#include "geodefb.h"
+#include "video_gx.h"
+
+void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs)
+{
+ int timeout = 1000;
+
+ u64 rstpll, dotpll;
+
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ dotpll &= 0x00000000ffffffffull;
+ dotpll |= regs->msr.dotpll & 0xffffffff00000000ull;
+
+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
+
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ rstpll |= (regs->msr.rstpll &
+ ( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 |
+ MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 |
+ MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3));
+
+ wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ do {
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
+}
+
+/* FIXME: Make sure nothing is read to clear */
+
+void gx_save_regs(struct fb_info *info, struct geoderegs *regs)
+{
+ struct geodefb_par *par = info->par;
+ int i;
+
+ /* Wait for the BLT engine to stop being busy */
+ while(readl(par->gp_regs + 0x44) & 0x05);
+
+ rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
+ rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll);
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll);
+
+ writel(0x4758, par->dc_regs + 0x00);
+
+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE);
+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE);
+ memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE);
+ memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE);
+
+ /* Save the palettes */
+ writel(0, par->dc_regs + 0x70);
+
+ for(i = 0; i < DC_PAL_SIZE; i++)
+ regs->pal[i] = readl(par->dc_regs + 0x74);
+
+ writel(0, par->vid_regs + 0x38);
+
+ for(i = 0; i < 0xFF; i++)
+ regs->gamma[i] = readl(par->vid_regs + 0x40);
+}
+
+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs)
+{
+ struct geodefb_par *par = info->par;
+ u32 val, i;
+
+ /* DOTPLL */
+ gx_set_dotpll(info, regs);
+
+ /* GP */
+
+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00);
+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04);
+ writel(regs->gp.r.stride, par->gp_regs + 0x08);
+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C);
+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10);
+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14);
+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18);
+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C);
+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20);
+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24);
+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28);
+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C);
+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30);
+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34);
+
+ /* Don't write the raster / vector / blt mode regs */
+ /* status register is read only */
+
+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48);
+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c);
+
+ /* DC */
+
+ /* Write the unlock value */
+ writel(0x4758, par->dc_regs + 0x00);
+
+ writel(0, par->dc_regs + 0x70);
+
+ for(i = 0; i < DC_PAL_SIZE; i++)
+ writel(regs->pal[i], par->dc_regs + 0x74);
+
+ /* Write the gcfg register without the enables */
+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04);
+
+ /* Write the vcfg register without the enables */
+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08);
+
+ /* Write the rest of the active registers */
+
+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10);
+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14);
+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18);
+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C);
+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20);
+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24);
+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28);
+ writel(regs->dc.r.line_size, par->dc_regs + 0x30);
+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34);
+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38);
+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40);
+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44);
+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48);
+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50);
+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54);
+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58);
+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60);
+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64);
+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68);
+
+ /* Don't write the line_cnt or diag registers */
+
+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80);
+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84);
+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C);
+
+ /* VP */
+
+ /* MSR */
+ wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
+
+ writel(0, par->vid_regs + 0x38);
+
+ for(i = 0; i < 0xFF; i++)
+ writel((u32) regs->gamma[i], par->vid_regs + 0x40);
+
+ /* Don't enable video yet */
+ writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00);
+
+ /* Don't enable the CRT yet */
+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08);
+
+ /* Write the rest of the VP registers */
+
+ writel((u32) regs->vp.r.vx, par->vid_regs + 0x10);
+ writel((u32) regs->vp.r.vy, par->vid_regs + 0x18);
+ writel((u32) regs->vp.r.vs, par->vid_regs + 0x20);
+ writel((u32) regs->vp.r.vck, par->vid_regs + 0x28);
+ writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30);
+ writel((u32) regs->vp.r.misc, par->vid_regs + 0x50);
+ writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58);
+ writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78);
+ writel((u32) regs->vp.r.vco, par->vid_regs + 0x80);
+ writel((u32) regs->vp.r.crc, par->vid_regs + 0x88);
+ writel((u32) regs->vp.r.vde, par->vid_regs + 0x98);
+ writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0);
+ writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8);
+ writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0);
+ writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8);
+ writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0);
+ writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8);
+ writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0);
+ writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8);
+ writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0);
+ writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8);
+ writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0);
+ writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8);
+ writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100);
+ writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108);
+ writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110);
+ writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118);
+ writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120);
+
+
+ /* FP registers */
+
+ writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400);
+ writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408);
+
+ writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418);
+ writel(regs->fp.r.blfsr, par->vid_regs + 0x420);
+ writel(regs->fp.r.rlfsr, par->vid_regs + 0x428);
+ writel(regs->fp.r.fmi, par->vid_regs + 0x430);
+ writel(regs->fp.r.fmd, par->vid_regs + 0x438);
+ writel(regs->fp.r.dca, par->vid_regs + 0x448);
+ writel(regs->fp.r.dmd, par->vid_regs + 0x450);
+ writel(regs->fp.r.crc, par->vid_regs + 0x458);
+ writel(regs->fp.r.fbb, par->vid_regs + 0x460);
+
+ /* Final enables */
+
+ val = readl(par->vid_regs + 0x410);
+
+ /* Control the panel */
+ if (regs->fp.r.pm & (1 << 24)) {
+
+ if (!(val & 0x09))
+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
+ }
+ else {
+ if (!(val & 0x05))
+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
+ }
+
+ /* Turn everything on */
+
+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04);
+ writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00);
+ writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08);
+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08);
+}
+
+
+#ifdef DEBUG
+
+void dump_regs(struct fb_info *info, int mode) {
+
+ struct geodefb_par *par = info->par;
+ u32 val;
+ int i;
+
+ if (mode == 0) {
+ for(i = 0; i < GP_REG_SIZE; i += 4) {
+ val = readl(par->gp_regs + i);
+ }
+ }
+
+ if (mode == 1) {
+ writel(0x4758, par->dc_regs + 0x00);
+
+ for(i = 0; i < DC_REG_SIZE; i += 4) {
+ val = readl(par->dc_regs + i);
+ printk("DC%x: %x\n", i, val);
+ }
+ }
+
+ if (mode == 2) {
+ for(i = 0; i < VP_REG_SIZE; i += 8) {
+ val = readl(par->vid_regs + i);
+ printk("VP%x: %x\n", i, val);
+ }
+ }
+
+ if (mode == 3) {
+ for(i = 0; i < FP_REG_SIZE; i += 8) {
+ val = readl(par->vid_regs + 0x400 + i);
+ printk("FP%x: %x\n", i, val);
+ }
+ }
+}
+
+#endif
diff --git a/target/linux/olpc/files/drivers/video/olpc_dcon.c b/target/linux/olpc/files/drivers/video/olpc_dcon.c
new file mode 100644
index 000000000..d4ef13867
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/olpc_dcon.c
@@ -0,0 +1,824 @@
+/*
+ * Mainly by David Woodhouse, somewhat modified by Jordan Crouse
+ *
+ * Copyright © 2006-2007 Red Hat, Inc.
+ * Copyright © 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software. You can redistribute it and/or
+ * modify it under the terms of version 2 of the GNU General Public
+ * License as published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/fb.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-id.h>
+#include <linux/pci.h>
+#include <linux/vt_kern.h>
+#include <linux/pci_ids.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/backlight.h>
+#include <linux/device.h>
+#include <asm/uaccess.h>
+#include <linux/ctype.h>
+#include <linux/reboot.h>
+#include <asm/tsc.h>
+#include <asm/olpc.h>
+
+#include "olpc_dcon.h"
+
+/* Module definitions */
+
+static int resumeline = 898;
+module_param(resumeline, int, 0444);
+
+static int noinit;
+module_param(noinit, int, 0444);
+
+/* Default off since it doesn't work on DCON ASIC in B-test OLPC board */
+static int useaa = 1;
+module_param(useaa, int, 0444);
+
+/* I2C structures */
+
+static struct i2c_driver dcon_driver;
+static struct i2c_client *dcon_client;
+
+/* Platform devices */
+static struct platform_device *dcon_device;
+
+/* Backlight device */
+static struct backlight_device *dcon_bl_dev;
+
+/* Base address of the GPIO registers */
+static unsigned long gpio_base;
+
+static struct fb_info *fbinfo;
+
+/* Current source, initialized at probe time */
+static int dcon_source;
+
+/* Desired source */
+static int dcon_pending;
+
+/* Current output type */
+static int dcon_output = DCON_OUTPUT_COLOR;
+
+/* Current sleep status (not yet implemented) */
+static int dcon_sleep_val = DCON_ACTIVE;
+
+/* Shadow register for the DCON_REG_MODE register */
+static unsigned short dcon_disp_mode;
+
+/* Variables used during switches */
+static int dcon_switched;
+
+static DECLARE_WAIT_QUEUE_HEAD(dcon_wait_queue);
+
+static unsigned short normal_i2c[] = { 0x0D, I2C_CLIENT_END };
+I2C_CLIENT_INSMOD;
+
+#define dcon_write(reg,val) i2c_smbus_write_word_data(dcon_client,reg,val)
+#define dcon_read(reg) i2c_smbus_read_word_data(dcon_client,reg)
+
+/* The current backlight value - this saves us some smbus traffic */
+static int bl_val = -1;
+
+/* ===== API functions - these are called by a variety of users ==== */
+
+/* Backlight notes - turning off the backlight enable bit in the DCON
+ * doesn't save us any power over just pushing the BL to zero, so we
+ * don't use that bit in this code.
+ */
+
+static int dcon_get_backlight(void)
+{
+ if (dcon_client == NULL)
+ return 0;
+
+ if (bl_val == -1)
+ bl_val = dcon_read(DCON_REG_BRIGHT) & 0x0F;
+
+ return bl_val;
+}
+
+static void dcon_set_backlight(int level)
+{
+ if (dcon_client == NULL)
+ return;
+
+ if (bl_val == (level & 0x0F))
+ return;
+
+ bl_val = level & 0x0F;
+ dcon_write(DCON_REG_BRIGHT, bl_val);
+
+ /* Purposely turn off the backlight when we go to level 0 */
+
+ if (bl_val == 0) {
+ dcon_disp_mode &= ~MODE_BL_ENABLE;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ }
+ else if (!(dcon_disp_mode & MODE_BL_ENABLE)) {
+ dcon_disp_mode |= MODE_BL_ENABLE;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ }
+}
+
+/* Set the output type to either color or mono */
+
+static int dcon_set_output(int arg)
+{
+ if (dcon_output == arg)
+ return 0;
+
+ dcon_output = arg;
+
+ if (arg == DCON_OUTPUT_MONO) {
+ dcon_disp_mode &= ~(MODE_CSWIZZLE | MODE_COL_AA);
+ dcon_disp_mode |= MODE_MONO_LUMA;
+ }
+ else {
+ dcon_disp_mode &= ~(MODE_MONO_LUMA);
+ dcon_disp_mode |= MODE_CSWIZZLE;
+ if (useaa)
+ dcon_disp_mode |= MODE_COL_AA;
+ }
+
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ return 0;
+}
+
+/* For now, this will be really stupid - we need to address how
+ * DCONLOAD works in a sleep and account for it accordingly
+ */
+
+static void dcon_sleep(int state)
+{
+ /* Turn off the backlight and put the DCON to sleep */
+
+ if (state == dcon_sleep_val)
+ return;
+
+ if (state == DCON_SLEEP) {
+ dcon_disp_mode &= ~MODE_BL_ENABLE;
+ dcon_disp_mode |= MODE_SLEEP;
+ }
+ else {
+ /* Only re-enable the backlight if the backlight value is set */
+
+ if (bl_val != 0)
+ dcon_disp_mode |= MODE_BL_ENABLE;
+
+ dcon_disp_mode &= ~MODE_SLEEP;
+ }
+
+ dcon_sleep_val = state;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+
+ /* We should turn off some stuff in the framebuffer - but what? */
+}
+
+/* Set the source of the display (CPU or DCON) */
+
+static void dcon_source_switch(struct work_struct *work)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ int source = dcon_pending;
+
+ if (dcon_source == source)
+ return;
+
+ dcon_switched = 0;
+
+ switch (source) {
+ case DCON_SOURCE_CPU:
+
+ /* Enable the scanline interrupt bit */
+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode | MODE_SCAN_INT))
+ printk(KERN_ERR "olpc-dcon: couldn't enable scanline interrupt!\n");
+ else {
+ /* Wait up to one second for the scanline interrupt */
+ wait_event_timeout(dcon_wait_queue, dcon_switched == 1, HZ);
+ }
+
+ if (!dcon_switched)
+ printk(KERN_ERR "olpc-dcon: Timeout entering CPU mode; expect a screen glitch.\n");
+
+ /*
+ * Ideally we'd like to disable interrupts here so that the
+ * fb_powerup and DCON turn on happen at a known time value;
+ * however, we can't do that right now with fb_set_suspend
+ * messing with semaphores.
+ *
+ * For now, we just hope..
+ */
+ if (fb_powerup(fbinfo)) {
+ printk(KERN_ERR "olpc-dcon: Failed to enter CPU mode\n");
+ dcon_pending = DCON_SOURCE_DCON;
+ return;
+ }
+
+ /* And turn off the DCON */
+ outl(1<<11, gpio_base + GPIOx_OUT_VAL);
+
+ /* Turn off the scanline interrupt */
+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode))
+ printk(KERN_ERR "olpc-dcon: couldn't disable scanline interrupt!\n");
+
+ printk(KERN_INFO "olpc-dcon: The CPU has control\n");
+ break;
+ case DCON_SOURCE_DCON:
+ {
+ int t;
+
+ add_wait_queue(&dcon_wait_queue, &wait);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+
+ /* Clear GPIO11 (DCONLOAD) - this implies that the DCON is in
+ control */
+
+ outl(1 << (11 + 16), gpio_base + GPIOx_OUT_VAL);
+
+ t = schedule_timeout(HZ/2);
+ remove_wait_queue(&dcon_wait_queue, &wait);
+ set_current_state(TASK_RUNNING);
+
+ if (!dcon_switched)
+ printk(KERN_ERR "olpc-dcon: Timeout entering DCON mode; expect a screen glitch.\n");
+
+ /* Turn off the graphics engine completely */
+ fb_powerdown(fbinfo);
+
+ printk(KERN_INFO "olpc-dcon: The DCON has control\n");
+ break;
+ }
+ default:
+ BUG();
+ }
+
+ dcon_source = source;
+}
+
+static DECLARE_WORK(dcon_work, dcon_source_switch);
+
+static int dcon_set_source(int arg)
+{
+ if (arg != DCON_SOURCE_CPU && arg != DCON_SOURCE_DCON)
+ return -EINVAL;
+
+ if (dcon_pending == arg)
+ return 0;
+
+ dcon_pending = arg;
+ if ((dcon_source != arg) && !work_pending(&dcon_work))
+ schedule_work(&dcon_work);
+
+ return 0;
+}
+
+static int dcon_set_source_sync(int arg)
+{
+ int ret = dcon_set_source(arg);
+ if (!ret)
+ flush_scheduled_work();
+ return ret;
+}
+
+static int dconbl_set(struct backlight_device *dev) {
+
+ int level = dev->props.brightness;
+
+ if (dev->props.power != FB_BLANK_UNBLANK)
+ level = 0;
+
+ dcon_set_backlight(level);
+ return 0;
+}
+
+static int dconbl_get(struct backlight_device *dev) {
+ return dcon_get_backlight();
+}
+
+static ssize_t dcon_mode_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%4.4X\n", dcon_disp_mode);
+}
+
+static ssize_t dcon_sleep_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_sleep_val);
+}
+
+static ssize_t /* __deprecated */ dcon_source_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n");
+ return sprintf(buf, "%d\n", dcon_source);
+}
+
+static ssize_t dcon_freeze_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_source == DCON_SOURCE_DCON ? 1 : 0);
+}
+
+static ssize_t dcon_output_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_output);
+}
+
+static ssize_t dcon_resumeline_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", resumeline);
+}
+
+static int _strtoul(const char *buf, int len, unsigned int *val)
+{
+
+ char *endp;
+ unsigned int output = simple_strtoul(buf, &endp, 0);
+ int size = endp - buf;
+
+ if (*endp && isspace(*endp))
+ size++;
+
+ if (size != len)
+ return -EINVAL;
+
+ *val = output;
+ return 0;
+}
+
+static ssize_t dcon_output_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ if (output == DCON_OUTPUT_COLOR || output == DCON_OUTPUT_MONO) {
+ dcon_set_output(output);
+ rc = count;
+ }
+
+ return rc;
+}
+
+static ssize_t /* __deprecated */ dcon_source_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n");
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ dcon_set_source(output);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_freeze_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &output))
+ return rc;
+
+ dcon_set_source(output ? DCON_SOURCE_DCON : DCON_SOURCE_CPU);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_resumeline_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int rl;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &rl))
+ return rc;
+
+ resumeline = rl;
+ dcon_write(DCON_REG_SCAN_INT, resumeline);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_sleep_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ dcon_sleep(output ? DCON_SLEEP : DCON_ACTIVE);
+ return count;
+}
+
+static struct device_attribute dcon_device_files[] = {
+ __ATTR(mode, 0444, dcon_mode_show, NULL),
+ __ATTR(sleep, 0644, dcon_sleep_show, dcon_sleep_store),
+ __ATTR(source, 0644, dcon_source_show, dcon_source_store),
+ __ATTR(freeze, 0644, dcon_freeze_show, dcon_freeze_store),
+ __ATTR(output, 0644, dcon_output_show, dcon_output_store),
+ __ATTR(resumeline, 0644, dcon_resumeline_show, dcon_resumeline_store),
+};
+
+static struct backlight_ops dcon_bl_ops = {
+ .get_brightness = dconbl_get,
+ .update_status = dconbl_set
+};
+
+/* List of GPIOs that we care about:
+ (in) GPIO12 -- DCONBLNK
+ (in) GPIO[56] -- DCONSTAT[01]
+ (out) GPIO11 -- DCONLOAD
+*/
+
+#define IN_GPIOS ((1<<5) | (1<<6) | (1<<7) | (1<<12))
+#define OUT_GPIOS (1<<11)
+
+static irqreturn_t dcon_interrupt(int, void *);
+
+static int dcon_request_irq(void)
+{
+ unsigned long lo, hi;
+ unsigned char lob;
+
+ rdmsr(MSR_LBAR_GPIO, lo, hi);
+
+ /* Check the mask and whether GPIO is enabled (sanity check) */
+ if (hi != 0x0000f001) {
+ printk(KERN_ERR "GPIO not enabled -- cannot use DCON\n");
+ return -ENODEV;
+ }
+
+ /* Mask off the IO base address */
+ gpio_base = lo & 0x0000ff00;
+
+ /* Turn off the event enable for GPIO7 just to be safe */
+ outl(1 << (16+7), gpio_base + GPIOx_EVNT_EN);
+
+ /* Set the directions for the GPIO pins */
+ outl(OUT_GPIOS | (IN_GPIOS << 16), gpio_base + GPIOx_OUT_EN);
+ outl(IN_GPIOS | (OUT_GPIOS << 16), gpio_base + GPIOx_IN_EN);
+
+ /* Set up the interrupt mappings */
+
+ /* Set the IRQ to pair 2 */
+ geode_gpio_event_irq(OLPC_GPIO_DCON_IRQ, 2);
+
+ /* Enable group 2 to trigger the DCON interrupt */
+ geode_gpio_set_irq(2, DCON_IRQ);
+
+ /* Select edge level for interrupt (in PIC) */
+
+ lob = inb(0x4d0);
+ lob &= ~(1 << DCON_IRQ);
+ outb(lob, 0x4d0);
+
+ /* Register the interupt handler */
+ if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", &dcon_driver))
+ return -EIO;
+
+ /* Clear INV_EN for GPIO7 (DCONIRQ) */
+ outl((1<<(16+7)), gpio_base + GPIOx_INV_EN);
+
+ /* Enable filter for GPIO12 (DCONBLANK) */
+ outl(1<<(12), gpio_base + GPIOx_IN_FLTR_EN);
+
+ /* Disable filter for GPIO7 */
+ outl(1<<(16+7), gpio_base + GPIOx_IN_FLTR_EN);
+
+ /* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+
+ outl(1<<(16+7), gpio_base + GPIOx_EVNTCNT_EN);
+ outl(1<<(16+12), gpio_base + GPIOx_EVNTCNT_EN);
+
+ /* Add GPIO12 to the Filter Event Pair #7 */
+ outb(12, gpio_base + GPIO_FE7_SEL);
+
+ /* Turn off negative Edge Enable for GPIO12 */
+ outl(1<<(16+12), gpio_base + GPIOx_NEGEDGE_EN);
+
+ /* Enable negative Edge Enable for GPIO7 */
+ outl(1<<7, gpio_base + GPIOx_NEGEDGE_EN);
+
+ /* Zero the filter amount for Filter Event Pair #7 */
+ outw(0, gpio_base + GPIO_FLT7_AMNT);
+
+ /* Clear the negative edge status for GPIO7 and GPIO12 */
+ outl((1<<7) | (1<<12), gpio_base+0x4c);
+
+ /* FIXME: Clear the posiitive status as well, just to be sure */
+ outl((1<<7) | (1<<12), gpio_base+0x48);
+
+ /* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+ outl((1<<(7))|(1<<12), gpio_base + GPIOx_EVNT_EN);
+
+ /* Determine the current state by reading the GPIO bit */
+ /* Earlier stages of the boot process have established the state */
+ dcon_source = inl(gpio_base + GPIOx_OUT_VAL) & (1<<11)
+ ? DCON_SOURCE_CPU
+ : DCON_SOURCE_DCON;
+ dcon_pending = dcon_source;
+
+ return 0;
+}
+
+static int dcon_reboot_notify(struct notifier_block *nb, unsigned long foo, void *bar)
+{
+ if (dcon_client == NULL)
+ return 0;
+
+ /* Turn off the DCON. Entirely. */
+ dcon_write(DCON_REG_MODE, 0x39);
+ dcon_write(DCON_REG_MODE, 0x32);
+ return 0;
+}
+
+static int dcon_conswitch_notify(struct notifier_block *nb,
+ unsigned long mode, void *dummy)
+{
+ if (mode == CONSOLE_EVENT_SWITCH_TEXT)
+ dcon_sleep(DCON_ACTIVE);
+
+ return 0;
+}
+
+static struct notifier_block dcon_nb = {
+ .notifier_call = dcon_reboot_notify,
+ .priority = -1,
+};
+
+static struct notifier_block dcon_console_nb = {
+ .notifier_call = dcon_conswitch_notify,
+ .priority = -1,
+};
+
+static int dcon_probe(struct i2c_adapter *adap, int addr, int kind)
+{
+ struct i2c_client *client;
+ uint16_t ver;
+ int rc, i;
+
+ if (!olpc_has_dcon()) {
+ printk("olpc-dcon: No DCON is attached.\n");
+ return -ENODEV;
+ }
+
+ if (num_registered_fb >= 1)
+ fbinfo = registered_fb[0];
+
+ if (adap->id != I2C_HW_SMBUS_SCX200) {
+ printk(KERN_ERR "olpc-dcon: Invalid I2C bus (%d not %d)\n",
+ adap->id, I2C_HW_SMBUS_SCX200);
+ return -ENXIO;
+ }
+
+ client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
+ if (client == NULL)
+ return -ENOMEM;
+
+ strncpy(client->name, "OLPC-DCON", I2C_NAME_SIZE);
+ client->addr = addr;
+ client->adapter = adap;
+ client->driver = &dcon_driver;
+
+ if ((rc = i2c_attach_client(client)) != 0) {
+ printk(KERN_ERR "olpc-dcon: Unable to attach the I2C client.\n");
+ goto eclient;
+ }
+
+ ver = i2c_smbus_read_word_data(client, DCON_REG_ID);
+
+ if ((ver >> 8) != 0xDC) {
+ printk(KERN_ERR "olpc-dcon: DCON ID not 0xDCxx: 0x%04x instead.\n", ver);
+ rc = -ENXIO;
+ goto ei2c;
+ }
+
+ if ((rc = dcon_request_irq())) {
+ printk(KERN_ERR "olpc-dcon: Unable to grab IRQ.\n");
+ goto ei2c;
+ }
+
+ if (ver < 0xdc02 && !noinit) {
+ /* Initialize the DCON registers */
+
+ /* Start with work-arounds for DCON ASIC */
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x0b, 0x007a);
+ i2c_smbus_write_word_data(client, 0x36, 0x025c);
+ i2c_smbus_write_word_data(client, 0x37, 0x025e);
+
+ /* Initialise SDRAM */
+
+ i2c_smbus_write_word_data(client, 0x3b, 0x002b);
+ i2c_smbus_write_word_data(client, 0x41, 0x0101);
+ i2c_smbus_write_word_data(client, 0x42, 0x0101);
+ }
+
+ /* Colour swizzle, AA, no passthrough, backlight */
+
+ dcon_disp_mode = MODE_PASSTHRU | MODE_BL_ENABLE | MODE_CSWIZZLE;
+ if (useaa)
+ dcon_disp_mode |= MODE_COL_AA;
+ i2c_smbus_write_word_data(client, DCON_REG_MODE, dcon_disp_mode);
+
+
+ /* Set the scanline to interrupt on during resume */
+
+ i2c_smbus_write_word_data(client, DCON_REG_SCAN_INT, resumeline);
+
+ /* Add the DCON device */
+
+ dcon_device = platform_device_alloc("dcon", -1);
+
+ if (dcon_device == NULL) {
+ printk(KERN_ERR "dcon: Unable to create the DCON device\n");
+ rc = -ENOMEM;
+ goto eirq;
+ }
+
+ if ((rc = platform_device_add(dcon_device))) {
+ printk(KERN_ERR "dcon: Unable to add the DCON device\n");
+ goto edev;
+ }
+
+ for(i = 0; i < ARRAY_SIZE(dcon_device_files); i++)
+ device_create_file(&dcon_device->dev, &dcon_device_files[i]);
+
+ /* Add the backlight device for the DCON */
+
+ dcon_client = client;
+
+ dcon_bl_dev = backlight_device_register("dcon-bl", &dcon_device->dev,
+ NULL, &dcon_bl_ops);
+
+ if (IS_ERR(dcon_bl_dev)) {
+ printk(KERN_INFO "Could not register the backlight device for the DCON (%ld)\n", PTR_ERR(dcon_bl_dev));
+ dcon_bl_dev = NULL;
+ }
+ else {
+ dcon_bl_dev->props.max_brightness = 15;
+ dcon_bl_dev->props.power = FB_BLANK_UNBLANK;
+ dcon_bl_dev->props.brightness = dcon_get_backlight();
+
+ backlight_update_status(dcon_bl_dev);
+ }
+
+ register_reboot_notifier(&dcon_nb);
+ console_event_register(&dcon_console_nb);
+
+ printk(KERN_INFO "olpc-dcon: Discovered DCON version %x\n", ver & 0xFF);
+
+ return 0;
+
+ edev:
+ platform_device_unregister(dcon_device);
+ dcon_device = NULL;
+ eirq:
+ free_irq(DCON_IRQ, &dcon_driver);
+ ei2c:
+ i2c_detach_client(client);
+ eclient:
+ kfree(client);
+
+ return rc;
+}
+
+static int dcon_attach(struct i2c_adapter *adap)
+{
+ int ret;
+
+ ret = i2c_probe(adap, &addr_data, dcon_probe);
+
+ if (dcon_client == NULL)
+ printk(KERN_ERR "olpc-dcon: No DCON found on SMBus\n");
+
+ return ret;
+}
+
+static int dcon_detach(struct i2c_client *client)
+{
+ int rc;
+ dcon_client = NULL;
+
+ unregister_reboot_notifier(&dcon_nb);
+ console_event_unregister(&dcon_console_nb);
+
+ free_irq(DCON_IRQ, &dcon_driver);
+
+ if ((rc = i2c_detach_client(client)) == 0)
+ kfree(i2c_get_clientdata(client));
+
+ if (dcon_bl_dev != NULL)
+ backlight_device_unregister(dcon_bl_dev);
+
+ if (dcon_device != NULL)
+ platform_device_unregister(dcon_device);
+ cancel_work_sync(&dcon_work);
+
+ return rc;
+}
+
+
+#ifdef CONFIG_PM
+static int dcon_suspend(struct i2c_client *client, pm_message_t state)
+{
+ if (dcon_sleep_val != DCON_ACTIVE)
+ return 0;
+
+ /* Set up the DCON to have the source */
+ return dcon_set_source_sync(DCON_SOURCE_DCON);
+}
+
+static int dcon_resume(struct i2c_client *client)
+{
+ int x;
+ if (dcon_sleep_val != DCON_ACTIVE)
+ return 0;
+
+ /* HACK: ensure the bus is stable */
+ do {
+ x = dcon_read(DCON_REG_ID);
+ } while (x < 0);
+
+ return dcon_set_source(DCON_SOURCE_CPU);
+}
+
+#endif
+
+static irqreturn_t dcon_interrupt(int irq, void *id)
+{
+ int status = inl(gpio_base + GPIOx_READ_BACK) >> 5;
+
+ /* Clear the negative edge status for GPIO7 */
+ outl(1 << 7, gpio_base + GPIOx_NEGEDGE_STS);
+
+ switch (status & 3) {
+ case 3:
+ printk(KERN_DEBUG "olpc-dcon: DCONLOAD_MISSED interrupt\n");
+ break;
+ case 2: /* switch to DCON mode */
+ case 1: /* switch to CPU mode */
+ dcon_switched = 1;
+ wake_up(&dcon_wait_queue);
+ break;
+ case 0:
+ printk(KERN_DEBUG "olpc-dcon: scanline interrupt w/CPU\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct i2c_driver dcon_driver = {
+ .driver = {
+ .name = "OLPC-DCON",
+ },
+ .id = I2C_DRIVERID_DCON,
+ .attach_adapter = dcon_attach,
+ .detach_client = dcon_detach,
+#ifdef CONFIG_PM
+ .suspend = dcon_suspend,
+ .resume = dcon_resume,
+#endif
+};
+
+
+static int __init olpc_dcon_init(void)
+{
+ i2c_add_driver(&dcon_driver);
+ return 0;
+}
+
+static void __exit olpc_dcon_exit(void)
+{
+ i2c_del_driver(&dcon_driver);
+}
+
+module_init(olpc_dcon_init);
+module_exit(olpc_dcon_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/target/linux/olpc/files/drivers/video/olpc_dcon.h b/target/linux/olpc/files/drivers/video/olpc_dcon.h
new file mode 100644
index 000000000..6453ca4ba
--- /dev/null
+++ b/target/linux/olpc/files/drivers/video/olpc_dcon.h
@@ -0,0 +1,75 @@
+#ifndef OLPC_DCON_H_
+#define OLPC_DCON_H_
+
+/* DCON registers */
+
+#define DCON_REG_ID 0
+#define DCON_REG_MODE 1
+
+#define MODE_PASSTHRU (1<<0)
+#define MODE_SLEEP (1<<1)
+#define MODE_SLEEP_AUTO (1<<2)
+#define MODE_BL_ENABLE (1<<3)
+#define MODE_BLANK (1<<4)
+#define MODE_CSWIZZLE (1<<5)
+#define MODE_COL_AA (1<<6)
+#define MODE_MONO_LUMA (1<<7)
+#define MODE_SCAN_INT (1<<8)
+#define MODE_CLOCKDIV (1<<9)
+#define MODE_DEBUG (1<<14)
+#define MODE_SELFTEST (1<<15)
+
+#define DCON_REG_HRES 2
+#define DCON_REG_HTOTAL 3
+#define DCON_REG_HSYNC_WIDTH 4
+#define DCON_REG_VRES 5
+#define DCON_REG_VTOTAL 6
+#define DCON_REG_VSYNC_WIDTH 7
+#define DCON_REG_TIMEOUT 8
+#define DCON_REG_SCAN_INT 9
+#define DCON_REG_BRIGHT 10
+
+/* GPIO registers (CS5536) */
+
+#define MSR_LBAR_GPIO 0x5140000C
+
+#define GPIOx_OUT_VAL 0x00
+#define GPIOx_OUT_EN 0x04
+#define GPIOx_IN_EN 0x20
+#define GPIOx_INV_EN 0x24
+#define GPIOx_IN_FLTR_EN 0x28
+#define GPIOx_EVNTCNT_EN 0x2C
+#define GPIOx_READ_BACK 0x30
+#define GPIOx_EVNT_EN 0x38
+#define GPIOx_NEGEDGE_EN 0x44
+#define GPIOx_NEGEDGE_STS 0x4C
+#define GPIO_FLT7_AMNT 0xD8
+#define GPIO_MAP_X 0xE0
+#define GPIO_MAP_Y 0xE4
+#define GPIO_FE7_SEL 0xF7
+
+
+/* Status values */
+
+#define DCONSTAT_SCANINT 0
+#define DCONSTAT_SCANINT_DCON 1
+#define DCONSTAT_DISPLAYLOAD 2
+#define DCONSTAT_MISSED 3
+
+/* Source values */
+
+#define DCON_SOURCE_DCON 0
+#define DCON_SOURCE_CPU 1
+
+/* Output values */
+#define DCON_OUTPUT_COLOR 0
+#define DCON_OUTPUT_MONO 1
+
+/* Sleep values */
+#define DCON_ACTIVE 0
+#define DCON_SLEEP 1
+
+/* Interrupt */
+#define DCON_IRQ 6
+
+#endif