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authorflorian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-01-17 22:29:13 +0000
committerflorian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>2013-01-17 22:29:13 +0000
commit0356f8631af0de5023269a7073b52ad6f98debd9 (patch)
tree28aaf81b887b4bcd8212e99aee3297f411265556 /target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch
parent47411308694ea2ad590808f778b5736e4ebd58b1 (diff)
mvebu: add preliminary support for PCI express
Signed-off-by: Florian Fainelli <florian@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35211 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch')
-rw-r--r--target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch44
1 files changed, 44 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch b/target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch
new file mode 100644
index 000000000..af15d4b85
--- /dev/null
+++ b/target/linux/mvebu/patches-3.8/040-arm_mvebu_add_pcie_axp_db.patch
@@ -0,0 +1,44 @@
+The Marvell evaluation board (DB) for the Armada XP SoC has 6
+physicals full-size PCIe slots, so we enable the corresponding PCIe
+interfaces in the Device Tree.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/armada-xp-db.dts | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm/boot/dts/armada-xp-db.dts
++++ b/arch/arm/boot/dts/armada-xp-db.dts
+@@ -109,5 +109,32 @@
+ usb@d0052000 {
+ status = "okay";
+ };
++
++ pcie-controller {
++ status = "okay";
++
++ /*
++ * All 6 slots are physically present as
++ * standard PCIe slots on the board.
++ */
++ pcie0.0@0xd0040000 {
++ status = "okay";
++ };
++ pcie0.1@0xd0044000 {
++ status = "okay";
++ };
++ pcie0.2@0xd0048000 {
++ status = "okay";
++ };
++ pcie0.3@0xd004C000 {
++ status = "okay";
++ };
++ pcie2@0xd0042000 {
++ status = "okay";
++ };
++ pcie3@0xd0082000 {
++ status = "okay";
++ };
++ };
+ };
+ };