diff options
| author | wbx <wbx@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2005-08-28 22:19:09 +0000 |
|---|---|---|
| committer | wbx <wbx@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2005-08-28 22:19:09 +0000 |
| commit | f8968501098182115a67b4d7bf664aec680cb356 (patch) | |
| tree | 35bf45631fbfb49931cba9b140a91c2128044251 /target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch | |
| parent | 8c1fd3fc2df82ae8290be58900f7bd7a4aeb6d0e (diff) | |
add squashfs 2.2 for kernel 2.6, cleanup broadcom patch, remove .orig files
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@1777 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch')
| -rw-r--r-- | target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch | 6692 |
1 files changed, 0 insertions, 6692 deletions
diff --git a/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch b/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch index 2e9bca7a1..3a4f78fc9 100644 --- a/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch +++ b/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch @@ -26,1672 +26,6 @@ diff -Nur linux-2.6.12.5/arch/mips/Kconfig linux-2.6.12.5-brcm/arch/mips/Kconfig default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 help Some MIPS machines can be configured for either little or big endian -diff -Nur linux-2.6.12.5/arch/mips/Kconfig.orig linux-2.6.12.5-brcm/arch/mips/Kconfig.orig ---- linux-2.6.12.5/arch/mips/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.12.5-brcm/arch/mips/Kconfig.orig 2005-08-15 02:20:18.000000000 +0200 -@@ -0,0 +1,1662 @@ -+config MIPS -+ bool -+ default y -+ # Horrible source of confusion. Die, die, die ... -+ select EMBEDDED -+ -+config MIPS64 -+ bool "64-bit kernel" -+ help -+ Select this option if you want to build a 64-bit kernel. You should -+ only select this option if you have hardware that actually has a -+ 64-bit processor and if your application will actually benefit from -+ 64-bit processing, otherwise say N. You must say Y for kernels for -+ SGI IP27 (Origin 200 and 2000) and SGI IP32 (O2). If in doubt say N. -+ -+config 64BIT -+ def_bool MIPS64 -+ -+config MIPS32 -+ bool -+ depends on MIPS64 = 'n' -+ default y -+ -+mainmenu "Linux/MIPS Kernel Configuration" -+ -+source "init/Kconfig" -+ -+menu "Machine selection" -+ -+config MACH_JAZZ -+ bool "Support for the Jazz family of machines" -+ select ARC -+ select ARC32 -+ select GENERIC_ISA_DMA -+ select I8259 -+ select ISA -+ help -+ This a family of machines based on the MIPS R4030 chipset which was -+ used by several vendors to build RISC/os and Windows NT workstations. -+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and -+ Olivetti M700-10 workstations. -+ -+config ACER_PICA_61 -+ bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" -+ depends on MACH_JAZZ && EXPERIMENTAL -+ select DMA_NONCOHERENT -+ help -+ This is a machine with a R4400 133/150 MHz CPU. To compile a Linux -+ kernel that runs on these, say Y here. For details about Linux on -+ the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at -+ <http://www.linux-mips.org/>. -+ -+config MIPS_MAGNUM_4000 -+ bool "Support for MIPS Magnum 4000" -+ depends on MACH_JAZZ -+ select DMA_NONCOHERENT -+ help -+ This is a machine with a R4000 100 MHz CPU. To compile a Linux -+ kernel that runs on these, say Y here. For details about Linux on -+ the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at -+ <http://www.linux-mips.org/>. -+ -+config OLIVETTI_M700 -+ bool "Support for Olivetti M700-10" -+ depends on MACH_JAZZ -+ select DMA_NONCOHERENT -+ help -+ This is a machine with a R4000 100 MHz CPU. To compile a Linux -+ kernel that runs on these, say Y here. For details about Linux on -+ the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at -+ <http://www.linux-mips.org/>. -+ -+config MACH_VR41XX -+ bool "Support for NEC VR41XX-based machines" -+ -+config NEC_CMBVR4133 -+ bool "Support for NEC CMB-VR4133" -+ depends on MACH_VR41XX -+ select CPU_VR41XX -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select HW_HAS_PCI -+ select PCI_VR41XX -+ -+config ROCKHOPPER -+ bool "Support for Rockhopper baseboard" -+ depends on NEC_CMBVR4133 -+ select I8259 -+ select HAVE_STD_PC_SERIAL_PORT -+ -+config CASIO_E55 -+ bool "Support for CASIO CASSIOPEIA E-10/15/55/65" -+ depends on MACH_VR41XX -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select ISA -+ -+config IBM_WORKPAD -+ bool "Support for IBM WorkPad z50" -+ depends on MACH_VR41XX -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select ISA -+ -+config TANBAC_TB0226 -+ bool "Support for TANBAC TB0226 (Mbase)" -+ depends on MACH_VR41XX -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ help -+ The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC. -+ Please refer to <http://www.tanbac.co.jp/> about Mbase. -+ -+config TANBAC_TB0229 -+ bool "Support for TANBAC TB0229 (VR4131DIMM)" -+ depends on MACH_VR41XX -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ help -+ The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC. -+ Please refer to <http://www.tanbac.co.jp/> about VR4131DIMM. -+ -+config VICTOR_MPC30X -+ bool "Support for Victor MP-C303/304" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ depends on MACH_VR41XX -+ -+config ZAO_CAPCELLA -+ bool "Support for ZAO Networks Capcella" -+ depends on MACH_VR41XX -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ -+config PCI_VR41XX -+ bool "Add PCI control unit support of NEC VR4100 series" -+ depends on MACH_VR41XX && PCI -+ -+config VRC4171 -+ tristate "Add NEC VRC4171 companion chip support" -+ depends on MACH_VR41XX && ISA -+ ---help--- -+ The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121. -+ -+config VRC4173 -+ tristate "Add NEC VRC4173 companion chip support" -+ depends on MACH_VR41XX && PCI_VR41XX -+ ---help--- -+ The NEC VRC4173 is a companion chip for NEC VR4122/VR4131. -+ -+config TOSHIBA_JMR3927 -+ bool "Support for Toshiba JMR-TX3927 board" -+ depends on MIPS32 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select SWAP_IO_SPACE -+ -+config MIPS_COBALT -+ bool "Support for Cobalt Server (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select I8259 -+ select IRQ_CPU -+ -+config MACH_DECSTATION -+ bool "Support for DECstations" -+ select BOOT_ELF32 -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ depends on MIPS32 || EXPERIMENTAL -+ ---help--- -+ This enables support for DEC's MIPS based workstations. For details -+ see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the -+ DECstation porting pages on <http://decstation.unix-ag.org/>. -+ -+ If you have one of the following DECstation Models you definitely -+ want to choose R4xx0 for the CPU Type: -+ -+ DECstation 5000/50 -+ DECstation 5000/150 -+ DECstation 5000/260 -+ DECsystem 5900/260 -+ -+ otherwise choose R3000. -+ -+config MIPS_EV64120 -+ bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select MIPS_GT64120 -+ help -+ This is an evaluation board based on the Galileo GT-64120 -+ single-chip system controller that contains a MIPS R5000 compatible -+ core running at 75/100MHz. Their website is located at -+ <http://www.marvell.com/>. Say Y here if you wish to build a -+ kernel for this platform. -+ -+config EVB_PCI1 -+ bool "Enable Second PCI (PCI1)" -+ depends on MIPS_EV64120 -+ -+config MIPS_EV96100 -+ bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select MIPS_GT96100 -+ select RM7000_CPU_SCACHE -+ select SWAP_IO_SPACE -+ help -+ This is an evaluation board based on the Galileo GT-96100 LAN/WAN -+ communications controllers containing a MIPS R5000 compatible core -+ running at 83MHz. Their website is <http://www.marvell.com/>. Say Y -+ here if you wish to build a kernel for this platform. -+ -+config MIPS_IVR -+ bool "Support for Globespan IVR board" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ help -+ This is an evaluation board built by Globespan to showcase thir -+ iVR (Internet Video Recorder) design. It utilizes a QED RM5231 -+ R5000 MIPS core. More information can be found out their website -+ located at <http://www.globespan.net/>. Say Y here if you wish to -+ build a kernel for this platform. -+ -+config LASAT -+ bool "Support for LASAT Networks platforms" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select MIPS_GT64120 -+ select R5000_CPU_SCACHE -+ -+config PICVUE -+ tristate "PICVUE LCD display driver" -+ depends on LASAT -+ -+config PICVUE_PROC -+ tristate "PICVUE LCD display driver /proc interface" -+ depends on PICVUE -+ -+config DS1603 -+ bool "DS1603 RTC driver" -+ depends on LASAT -+ -+config LASAT_SYSCTL -+ bool "LASAT sysctl interface" -+ depends on LASAT -+ -+config MIPS_ITE8172 -+ bool "Support for ITE 8172G board" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ help -+ Ths is an evaluation board made by ITE <http://www.ite.com.tw/> -+ with ATX form factor that utilizes a MIPS R5000 to work with its -+ ITE8172G companion internet appliance chip. The MIPS core can be -+ either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build -+ a kernel for this platform. -+ -+config IT8172_REVC -+ bool "Support for older IT8172 (Rev C)" -+ depends on MIPS_ITE8172 -+ help -+ Say Y here to support the older, Revision C version of the Integrated -+ Technology Express, Inc. ITE8172 SBC. Vendor page at -+ <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the -+ board at <http://www.mvista.com/partners/semiconductor/ite.html>. -+ -+config MIPS_ATLAS -+ bool "Support for MIPS Atlas board" -+ select BOOT_ELF32 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select MIPS_GT64120 -+ select SWAP_IO_SPACE -+ help -+ This enables support for the QED R5231-based MIPS Atlas evaluation -+ board. -+ -+config MIPS_MALTA -+ bool "Support for MIPS Malta board" -+ select BOOT_ELF32 -+ select HAVE_STD_PC_SERIAL_PORT -+ select DMA_NONCOHERENT -+ select GENERIC_ISA_DMA -+ select HW_HAS_PCI -+ select I8259 -+ select MIPS_GT64120 -+ select SWAP_IO_SPACE -+ help -+ This enables support for the VR5000-based MIPS Malta evaluation -+ board. -+ -+config MIPS_SEAD -+ bool "Support for MIPS SEAD board (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select IRQ_CPU -+ select DMA_NONCOHERENT -+ -+config MOMENCO_OCELOT -+ bool "Support for Momentum Ocelot board" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select IRQ_CPU_RM7K -+ select MIPS_GT64120 -+ select RM7000_CPU_SCACHE -+ select SWAP_IO_SPACE -+ help -+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by -+ Momentum Computer <http://www.momenco.com/>. -+ -+config MOMENCO_OCELOT_G -+ bool "Support for Momentum Ocelot-G board" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select IRQ_CPU_RM7K -+ select PCI_MARVELL -+ select RM7000_CPU_SCACHE -+ select SWAP_IO_SPACE -+ help -+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by -+ Momentum Computer <http://www.momenco.com/>. -+ -+config MOMENCO_OCELOT_C -+ bool "Support for Momentum Ocelot-C board" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select IRQ_MV64340 -+ select PCI_MARVELL -+ select RM7000_CPU_SCACHE -+ select SWAP_IO_SPACE -+ help -+ The Ocelot is a MIPS-based Single Board Computer (SBC) made by -+ Momentum Computer <http://www.momenco.com/>. -+ -+config MOMENCO_OCELOT_3 -+ bool "Support for Momentum Ocelot-3 board" -+ select BOOT_ELF32 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select IRQ_CPU_RM7K -+ select IRQ_MV64340 -+ select PCI_MARVELL -+ select RM7000_CPU_SCACHE -+ select SWAP_IO_SPACE -+ help -+ The Ocelot-3 is based off Discovery III System Controller and -+ PMC-Sierra Rm79000 core. -+ -+config MOMENCO_JAGUAR_ATX -+ bool "Support for Momentum Jaguar board" -+ select BOOT_ELF32 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select IRQ_CPU_RM7K -+ select IRQ_MV64340 -+ select LIMITED_DMA -+ select PCI_MARVELL -+ select RM7000_CPU_SCACHE -+ select SWAP_IO_SPACE -+ help -+ The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by -+ Momentum Computer <http://www.momenco.com/>. -+ -+config JAGUAR_DMALOW -+ bool "Low DMA Mode" -+ depends on MOMENCO_JAGUAR_ATX -+ help -+ Select to Y if jump JP5 is set on your board, N otherwise. Normally -+ the jumper is set, so if you feel unsafe, just say Y. -+ -+config PMC_YOSEMITE -+ bool "Support for PMC-Sierra Yosemite eval board" -+ select DMA_COHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select IRQ_CPU_RM7K -+ select IRQ_CPU_RM9K -+ select SWAP_IO_SPACE -+ help -+ Yosemite is an evaluation board for the RM9000x2 processor -+ manufactured by PMC-Sierra -+ -+config HYPERTRANSPORT -+ bool "Hypertransport Support for PMC-Sierra Yosemite" -+ depends on PMC_YOSEMITE -+ -+config DDB5074 -+ bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select DMA_NONCOHERENT -+ select HAVE_STD_PC_SERIAL_PORT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select I8259 -+ select ISA -+ help -+ This enables support for the VR5000-based NEC DDB Vrc-5074 -+ evaluation board. -+ -+config DDB5476 -+ bool "Support for NEC DDB Vrc-5476" -+ select DMA_NONCOHERENT -+ select HAVE_STD_PC_SERIAL_PORT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select I8259 -+ select ISA -+ help -+ This enables support for the R5432-based NEC DDB Vrc-5476 -+ evaluation board. -+ -+ Features : kernel debugging, serial terminal, NFS root fs, on-board -+ ether port USB, AC97, PCI, PCI VGA card & framebuffer console, -+ IDE controller, PS2 keyboard, PS2 mouse, etc. -+ -+config DDB5477 -+ bool "Support for NEC DDB Vrc-5477" -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select I8259 -+ select IRQ_CPU -+ help -+ This enables support for the R5432-based NEC DDB Vrc-5477, -+ or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. -+ -+ Features : kernel debugging, serial terminal, NFS root fs, on-board -+ ether port USB, AC97, PCI, etc. -+ -+config DDB5477_BUS_FREQUENCY -+ int "bus frequency (in kHZ, 0 for auto-detect)" -+ depends on DDB5477 -+ default 0 -+ -+config NEC_OSPREY -+ bool "Support for NEC Osprey board" -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ -+config SGI_IP22 -+ bool "Support for SGI IP22 (Indy/Indigo2)" -+ select ARC -+ select ARC32 -+ select BOOT_ELF32 -+ select DMA_NONCOHERENT -+ select IP22_CPU_SCACHE -+ select IRQ_CPU -+ select SWAP_IO_SPACE -+ help -+ This are the SGI Indy, Challenge S and Indigo2, as well as certain -+ OEM variants like the Tandem CMN B006S. To compile a Linux kernel -+ that runs on these, say Y here. -+ -+config SGI_IP27 -+ bool "Support for SGI IP27 (Origin200/2000)" -+ depends on MIPS64 -+ select ARC -+ select ARC64 -+ select DMA_IP27 -+ select HW_HAS_PCI -+ select PCI_DOMAINS -+ help -+ This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics -+ workstations. To compile a Linux kernel that runs on these, say Y -+ here. -+ -+#config SGI_SN0_XXL -+# bool "IP27 XXL" -+# depends on SGI_IP27 -+# This options adds support for userspace processes upto 16TB size. -+# Normally the limit is just .5TB. -+ -+config SGI_SN0_N_MODE -+ bool "IP27 N-Mode" -+ depends on SGI_IP27 -+ help -+ The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be -+ configured in either N-Modes which allows for more nodes or M-Mode -+ which allows for more memory. Your system is most probably -+ running in M-Mode, so you should say N here. -+ -+config DISCONTIGMEM -+ bool -+ default y if SGI_IP27 -+ help -+ Say Y to upport efficient handling of discontiguous physical memory, -+ for architectures which are either NUMA (Non-Uniform Memory Access) -+ or have huge holes in the physical address space for other reasons. -+ See <file:Documentation/vm/numa> for more. -+ -+config NUMA -+ bool "NUMA Support" -+ depends on SGI_IP27 -+ help -+ Say Y to compile the kernel to support NUMA (Non-Uniform Memory -+ Access). This option is for configuring high-end multiprocessor -+ server machines. If in doubt, say N. -+ -+config MAPPED_KERNEL -+ bool "Mapped kernel support" -+ depends on SGI_IP27 -+ help -+ Change the way a Linux kernel is loaded into memory on a MIPS64 -+ machine. This is required in order to support text replication and -+ NUMA. If you need to understand it, read the source code. -+ -+config REPLICATE_KTEXT -+ bool "Kernel text replication support" -+ depends on SGI_IP27 -+ help -+ Say Y here to enable replicating the kernel text across multiple -+ nodes in a NUMA cluster. This trades memory for speed. -+ -+config REPLICATE_EXHANDLERS -+ bool "Exception handler replication support" -+ depends on SGI_IP27 -+ help -+ Say Y here to enable replicating the kernel exception handlers -+ across multiple nodes in a NUMA cluster. This trades memory for -+ speed. -+ -+config SGI_IP32 -+ bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" -+ depends on MIPS64 && EXPERIMENTAL -+ select ARC -+ select ARC32 -+ select BOOT_ELF32 -+ select OWN_DMA -+ select DMA_IP32 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select R5000_CPU_SCACHE -+ select RM7000_CPU_SCACHE -+ help -+ If you want this kernel to run on SGI O2 workstation, say Y here. -+ -+config SOC_AU1X00 -+ depends on MIPS32 -+ bool "Support for AMD/Alchemy Au1X00 SOCs" -+ -+choice -+ prompt "Au1X00 SOC Type" -+ depends on SOC_AU1X00 -+ help -+ Say Y here to enable support for one of three AMD/Alchemy -+ SOCs. For additional documentation see www.amd.com. -+ -+config SOC_AU1000 -+ bool "SOC_AU1000" -+config SOC_AU1100 -+ bool "SOC_AU1100" -+config SOC_AU1500 -+ bool "SOC_AU1500" -+config SOC_AU1550 -+ bool "SOC_AU1550" -+ -+endchoice -+ -+choice -+ prompt "AMD/Alchemy Au1x00 board support" -+ depends on SOC_AU1X00 -+ help -+ These are evaluation boards built by AMD/Alchemy to -+ showcase their Au1X00 Internet Edge Processors. The SOC design -+ is based on the MIPS32 architecture running at 266/400/500MHz -+ with many integrated peripherals. Further information can be -+ found at their website, <http://www.amd.com/>. Say Y here if you -+ wish to build a kernel for this platform. -+ -+config MIPS_PB1000 -+ bool "PB1000 board" -+ depends on SOC_AU1000 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select SWAP_IO_SPACE -+ -+config MIPS_PB1100 -+ bool "PB1100 board" -+ depends on SOC_AU1100 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select SWAP_IO_SPACE -+ -+config MIPS_PB1500 -+ bool "PB1500 board" -+ depends on SOC_AU1500 -+ select DMA_COHERENT -+ select HW_HAS_PCI -+ -+config MIPS_PB1550 -+ bool "PB1550 board" -+ depends on SOC_AU1550 -+ select DMA_COHERENT -+ select HW_HAS_PCI -+ select MIPS_DISABLE_OBSOLETE_IDE -+ -+config MIPS_DB1000 -+ bool "DB1000 board" -+ depends on SOC_AU1000 -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ -+config MIPS_DB1100 -+ bool "DB1100 board" -+ depends on SOC_AU1100 -+ select DMA_NONCOHERENT -+ -+config MIPS_DB1500 -+ bool "DB1500 board" -+ depends on SOC_AU1500 -+ select DMA_COHERENT -+ select HW_HAS_PCI -+ select MIPS_DISABLE_OBSOLETE_IDE -+ -+config MIPS_DB1550 -+ bool "DB1550 board" -+ depends on SOC_AU1550 -+ select HW_HAS_PCI -+ select DMA_COHERENT -+ select MIPS_DISABLE_OBSOLETE_IDE -+ -+config MIPS_BOSPORUS -+ bool "Bosporus board" -+ depends on SOC_AU1500 -+ select DMA_NONCOHERENT -+ -+config MIPS_MIRAGE -+ bool "Mirage board" -+ depends on SOC_AU1500 -+ select DMA_NONCOHERENT -+ -+config MIPS_XXS1500 -+ bool "MyCable XXS1500 board" -+ depends on SOC_AU1500 -+ select DMA_NONCOHERENT -+ -+config MIPS_MTX1 -+ bool "4G Systems MTX-1 board" -+ depends on SOC_AU1500 -+ select HW_HAS_PCI -+ select DMA_NONCOHERENT -+ -+endchoice -+ -+config SIBYTE_SB1xxx_SOC -+ bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select BOOT_ELF32 -+ select DMA_COHERENT -+ select SWAP_IO_SPACE -+ -+choice -+ prompt "BCM1xxx SOC-based board" -+ depends on SIBYTE_SB1xxx_SOC -+ default SIBYTE_SWARM -+ help -+ Enable support for boards based on the SiByte line of SOCs -+ from Broadcom. There are configurations for the known -+ evaluation boards, or you can choose "Other" and add your -+ own board support code. -+ -+config SIBYTE_SWARM -+ bool "BCM91250A-SWARM" -+ select SIBYTE_SB1250 -+ -+config SIBYTE_SENTOSA -+ bool "BCM91250E-Sentosa" -+ select SIBYTE_SB1250 -+ -+config SIBYTE_RHONE -+ bool "BCM91125E-Rhone" -+ select SIBYTE_BCM1125H -+ -+config SIBYTE_CARMEL -+ bool "BCM91120x-Carmel" -+ select SIBYTE_BCM1120 -+ -+config SIBYTE_PTSWARM -+ bool "BCM91250PT-PTSWARM" -+ select SIBYTE_SB1250 -+ -+config SIBYTE_LITTLESUR -+ bool "BCM91250C2-LittleSur" -+ select SIBYTE_SB1250 -+ -+config SIBYTE_CRHINE -+ bool "BCM91120C-CRhine" -+ select SIBYTE_BCM1120 -+ -+config SIBYTE_CRHONE -+ bool "BCM91125C-CRhone" -+ select SIBYTE_BCM1125 -+ -+config SIBYTE_UNKNOWN -+ bool "Other" -+ -+endchoice -+ -+config SIBYTE_BOARD -+ bool -+ depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN -+ default y -+ -+choice -+ prompt "BCM1xxx SOC Type" -+ depends on SIBYTE_UNKNOWN -+ default SIBYTE_UNK_BCM1250 -+ help -+ Since you haven't chosen a known evaluation board from -+ Broadcom, you must explicitly pick the SOC this kernel is -+ targetted for. -+ -+config SIBYTE_UNK_BCM1250 -+ bool "BCM1250" -+ select SIBYTE_SB1250 -+ -+config SIBYTE_UNK_BCM1120 -+ bool "BCM1120" -+ select SIBYTE_BCM1120 -+ -+config SIBYTE_UNK_BCM1125 -+ bool "BCM1125" -+ select SIBYTE_BCM1125 -+ -+config SIBYTE_UNK_BCM1125H -+ bool "BCM1125H" -+ select SIBYTE_BCM1125H -+ -+endchoice -+ -+config SIBYTE_SB1250 -+ bool -+ select HW_HAS_PCI -+ -+config SIBYTE_BCM1120 -+ bool -+ select SIBYTE_BCM112X -+ -+config SIBYTE_BCM1125 -+ bool -+ select HW_HAS_PCI -+ select SIBYTE_BCM112X -+ -+config SIBYTE_BCM1125H -+ bool -+ select HW_HAS_PCI -+ select SIBYTE_BCM112X -+ -+config SIBYTE_BCM112X -+ bool -+ -+choice -+ prompt "SiByte SOC Stepping" -+ depends on SIBYTE_SB1xxx_SOC -+ -+config CPU_SB1_PASS_1 -+ bool "1250 Pass1" -+ depends on SIBYTE_SB1250 -+ select CPU_HAS_PREFETCH -+ -+config CPU_SB1_PASS_2_1250 -+ bool "1250 An" -+ depends on SIBYTE_SB1250 -+ select CPU_SB1_PASS_2 -+ help -+ Also called BCM1250 Pass 2 -+ -+config CPU_SB1_PASS_2_2 -+ bool "1250 Bn" -+ depends on SIBYTE_SB1250 -+ select CPU_HAS_PREFETCH -+ help -+ Also called BCM1250 Pass 2.2 -+ -+config CPU_SB1_PASS_4 -+ bool "1250 Cn" -+ depends on SIBYTE_SB1250 -+ select CPU_HAS_PREFETCH -+ help -+ Also called BCM1250 Pass 3 -+ -+config CPU_SB1_PASS_2_112x -+ bool "112x Hybrid" -+ depends on SIBYTE_BCM112X -+ select CPU_SB1_PASS_2 -+ -+config CPU_SB1_PASS_3 -+ bool "112x An" -+ depends on SIBYTE_BCM112X -+ select CPU_HAS_PREFETCH -+ -+endchoice -+ -+config CPU_SB1_PASS_2 -+ bool -+ -+config SIBYTE_HAS_LDT -+ bool -+ depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) -+ default y -+ -+config SIMULATION -+ bool "Running under simulation" -+ depends on SIBYTE_SB1xxx_SOC -+ help -+ Build a kernel suitable for running under the GDB simulator. -+ Primarily adjusts the kernel's notion of time. -+ -+config SIBYTE_CFE -+ bool "Booting from CFE" -+ depends on SIBYTE_SB1xxx_SOC -+ help -+ Make use of the CFE API for enumerating available memory, -+ controlling secondary CPUs, and possibly console output. -+ -+config SIBYTE_CFE_CONSOLE -+ bool "Use firmware console" -+ depends on SIBYTE_CFE -+ help -+ Use the CFE API's console write routines during boot. Other console -+ options (VT console, sb1250 duart console, etc.) should not be -+ configured. -+ -+config SIBYTE_STANDALONE -+ bool -+ depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE -+ default y -+ -+config SIBYTE_STANDALONE_RAM_SIZE -+ int "Memory size (in megabytes)" -+ depends on SIBYTE_STANDALONE -+ default "32" -+ -+config SIBYTE_BUS_WATCHER -+ bool "Support for Bus Watcher statistics" -+ depends on SIBYTE_SB1xxx_SOC -+ help -+ Handle and keep statistics on the bus error interrupts (COR_ECC, -+ BAD_ECC, IO_BUS). -+ -+config SIBYTE_BW_TRACE -+ bool "Capture bus trace before bus error" -+ depends on SIBYTE_BUS_WATCHER -+ help -+ Run a continuous bus trace, dumping the raw data as soon as -+ a ZBbus error is detected. Cannot work if ZBbus profiling -+ is turned on, and also will interfere with JTAG-based trace -+ buffer activity. Raw buffer data is dumped to console, and -+ must be processed off-line. -+ -+config SIBYTE_SB1250_PROF -+ bool "Support for SB1/SOC profiling - SB1/SCD perf counters" -+ depends on SIBYTE_SB1xxx_SOC -+ -+config SIBYTE_TBPROF -+ bool "Support for ZBbus profiling" -+ depends on SIBYTE_SB1xxx_SOC -+ -+config SNI_RM200_PCI -+ bool "Support for SNI RM200 PCI" -+ select ARC -+ select ARC32 -+ select BOOT_ELF32 -+ select DMA_NONCOHERENT -+ select GENERIC_ISA_DMA -+ select HAVE_STD_PC_SERIAL_PORT -+ select HW_HAS_PCI -+ select I8259 -+ select ISA -+ help -+ The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens -+ Nixdorf Informationssysteme (SNI), parent company of Pyramid -+ Technology and now in turn merged with Fujitsu. Say Y here to -+ support this machine type. -+ -+config TOSHIBA_RBTX4927 -+ bool "Support for Toshiba TBTX49[23]7 board" -+ depends on MIPS32 -+ select DMA_NONCOHERENT -+ select HAS_TXX9_SERIAL -+ select HW_HAS_PCI -+ select I8259 -+ select ISA -+ select SWAP_IO_SPACE -+ help -+ This Toshiba board is based on the TX4927 processor. Say Y here to -+ support this machine type -+ -+config TOSHIBA_FPCIB0 -+ bool "FPCIB0 Backplane Support" -+ depends on TOSHIBA_RBTX4927 -+ -+config RWSEM_GENERIC_SPINLOCK -+ bool -+ default y -+ -+config RWSEM_XCHGADD_ALGORITHM -+ bool -+ -+config GENERIC_CALIBRATE_DELAY -+ bool -+ default y -+ -+config HAVE_DEC_LOCK -+ bool -+ default y -+ -+# -+# Select some configuration options automatically based on user selections. -+# -+config ARC -+ bool -+ depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 -+ default y -+ -+config DMA_COHERENT -+ bool -+ -+config DMA_IP27 -+ bool -+ -+config DMA_NONCOHERENT -+ bool -+ -+config EARLY_PRINTK -+ bool -+ depends on MACH_DECSTATION -+ default y -+ -+config GENERIC_ISA_DMA -+ bool -+ depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA -+ default y -+ -+config I8259 -+ bool -+ depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT -+ default y -+ -+config LIMITED_DMA -+ bool -+ select HIGHMEM -+ -+config MIPS_BONITO64 -+ bool -+ depends on MIPS_ATLAS || MIPS_MALTA -+ default y -+ -+config MIPS_MSC -+ bool -+ depends on MIPS_ATLAS || MIPS_MALTA -+ default y -+ -+config MIPS_NILE4 -+ bool -+ depends on LASAT -+ default y -+ -+config MIPS_DISABLE_OBSOLETE_IDE -+ bool -+ -+config CPU_LITTLE_ENDIAN -+ bool "Generate little endian code" -+ default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA -+ default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 -+ help -+ Some MIPS machines can be configured for either little or big endian -+ byte order. These modes require different kernels. Say Y if your -+ machine is little endian, N if it's a big endian machine. -+ -+config IRQ_CPU -+ bool -+ -+config IRQ_CPU_RM7K -+ bool -+ -+config IRQ_MV64340 -+ bool -+ -+config DDB5XXX_COMMON -+ bool -+ depends on DDB5074 || DDB5476 || DDB5477 -+ default y -+ -+config MIPS_BOARDS_GEN -+ bool -+ depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD -+ default y -+ -+config MIPS_GT64111 -+ bool -+ depends on MIPS_COBALT -+ default y -+ -+config MIPS_GT64120 -+ bool -+ depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT -+ default y -+ -+config MIPS_TX3927 -+ bool -+ depends on TOSHIBA_JMR3927 -+ select HAS_TXX9_SERIAL -+ default y -+ -+config PCI_MARVELL -+ bool -+ -+config ITE_BOARD_GEN -+ bool -+ depends on MIPS_IVR || MIPS_ITE8172 -+ default y -+ -+config SWAP_IO_SPACE -+ bool -+ -+# -+# Unfortunately not all GT64120 systems run the chip at the same clock. -+# As the user for the clock rate and try to minimize the available options. -+# -+choice -+ prompt "Galileo Chip Clock" -+ #default SYSCLK_83 if MIPS_EV64120 -+ depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G -+ default SYSCLK_83 if MIPS_EV64120 -+ default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G -+ -+config SYSCLK_75 -+ bool "75" if MIPS_EV64120 -+ -+config SYSCLK_83 -+ bool "83.3" if MIPS_EV64120 -+ -+config SYSCLK_100 -+ bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G -+ -+endchoice -+ -+config AU1X00_USB_DEVICE -+ bool -+ depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 -+ default n -+ -+config MIPS_GT96100 -+ bool -+ depends on MIPS_EV96100 -+ default y -+ help -+ Say Y here to support the Galileo Technology GT96100 communications -+ controller card. There is a web page at <http://www.galileot.com/>. -+ -+config IT8172_CIR -+ bool -+ depends on MIPS_ITE8172 || MIPS_IVR -+ default y -+ -+config IT8712 -+ bool -+ depends on MIPS_ITE8172 -+ default y -+ -+config BOOT_ELF32 -+ bool -+ depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI -+ default y -+ -+config MIPS_L1_CACHE_SHIFT -+ int -+ default "4" if MACH_DECSTATION -+ default "7" if SGI_IP27 -+ default "5" -+ -+config ARC32 -+ bool -+ depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 -+ default y -+ -+config FB -+ bool -+ depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 -+ default y -+ ---help--- -+ The frame buffer device provides an abstraction for the graphics -+ hardware. It represents the frame buffer of some video hardware and -+ allows application software to access the graphics hardware through -+ a well-defined interface, so the software doesn't need to know -+ anything about the low-level (hardware register) stuff. -+ -+ Frame buffer devices work identically across the different -+ architectures supported by Linux and make the implementation of -+ application programs easier and more portable; at this point, an X -+ server exists which uses the frame buffer device exclusively. -+ On several non-X86 architectures, the frame buffer device is the -+ only way to use the graphics hardware. -+ -+ The device is accessed through special device nodes, usually located -+ in the /dev directory, i.e. /dev/fb*. -+ -+ You need an utility program called fbset to make full use of frame -+ buffer devices. Please read <file:Documentation/fb/framebuffer.txt> -+ and the Framebuffer-HOWTO at <http://www.tldp.org/docs.html#howto> -+ for more information. -+ -+ Say Y here and to the driver for your graphics board below if you -+ are compiling a kernel for a non-x86 architecture. -+ -+ If you are compiling for the x86 architecture, you can say Y if you -+ want to play with it, but it is not essential. Please note that -+ running graphical applications that directly touch the hardware -+ (e.g. an accelerated X server) and that are not frame buffer -+ device-aware may cause unexpected results. If unsure, say N. -+ -+config HAVE_STD_PC_SERIAL_PORT -+ bool -+ -+config VR4181 -+ bool -+ depends on NEC_OSPREY -+ default y -+ -+config ARC_CONSOLE -+ bool "ARC console support" -+ depends on SGI_IP22 || SNI_RM200_PCI -+ -+config ARC_MEMORY -+ bool -+ depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP32 -+ default y -+ -+config ARC_PROMLIB -+ bool -+ depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 -+ default y -+ -+config ARC64 -+ bool -+ depends on SGI_IP27 -+ default y -+ -+config BOOT_ELF64 -+ bool -+ depends on SGI_IP27 -+ default y -+ -+#config MAPPED_PCI_IO y -+# bool -+# depends on SGI_IP27 -+# default y -+ -+config QL_ISP_A64 -+ bool -+ depends on SGI_IP27 -+ default y -+ -+config TOSHIBA_BOARDS -+ bool -+ depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 -+ default y -+ -+endmenu -+ -+menu "CPU selection" -+ -+choice -+ prompt "CPU type" -+ default CPU_R4X00 -+ -+config CPU_MIPS32 -+ bool "MIPS32" -+ -+config CPU_MIPS64 -+ bool "MIPS64" -+ -+config CPU_R3000 -+ bool "R3000" -+ depends on MIPS32 -+ help -+ Please make sure to pick the right CPU type. Linux/MIPS is not -+ designed to be generic, i.e. Kernels compiled for R3000 CPUs will -+ *not* work on R4000 machines and vice versa. However, since most -+ of the supported machines have an R4000 (or similar) CPU, R4x00 -+ might be a safe bet. If the resulting kernel does not work, -+ try to recompile with R3000. -+ -+config CPU_TX39XX -+ bool "R39XX" -+ depends on MIPS32 -+ -+config CPU_VR41XX -+ bool "R41xx" -+ help -+ The options selects support for the NEC VR41xx series of processors. -+ Only choose this option if you have one of these processors as a -+ kernel built with this option will not run on any other type of -+ processor or vice versa. -+ -+config CPU_R4300 -+ bool "R4300" -+ help -+ MIPS Technologies R4300-series processors. -+ -+config CPU_R4X00 -+ bool "R4x00" -+ help -+ MIPS Technologies R4000-series processors other than 4300, including -+ the R4000, R4400, R4600, and 4700. -+ -+config CPU_TX49XX -+ bool "R49XX" -+ -+config CPU_R5000 -+ bool "R5000" -+ help -+ MIPS Technologies R5000-series processors other than the Nevada. -+ -+config CPU_R5432 -+ bool "R5432" -+ -+config CPU_R6000 -+ bool "R6000" -+ depends on MIPS32 && EXPERIMENTAL -+ help -+ MIPS Technologies R6000 and R6000A series processors. Note these -+ processors are extremly rare and the support for them is incomplete. -+ -+config CPU_NEVADA -+ bool "RM52xx" -+ help -+ QED / PMC-Sierra RM52xx-series ("Nevada") processors. -+ -+config CPU_R8000 -+ bool "R8000" -+ depends on MIPS64 && EXPERIMENTAL -+ help -+ MIPS Technologies R8000 processors. Note these processors are -+ uncommon and the support for them is incomplete. -+ -+config CPU_R10000 -+ bool "R10000" -+ help -+ MIPS Technologies R10000-series processors. -+ -+config CPU_RM7000 -+ bool "RM7000" -+ -+config CPU_RM9000 -+ bool "RM9000" -+ -+config CPU_SB1 -+ bool "SB1" -+ -+endchoice -+ -+choice -+ prompt "Kernel page size" -+ default PAGE_SIZE_4KB -+ -+config PAGE_SIZE_4KB -+ bool "4kB" -+ help -+ This option select the standard 4kB Linux page size. On some -+ R3000-family processors this is the only available page size. Using -+ 4kB page size will minimize memory consumption and is therefore -+ recommended for low memory systems. -+ -+config PAGE_SIZE_8KB -+ bool "8kB" -+ depends on EXPERIMENTAL && CPU_R8000 -+ help -+ Using 8kB page size will result in higher performance kernel at -+ the price of higher memory consumption. This option is available -+ only on the R8000 processor. Not that at the time of this writing -+ this option is still high experimental; there are also issues with -+ compatibility of user applications. -+ -+config PAGE_SIZE_16KB -+ bool "16kB" -+ depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX -+ help -+ Using 16kB page size will result in higher performance kernel at -+ the price of higher memory consumption. This option is available on -+ all non-R3000 family processor. Not that at the time of this -+ writing this option is still high experimental; there are also -+ issues with compatibility of user applications. -+ -+config PAGE_SIZE_64KB -+ bool "64kB" -+ depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX -+ help -+ Using 64kB page size will result in higher performance kernel at -+ the price of higher memory consumption. This option is available on -+ all non-R3000 family processor. Not that at the time of this -+ writing this option is still high experimental; there are also -+ issues with compatibility of user applications. -+ -+endchoice -+ -+config BOARD_SCACHE -+ bool -+ -+config IP22_CPU_SCACHE -+ bool -+ select BOARD_SCACHE -+ -+config R5000_CPU_SCACHE -+ bool -+ select BOARD_SCACHE -+ -+config RM7000_CPU_SCACHE -+ bool -+ select BOARD_SCACHE -+ -+config SIBYTE_DMA_PAGEOPS -+ bool "Use DMA to clear/copy pages" -+ depends on CPU_SB1 -+ help -+ Instead of using the CPU to zero and copy pages, use a Data Mover -+ channel. These DMA channels are otherwise unused by the standard -+ SiByte Linux port. Seems to give a small performance benefit. -+ -+config CPU_HAS_PREFETCH -+ bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2 -+ default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 -+ -+config VTAG_ICACHE -+ bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32 -+ default y if CPU_SB1 -+ -+config SB1_PASS_1_WORKAROUNDS -+ bool -+ depends on CPU_SB1_PASS_1 -+ default y -+ -+config SB1_PASS_2_WORKAROUNDS -+ bool -+ depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2) -+ default y -+ -+config SB1_PASS_2_1_WORKAROUNDS -+ bool -+ depends on CPU_SB1 && CPU_SB1_PASS_2 -+ default y -+ -+config 64BIT_PHYS_ADDR -+ bool "Support for 64-bit physical address space" -+ depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32 -+ -+config CPU_ADVANCED -+ bool "Override CPU Options" -+ depends on MIPS32 -+ help -+ Saying yes here allows you to select support for various features -+ your CPU may or may not have. Most people should say N here. -+ -+config CPU_HAS_LLSC -+ bool "ll/sc Instructions available" if CPU_ADVANCED -+ default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX -+ help -+ MIPS R4000 series and later provide the Load Linked (ll) -+ and Store Conditional (sc) instructions. More information is -+ available at <http://www.go-ecs.com/mips/miptek1.htm>. -+ -+ Say Y here if your CPU has the ll and sc instructions. Say Y here -+ for better performance, N if you don't know. You must say Y here -+ for multiprocessor machines. -+ -+config CPU_HAS_LLDSCD -+ bool "lld/scd Instructions available" if CPU_ADVANCED -+ default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32 -+ help -+ Say Y here if your CPU has the lld and scd instructions, the 64-bit -+ equivalents of ll and sc. Say Y here for better performance, N if -+ you don't know. You must say Y here for multiprocessor machines. -+ -+config CPU_HAS_WB -+ bool "Writeback Buffer available" if CPU_ADVANCED -+ default y if !CPU_ADVANCED && CPU_R3000 && MACH_DECSTATION -+ help -+ Say N here for slightly better performance. You must say Y here for -+ machines which require flushing of write buffers in software. Saying -+ Y is the safe option; N may result in kernel malfunction and crashes. -+ -+config CPU_HAS_SYNC -+ bool -+ depends on !CPU_R3000 -+ default y -+ -+# -+# - Highmem only makes sense for the 32-bit kernel. -+# - The current highmem code will only work properly on physically indexed -+# caches such as R3000, SB1, R7000 or those that look like they're virtually -+# indexed such as R4000/R4400 SC and MC versions or R10000. So for the -+# moment we protect the user and offer the highmem option only on machines -+# where it's known to be safe. This will not offer highmem on a few systems -+# such as MIPS32 and MIPS64 CPUs which may have virtual and physically -+# indexed CPUs but we're playing safe. -+# - We should not offer highmem for system of which we already know that they -+# don't have memory configurations that could gain from highmem support in -+# the kernel because they don't support configurations with RAM at physical -+# addresses > 0x20000000. -+# -+config HIGHMEM -+ bool "High Memory Support" -+ depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) -+ -+config SMP -+ bool "Multi-Processing support" -+ depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 -+ ---help--- -+ This enables support for systems with more than one CPU. If you have -+ a system with only one CPU, like most personal computers, say N. If -+ you have a system with more than one CPU, say Y. -+ -+ If you say N here, the kernel will run on single and multiprocessor -+ machines, but will use only one CPU of a multiprocessor machine. If -+ you say Y here, the kernel will run on many, but not all, -+ singleprocessor machines. On a singleprocessor machine, the kernel -+ will run faster if you say N here. -+ -+ People using multiprocessor machines who say Y here should also say -+ Y to "Enhanced Real Time Clock Support", below. -+ -+ See also the <file:Documentation/smp.txt> and the SMP-HOWTO -+ available at <http://www.tldp.org/docs.html#howto>. -+ -+ If you don't know what to do here, say N. -+ -+config NR_CPUS -+ int "Maximum number of CPUs (2-64)" -+ range 2 64 -+ depends on SMP -+ default "64" if SGI_IP27 -+ default "2" -+ help -+ This allows you to specify the maximum number of CPUs which this -+ kernel will support. The maximum supported value is 32 for 32-bit -+ kernel and 64 for 64-bit kernels; the minimum value which makes -+ sense is 2. -+ -+ This is purely to save memory - each supported CPU adds -+ approximately eight kilobytes to the kernel image. -+ -+config PREEMPT -+ bool "Preemptible Kernel" -+ help -+ This option reduces the latency of the kernel when reacting to -+ real-time or interactive events by allowing a low priority process to -+ be preempted even if it is in kernel mode executing a system call. -+ This allows applications to run more reliably even when the system is -+ under load. -+ -+config RTC_DS1742 -+ bool "DS1742 BRAM/RTC support" -+ depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 -+ -+config MIPS_INSANE_LARGE -+ bool "Support for large 64-bit configurations" -+ depends on CPU_R10000 && MIPS64 -+ help -+ MIPS R10000 does support a 44 bit / 16TB address space as opposed to -+ previous 64-bit processors which only supported 40 bit / 1TB. If you -+ need processes of more than 1TB virtual address space, say Y here. -+ This will result in additional memory usage, so it is not -+ recommended for normal users. -+ -+config RWSEM_GENERIC_SPINLOCK -+ bool -+ default y -+ -+endmenu -+ -+menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" -+ -+config HW_HAS_PCI -+ bool -+ -+config PCI -+ bool "Support for PCI controller" -+ depends on HW_HAS_PCI -+ help -+ Find out whether you have a PCI motherboard. PCI is the name of a -+ bus system, i.e. the way the CPU talks to the other stuff inside -+ your box. Other bus systems are ISA, EISA, or VESA. If you have PCI, -+ say Y, otherwise N. -+ -+ The PCI-HOWTO, available from -+ <http://www.tldp.org/docs.html#howto>, contains valuable -+ information about which PCI hardware does work under Linux and which -+ doesn't. -+ -+config PCI_DOMAINS -+ bool -+ depends on PCI -+ -+source "drivers/pci/Kconfig" -+ -+# -+# ISA support is now enabled via select. Too many systems still have the one -+# or other ISA chip on the board that users don't know about so don't expect -+# users to choose the right thing ... -+# -+config ISA -+ bool -+ -+config EISA -+ bool "EISA support" -+ depends on SGI_IP22 || SNI_RM200_PCI -+ select ISA -+ ---help--- -+ The Extended Industry Standard Architecture (EISA) bus was -+ developed as an open alternative to the IBM MicroChannel bus. -+ -+ The EISA bus provided some of the features of the IBM MicroChannel -+ bus while maintaining backward compatibility with cards made for -+ the older ISA bus. The EISA bus saw limited use between 1988 and -+ 1995 when it was made obsolete by the PCI bus. -+ -+ Say Y here if you are building a kernel for an EISA-based machine. -+ -+ Otherwise, say N. -+ -+source "drivers/eisa/Kconfig" -+ -+config TC -+ bool "TURBOchannel support" -+ depends on MACH_DECSTATION -+ help -+ TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS -+ processors. Documentation on writing device drivers for TurboChannel -+ is available at: -+ <http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PS3HD-TET1_html/TITLE.html>. -+ -+#config ACCESSBUS -+# bool "Access.Bus support" -+# depends on TC -+ -+config MMU -+ bool -+ default y -+ -+config MCA -+ bool -+ -+config SBUS -+ bool -+ -+source "drivers/pcmcia/Kconfig" -+ -+source "drivers/pci/hotplug/Kconfig" -+ -+endmenu -+ -+menu "Executable file formats" -+ -+source "fs/Kconfig.binfmt" -+ -+config TRAD_SIGNALS -+ bool -+ default y if MIPS32 -+ -+config BUILD_ELF64 -+ bool "Use 64-bit ELF format for building" -+ depends on MIPS64 -+ help -+ A 64-bit kernel is usually built using the 64-bit ELF binary object -+ format as it's one that allows arbitrary 64-bit constructs. For -+ kernels that are loaded within the KSEG compatibility segments the -+ 32-bit ELF format can optionally be used resulting in a somewhat -+ smaller binary, but this option is not explicitly supported by the -+ toolchain and since binutils 2.14 it does not even work at all. -+ -+ Say Y to use the 64-bit format or N to use the 32-bit one. -+ -+ If unsure say Y. -+ -+config BINFMT_IRIX -+ bool "Include IRIX binary compatibility" -+ depends on !CPU_LITTLE_ENDIAN && MIPS32 && BROKEN -+ -+config MIPS32_COMPAT -+ bool "Kernel support for Linux/MIPS 32-bit binary compatibility" -+ depends on MIPS64 -+ help -+ Select this option if you want Linux/MIPS 32-bit binary -+ compatibility. Since all software available for Linux/MIPS is -+ currently 32-bit you should say Y here. -+ -+config COMPAT -+ bool -+ depends on MIPS32_COMPAT -+ default y -+ -+config MIPS32_O32 -+ bool "Kernel support for o32 binaries" -+ depends on MIPS32_COMPAT -+ help -+ Select this option if you want to run o32 binaries. These are pure -+ 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of -+ existing binaries are in this format. -+ -+ If unsure, say Y. -+ -+config MIPS32_N32 -+ bool "Kernel support for n32 binaries" -+ depends on MIPS32_COMPAT -+ help -+ Select this option if you want to run n32 binaries. These are -+ 64-bit binaries using 32-bit quantities for addressing and certain -+ data that would normally be 64-bit. They are used in special -+ cases. -+ -+ If unsure, say N. -+ -+config BINFMT_ELF32 -+ bool -+ default y if MIPS32_O32 || MIPS32_N32 -+ -+config PM -+ bool "Power Management support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && MACH_AU1X00 -+ -+endmenu -+ -+source "drivers/Kconfig" -+ -+source "fs/Kconfig" -+ -+source "arch/mips/Kconfig.debug" -+ -+source "security/Kconfig" -+ -+source "crypto/Kconfig" -+ -+source "lib/Kconfig" -+ -+# -+# Use the generic interrupt handling code in kernel/irq/: -+# -+config GENERIC_HARDIRQS -+ bool -+ default y -+ -+config GENERIC_IRQ_PROBE -+ bool -+ default y -+ -+config ISA_DMA_API -+ bool -+ default y diff -Nur linux-2.6.12.5/arch/mips/Makefile linux-2.6.12.5-brcm/arch/mips/Makefile --- linux-2.6.12.5/arch/mips/Makefile 2005-08-15 02:20:18.000000000 +0200 +++ linux-2.6.12.5-brcm/arch/mips/Makefile 2005-08-28 16:39:59.077334424 +0200 @@ -15650,1988 +13984,6 @@ diff -Nur linux-2.6.12.5/drivers/net/b44.c linux-2.6.12.5-brcm/drivers/net/b44.c free_netdev(dev); pci_release_regions(pdev); pci_disable_device(pdev); -diff -Nur linux-2.6.12.5/drivers/net/b44.c.orig linux-2.6.12.5-brcm/drivers/net/b44.c.orig ---- linux-2.6.12.5/drivers/net/b44.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.12.5-brcm/drivers/net/b44.c.orig 2005-08-15 02:20:18.000000000 +0200 -@@ -0,0 +1,1978 @@ -+/* b44.c: Broadcom 4400 device driver. -+ * -+ * Copyright (C) 2002 David S. Miller (davem@redhat.com) -+ * Fixed by Pekka Pietikainen (pp@ee.oulu.fi) -+ * -+ * Distribute under GPL. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/moduleparam.h> -+#include <linux/types.h> -+#include <linux/netdevice.h> -+#include <linux/ethtool.h> -+#include <linux/mii.h> -+#include <linux/if_ether.h> -+#include <linux/etherdevice.h> -+#include <linux/pci.h> -+#include <linux/delay.h> -+#include <linux/init.h> -+#include <linux/version.h> -+ -+#include <asm/uaccess.h> -+#include <asm/io.h> -+#include <asm/irq.h> -+ -+#include "b44.h" -+ -+#define DRV_MODULE_NAME "b44" -+#define PFX DRV_MODULE_NAME ": " -+#define DRV_MODULE_VERSION "0.95" -+#define DRV_MODULE_RELDATE "Aug 3, 2004" -+ -+#define B44_DEF_MSG_ENABLE \ -+ (NETIF_MSG_DRV | \ -+ NETIF_MSG_PROBE | \ -+ NETIF_MSG_LINK | \ -+ NETIF_MSG_TIMER | \ -+ NETIF_MSG_IFDOWN | \ -+ NETIF_MSG_IFUP | \ -+ NETIF_MSG_RX_ERR | \ -+ NETIF_MSG_TX_ERR) -+ -+/* length of time before we decide the hardware is borked, -+ * and dev->tx_timeout() should be called to fix the problem -+ */ -+#define B44_TX_TIMEOUT (5 * HZ) -+ -+/* hardware minimum and maximum for a single frame's data payload */ -+#define B44_MIN_MTU 60 -+#define B44_MAX_MTU 1500 -+ -+#define B44_RX_RING_SIZE 512 -+#define B44_DEF_RX_RING_PENDING 200 -+#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \ -+ B44_RX_RING_SIZE) -+#define B44_TX_RING_SIZE 512 -+#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1) -+#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \ -+ B44_TX_RING_SIZE) -+#define B44_DMA_MASK 0x3fffffff -+ -+#define TX_RING_GAP(BP) \ -+ (B44_TX_RING_SIZE - (BP)->tx_pending) -+#define TX_BUFFS_AVAIL(BP) \ -+ (((BP)->tx_cons <= (BP)->tx_prod) ? \ -+ (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \ -+ (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP)) -+#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1)) -+ -+#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64) -+#define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8) -+ -+/* minimum number of free TX descriptors required to wake up TX process */ -+#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4) -+ -+static char version[] __devinitdata = -+ DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; -+ -+MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller"); -+MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(DRV_MODULE_VERSION); -+ -+static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */ -+module_param(b44_debug, int, 0); -+MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value"); -+ -+static struct pci_device_id b44_pci_tbl[] = { -+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, -+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, -+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, -+ { } /* terminate list with empty entry */ -+}; -+ -+MODULE_DEVICE_TABLE(pci, b44_pci_tbl); -+ -+static void b44_halt(struct b44 *); -+static void b44_init_rings(struct b44 *); -+static void b44_init_hw(struct b44 *); -+static int b44_poll(struct net_device *dev, int *budget); -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void b44_poll_controller(struct net_device *dev); -+#endif -+ -+static inline unsigned long br32(const struct b44 *bp, unsigned long reg) -+{ -+ return readl(bp->regs + reg); -+} -+ -+static inline void bw32(const struct b44 *bp, -+ unsigned long reg, unsigned long val) -+{ -+ writel(val, bp->regs + reg); -+} -+ -+static int b44_wait_bit(struct b44 *bp, unsigned long reg, -+ u32 bit, unsigned long timeout, const int clear) -+{ -+ unsigned long i; -+ -+ for (i = 0; i < timeout; i++) { -+ u32 val = br32(bp, reg); -+ -+ if (clear && !(val & bit)) -+ break; -+ if (!clear && (val & bit)) -+ break; -+ udelay(10); -+ } -+ if (i == timeout) { -+ printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register " -+ "%lx to %s.\n", -+ bp->dev->name, -+ bit, reg, -+ (clear ? "clear" : "set")); -+ return -ENODEV; -+ } -+ return 0; -+} -+ -+/* Sonics SiliconBackplane support routines. ROFL, you should see all the -+ * buzz words used on this company's website :-) -+ * -+ * All of these routines must be invoked with bp->lock held and -+ * interrupts disabled. -+ */ -+ -+#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */ -+#define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */ -+ -+static u32 ssb_get_core_rev(struct b44 *bp) -+{ -+ return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK); -+} -+ -+static u32 ssb_pci_setup(struct b44 *bp, u32 cores) -+{ -+ u32 bar_orig, pci_rev, val; -+ -+ pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig); -+ pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR); -+ pci_rev = ssb_get_core_rev(bp); -+ -+ val = br32(bp, B44_SBINTVEC); -+ val |= cores; -+ bw32(bp, B44_SBINTVEC, val); -+ -+ val = br32(bp, SSB_PCI_TRANS_2); -+ val |= SSB_PCI_PREF | SSB_PCI_BURST; -+ bw32(bp, SSB_PCI_TRANS_2, val); -+ -+ pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig); -+ -+ return pci_rev; -+} -+ -+static void ssb_core_disable(struct b44 *bp) -+{ -+ if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET) -+ return; -+ -+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); -+ b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0); -+ b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1); -+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | -+ SBTMSLOW_REJECT | SBTMSLOW_RESET)); -+ br32(bp, B44_SBTMSLOW); -+ udelay(1); -+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET)); -+ br32(bp, B44_SBTMSLOW); -+ udelay(1); -+} -+ -+static void ssb_core_reset(struct b44 *bp) -+{ -+ u32 val; -+ -+ ssb_core_disable(bp); -+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC)); -+ br32(bp, B44_SBTMSLOW); -+ udelay(1); -+ -+ /* Clear SERR if set, this is a hw bug workaround. */ -+ if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR) -+ bw32(bp, B44_SBTMSHIGH, 0); -+ -+ val = br32(bp, B44_SBIMSTATE); -+ if (val & (SBIMSTATE_IBE | SBIMSTATE_TO)) -+ bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO)); -+ -+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); -+ br32(bp, B44_SBTMSLOW); -+ udelay(1); -+ -+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); -+ br32(bp, B44_SBTMSLOW); -+ udelay(1); -+} -+ -+static int ssb_core_unit(struct b44 *bp) -+{ -+#if 0 -+ u32 val = br32(bp, B44_SBADMATCH0); -+ u32 base; -+ -+ type = val & SBADMATCH0_TYPE_MASK; -+ switch (type) { -+ case 0: -+ base = val & SBADMATCH0_BS0_MASK; -+ break; -+ -+ case 1: -+ base = val & SBADMATCH0_BS1_MASK; -+ break; -+ -+ case 2: -+ default: -+ base = val & SBADMATCH0_BS2_MASK; -+ break; -+ }; -+#endif -+ return 0; -+} -+ -+static int ssb_is_core_up(struct b44 *bp) -+{ -+ return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK)) -+ == SBTMSLOW_CLOCK); -+} -+ -+static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index) -+{ -+ u32 val; -+ -+ val = ((u32) data[2]) << 24; -+ val |= ((u32) data[3]) << 16; -+ val |= ((u32) data[4]) << 8; -+ val |= ((u32) data[5]) << 0; -+ bw32(bp, B44_CAM_DATA_LO, val); -+ val = (CAM_DATA_HI_VALID | -+ (((u32) data[0]) << 8) | -+ (((u32) data[1]) << 0)); -+ bw32(bp, B44_CAM_DATA_HI, val); -+ bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE | -+ (index << CAM_CTRL_INDEX_SHIFT))); -+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); -+} -+ -+static inline void __b44_disable_ints(struct b44 *bp) -+{ -+ bw32(bp, B44_IMASK, 0); -+} -+ -+static void b44_disable_ints(struct b44 *bp) -+{ -+ __b44_disable_ints(bp); -+ -+ /* Flush posted writes. */ -+ br32(bp, B44_IMASK); -+} -+ -+static void b44_enable_ints(struct b44 *bp) -+{ -+ bw32(bp, B44_IMASK, bp->imask); -+} -+ -+static int b44_readphy(struct b44 *bp, int reg, u32 *val) -+{ -+ int err; -+ -+ bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); -+ bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | -+ (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) | -+ (bp->phy_addr << MDIO_DATA_PMD_SHIFT) | -+ (reg << MDIO_DATA_RA_SHIFT) | -+ (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT))); -+ err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); -+ *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA; -+ -+ return err; -+} -+ -+static int b44_writephy(struct b44 *bp, int reg, u32 val) -+{ -+ bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII); -+ bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | -+ (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) | -+ (bp->phy_addr << MDIO_DATA_PMD_SHIFT) | -+ (reg << MDIO_DATA_RA_SHIFT) | -+ (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) | -+ (val & MDIO_DATA_DATA))); -+ return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0); -+} -+ -+/* miilib interface */ -+/* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional -+ * due to code existing before miilib use was added to this driver. -+ * Someone should remove this artificial driver limitation in -+ * b44_{read,write}phy. bp->phy_addr itself is fine (and needed). -+ */ -+static int b44_mii_read(struct net_device *dev, int phy_id, int location) -+{ -+ u32 val; -+ struct b44 *bp = netdev_priv(dev); -+ int rc = b44_readphy(bp, location, &val); -+ if (rc) -+ return 0xffffffff; -+ return val; -+} -+ -+static void b44_mii_write(struct net_device *dev, int phy_id, int location, -+ int val) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ b44_writephy(bp, location, val); -+} -+ -+static int b44_phy_reset(struct b44 *bp) -+{ -+ u32 val; -+ int err; -+ -+ err = b44_writephy(bp, MII_BMCR, BMCR_RESET); -+ if (err) -+ return err; -+ udelay(100); -+ err = b44_readphy(bp, MII_BMCR, &val); -+ if (!err) { -+ if (val & BMCR_RESET) { -+ printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n", -+ bp->dev->name); -+ err = -ENODEV; -+ } -+ } -+ -+ return 0; -+} -+ -+static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags) -+{ -+ u32 val; -+ -+ bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE); -+ bp->flags |= pause_flags; -+ -+ val = br32(bp, B44_RXCONFIG); -+ if (pause_flags & B44_FLAG_RX_PAUSE) -+ val |= RXCONFIG_FLOW; -+ else -+ val &= ~RXCONFIG_FLOW; -+ bw32(bp, B44_RXCONFIG, val); -+ -+ val = br32(bp, B44_MAC_FLOW); -+ if (pause_flags & B44_FLAG_TX_PAUSE) -+ val |= (MAC_FLOW_PAUSE_ENAB | -+ (0xc0 & MAC_FLOW_RX_HI_WATER)); -+ else -+ val &= ~MAC_FLOW_PAUSE_ENAB; -+ bw32(bp, B44_MAC_FLOW, val); -+} -+ -+static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote) -+{ -+ u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE | -+ B44_FLAG_RX_PAUSE); -+ -+ if (local & ADVERTISE_PAUSE_CAP) { -+ if (local & ADVERTISE_PAUSE_ASYM) { -+ if (remote & LPA_PAUSE_CAP) -+ pause_enab |= (B44_FLAG_TX_PAUSE | -+ B44_FLAG_RX_PAUSE); -+ else if (remote & LPA_PAUSE_ASYM) -+ pause_enab |= B44_FLAG_RX_PAUSE; -+ } else { -+ if (remote & LPA_PAUSE_CAP) -+ pause_enab |= (B44_FLAG_TX_PAUSE | -+ B44_FLAG_RX_PAUSE); -+ } -+ } else if (local & ADVERTISE_PAUSE_ASYM) { -+ if ((remote & LPA_PAUSE_CAP) && -+ (remote & LPA_PAUSE_ASYM)) -+ pause_enab |= B44_FLAG_TX_PAUSE; -+ } -+ -+ __b44_set_flow_ctrl(bp, pause_enab); -+} -+ -+static int b44_setup_phy(struct b44 *bp) -+{ -+ u32 val; -+ int err; -+ -+ if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0) -+ goto out; -+ if ((err = b44_writephy(bp, B44_MII_ALEDCTRL, -+ val & MII_ALEDCTRL_ALLMSK)) != 0) -+ goto out; -+ if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0) -+ goto out; -+ if ((err = b44_writephy(bp, B44_MII_TLEDCTRL, -+ val | MII_TLEDCTRL_ENABLE)) != 0) -+ goto out; -+ -+ if (!(bp->flags & B44_FLAG_FORCE_LINK)) { -+ u32 adv = ADVERTISE_CSMA; -+ -+ if (bp->flags & B44_FLAG_ADV_10HALF) -+ adv |= ADVERTISE_10HALF; -+ if (bp->flags & B44_FLAG_ADV_10FULL) -+ adv |= ADVERTISE_10FULL; -+ if (bp->flags & B44_FLAG_ADV_100HALF) -+ adv |= ADVERTISE_100HALF; -+ if (bp->flags & B44_FLAG_ADV_100FULL) -+ adv |= ADVERTISE_100FULL; -+ -+ if (bp->flags & B44_FLAG_PAUSE_AUTO) -+ adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; -+ -+ if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0) -+ goto out; -+ if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE | -+ BMCR_ANRESTART))) != 0) -+ goto out; -+ } else { -+ u32 bmcr; -+ -+ if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0) -+ goto out; -+ bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100); -+ if (bp->flags & B44_FLAG_100_BASE_T) -+ bmcr |= BMCR_SPEED100; -+ if (bp->flags & B44_FLAG_FULL_DUPLEX) -+ bmcr |= BMCR_FULLDPLX; -+ if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0) -+ goto out; -+ -+ /* Since we will not be negotiating there is no safe way -+ * to determine if the link partner supports flow control -+ * or not. So just disable it completely in this case. -+ */ -+ b44_set_flow_ctrl(bp, 0, 0); -+ } -+ -+out: -+ return err; -+} -+ -+static void b44_stats_update(struct b44 *bp) -+{ -+ unsigned long reg; -+ u32 *val; -+ -+ val = &bp->hw_stats.tx_good_octets; -+ for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) { -+ *val++ += br32(bp, reg); -+ } -+ val = &bp->hw_stats.rx_good_octets; -+ for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) { -+ *val++ += br32(bp, reg); -+ } -+} -+ -+static void b44_link_report(struct b44 *bp) -+{ -+ if (!netif_carrier_ok(bp->dev)) { -+ printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name); -+ } else { -+ printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n", -+ bp->dev->name, -+ (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10, -+ (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half"); -+ -+ printk(KERN_INFO PFX "%s: Flow control is %s for TX and " -+ "%s for RX.\n", -+ bp->dev->name, -+ (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off", -+ (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off"); -+ } -+} -+ -+static void b44_check_phy(struct b44 *bp) -+{ -+ u32 bmsr, aux; -+ -+ if (!b44_readphy(bp, MII_BMSR, &bmsr) && -+ !b44_readphy(bp, B44_MII_AUXCTRL, &aux) && -+ (bmsr != 0xffff)) { -+ if (aux & MII_AUXCTRL_SPEED) -+ bp->flags |= B44_FLAG_100_BASE_T; -+ else -+ bp->flags &= ~B44_FLAG_100_BASE_T; -+ if (aux & MII_AUXCTRL_DUPLEX) -+ bp->flags |= B44_FLAG_FULL_DUPLEX; -+ else -+ bp->flags &= ~B44_FLAG_FULL_DUPLEX; -+ -+ if (!netif_carrier_ok(bp->dev) && -+ (bmsr & BMSR_LSTATUS)) { -+ u32 val = br32(bp, B44_TX_CTRL); -+ u32 local_adv, remote_adv; -+ -+ if (bp->flags & B44_FLAG_FULL_DUPLEX) -+ val |= TX_CTRL_DUPLEX; -+ else -+ val &= ~TX_CTRL_DUPLEX; -+ bw32(bp, B44_TX_CTRL, val); -+ -+ if (!(bp->flags & B44_FLAG_FORCE_LINK) && -+ !b44_readphy(bp, MII_ADVERTISE, &local_adv) && -+ !b44_readphy(bp, MII_LPA, &remote_adv)) -+ b44_set_flow_ctrl(bp, local_adv, remote_adv); -+ -+ /* Link now up */ -+ netif_carrier_on(bp->dev); -+ b44_link_report(bp); -+ } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) { -+ /* Link now down */ -+ netif_carrier_off(bp->dev); -+ b44_link_report(bp); -+ } -+ -+ if (bmsr & BMSR_RFAULT) -+ printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n", -+ bp->dev->name); -+ if (bmsr & BMSR_JCD) -+ printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n", -+ bp->dev->name); -+ } -+} -+ -+static void b44_timer(unsigned long __opaque) -+{ -+ struct b44 *bp = (struct b44 *) __opaque; -+ -+ spin_lock_irq(&bp->lock); -+ -+ b44_check_phy(bp); -+ -+ b44_stats_update(bp); -+ -+ spin_unlock_irq(&bp->lock); -+ -+ bp->timer.expires = jiffies + HZ; -+ add_timer(&bp->timer); -+} -+ -+static void b44_tx(struct b44 *bp) -+{ -+ u32 cur, cons; -+ -+ cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK; -+ cur /= sizeof(struct dma_desc); -+ -+ /* XXX needs updating when NETIF_F_SG is supported */ -+ for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) { -+ struct ring_info *rp = &bp->tx_buffers[cons]; -+ struct sk_buff *skb = rp->skb; -+ -+ if (unlikely(skb == NULL)) -+ BUG(); -+ -+ pci_unmap_single(bp->pdev, -+ pci_unmap_addr(rp, mapping), -+ skb->len, -+ PCI_DMA_TODEVICE); -+ rp->skb = NULL; -+ dev_kfree_skb_irq(skb); -+ } -+ -+ bp->tx_cons = cons; -+ if (netif_queue_stopped(bp->dev) && -+ TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH) -+ netif_wake_queue(bp->dev); -+ -+ bw32(bp, B44_GPTIMER, 0); -+} -+ -+/* Works like this. This chip writes a 'struct rx_header" 30 bytes -+ * before the DMA address you give it. So we allocate 30 more bytes -+ * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then -+ * point the chip at 30 bytes past where the rx_header will go. -+ */ -+static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked) -+{ -+ struct dma_desc *dp; -+ struct ring_info *src_map, *map; -+ struct rx_header *rh; -+ struct sk_buff *skb; -+ dma_addr_t mapping; -+ int dest_idx; -+ u32 ctrl; -+ -+ src_map = NULL; -+ if (src_idx >= 0) -+ src_map = &bp->rx_buffers[src_idx]; -+ dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1); -+ map = &bp->rx_buffers[dest_idx]; -+ skb = dev_alloc_skb(RX_PKT_BUF_SZ); -+ if (skb == NULL) -+ return -ENOMEM; -+ -+ mapping = pci_map_single(bp->pdev, skb->data, -+ RX_PKT_BUF_SZ, -+ PCI_DMA_FROMDEVICE); -+ -+ /* Hardware bug work-around, the chip is unable to do PCI DMA -+ to/from anything above 1GB :-( */ -+ if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) { -+ /* Sigh... */ -+ pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE); -+ dev_kfree_skb_any(skb); -+ skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA); -+ if (skb == NULL) -+ return -ENOMEM; -+ mapping = pci_map_single(bp->pdev, skb->data, -+ RX_PKT_BUF_SZ, -+ PCI_DMA_FROMDEVICE); -+ if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) { -+ pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE); -+ dev_kfree_skb_any(skb); -+ return -ENOMEM; -+ } -+ } -+ -+ skb->dev = bp->dev; -+ skb_reserve(skb, bp->rx_offset); -+ -+ rh = (struct rx_header *) -+ (skb->data - bp->rx_offset); -+ rh->len = 0; -+ rh->flags = 0; -+ -+ map->skb = skb; -+ pci_unmap_addr_set(map, mapping, mapping); -+ -+ if (src_map != NULL) -+ src_map->skb = NULL; -+ -+ ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset)); -+ if (dest_idx == (B44_RX_RING_SIZE - 1)) -+ ctrl |= DESC_CTRL_EOT; -+ -+ dp = &bp->rx_ring[dest_idx]; -+ dp->ctrl = cpu_to_le32(ctrl); -+ dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset); -+ -+ return RX_PKT_BUF_SZ; -+} -+ -+static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked) -+{ -+ struct dma_desc *src_desc, *dest_desc; -+ struct ring_info *src_map, *dest_map; -+ struct rx_header *rh; -+ int dest_idx; -+ u32 ctrl; -+ -+ dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1); -+ dest_desc = &bp->rx_ring[dest_idx]; -+ dest_map = &bp->rx_buffers[dest_idx]; -+ src_desc = &bp->rx_ring[src_idx]; -+ src_map = &bp->rx_buffers[src_idx]; -+ -+ dest_map->skb = src_map->skb; -+ rh = (struct rx_header *) src_map->skb->data; -+ rh->len = 0; -+ rh->flags = 0; -+ pci_unmap_addr_set(dest_map, mapping, -+ pci_unmap_addr(src_map, mapping)); -+ -+ ctrl = src_desc->ctrl; -+ if (dest_idx == (B44_RX_RING_SIZE - 1)) -+ ctrl |= cpu_to_le32(DESC_CTRL_EOT); -+ else -+ ctrl &= cpu_to_le32(~DESC_CTRL_EOT); -+ -+ dest_desc->ctrl = ctrl; -+ dest_desc->addr = src_desc->addr; -+ src_map->skb = NULL; -+ -+ pci_dma_sync_single_for_device(bp->pdev, src_desc->addr, -+ RX_PKT_BUF_SZ, -+ PCI_DMA_FROMDEVICE); -+} -+ -+static int b44_rx(struct b44 *bp, int budget) -+{ -+ int received; -+ u32 cons, prod; -+ -+ received = 0; -+ prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK; -+ prod /= sizeof(struct dma_desc); -+ cons = bp->rx_cons; -+ -+ while (cons != prod && budget > 0) { -+ struct ring_info *rp = &bp->rx_buffers[cons]; -+ struct sk_buff *skb = rp->skb; -+ dma_addr_t map = pci_unmap_addr(rp, mapping); -+ struct rx_header *rh; -+ u16 len; -+ -+ pci_dma_sync_single_for_cpu(bp->pdev, map, -+ RX_PKT_BUF_SZ, -+ PCI_DMA_FROMDEVICE); -+ rh = (struct rx_header *) skb->data; -+ len = cpu_to_le16(rh->len); -+ if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) || -+ (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) { -+ drop_it: -+ b44_recycle_rx(bp, cons, bp->rx_prod); -+ drop_it_no_recycle: -+ bp->stats.rx_dropped++; -+ goto next_pkt; -+ } -+ -+ if (len == 0) { -+ int i = 0; -+ -+ do { -+ udelay(2); -+ barrier(); -+ len = cpu_to_le16(rh->len); -+ } while (len == 0 && i++ < 5); -+ if (len == 0) -+ goto drop_it; -+ } -+ -+ /* Omit CRC. */ -+ len -= 4; -+ -+ if (len > RX_COPY_THRESHOLD) { -+ int skb_size; -+ skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod); -+ if (skb_size < 0) -+ goto drop_it; -+ pci_unmap_single(bp->pdev, map, -+ skb_size, PCI_DMA_FROMDEVICE); -+ /* Leave out rx_header */ -+ skb_put(skb, len+bp->rx_offset); -+ skb_pull(skb,bp->rx_offset); -+ } else { -+ struct sk_buff *copy_skb; -+ -+ b44_recycle_rx(bp, cons, bp->rx_prod); -+ copy_skb = dev_alloc_skb(len + 2); -+ if (copy_skb == NULL) -+ goto drop_it_no_recycle; -+ -+ copy_skb->dev = bp->dev; -+ skb_reserve(copy_skb, 2); -+ skb_put(copy_skb, len); -+ /* DMA sync done above, copy just the actual packet */ -+ memcpy(copy_skb->data, skb->data+bp->rx_offset, len); -+ -+ skb = copy_skb; -+ } -+ skb->ip_summed = CHECKSUM_NONE; -+ skb->protocol = eth_type_trans(skb, bp->dev); -+ netif_receive_skb(skb); -+ bp->dev->last_rx = jiffies; -+ received++; -+ budget--; -+ next_pkt: -+ bp->rx_prod = (bp->rx_prod + 1) & -+ (B44_RX_RING_SIZE - 1); -+ cons = (cons + 1) & (B44_RX_RING_SIZE - 1); -+ } -+ -+ bp->rx_cons = cons; -+ bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc)); -+ -+ return received; -+} -+ -+static int b44_poll(struct net_device *netdev, int *budget) -+{ -+ struct b44 *bp = netdev_priv(netdev); -+ int done; -+ -+ spin_lock_irq(&bp->lock); -+ -+ if (bp->istat & (ISTAT_TX | ISTAT_TO)) { -+ /* spin_lock(&bp->tx_lock); */ -+ b44_tx(bp); -+ /* spin_unlock(&bp->tx_lock); */ -+ } -+ spin_unlock_irq(&bp->lock); -+ -+ done = 1; -+ if (bp->istat & ISTAT_RX) { -+ int orig_budget = *budget; -+ int work_done; -+ -+ if (orig_budget > netdev->quota) -+ orig_budget = netdev->quota; -+ -+ work_done = b44_rx(bp, orig_budget); -+ -+ *budget -= work_done; -+ netdev->quota -= work_done; -+ -+ if (work_done >= orig_budget) -+ done = 0; -+ } -+ -+ if (bp->istat & ISTAT_ERRORS) { -+ spin_lock_irq(&bp->lock); -+ b44_halt(bp); -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ netif_wake_queue(bp->dev); -+ spin_unlock_irq(&bp->lock); -+ done = 1; -+ } -+ -+ if (done) { -+ netif_rx_complete(netdev); -+ b44_enable_ints(bp); -+ } -+ -+ return (done ? 0 : 1); -+} -+ -+static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs) -+{ -+ struct net_device *dev = dev_id; -+ struct b44 *bp = netdev_priv(dev); -+ unsigned long flags; -+ u32 istat, imask; -+ int handled = 0; -+ -+ spin_lock_irqsave(&bp->lock, flags); -+ -+ istat = br32(bp, B44_ISTAT); -+ imask = br32(bp, B44_IMASK); -+ -+ /* ??? What the fuck is the purpose of the interrupt mask -+ * ??? register if we have to mask it out by hand anyways? -+ */ -+ istat &= imask; -+ if (istat) { -+ handled = 1; -+ if (netif_rx_schedule_prep(dev)) { -+ /* NOTE: These writes are posted by the readback of -+ * the ISTAT register below. -+ */ -+ bp->istat = istat; -+ __b44_disable_ints(bp); -+ __netif_rx_schedule(dev); -+ } else { -+ printk(KERN_ERR PFX "%s: Error, poll already scheduled\n", -+ dev->name); -+ } -+ -+ bw32(bp, B44_ISTAT, istat); -+ br32(bp, B44_ISTAT); -+ } -+ spin_unlock_irqrestore(&bp->lock, flags); -+ return IRQ_RETVAL(handled); -+} -+ -+static void b44_tx_timeout(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", -+ dev->name); -+ -+ spin_lock_irq(&bp->lock); -+ -+ b44_halt(bp); -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ -+ spin_unlock_irq(&bp->lock); -+ -+ b44_enable_ints(bp); -+ -+ netif_wake_queue(dev); -+} -+ -+static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ struct sk_buff *bounce_skb; -+ dma_addr_t mapping; -+ u32 len, entry, ctrl; -+ -+ len = skb->len; -+ spin_lock_irq(&bp->lock); -+ -+ /* This is a hard error, log it. */ -+ if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) { -+ netif_stop_queue(dev); -+ spin_unlock_irq(&bp->lock); -+ printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", -+ dev->name); -+ return 1; -+ } -+ -+ mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); -+ if(mapping+len > B44_DMA_MASK) { -+ /* Chip can't handle DMA to/from >1GB, use bounce buffer */ -+ pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE); -+ -+ bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ, -+ GFP_ATOMIC|GFP_DMA); -+ if (!bounce_skb) -+ return NETDEV_TX_BUSY; -+ -+ mapping = pci_map_single(bp->pdev, bounce_skb->data, -+ len, PCI_DMA_TODEVICE); -+ if(mapping+len > B44_DMA_MASK) { -+ pci_unmap_single(bp->pdev, mapping, -+ len, PCI_DMA_TODEVICE); -+ dev_kfree_skb_any(bounce_skb); -+ return NETDEV_TX_BUSY; -+ } -+ -+ memcpy(skb_put(bounce_skb, len), skb->data, skb->len); -+ dev_kfree_skb_any(skb); -+ skb = bounce_skb; -+ } -+ -+ entry = bp->tx_prod; -+ bp->tx_buffers[entry].skb = skb; -+ pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping); -+ -+ ctrl = (len & DESC_CTRL_LEN); -+ ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF; -+ if (entry == (B44_TX_RING_SIZE - 1)) -+ ctrl |= DESC_CTRL_EOT; -+ -+ bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl); -+ bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset); -+ -+ entry = NEXT_TX(entry); -+ -+ bp->tx_prod = entry; -+ -+ wmb(); -+ -+ bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc)); -+ if (bp->flags & B44_FLAG_BUGGY_TXPTR) -+ bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc)); -+ if (bp->flags & B44_FLAG_REORDER_BUG) -+ br32(bp, B44_DMATX_PTR); -+ -+ if (TX_BUFFS_AVAIL(bp) < 1) -+ netif_stop_queue(dev); -+ -+ spin_unlock_irq(&bp->lock); -+ -+ dev->trans_start = jiffies; -+ -+ return 0; -+} -+ -+static int b44_change_mtu(struct net_device *dev, int new_mtu) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU) -+ return -EINVAL; -+ -+ if (!netif_running(dev)) { -+ /* We'll just catch it later when the -+ * device is up'd. -+ */ -+ dev->mtu = new_mtu; -+ return 0; -+ } -+ -+ spin_lock_irq(&bp->lock); -+ b44_halt(bp); -+ dev->mtu = new_mtu; -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ spin_unlock_irq(&bp->lock); -+ -+ b44_enable_ints(bp); -+ -+ return 0; -+} -+ -+/* Free up pending packets in all rx/tx rings. -+ * -+ * The chip has been shut down and the driver detached from -+ * the networking, so no interrupts or new tx packets will -+ * end up in the driver. bp->lock is not held and we are not -+ * in an interrupt context and thus may sleep. -+ */ -+static void b44_free_rings(struct b44 *bp) -+{ -+ struct ring_info *rp; -+ int i; -+ -+ for (i = 0; i < B44_RX_RING_SIZE; i++) { -+ rp = &bp->rx_buffers[i]; -+ -+ if (rp->skb == NULL) -+ continue; -+ pci_unmap_single(bp->pdev, -+ pci_unmap_addr(rp, mapping), -+ RX_PKT_BUF_SZ, -+ PCI_DMA_FROMDEVICE); -+ dev_kfree_skb_any(rp->skb); -+ rp->skb = NULL; -+ } -+ -+ /* XXX needs changes once NETIF_F_SG is set... */ -+ for (i = 0; i < B44_TX_RING_SIZE; i++) { -+ rp = &bp->tx_buffers[i]; -+ -+ if (rp->skb == NULL) -+ continue; -+ pci_unmap_single(bp->pdev, -+ pci_unmap_addr(rp, mapping), -+ rp->skb->len, -+ PCI_DMA_TODEVICE); -+ dev_kfree_skb_any(rp->skb); -+ rp->skb = NULL; -+ } -+} -+ -+/* Initialize tx/rx rings for packet processing. -+ * -+ * The chip has been shut down and the driver detached from -+ * the networking, so no interrupts or new tx packets will -+ * end up in the driver. bp->lock is not held and we are not -+ * in an interrupt context and thus may sleep. -+ */ -+static void b44_init_rings(struct b44 *bp) -+{ -+ int i; -+ -+ b44_free_rings(bp); -+ -+ memset(bp->rx_ring, 0, B44_RX_RING_BYTES); -+ memset(bp->tx_ring, 0, B44_TX_RING_BYTES); -+ -+ for (i = 0; i < bp->rx_pending; i++) { -+ if (b44_alloc_rx_skb(bp, -1, i) < 0) -+ break; -+ } -+} -+ -+/* -+ * Must not be invoked with interrupt sources disabled and -+ * the hardware shutdown down. -+ */ -+static void b44_free_consistent(struct b44 *bp) -+{ -+ if (bp->rx_buffers) { -+ kfree(bp->rx_buffers); -+ bp->rx_buffers = NULL; -+ } -+ if (bp->tx_buffers) { -+ kfree(bp->tx_buffers); -+ bp->tx_buffers = NULL; -+ } -+ if (bp->rx_ring) { -+ pci_free_consistent(bp->pdev, DMA_TABLE_BYTES, -+ bp->rx_ring, bp->rx_ring_dma); -+ bp->rx_ring = NULL; -+ } -+ if (bp->tx_ring) { -+ pci_free_consistent(bp->pdev, DMA_TABLE_BYTES, -+ bp->tx_ring, bp->tx_ring_dma); -+ bp->tx_ring = NULL; -+ } -+} -+ -+/* -+ * Must not be invoked with interrupt sources disabled and -+ * the hardware shutdown down. Can sleep. -+ */ -+static int b44_alloc_consistent(struct b44 *bp) -+{ -+ int size; -+ -+ size = B44_RX_RING_SIZE * sizeof(struct ring_info); -+ bp->rx_buffers = kmalloc(size, GFP_KERNEL); -+ if (!bp->rx_buffers) -+ goto out_err; -+ memset(bp->rx_buffers, 0, size); -+ -+ size = B44_TX_RING_SIZE * sizeof(struct ring_info); -+ bp->tx_buffers = kmalloc(size, GFP_KERNEL); -+ if (!bp->tx_buffers) -+ goto out_err; -+ memset(bp->tx_buffers, 0, size); -+ -+ size = DMA_TABLE_BYTES; -+ bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma); -+ if (!bp->rx_ring) -+ goto out_err; -+ -+ bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma); -+ if (!bp->tx_ring) -+ goto out_err; -+ -+ return 0; -+ -+out_err: -+ b44_free_consistent(bp); -+ return -ENOMEM; -+} -+ -+/* bp->lock is held. */ -+static void b44_clear_stats(struct b44 *bp) -+{ -+ unsigned long reg; -+ -+ bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); -+ for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) -+ br32(bp, reg); -+ for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) -+ br32(bp, reg); -+} -+ -+/* bp->lock is held. */ -+static void b44_chip_reset(struct b44 *bp) -+{ -+ if (ssb_is_core_up(bp)) { -+ bw32(bp, B44_RCV_LAZY, 0); -+ bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE); -+ b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1); -+ bw32(bp, B44_DMATX_CTRL, 0); -+ bp->tx_prod = bp->tx_cons = 0; -+ if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) { -+ b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE, -+ 100, 0); -+ } -+ bw32(bp, B44_DMARX_CTRL, 0); -+ bp->rx_prod = bp->rx_cons = 0; -+ } else { -+ ssb_pci_setup(bp, (bp->core_unit == 0 ? -+ SBINTVEC_ENET0 : -+ SBINTVEC_ENET1)); -+ } -+ -+ ssb_core_reset(bp); -+ -+ b44_clear_stats(bp); -+ -+ /* Make PHY accessible. */ -+ bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE | -+ (0x0d & MDIO_CTRL_MAXF_MASK))); -+ br32(bp, B44_MDIO_CTRL); -+ -+ if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) { -+ bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL); -+ br32(bp, B44_ENET_CTRL); -+ bp->flags &= ~B44_FLAG_INTERNAL_PHY; -+ } else { -+ u32 val = br32(bp, B44_DEVCTRL); -+ -+ if (val & DEVCTRL_EPR) { -+ bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR)); -+ br32(bp, B44_DEVCTRL); -+ udelay(100); -+ } -+ bp->flags |= B44_FLAG_INTERNAL_PHY; -+ } -+} -+ -+/* bp->lock is held. */ -+static void b44_halt(struct b44 *bp) -+{ -+ b44_disable_ints(bp); -+ b44_chip_reset(bp); -+} -+ -+/* bp->lock is held. */ -+static void __b44_set_mac_addr(struct b44 *bp) -+{ -+ bw32(bp, B44_CAM_CTRL, 0); -+ if (!(bp->dev->flags & IFF_PROMISC)) { -+ u32 val; -+ -+ __b44_cam_write(bp, bp->dev->dev_addr, 0); -+ val = br32(bp, B44_CAM_CTRL); -+ bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); -+ } -+} -+ -+static int b44_set_mac_addr(struct net_device *dev, void *p) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ struct sockaddr *addr = p; -+ -+ if (netif_running(dev)) -+ return -EBUSY; -+ -+ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); -+ -+ spin_lock_irq(&bp->lock); -+ __b44_set_mac_addr(bp); -+ spin_unlock_irq(&bp->lock); -+ -+ return 0; -+} -+ -+/* Called at device open time to get the chip ready for -+ * packet processing. Invoked with bp->lock held. -+ */ -+static void __b44_set_rx_mode(struct net_device *); -+static void b44_init_hw(struct b44 *bp) -+{ -+ u32 val; -+ -+ b44_chip_reset(bp); -+ b44_phy_reset(bp); -+ b44_setup_phy(bp); -+ -+ /* Enable CRC32, set proper LED modes and power on PHY */ -+ bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL); -+ bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT)); -+ -+ /* This sets the MAC address too. */ -+ __b44_set_rx_mode(bp->dev); -+ -+ /* MTU + eth header + possible VLAN tag + struct rx_header */ -+ bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN); -+ bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN); -+ -+ bw32(bp, B44_TX_WMARK, 56); /* XXX magic */ -+ bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE); -+ bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset); -+ bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE | -+ (bp->rx_offset << DMARX_CTRL_ROSHIFT))); -+ bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset); -+ -+ bw32(bp, B44_DMARX_PTR, bp->rx_pending); -+ bp->rx_prod = bp->rx_pending; -+ -+ bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); -+ -+ val = br32(bp, B44_ENET_CTRL); -+ bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE)); -+} -+ -+static int b44_open(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ int err; -+ -+ err = b44_alloc_consistent(bp); -+ if (err) -+ return err; -+ -+ err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev); -+ if (err) -+ goto err_out_free; -+ -+ spin_lock_irq(&bp->lock); -+ -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ bp->flags |= B44_FLAG_INIT_COMPLETE; -+ -+ spin_unlock_irq(&bp->lock); -+ -+ init_timer(&bp->timer); -+ bp->timer.expires = jiffies + HZ; -+ bp->timer.data = (unsigned long) bp; -+ bp->timer.function = b44_timer; -+ add_timer(&bp->timer); -+ -+ b44_enable_ints(bp); -+ -+ return 0; -+ -+err_out_free: -+ b44_free_consistent(bp); -+ return err; -+} -+ -+#if 0 -+/*static*/ void b44_dump_state(struct b44 *bp) -+{ -+ u32 val32, val32_2, val32_3, val32_4, val32_5; -+ u16 val16; -+ -+ pci_read_config_word(bp->pdev, PCI_STATUS, &val16); -+ printk("DEBUG: PCI status [%04x] \n", val16); -+ -+} -+#endif -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+/* -+ * Polling receive - used by netconsole and other diagnostic tools -+ * to allow network i/o with interrupts disabled. -+ */ -+static void b44_poll_controller(struct net_device *dev) -+{ -+ disable_irq(dev->irq); -+ b44_interrupt(dev->irq, dev, NULL); -+ enable_irq(dev->irq); -+} -+#endif -+ -+static int b44_close(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ netif_stop_queue(dev); -+ -+ del_timer_sync(&bp->timer); -+ -+ spin_lock_irq(&bp->lock); -+ -+#if 0 -+ b44_dump_state(bp); -+#endif -+ b44_halt(bp); -+ b44_free_rings(bp); -+ bp->flags &= ~B44_FLAG_INIT_COMPLETE; -+ netif_carrier_off(bp->dev); -+ -+ spin_unlock_irq(&bp->lock); -+ -+ free_irq(dev->irq, dev); -+ -+ b44_free_consistent(bp); -+ -+ return 0; -+} -+ -+static struct net_device_stats *b44_get_stats(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ struct net_device_stats *nstat = &bp->stats; -+ struct b44_hw_stats *hwstat = &bp->hw_stats; -+ -+ /* Convert HW stats into netdevice stats. */ -+ nstat->rx_packets = hwstat->rx_pkts; -+ nstat->tx_packets = hwstat->tx_pkts; -+ nstat->rx_bytes = hwstat->rx_octets; -+ nstat->tx_bytes = hwstat->tx_octets; -+ nstat->tx_errors = (hwstat->tx_jabber_pkts + -+ hwstat->tx_oversize_pkts + -+ hwstat->tx_underruns + -+ hwstat->tx_excessive_cols + -+ hwstat->tx_late_cols); -+ nstat->multicast = hwstat->tx_multicast_pkts; -+ nstat->collisions = hwstat->tx_total_cols; -+ -+ nstat->rx_length_errors = (hwstat->rx_oversize_pkts + -+ hwstat->rx_undersize); -+ nstat->rx_over_errors = hwstat->rx_missed_pkts; -+ nstat->rx_frame_errors = hwstat->rx_align_errs; -+ nstat->rx_crc_errors = hwstat->rx_crc_errs; -+ nstat->rx_errors = (hwstat->rx_jabber_pkts + -+ hwstat->rx_oversize_pkts + -+ hwstat->rx_missed_pkts + -+ hwstat->rx_crc_align_errs + -+ hwstat->rx_undersize + -+ hwstat->rx_crc_errs + -+ hwstat->rx_align_errs + -+ hwstat->rx_symbol_errs); -+ -+ nstat->tx_aborted_errors = hwstat->tx_underruns; -+#if 0 -+ /* Carrier lost counter seems to be broken for some devices */ -+ nstat->tx_carrier_errors = hwstat->tx_carrier_lost; -+#endif -+ -+ return nstat; -+} -+ -+static int __b44_load_mcast(struct b44 *bp, struct net_device *dev) -+{ -+ struct dev_mc_list *mclist; -+ int i, num_ents; -+ -+ num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE); -+ mclist = dev->mc_list; -+ for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) { -+ __b44_cam_write(bp, mclist->dmi_addr, i + 1); -+ } -+ return i+1; -+} -+ -+static void __b44_set_rx_mode(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ u32 val; -+ int i=0; -+ unsigned char zero[6] = {0,0,0,0,0,0}; -+ -+ val = br32(bp, B44_RXCONFIG); -+ val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI); -+ if (dev->flags & IFF_PROMISC) { -+ val |= RXCONFIG_PROMISC; -+ bw32(bp, B44_RXCONFIG, val); -+ } else { -+ __b44_set_mac_addr(bp); -+ -+ if (dev->flags & IFF_ALLMULTI) -+ val |= RXCONFIG_ALLMULTI; -+ else -+ i=__b44_load_mcast(bp, dev); -+ -+ for(;i<64;i++) { -+ __b44_cam_write(bp, zero, i); -+ } -+ bw32(bp, B44_RXCONFIG, val); -+ val = br32(bp, B44_CAM_CTRL); -+ bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE); -+ } -+} -+ -+static void b44_set_rx_mode(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ spin_lock_irq(&bp->lock); -+ __b44_set_rx_mode(dev); -+ spin_unlock_irq(&bp->lock); -+} -+ -+static u32 b44_get_msglevel(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ return bp->msg_enable; -+} -+ -+static void b44_set_msglevel(struct net_device *dev, u32 value) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ bp->msg_enable = value; -+} -+ -+static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ struct pci_dev *pci_dev = bp->pdev; -+ -+ strcpy (info->driver, DRV_MODULE_NAME); -+ strcpy (info->version, DRV_MODULE_VERSION); -+ strcpy (info->bus_info, pci_name(pci_dev)); -+} -+ -+static int b44_nway_reset(struct net_device *dev) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ u32 bmcr; -+ int r; -+ -+ spin_lock_irq(&bp->lock); -+ b44_readphy(bp, MII_BMCR, &bmcr); -+ b44_readphy(bp, MII_BMCR, &bmcr); -+ r = -EINVAL; -+ if (bmcr & BMCR_ANENABLE) { -+ b44_writephy(bp, MII_BMCR, -+ bmcr | BMCR_ANRESTART); -+ r = 0; -+ } -+ spin_unlock_irq(&bp->lock); -+ -+ return r; -+} -+ -+static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ if (!(bp->flags & B44_FLAG_INIT_COMPLETE)) -+ return -EAGAIN; -+ cmd->supported = (SUPPORTED_Autoneg); -+ cmd->supported |= (SUPPORTED_100baseT_Half | -+ SUPPORTED_100baseT_Full | -+ SUPPORTED_10baseT_Half | -+ SUPPORTED_10baseT_Full | -+ SUPPORTED_MII); -+ -+ cmd->advertising = 0; -+ if (bp->flags & B44_FLAG_ADV_10HALF) -+ cmd->advertising |= ADVERTISE_10HALF; -+ if (bp->flags & B44_FLAG_ADV_10FULL) -+ cmd->advertising |= ADVERTISE_10FULL; -+ if (bp->flags & B44_FLAG_ADV_100HALF) -+ cmd->advertising |= ADVERTISE_100HALF; -+ if (bp->flags & B44_FLAG_ADV_100FULL) -+ cmd->advertising |= ADVERTISE_100FULL; -+ cmd->advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; -+ cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ? -+ SPEED_100 : SPEED_10; -+ cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ? -+ DUPLEX_FULL : DUPLEX_HALF; -+ cmd->port = 0; -+ cmd->phy_address = bp->phy_addr; -+ cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ? -+ XCVR_INTERNAL : XCVR_EXTERNAL; -+ cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ? -+ AUTONEG_DISABLE : AUTONEG_ENABLE; -+ cmd->maxtxpkt = 0; -+ cmd->maxrxpkt = 0; -+ return 0; -+} -+ -+static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ if (!(bp->flags & B44_FLAG_INIT_COMPLETE)) -+ return -EAGAIN; -+ -+ /* We do not support gigabit. */ -+ if (cmd->autoneg == AUTONEG_ENABLE) { -+ if (cmd->advertising & -+ (ADVERTISED_1000baseT_Half | -+ ADVERTISED_1000baseT_Full)) -+ return -EINVAL; -+ } else if ((cmd->speed != SPEED_100 && -+ cmd->speed != SPEED_10) || -+ (cmd->duplex != DUPLEX_HALF && -+ cmd->duplex != DUPLEX_FULL)) { -+ return -EINVAL; -+ } -+ -+ spin_lock_irq(&bp->lock); -+ -+ if (cmd->autoneg == AUTONEG_ENABLE) { -+ bp->flags &= ~B44_FLAG_FORCE_LINK; -+ bp->flags &= ~(B44_FLAG_ADV_10HALF | -+ B44_FLAG_ADV_10FULL | -+ B44_FLAG_ADV_100HALF | -+ B44_FLAG_ADV_100FULL); -+ if (cmd->advertising & ADVERTISE_10HALF) -+ bp->flags |= B44_FLAG_ADV_10HALF; -+ if (cmd->advertising & ADVERTISE_10FULL) -+ bp->flags |= B44_FLAG_ADV_10FULL; -+ if (cmd->advertising & ADVERTISE_100HALF) -+ bp->flags |= B44_FLAG_ADV_100HALF; -+ if (cmd->advertising & ADVERTISE_100FULL) -+ bp->flags |= B44_FLAG_ADV_100FULL; -+ } else { -+ bp->flags |= B44_FLAG_FORCE_LINK; -+ if (cmd->speed == SPEED_100) -+ bp->flags |= B44_FLAG_100_BASE_T; -+ if (cmd->duplex == DUPLEX_FULL) -+ bp->flags |= B44_FLAG_FULL_DUPLEX; -+ } -+ -+ b44_setup_phy(bp); -+ -+ spin_unlock_irq(&bp->lock); -+ -+ return 0; -+} -+ -+static void b44_get_ringparam(struct net_device *dev, -+ struct ethtool_ringparam *ering) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ ering->rx_max_pending = B44_RX_RING_SIZE - 1; -+ ering->rx_pending = bp->rx_pending; -+ -+ /* XXX ethtool lacks a tx_max_pending, oops... */ -+} -+ -+static int b44_set_ringparam(struct net_device *dev, -+ struct ethtool_ringparam *ering) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ if ((ering->rx_pending > B44_RX_RING_SIZE - 1) || -+ (ering->rx_mini_pending != 0) || -+ (ering->rx_jumbo_pending != 0) || -+ (ering->tx_pending > B44_TX_RING_SIZE - 1)) -+ return -EINVAL; -+ -+ spin_lock_irq(&bp->lock); -+ -+ bp->rx_pending = ering->rx_pending; -+ bp->tx_pending = ering->tx_pending; -+ -+ b44_halt(bp); -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ netif_wake_queue(bp->dev); -+ spin_unlock_irq(&bp->lock); -+ -+ b44_enable_ints(bp); -+ -+ return 0; -+} -+ -+static void b44_get_pauseparam(struct net_device *dev, -+ struct ethtool_pauseparam *epause) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ epause->autoneg = -+ (bp->flags & B44_FLAG_PAUSE_AUTO) != 0; -+ epause->rx_pause = -+ (bp->flags & B44_FLAG_RX_PAUSE) != 0; -+ epause->tx_pause = -+ (bp->flags & B44_FLAG_TX_PAUSE) != 0; -+} -+ -+static int b44_set_pauseparam(struct net_device *dev, -+ struct ethtool_pauseparam *epause) -+{ -+ struct b44 *bp = netdev_priv(dev); -+ -+ spin_lock_irq(&bp->lock); -+ if (epause->autoneg) -+ bp->flags |= B44_FLAG_PAUSE_AUTO; -+ else -+ bp->flags &= ~B44_FLAG_PAUSE_AUTO; -+ if (epause->rx_pause) -+ bp->flags |= B44_FLAG_RX_PAUSE; -+ else -+ bp->flags &= ~B44_FLAG_RX_PAUSE; -+ if (epause->tx_pause) -+ bp->flags |= B44_FLAG_TX_PAUSE; -+ else -+ bp->flags &= ~B44_FLAG_TX_PAUSE; -+ if (bp->flags & B44_FLAG_PAUSE_AUTO) { -+ b44_halt(bp); -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ } else { -+ __b44_set_flow_ctrl(bp, bp->flags); -+ } -+ spin_unlock_irq(&bp->lock); -+ -+ b44_enable_ints(bp); -+ -+ return 0; -+} -+ -+static struct ethtool_ops b44_ethtool_ops = { -+ .get_drvinfo = b44_get_drvinfo, -+ .get_settings = b44_get_settings, -+ .set_settings = b44_set_settings, -+ .nway_reset = b44_nway_reset, -+ .get_link = ethtool_op_get_link, -+ .get_ringparam = b44_get_ringparam, -+ .set_ringparam = b44_set_ringparam, -+ .get_pauseparam = b44_get_pauseparam, -+ .set_pauseparam = b44_set_pauseparam, -+ .get_msglevel = b44_get_msglevel, -+ .set_msglevel = b44_set_msglevel, -+}; -+ -+static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = if_mii(ifr); -+ struct b44 *bp = netdev_priv(dev); -+ int err; -+ -+ spin_lock_irq(&bp->lock); -+ err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL); -+ spin_unlock_irq(&bp->lock); -+ -+ return err; -+} -+ -+/* Read 128-bytes of EEPROM. */ -+static int b44_read_eeprom(struct b44 *bp, u8 *data) -+{ -+ long i; -+ u16 *ptr = (u16 *) data; -+ -+ for (i = 0; i < 128; i += 2) -+ ptr[i / 2] = readw(bp->regs + 4096 + i); -+ -+ return 0; -+} -+ -+static int __devinit b44_get_invariants(struct b44 *bp) -+{ -+ u8 eeprom[128]; -+ int err; -+ -+ err = b44_read_eeprom(bp, &eeprom[0]); -+ if (err) -+ goto out; -+ -+ bp->dev->dev_addr[0] = eeprom[79]; -+ bp->dev->dev_addr[1] = eeprom[78]; -+ bp->dev->dev_addr[2] = eeprom[81]; -+ bp->dev->dev_addr[3] = eeprom[80]; -+ bp->dev->dev_addr[4] = eeprom[83]; -+ bp->dev->dev_addr[5] = eeprom[82]; -+ -+ bp->phy_addr = eeprom[90] & 0x1f; -+ -+ /* With this, plus the rx_header prepended to the data by the -+ * hardware, we'll land the ethernet header on a 2-byte boundary. -+ */ -+ bp->rx_offset = 30; -+ -+ bp->imask = IMASK_DEF; -+ -+ bp->core_unit = ssb_core_unit(bp); -+ bp->dma_offset = SB_PCI_DMA; -+ -+ /* XXX - really required? -+ bp->flags |= B44_FLAG_BUGGY_TXPTR; -+ */ -+out: -+ return err; -+} -+ -+static int __devinit b44_init_one(struct pci_dev *pdev, -+ const struct pci_device_id *ent) -+{ -+ static int b44_version_printed = 0; -+ unsigned long b44reg_base, b44reg_len; -+ struct net_device *dev; -+ struct b44 *bp; -+ int err, i; -+ -+ if (b44_version_printed++ == 0) -+ printk(KERN_INFO "%s", version); -+ -+ err = pci_enable_device(pdev); -+ if (err) { -+ printk(KERN_ERR PFX "Cannot enable PCI device, " -+ "aborting.\n"); -+ return err; -+ } -+ -+ if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { -+ printk(KERN_ERR PFX "Cannot find proper PCI device " -+ "base address, aborting.\n"); -+ err = -ENODEV; -+ goto err_out_disable_pdev; -+ } -+ -+ err = pci_request_regions(pdev, DRV_MODULE_NAME); -+ if (err) { -+ printk(KERN_ERR PFX "Cannot obtain PCI resources, " -+ "aborting.\n"); -+ goto err_out_disable_pdev; -+ } -+ -+ pci_set_master(pdev); -+ -+ err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK); -+ if (err) { -+ printk(KERN_ERR PFX "No usable DMA configuration, " -+ "aborting.\n"); -+ goto err_out_free_res; -+ } -+ -+ err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK); -+ if (err) { -+ printk(KERN_ERR PFX "No usable DMA configuration, " -+ "aborting.\n"); -+ goto err_out_free_res; -+ } -+ -+ b44reg_base = pci_resource_start(pdev, 0); -+ b44reg_len = pci_resource_len(pdev, 0); -+ -+ dev = alloc_etherdev(sizeof(*bp)); -+ if (!dev) { -+ printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n"); -+ err = -ENOMEM; -+ goto err_out_free_res; -+ } -+ -+ SET_MODULE_OWNER(dev); -+ SET_NETDEV_DEV(dev,&pdev->dev); -+ -+ /* No interesting netdevice features in this card... */ -+ dev->features |= 0; -+ -+ bp = netdev_priv(dev); -+ bp->pdev = pdev; -+ bp->dev = dev; -+ if (b44_debug >= 0) -+ bp->msg_enable = (1 << b44_debug) - 1; -+ else -+ bp->msg_enable = B44_DEF_MSG_ENABLE; -+ -+ spin_lock_init(&bp->lock); -+ -+ bp->regs = ioremap(b44reg_base, b44reg_len); -+ if (bp->regs == 0UL) { -+ printk(KERN_ERR PFX "Cannot map device registers, " -+ "aborting.\n"); -+ err = -ENOMEM; -+ goto err_out_free_dev; -+ } -+ -+ bp->rx_pending = B44_DEF_RX_RING_PENDING; -+ bp->tx_pending = B44_DEF_TX_RING_PENDING; -+ -+ dev->open = b44_open; -+ dev->stop = b44_close; -+ dev->hard_start_xmit = b44_start_xmit; -+ dev->get_stats = b44_get_stats; -+ dev->set_multicast_list = b44_set_rx_mode; -+ dev->set_mac_address = b44_set_mac_addr; -+ dev->do_ioctl = b44_ioctl; -+ dev->tx_timeout = b44_tx_timeout; -+ dev->poll = b44_poll; -+ dev->weight = 64; -+ dev->watchdog_timeo = B44_TX_TIMEOUT; -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ dev->poll_controller = b44_poll_controller; -+#endif -+ dev->change_mtu = b44_change_mtu; -+ dev->irq = pdev->irq; -+ SET_ETHTOOL_OPS(dev, &b44_ethtool_ops); -+ -+ err = b44_get_invariants(bp); -+ if (err) { -+ printk(KERN_ERR PFX "Problem fetching invariants of chip, " -+ "aborting.\n"); -+ goto err_out_iounmap; -+ } -+ -+ bp->mii_if.dev = dev; -+ bp->mii_if.mdio_read = b44_mii_read; -+ bp->mii_if.mdio_write = b44_mii_write; -+ bp->mii_if.phy_id = bp->phy_addr; -+ bp->mii_if.phy_id_mask = 0x1f; -+ bp->mii_if.reg_num_mask = 0x1f; -+ -+ /* By default, advertise all speed/duplex settings. */ -+ bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL | -+ B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL); -+ -+ /* By default, auto-negotiate PAUSE. */ -+ bp->flags |= B44_FLAG_PAUSE_AUTO; -+ -+ err = register_netdev(dev); -+ if (err) { -+ printk(KERN_ERR PFX "Cannot register net device, " -+ "aborting.\n"); -+ goto err_out_iounmap; -+ } -+ -+ pci_set_drvdata(pdev, dev); -+ -+ pci_save_state(bp->pdev); -+ -+ printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); -+ for (i = 0; i < 6; i++) -+ printk("%2.2x%c", dev->dev_addr[i], -+ i == 5 ? '\n' : ':'); -+ -+ return 0; -+ -+err_out_iounmap: -+ iounmap(bp->regs); -+ -+err_out_free_dev: -+ free_netdev(dev); -+ -+err_out_free_res: -+ pci_release_regions(pdev); -+ -+err_out_disable_pdev: -+ pci_disable_device(pdev); -+ pci_set_drvdata(pdev, NULL); -+ return err; -+} -+ -+static void __devexit b44_remove_one(struct pci_dev *pdev) -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ -+ if (dev) { -+ struct b44 *bp = netdev_priv(dev); -+ -+ unregister_netdev(dev); -+ iounmap(bp->regs); -+ free_netdev(dev); -+ pci_release_regions(pdev); -+ pci_disable_device(pdev); -+ pci_set_drvdata(pdev, NULL); -+ } -+} -+ -+static int b44_suspend(struct pci_dev *pdev, pm_message_t state) -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ struct b44 *bp = netdev_priv(dev); -+ -+ if (!netif_running(dev)) -+ return 0; -+ -+ del_timer_sync(&bp->timer); -+ -+ spin_lock_irq(&bp->lock); -+ -+ b44_halt(bp); -+ netif_carrier_off(bp->dev); -+ netif_device_detach(bp->dev); -+ b44_free_rings(bp); -+ -+ spin_unlock_irq(&bp->lock); -+ return 0; -+} -+ -+static int b44_resume(struct pci_dev *pdev) -+{ -+ struct net_device *dev = pci_get_drvdata(pdev); -+ struct b44 *bp = netdev_priv(dev); -+ -+ pci_restore_state(pdev); -+ -+ if (!netif_running(dev)) -+ return 0; -+ -+ spin_lock_irq(&bp->lock); -+ -+ b44_init_rings(bp); -+ b44_init_hw(bp); -+ netif_device_attach(bp->dev); -+ spin_unlock_irq(&bp->lock); -+ -+ bp->timer.expires = jiffies + HZ; -+ add_timer(&bp->timer); -+ -+ b44_enable_ints(bp); -+ return 0; -+} -+ -+static struct pci_driver b44_driver = { -+ .name = DRV_MODULE_NAME, -+ .id_table = b44_pci_tbl, -+ .probe = b44_init_one, -+ .remove = __devexit_p(b44_remove_one), -+ .suspend = b44_suspend, -+ .resume = b44_resume, -+}; -+ -+static int __init b44_init(void) -+{ -+ return pci_module_init(&b44_driver); -+} -+ -+static void __exit b44_cleanup(void) -+{ -+ pci_unregister_driver(&b44_driver); -+} -+ -+module_init(b44_init); -+module_exit(b44_cleanup); -+ diff -Nur linux-2.6.12.5/drivers/net/b44.h linux-2.6.12.5-brcm/drivers/net/b44.h --- linux-2.6.12.5/drivers/net/b44.h 2005-08-15 02:20:18.000000000 +0200 +++ linux-2.6.12.5-brcm/drivers/net/b44.h 2005-08-28 11:12:20.694819024 +0200 @@ -17663,437 +14015,6 @@ diff -Nur linux-2.6.12.5/drivers/net/b44.h linux-2.6.12.5-brcm/drivers/net/b44.h struct pci_dev *pdev; struct net_device *dev; -diff -Nur linux-2.6.12.5/drivers/net/b44.h.orig linux-2.6.12.5-brcm/drivers/net/b44.h.orig ---- linux-2.6.12.5/drivers/net/b44.h.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.12.5-brcm/drivers/net/b44.h.orig 2005-08-15 02:20:18.000000000 +0200 -@@ -0,0 +1,427 @@ -+#ifndef _B44_H -+#define _B44_H -+ -+/* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */ -+#define B44_DEVCTRL 0x0000UL /* Device Control */ -+#define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */ -+#define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */ -+#define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */ -+#define DEVCTRL_EPR 0x00008000 /* EPHY Reset */ -+#define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */ -+#define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */ -+#define DEVCTRL_PADDR 0x0007c000 /* PHY Address */ -+#define DEVCTRL_PADDR_SHIFT 18 -+#define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ -+#define B44_WKUP_LEN 0x0010UL /* Wakeup Length */ -+#define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */ -+#define WKUP_LEN_D0 0x00000080 -+#define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */ -+#define WKUP_LEN_P1_SHIFT 8 -+#define WKUP_LEN_D1 0x00008000 -+#define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */ -+#define WKUP_LEN_P2_SHIFT 16 -+#define WKUP_LEN_D2 0x00000000 -+#define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */ -+#define WKUP_LEN_P3_SHIFT 24 -+#define WKUP_LEN_D3 0x80000000 -+#define B44_ISTAT 0x0020UL /* Interrupt Status */ -+#define ISTAT_LS 0x00000020 /* Link Change (B0 only) */ -+#define ISTAT_PME 0x00000040 /* Power Management Event */ -+#define ISTAT_TO 0x00000080 /* General Purpose Timeout */ -+#define ISTAT_DSCE 0x00000400 /* Descriptor Error */ -+#define ISTAT_DATAE 0x00000800 /* Data Error */ -+#define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ -+#define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ -+#define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ -+#define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ -+#define ISTAT_RX 0x00010000 /* RX Interrupt */ -+#define ISTAT_TX 0x01000000 /* TX Interrupt */ -+#define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ -+#define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ -+#define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ -+#define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) -+#define B44_IMASK 0x0024UL /* Interrupt Mask */ -+#define IMASK_DEF (ISTAT_ERRORS | ISTAT_TO | ISTAT_RX | ISTAT_TX) -+#define B44_GPTIMER 0x0028UL /* General Purpose Timer */ -+#define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */ -+#define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */ -+#define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */ -+#define B44_FILT_DATA 0x0094UL /* ENET Filter Data */ -+#define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ -+#define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ -+#define B44_MAC_CTRL 0x00A8UL /* MAC Control */ -+#define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ -+#define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ -+#define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */ -+#define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */ -+#define MAC_CTRL_PHY_LEDCTRL_SHIFT 5 -+#define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */ -+#define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */ -+#define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ -+#define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */ -+#define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */ -+#define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */ -+#define RCV_LAZY_FC_SHIFT 24 -+#define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */ -+#define DMATX_CTRL_ENABLE 0x00000001 /* Enable */ -+#define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ -+#define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ -+#define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */ -+#define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */ -+#define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */ -+#define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */ -+#define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */ -+#define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ -+#define DMATX_STAT_SMASK 0x0000f000 /* State Mask */ -+#define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */ -+#define DMATX_STAT_SACTIVE 0x00001000 /* State Active */ -+#define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */ -+#define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */ -+#define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */ -+#define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */ -+#define DMATX_STAT_ENONE 0x00000000 /* Error None */ -+#define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ -+#define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ -+#define DMATX_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ -+#define DMATX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ -+#define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */ -+#define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ -+#define DMARX_CTRL_ENABLE 0x00000001 /* Enable */ -+#define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ -+#define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ -+#define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */ -+#define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */ -+#define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ -+#define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ -+#define DMARX_STAT_SMASK 0x0000f000 /* State Mask */ -+#define DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */ -+#define DMARX_STAT_SACTIVE 0x00001000 /* State Active */ -+#define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */ -+#define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */ -+#define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */ -+#define DMARX_STAT_ENONE 0x00000000 /* Error None */ -+#define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ -+#define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */ -+#define DMARX_STAT_EBEBW 0x00030000 /* Error Bus Error on Buffer Write */ -+#define DMARX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ -+#define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */ -+#define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */ -+#define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */ -+#define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */ -+#define DMAFIFO_AD_SXDP 0x00010000 /* Select Transmit DMA Pointers */ -+#define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */ -+#define DMAFIFO_AD_SRDP 0x00050000 /* Select Receive DMA Pointers */ -+#define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */ -+#define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */ -+#define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */ -+#define DMAFIFO_AD_SRFP 0x000c0000 /* Select Receive FIFO Pointers */ -+#define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */ -+#define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */ -+#define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ -+#define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */ -+#define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */ -+#define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Receive Disable While Transmitting */ -+#define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */ -+#define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */ -+#define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */ -+#define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ -+#define RXCONFIG_RFILT 0x00000080 /* Reject Filter */ -+#define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */ -+#define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */ -+#define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */ -+#define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */ -+#define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */ -+#define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */ -+#define MDIO_DATA_DATA 0x0000ffff /* R/W Data */ -+#define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */ -+#define MDIO_DATA_TA_SHIFT 16 -+#define MDIO_TA_VALID 2 -+#define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */ -+#define MDIO_DATA_RA_SHIFT 18 -+#define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */ -+#define MDIO_DATA_PMD_SHIFT 23 -+#define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */ -+#define MDIO_DATA_OP_SHIFT 28 -+#define MDIO_OP_WRITE 1 -+#define MDIO_OP_READ 2 -+#define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */ -+#define MDIO_DATA_SB_SHIFT 30 -+#define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */ -+#define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */ -+#define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */ -+#define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ -+#define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ -+#define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ -+#define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */ -+#define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */ -+#define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */ -+#define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */ -+#define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */ -+#define CAM_CTRL_MSEL 0x00000002 /* Mask Select */ -+#define CAM_CTRL_READ 0x00000004 /* Read */ -+#define CAM_CTRL_WRITE 0x00000008 /* Read */ -+#define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */ -+#define CAM_CTRL_INDEX_SHIFT 16 -+#define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */ -+#define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */ -+#define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */ -+#define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */ -+#define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */ -+#define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */ -+#define B44_TX_CTRL 0x0430UL /* EMAC TX Control */ -+#define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */ -+#define TX_CTRL_FMODE 0x00000002 /* Flow Mode */ -+#define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */ -+#define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */ -+#define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */ -+#define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */ -+#define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */ -+#define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */ -+#define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */ -+#define B44_TX_O 0x0508UL /* MIB TX Octets */ -+#define B44_TX_P 0x050CUL /* MIB TX Packets */ -+#define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */ -+#define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */ -+#define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */ -+#define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */ -+#define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */ -+#define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */ -+#define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */ -+#define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */ -+#define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */ -+#define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */ -+#define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */ -+#define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */ -+#define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */ -+#define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */ -+#define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */ -+#define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */ -+#define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */ -+#define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */ -+#define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */ -+#define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */ -+#define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */ -+#define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */ -+#define B44_RX_O 0x0588UL /* MIB RX Octets */ -+#define B44_RX_P 0x058CUL /* MIB RX Packets */ -+#define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */ -+#define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */ -+#define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */ -+#define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */ -+#define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */ -+#define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */ -+#define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */ -+#define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */ -+#define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */ -+#define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */ -+#define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */ -+#define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */ -+#define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */ -+#define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */ -+#define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */ -+#define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */ -+#define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */ -+#define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */ -+#define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */ -+ -+/* Silicon backplane register definitions */ -+#define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */ -+#define SBIMSTATE_PC 0x0000000f /* Pipe Count */ -+#define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ -+#define SBIMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */ -+#define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */ -+#define SBIMSTATE_AP_TK 0x00000020 /* Use token only */ -+#define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */ -+#define SBIMSTATE_IBE 0x00020000 /* In Band Error */ -+#define SBIMSTATE_TO 0x00040000 /* Timeout */ -+#define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */ -+#define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ -+#define SBINTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ -+#define SBINTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ -+#define SBINTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ -+#define SBINTVEC_USB 0x00000010 /* Enable interrupts for usb */ -+#define SBINTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ -+#define SBINTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ -+#define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */ -+#define SBTMSLOW_RESET 0x00000001 /* Reset */ -+#define SBTMSLOW_REJECT 0x00000002 /* Reject */ -+#define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ -+#define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ -+#define SBTMSLOW_PE 0x40000000 /* Power Management Enable */ -+#define SBTMSLOW_BE 0x80000000 /* BIST Enable */ -+#define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */ -+#define SBTMSHIGH_SERR 0x00000001 /* S-error */ -+#define SBTMSHIGH_INT 0x00000002 /* Interrupt */ -+#define SBTMSHIGH_BUSY 0x00000004 /* Busy */ -+#define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */ -+#define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */ -+#define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */ -+#define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */ -+#define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */ -+#define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */ -+#define SBIDHIGH_CC_SHIFT 4 -+#define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */ -+#define SBIDHIGH_VC_SHIFT 16 -+ -+/* SSB PCI config space registers. */ -+#define SSB_BAR0_WIN 0x80 -+#define SSB_BAR1_WIN 0x84 -+#define SSB_SPROM_CONTROL 0x88 -+#define SSB_BAR1_CONTROL 0x8c -+ -+/* SSB core and host control registers. */ -+#define SSB_CONTROL 0x0000UL -+#define SSB_ARBCONTROL 0x0010UL -+#define SSB_ISTAT 0x0020UL -+#define SSB_IMASK 0x0024UL -+#define SSB_MBOX 0x0028UL -+#define SSB_BCAST_ADDR 0x0050UL -+#define SSB_BCAST_DATA 0x0054UL -+#define SSB_PCI_TRANS_0 0x0100UL -+#define SSB_PCI_TRANS_1 0x0104UL -+#define SSB_PCI_TRANS_2 0x0108UL -+#define SSB_SPROM 0x0800UL -+ -+#define SSB_PCI_MEM 0x00000000 -+#define SSB_PCI_IO 0x00000001 -+#define SSB_PCI_CFG0 0x00000002 -+#define SSB_PCI_CFG1 0x00000003 -+#define SSB_PCI_PREF 0x00000004 -+#define SSB_PCI_BURST 0x00000008 -+#define SSB_PCI_MASK0 0xfc000000 -+#define SSB_PCI_MASK1 0xfc000000 -+#define SSB_PCI_MASK2 0xc0000000 -+ -+/* 4400 PHY registers */ -+#define B44_MII_AUXCTRL 24 /* Auxiliary Control */ -+#define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */ -+#define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */ -+#define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */ -+#define B44_MII_ALEDCTRL 26 /* Activity LED */ -+#define MII_ALEDCTRL_ALLMSK 0x7fff -+#define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */ -+#define MII_TLEDCTRL_ENABLE 0x0040 -+ -+struct dma_desc { -+ u32 ctrl; -+ u32 addr; -+}; -+ -+/* There are only 12 bits in the DMA engine for descriptor offsetting -+ * so the table must be aligned on a boundary of this. -+ */ -+#define DMA_TABLE_BYTES 4096 -+ -+#define DESC_CTRL_LEN 0x00001fff -+#define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */ -+#define DESC_CTRL_EOT 0x10000000 /* End of Table */ -+#define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */ -+#define DESC_CTRL_EOF 0x40000000 /* End of Frame */ -+#define DESC_CTRL_SOF 0x80000000 /* Start of Frame */ -+ -+#define RX_COPY_THRESHOLD 256 -+ -+struct rx_header { -+ u16 len; -+ u16 flags; -+ u16 pad[12]; -+}; -+#define RX_HEADER_LEN 28 -+ -+#define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ -+#define RX_FLAG_CRCERR 0x00000002 /* CRC Error */ -+#define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ -+#define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ -+#define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ -+#define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ -+#define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ -+#define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ -+#define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ -+#define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR | RX_FLAG_CRCERR | RX_FLAG_OFIFO) -+ -+struct ring_info { -+ struct sk_buff *skb; -+ DECLARE_PCI_UNMAP_ADDR(mapping); -+}; -+ -+#define B44_MCAST_TABLE_SIZE 32 -+ -+/* SW copy of device statistics, kept up to date by periodic timer -+ * which probes HW values. Must have same relative layout as HW -+ * register above, because b44_stats_update depends upon this. -+ */ -+struct b44_hw_stats { -+ u32 tx_good_octets, tx_good_pkts, tx_octets; -+ u32 tx_pkts, tx_broadcast_pkts, tx_multicast_pkts; -+ u32 tx_len_64, tx_len_65_to_127, tx_len_128_to_255; -+ u32 tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max; -+ u32 tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts; -+ u32 tx_underruns, tx_total_cols, tx_single_cols; -+ u32 tx_multiple_cols, tx_excessive_cols, tx_late_cols; -+ u32 tx_defered, tx_carrier_lost, tx_pause_pkts; -+ u32 __pad1[8]; -+ -+ u32 rx_good_octets, rx_good_pkts, rx_octets; -+ u32 rx_pkts, rx_broadcast_pkts, rx_multicast_pkts; -+ u32 rx_len_64, rx_len_65_to_127, rx_len_128_to_255; -+ u32 rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max; -+ u32 rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts; -+ u32 rx_missed_pkts, rx_crc_align_errs, rx_undersize; -+ u32 rx_crc_errs, rx_align_errs, rx_symbol_errs; -+ u32 rx_pause_pkts, rx_nonpause_pkts; -+}; -+ -+struct b44 { -+ spinlock_t lock; -+ -+ u32 imask, istat; -+ -+ struct dma_desc *rx_ring, *tx_ring; -+ -+ u32 tx_prod, tx_cons; -+ u32 rx_prod, rx_cons; -+ -+ struct ring_info *rx_buffers; -+ struct ring_info *tx_buffers; -+ -+ u32 dma_offset; -+ u32 flags; -+#define B44_FLAG_INIT_COMPLETE 0x00000001 -+#define B44_FLAG_BUGGY_TXPTR 0x00000002 -+#define B44_FLAG_REORDER_BUG 0x00000004 -+#define B44_FLAG_PAUSE_AUTO 0x00008000 -+#define B44_FLAG_FULL_DUPLEX 0x00010000 -+#define B44_FLAG_100_BASE_T 0x00020000 -+#define B44_FLAG_TX_PAUSE 0x00040000 -+#define B44_FLAG_RX_PAUSE 0x00080000 -+#define B44_FLAG_FORCE_LINK 0x00100000 -+#define B44_FLAG_ADV_10HALF 0x01000000 -+#define B44_FLAG_ADV_10FULL 0x02000000 -+#define B44_FLAG_ADV_100HALF 0x04000000 -+#define B44_FLAG_ADV_100FULL 0x08000000 -+#define B44_FLAG_INTERNAL_PHY 0x10000000 -+ -+ u32 rx_offset; -+ -+ u32 msg_enable; -+ -+ struct timer_list timer; -+ -+ struct net_device_stats stats; -+ struct b44_hw_stats hw_stats; -+ -+ void __iomem *regs; -+ struct pci_dev *pdev; -+ struct net_device *dev; -+ -+ dma_addr_t rx_ring_dma, tx_ring_dma; -+ -+ u32 rx_pending; -+ u32 tx_pending; -+ u8 phy_addr; -+ u8 core_unit; -+ -+ struct mii_if_info mii_if; -+}; -+ -+#endif /* _B44_H */ diff -Nur linux-2.6.12.5/include/asm-mips/bootinfo.h linux-2.6.12.5-brcm/include/asm-mips/bootinfo.h --- linux-2.6.12.5/include/asm-mips/bootinfo.h 2005-08-15 02:20:18.000000000 +0200 +++ linux-2.6.12.5-brcm/include/asm-mips/bootinfo.h 2005-08-28 11:12:20.695818872 +0200 @@ -18183,2616 +14104,3 @@ diff -Nur linux-2.6.12.5/include/linux/pci_ids.h linux-2.6.12.5-brcm/include/lin #define PCI_VENDOR_ID_TOPIC 0x151f #define PCI_DEVICE_ID_TOPIC_TP560 0x0000 -diff -Nur linux-2.6.12.5/include/linux/pci_ids.h.orig linux-2.6.12.5-brcm/include/linux/pci_ids.h.orig ---- linux-2.6.12.5/include/linux/pci_ids.h.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.12.5-brcm/include/linux/pci_ids.h.orig 2005-08-15 02:20:18.000000000 +0200 -@@ -0,0 +1,2609 @@ -+/* -+ * PCI Class, Vendor and Device IDs -+ * -+ * Please keep sorted. -+ */ -+ -+/* Device classes and subclasses */ -+ -+#define PCI_CLASS_NOT_DEFINED 0x0000 -+#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 -+ -+#define PCI_BASE_CLASS_STORAGE 0x01 -+#define PCI_CLASS_STORAGE_SCSI 0x0100 -+#define PCI_CLASS_STORAGE_IDE 0x0101 -+#define PCI_CLASS_STORAGE_FLOPPY 0x0102 -+#define PCI_CLASS_STORAGE_IPI 0x0103 -+#define PCI_CLASS_STORAGE_RAID 0x0104 -+#define PCI_CLASS_STORAGE_OTHER 0x0180 -+ -+#define PCI_BASE_CLASS_NETWORK 0x02 -+#define PCI_CLASS_NETWORK_ETHERNET 0x0200 -+#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 -+#define PCI_CLASS_NETWORK_FDDI 0x0202 -+#define PCI_CLASS_NETWORK_ATM 0x0203 -+#define PCI_CLASS_NETWORK_OTHER 0x0280 -+ -+#define PCI_BASE_CLASS_DISPLAY 0x03 -+#define PCI_CLASS_DISPLAY_VGA 0x0300 -+#define PCI_CLASS_DISPLAY_XGA 0x0301 -+#define PCI_CLASS_DISPLAY_3D 0x0302 -+#define PCI_CLASS_DISPLAY_OTHER 0x0380 -+ -+#define PCI_BASE_CLASS_MULTIMEDIA 0x04 -+#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 -+#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 -+#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 -+#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 -+ -+#define PCI_BASE_CLASS_MEMORY 0x05 -+#define PCI_CLASS_MEMORY_RAM 0x0500 -+#define PCI_CLASS_MEMORY_FLASH 0x0501 -+#define PCI_CLASS_MEMORY_OTHER 0x0580 -+ -+#define PCI_BASE_CLASS_BRIDGE 0x06 -+#define PCI_CLASS_BRIDGE_HOST 0x0600 -+#define PCI_CLASS_BRIDGE_ISA 0x0601 -+#define PCI_CLASS_BRIDGE_EISA 0x0602 -+#define PCI_CLASS_BRIDGE_MC 0x0603 -+#define PCI_CLASS_BRIDGE_PCI 0x0604 -+#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 -+#define PCI_CLASS_BRIDGE_NUBUS 0x0606 -+#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 -+#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 -+#define PCI_CLASS_BRIDGE_OTHER 0x0680 -+ -+#define PCI_BASE_CLASS_COMMUNICATION 0x07 -+#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 -+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 -+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 -+#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 -+#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 -+ -+#define PCI_BASE_CLASS_SYSTEM 0x08 -+#define PCI_CLASS_SYSTEM_PIC 0x0800 -+#define PCI_CLASS_SYSTEM_DMA 0x0801 -+#define PCI_CLASS_SYSTEM_TIMER 0x0802 -+#define PCI_CLASS_SYSTEM_RTC 0x0803 -+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 -+#define PCI_CLASS_SYSTEM_OTHER 0x0880 -+ -+#define PCI_BASE_CLASS_INPUT 0x09 -+#define PCI_CLASS_INPUT_KEYBOARD 0x0900 -+#define PCI_CLASS_INPUT_PEN 0x0901 -+#define PCI_CLASS_INPUT_MOUSE 0x0902 -+#define PCI_CLASS_INPUT_SCANNER 0x0903 -+#define PCI_CLASS_INPUT_GAMEPORT 0x0904 -+#define PCI_CLASS_INPUT_OTHER 0x0980 -+ -+#define PCI_BASE_CLASS_DOCKING 0x0a -+#define PCI_CLASS_DOCKING_GENERIC 0x0a00 -+#define PCI_CLASS_DOCKING_OTHER 0x0a80 -+ -+#define PCI_BASE_CLASS_PROCESSOR 0x0b -+#define PCI_CLASS_PROCESSOR_386 0x0b00 -+#define PCI_CLASS_PROCESSOR_486 0x0b01 -+#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 -+#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 -+#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 -+#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 -+#define PCI_CLASS_PROCESSOR_CO 0x0b40 -+ -+#define PCI_BASE_CLASS_SERIAL 0x0c -+#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 -+#define PCI_CLASS_SERIAL_ACCESS 0x0c01 -+#define PCI_CLASS_SERIAL_SSA 0x0c02 -+#define PCI_CLASS_SERIAL_USB 0x0c03 -+#define PCI_CLASS_SERIAL_FIBER 0x0c04 -+#define PCI_CLASS_SERIAL_SMBUS 0x0c05 -+ -+#define PCI_BASE_CLASS_INTELLIGENT 0x0e -+#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 -+ -+#define PCI_BASE_CLASS_SATELLITE 0x0f -+#define PCI_CLASS_SATELLITE_TV 0x0f00 -+#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 -+#define PCI_CLASS_SATELLITE_VOICE 0x0f03 -+#define PCI_CLASS_SATELLITE_DATA 0x0f04 -+ -+#define PCI_BASE_CLASS_CRYPT 0x10 -+#define PCI_CLASS_CRYPT_NETWORK 0x1000 -+#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 -+#define PCI_CLASS_CRYPT_OTHER 0x1080 -+ -+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 -+#define PCI_CLASS_SP_DPIO 0x1100 -+#define PCI_CLASS_SP_OTHER 0x1180 -+ -+#define PCI_CLASS_OTHERS 0xff -+ -+/* Vendors and devices. Sort key: vendor first, device next. */ -+ -+#define PCI_VENDOR_ID_DYNALINK 0x0675 -+#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 -+ -+#define PCI_VENDOR_ID_BERKOM 0x0871 -+#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 -+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 -+#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 -+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 -+ -+#define PCI_VENDOR_ID_COMPAQ 0x0e11 -+#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 -+#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 -+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 -+#define PCI_DEVICE_ID_COMPAQ_6010 0x6010 -+#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc -+#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 -+#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 -+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 -+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 -+#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 -+#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 -+#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 -+#define PCI_DEVICE_ID_COMPAQ_CISSC 0x46 -+#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 -+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 -+ -+#define PCI_VENDOR_ID_NCR 0x1000 -+#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 -+#define PCI_DEVICE_ID_NCR_53C810 0x0001 -+#define PCI_DEVICE_ID_NCR_53C820 0x0002 -+#define PCI_DEVICE_ID_NCR_53C825 0x0003 -+#define PCI_DEVICE_ID_NCR_53C815 0x0004 -+#define PCI_DEVICE_ID_LSI_53C810AP 0x0005 -+#define PCI_DEVICE_ID_NCR_53C860 0x0006 -+#define PCI_DEVICE_ID_LSI_53C1510 0x000a -+#define PCI_DEVICE_ID_NCR_53C896 0x000b -+#define PCI_DEVICE_ID_NCR_53C895 0x000c -+#define PCI_DEVICE_ID_NCR_53C885 0x000d -+#define PCI_DEVICE_ID_NCR_53C875 0x000f -+#define PCI_DEVICE_ID_NCR_53C1510 0x0010 -+#define PCI_DEVICE_ID_LSI_53C895A 0x0012 -+#define PCI_DEVICE_ID_LSI_53C875A 0x0013 -+#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020 -+#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021 -+#define PCI_DEVICE_ID_LSI_53C1030 0x0030 -+#define PCI_DEVICE_ID_LSI_1030_53C1035 0x0032 -+#define PCI_DEVICE_ID_LSI_53C1035 0x0040 -+#define PCI_DEVICE_ID_NCR_53C875J 0x008f -+#define PCI_DEVICE_ID_LSI_FC909 0x0621 -+#define PCI_DEVICE_ID_LSI_FC929 0x0622 -+#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 -+#define PCI_DEVICE_ID_LSI_FC919 0x0624 -+#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 -+#define PCI_DEVICE_ID_LSI_FC929X 0x0626 -+#define PCI_DEVICE_ID_LSI_FC939X 0x0642 -+#define PCI_DEVICE_ID_LSI_FC949X 0x0640 -+#define PCI_DEVICE_ID_LSI_FC919X 0x0628 -+#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 -+#define PCI_DEVICE_ID_LSI_61C102 0x0901 -+#define PCI_DEVICE_ID_LSI_63C815 0x1000 -+#define PCI_DEVICE_ID_LSI_SAS1064 0x0050 -+#define PCI_DEVICE_ID_LSI_SAS1066 0x005E -+#define PCI_DEVICE_ID_LSI_SAS1068 0x0054 -+#define PCI_DEVICE_ID_LSI_SAS1064A 0x005C -+#define PCI_DEVICE_ID_LSI_SAS1064E 0x0056 -+#define PCI_DEVICE_ID_LSI_SAS1066E 0x005A -+#define PCI_DEVICE_ID_LSI_SAS1068E 0x0058 -+#define PCI_DEVICE_ID_LSI_SAS1078 0x0060 -+ -+#define PCI_VENDOR_ID_ATI 0x1002 -+/* Mach64 */ -+#define PCI_DEVICE_ID_ATI_68800 0x4158 -+#define PCI_DEVICE_ID_ATI_215CT222 0x4354 -+#define PCI_DEVICE_ID_ATI_210888CX 0x4358 -+#define PCI_DEVICE_ID_ATI_215ET222 0x4554 -+/* Mach64 / Rage */ -+#define PCI_DEVICE_ID_ATI_215GB 0x4742 -+#define PCI_DEVICE_ID_ATI_215GD 0x4744 -+#define PCI_DEVICE_ID_ATI_215GI 0x4749 -+#define PCI_DEVICE_ID_ATI_215GP 0x4750 -+#define PCI_DEVICE_ID_ATI_215GQ 0x4751 -+#define PCI_DEVICE_ID_ATI_215XL 0x4752 -+#define PCI_DEVICE_ID_ATI_215GT 0x4754 -+#define PCI_DEVICE_ID_ATI_215GTB 0x4755 -+#define PCI_DEVICE_ID_ATI_215_IV 0x4756 -+#define PCI_DEVICE_ID_ATI_215_IW 0x4757 -+#define PCI_DEVICE_ID_ATI_215_IZ 0x475A -+#define PCI_DEVICE_ID_ATI_210888GX 0x4758 -+#define PCI_DEVICE_ID_ATI_215_LB 0x4c42 -+#define PCI_DEVICE_ID_ATI_215_LD 0x4c44 -+#define PCI_DEVICE_ID_ATI_215_LG 0x4c47 -+#define PCI_DEVICE_ID_ATI_215_LI 0x4c49 -+#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D -+#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E -+#define PCI_DEVICE_ID_ATI_215_LR 0x4c52 -+#define PCI_DEVICE_ID_ATI_215_LS 0x4c53 -+#define PCI_DEVICE_ID_ATI_264_LT 0x4c54 -+/* Mach64 VT */ -+#define PCI_DEVICE_ID_ATI_264VT 0x5654 -+#define PCI_DEVICE_ID_ATI_264VU 0x5655 -+#define PCI_DEVICE_ID_ATI_264VV 0x5656 -+/* Rage128 GL */ -+#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 -+#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 -+#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x5247 -+/* Rage128 VR */ -+#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b -+#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c -+#define PCI_DEVICE_ID_ATI_RAGE128_SE 0x5345 -+#define PCI_DEVICE_ID_ATI_RAGE128_SF 0x5346 -+#define PCI_DEVICE_ID_ATI_RAGE128_SG 0x5347 -+#define PCI_DEVICE_ID_ATI_RAGE128_SH 0x5348 -+#define PCI_DEVICE_ID_ATI_RAGE128_SK 0x534b -+#define PCI_DEVICE_ID_ATI_RAGE128_SL 0x534c -+#define PCI_DEVICE_ID_ATI_RAGE128_SM 0x534d -+#define PCI_DEVICE_ID_ATI_RAGE128_SN 0x534e -+/* Rage128 Ultra */ -+#define PCI_DEVICE_ID_ATI_RAGE128_TF 0x5446 -+#define PCI_DEVICE_ID_ATI_RAGE128_TL 0x544c -+#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 -+#define PCI_DEVICE_ID_ATI_RAGE128_TS 0x5453 -+#define PCI_DEVICE_ID_ATI_RAGE128_TT 0x5454 -+#define PCI_DEVICE_ID_ATI_RAGE128_TU 0x5455 -+/* Rage128 M3 */ -+#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 -+#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 -+/* Rage128 M4 */ -+#define PCI_DEVICE_ID_ATI_RAGE128_MF 0x4d46 -+#define PCI_DEVICE_ID_ATI_RAGE128_ML 0x4d4c -+/* Rage128 Pro GL */ -+#define PCI_DEVICE_ID_ATI_RAGE128_PA 0x5041 -+#define PCI_DEVICE_ID_ATI_RAGE128_PB 0x5042 -+#define PCI_DEVICE_ID_ATI_RAGE128_PC 0x5043 -+#define PCI_DEVICE_ID_ATI_RAGE128_PD 0x5044 -+#define PCI_DEVICE_ID_ATI_RAGE128_PE 0x5045 -+#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 -+/* Rage128 Pro VR */ -+#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 -+#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048 -+#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049 -+#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A -+#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B -+#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C -+#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D -+#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E -+#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F -+#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 -+#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 -+#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 -+#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 -+#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 -+#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 -+#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 -+#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056 -+#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 -+#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 -+/* Rage128 M4 */ -+#define PCI_DEVICE_ID_ATI_RADEON_LE 0x4d45 -+#define PCI_DEVICE_ID_ATI_RADEON_LF 0x4d46 -+/* Radeon R100 */ -+#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 -+#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 -+#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146 -+#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147 -+/* Radeon RV100 (VE) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 -+#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a -+/* Radeon R200 (8500) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c -+#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e -+#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f -+#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c -+#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242 -+/* Radeon R200 (9100) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d -+/* Radeon RV200 (7500) */ -+#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 -+#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 -+/* Radeon NV-100 */ -+#define PCI_DEVICE_ID_ATI_RADEON_N1 0x5159 -+#define PCI_DEVICE_ID_ATI_RADEON_N2 0x515a -+/* Radeon RV250 (9000) */ -+#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 -+#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 -+#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 -+#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 -+/* Radeon RV280 (9200) */ -+#define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960 -+#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 -+#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 -+/* Radeon R300 (9500) */ -+#define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144 -+/* Radeon R300 (9700) */ -+#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 -+#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 -+#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 -+#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 -+#define PCI_DEVICE_ID_ATI_RADEON_AE 0x4145 -+#define PCI_DEVICE_ID_ATI_RADEON_AF 0x4146 -+/* Radeon R350 (9800) */ -+#define PCI_DEVICE_ID_ATI_RADEON_NH 0x4e48 -+#define PCI_DEVICE_ID_ATI_RADEON_NI 0x4e49 -+/* Radeon RV350 (9600) */ -+#define PCI_DEVICE_ID_ATI_RADEON_AP 0x4150 -+#define PCI_DEVICE_ID_ATI_RADEON_AR 0x4152 -+/* Radeon M6 */ -+#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 -+#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a -+/* Radeon M7 */ -+#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57 -+#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58 -+/* Radeon M9 */ -+#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64 -+#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65 -+#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 -+#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 -+/* Radeon */ -+#define PCI_DEVICE_ID_ATI_RADEON_RA 0x5144 -+#define PCI_DEVICE_ID_ATI_RADEON_RB 0x5145 -+#define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 -+#define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 -+/* RadeonIGP */ -+#define PCI_DEVICE_ID_ATI_RS100 0xcab0 -+#define PCI_DEVICE_ID_ATI_RS200 0xcab2 -+#define PCI_DEVICE_ID_ATI_RS200_B 0xcbb2 -+#define PCI_DEVICE_ID_ATI_RS250 0xcab3 -+#define PCI_DEVICE_ID_ATI_RS300_100 0x5830 -+#define PCI_DEVICE_ID_ATI_RS300_133 0x5831 -+#define PCI_DEVICE_ID_ATI_RS300_166 0x5832 -+#define PCI_DEVICE_ID_ATI_RS300_200 0x5833 -+#define PCI_DEVICE_ID_ATI_RS350_100 0x7830 -+#define PCI_DEVICE_ID_ATI_RS350_133 0x7831 -+#define PCI_DEVICE_ID_ATI_RS350_166 0x7832 -+#define PCI_DEVICE_ID_ATI_RS350_200 0x7833 -+#define PCI_DEVICE_ID_ATI_RS400_100 0x5a30 -+#define PCI_DEVICE_ID_ATI_RS400_133 0x5a31 -+#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32 -+#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33 -+#define PCI_DEVICE_ID_ATI_RS480 0x5950 -+/* ATI IXP Chipset */ -+#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349 -+#define PCI_DEVICE_ID_ATI_IXP300_IDE 0x4369 -+#define PCI_DEVICE_ID_ATI_IXP300_SATA 0x436e -+#define PCI_DEVICE_ID_ATI_IXP400_IDE 0x4376 -+#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379 -+ -+#define PCI_VENDOR_ID_VLSI 0x1004 -+#define PCI_DEVICE_ID_VLSI_82C592 0x0005 -+#define PCI_DEVICE_ID_VLSI_82C593 0x0006 -+#define PCI_DEVICE_ID_VLSI_82C594 0x0007 -+#define PCI_DEVICE_ID_VLSI_82C597 0x0009 -+#define PCI_DEVICE_ID_VLSI_82C541 0x000c -+#define PCI_DEVICE_ID_VLSI_82C543 0x000d -+#define PCI_DEVICE_ID_VLSI_82C532 0x0101 -+#define PCI_DEVICE_ID_VLSI_82C534 0x0102 -+#define PCI_DEVICE_ID_VLSI_82C535 0x0104 -+#define PCI_DEVICE_ID_VLSI_82C147 0x0105 -+#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 -+ -+#define PCI_VENDOR_ID_ADL 0x1005 -+#define PCI_DEVICE_ID_ADL_2301 0x2301 -+ -+#define PCI_VENDOR_ID_NS 0x100b -+#define PCI_DEVICE_ID_NS_87415 0x0002 -+#define PCI_DEVICE_ID_NS_87560_LIO 0x000e -+#define PCI_DEVICE_ID_NS_87560_USB 0x0012 -+#define PCI_DEVICE_ID_NS_83815 0x0020 -+#define PCI_DEVICE_ID_NS_83820 0x0022 -+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 -+#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 -+#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 -+#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 -+#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 -+#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 -+#define PCI_DEVICE_ID_NS_SC1100_BRIDGE 0x0510 -+#define PCI_DEVICE_ID_NS_SC1100_SMI 0x0511 -+#define PCI_DEVICE_ID_NS_SC1100_XBUS 0x0515 -+#define PCI_DEVICE_ID_NS_87410 0xd001 -+ -+#define PCI_VENDOR_ID_TSENG 0x100c -+#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 -+#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 -+#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 -+#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 -+#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 -+ -+#define PCI_VENDOR_ID_WEITEK 0x100e -+#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 -+#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 -+ -+#define PCI_VENDOR_ID_DEC 0x1011 -+#define PCI_DEVICE_ID_DEC_BRD 0x0001 -+#define PCI_DEVICE_ID_DEC_TULIP 0x0002 -+#define PCI_DEVICE_ID_DEC_TGA 0x0004 -+#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 -+#define PCI_DEVICE_ID_DEC_TGA2 0x000D -+#define PCI_DEVICE_ID_DEC_FDDI 0x000F -+#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 -+#define PCI_DEVICE_ID_DEC_21142 0x0019 -+#define PCI_DEVICE_ID_DEC_21052 0x0021 -+#define PCI_DEVICE_ID_DEC_21150 0x0022 -+#define PCI_DEVICE_ID_DEC_21152 0x0024 -+#define PCI_DEVICE_ID_DEC_21153 0x0025 -+#define PCI_DEVICE_ID_DEC_21154 0x0026 -+#define PCI_DEVICE_ID_DEC_21285 0x1065 -+#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 -+ -+#define PCI_VENDOR_ID_CIRRUS 0x1013 -+#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 -+#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 -+#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 -+#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 -+#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac -+#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 -+#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc -+#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 -+#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 -+#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 -+#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 -+#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 -+#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 -+#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 -+#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 -+ -+#define PCI_VENDOR_ID_IBM 0x1014 -+#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a -+#define PCI_DEVICE_ID_IBM_TR 0x0018 -+#define PCI_DEVICE_ID_IBM_82G2675 0x001d -+#define PCI_DEVICE_ID_IBM_MCA 0x0020 -+#define PCI_DEVICE_ID_IBM_82351 0x0022 -+#define PCI_DEVICE_ID_IBM_PYTHON 0x002d -+#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e -+#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e -+#define PCI_DEVICE_ID_IBM_MPIC 0x0046 -+#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d -+#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096 -+#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc -+#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105 -+#define PCI_DEVICE_ID_IBM_405GP 0x0156 -+#define PCI_DEVICE_ID_IBM_SNIPE 0x0180 -+#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd -+#define PCI_DEVICE_ID_IBM_CITRINE 0x028C -+#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166 -+#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff -+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031 -+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219 -+#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A -+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251 -+#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 -+ -+#define PCI_VENDOR_ID_COMPEX2 0x101a // pci.ids says "AT&T GIS (NCR)" -+#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 -+ -+#define PCI_VENDOR_ID_WD 0x101c -+#define PCI_DEVICE_ID_WD_7197 0x3296 -+#define PCI_DEVICE_ID_WD_90C 0xc24a -+ -+#define PCI_VENDOR_ID_AMI 0x101e -+#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 -+#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 -+#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 -+ -+#define PCI_VENDOR_ID_AMD 0x1022 -+#define PCI_DEVICE_ID_AMD_LANCE 0x2000 -+#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 -+#define PCI_DEVICE_ID_AMD_SCSI 0x2020 -+#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 -+#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 -+#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 -+#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C -+#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D -+#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E -+#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F -+#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 -+#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 -+#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 -+#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404 -+#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408 -+#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 -+#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B -+#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C -+#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 -+#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 -+#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 -+#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 -+#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440 -+# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440 -+#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 -+# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441 -+#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 -+# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443 -+#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445 -+#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448 -+# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448 -+#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449 -+# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449 -+#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462 -+#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468 -+#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 -+#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a -+#define PCI_DEVICE_ID_AMD_8111_SMBUS 0x746b -+#define PCI_DEVICE_ID_AMD_8111_AUDIO 0x746d -+#define PCI_DEVICE_ID_AMD_8151_0 0x7454 -+#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450 -+ -+#define PCI_VENDOR_ID_TRIDENT 0x1023 -+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 -+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 -+#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 -+#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 -+#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 -+#define PCI_DEVICE_ID_TRIDENT_939A 0x939A -+#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 -+#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 -+#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 -+#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 -+#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 -+#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 -+#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 -+#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 -+#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 -+#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 -+#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 -+ -+#define PCI_VENDOR_ID_AI 0x1025 -+#define PCI_DEVICE_ID_AI_M1435 0x1435 -+ -+#define PCI_VENDOR_ID_DELL 0x1028 -+#define PCI_DEVICE_ID_DELL_RACIII 0x0008 -+#define PCI_DEVICE_ID_DELL_RAC4 0x0012 -+ -+#define PCI_VENDOR_ID_MATROX 0x102B -+#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 -+#define PCI_DEVICE_ID_MATROX_MIL 0x0519 -+#define PCI_DEVICE_ID_MATROX_MYS 0x051A -+#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b -+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f -+#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 -+#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 -+#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 -+#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 -+#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 -+#define PCI_DEVICE_ID_MATROX_G400 0x0525 -+#define PCI_DEVICE_ID_MATROX_G550 0x2527 -+#define PCI_DEVICE_ID_MATROX_VIA 0x4536 -+ -+#define PCI_VENDOR_ID_CT 0x102c -+#define PCI_DEVICE_ID_CT_69000 0x00c0 -+#define PCI_DEVICE_ID_CT_65545 0x00d8 -+#define PCI_DEVICE_ID_CT_65548 0x00dc -+#define PCI_DEVICE_ID_CT_65550 0x00e0 -+#define PCI_DEVICE_ID_CT_65554 0x00e4 -+#define PCI_DEVICE_ID_CT_65555 0x00e5 -+ -+#define PCI_VENDOR_ID_MIRO 0x1031 -+#define PCI_DEVICE_ID_MIRO_36050 0x5601 -+#define PCI_DEVICE_ID_MIRO_DC10PLUS 0x7efe -+#define PCI_DEVICE_ID_MIRO_DC30PLUS 0xd801 -+ -+#define PCI_VENDOR_ID_NEC 0x1033 -+#define PCI_DEVICE_ID_NEC_CBUS_1 0x0001 /* PCI-Cbus Bridge */ -+#define PCI_DEVICE_ID_NEC_LOCAL 0x0002 /* Local Bridge */ -+#define PCI_DEVICE_ID_NEC_ATM 0x0003 /* ATM LAN Controller */ -+#define PCI_DEVICE_ID_NEC_R4000 0x0004 /* R4000 Bridge */ -+#define PCI_DEVICE_ID_NEC_486 0x0005 /* 486 Like Peripheral Bus Bridge */ -+#define PCI_DEVICE_ID_NEC_ACCEL_1 0x0006 /* Graphic Accelerator */ -+#define PCI_DEVICE_ID_NEC_UXBUS 0x0007 /* UX-Bus Bridge */ -+#define PCI_DEVICE_ID_NEC_ACCEL_2 0x0008 /* Graphic Accelerator */ -+#define PCI_DEVICE_ID_NEC_GRAPH 0x0009 /* PCI-CoreGraph Bridge */ -+#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */ -+#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */ -+#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */ -+#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */ -+#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b -+#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e -+#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */ -+#define PCI_DEVICE_ID_NEC_NILE4 0x005a -+#define PCI_DEVICE_ID_NEC_VRC5476 0x009b -+#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 -+#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 -+#define PCI_DEVICE_ID_NEC_PC9821CS01 0x800c /* PC-9821-CS01 */ -+#define PCI_DEVICE_ID_NEC_PC9821NRB06 0x800d /* PC-9821NR-B06 */ -+ -+#define PCI_VENDOR_ID_FD 0x1036 -+#define PCI_DEVICE_ID_FD_36C70 0x0000 -+ -+#define PCI_VENDOR_ID_SI 0x1039 -+#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 -+#define PCI_DEVICE_ID_SI_6202 0x0002 -+#define PCI_DEVICE_ID_SI_503 0x0008 -+#define PCI_DEVICE_ID_SI_ACPI 0x0009 -+#define PCI_DEVICE_ID_SI_SMBUS 0x0016 -+#define PCI_DEVICE_ID_SI_LPC 0x0018 -+#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 -+#define PCI_DEVICE_ID_SI_6205 0x0205 -+#define PCI_DEVICE_ID_SI_501 0x0406 -+#define PCI_DEVICE_ID_SI_496 0x0496 -+#define PCI_DEVICE_ID_SI_300 0x0300 -+#define PCI_DEVICE_ID_SI_315H 0x0310 -+#define PCI_DEVICE_ID_SI_315 0x0315 -+#define PCI_DEVICE_ID_SI_315PRO 0x0325 -+#define PCI_DEVICE_ID_SI_530 0x0530 -+#define PCI_DEVICE_ID_SI_540 0x0540 -+#define PCI_DEVICE_ID_SI_550 0x0550 -+#define PCI_DEVICE_ID_SI_540_VGA 0x5300 -+#define PCI_DEVICE_ID_SI_550_VGA 0x5315 -+#define PCI_DEVICE_ID_SI_601 0x0601 -+#define PCI_DEVICE_ID_SI_620 0x0620 -+#define PCI_DEVICE_ID_SI_630 0x0630 -+#define PCI_DEVICE_ID_SI_633 0x0633 -+#define PCI_DEVICE_ID_SI_635 0x0635 -+#define PCI_DEVICE_ID_SI_640 0x0640 -+#define PCI_DEVICE_ID_SI_645 0x0645 -+#define PCI_DEVICE_ID_SI_646 0x0646 -+#define PCI_DEVICE_ID_SI_648 0x0648 -+#define PCI_DEVICE_ID_SI_650 0x0650 -+#define PCI_DEVICE_ID_SI_651 0x0651 -+#define PCI_DEVICE_ID_SI_652 0x0652 -+#define PCI_DEVICE_ID_SI_655 0x0655 -+#define PCI_DEVICE_ID_SI_661 0x0661 -+#define PCI_DEVICE_ID_SI_730 0x0730 -+#define PCI_DEVICE_ID_SI_733 0x0733 -+#define PCI_DEVICE_ID_SI_630_VGA 0x6300 -+#define PCI_DEVICE_ID_SI_730_VGA 0x7300 -+#define PCI_DEVICE_ID_SI_735 0x0735 -+#define PCI_DEVICE_ID_SI_740 0x0740 -+#define PCI_DEVICE_ID_SI_741 0x0741 -+#define PCI_DEVICE_ID_SI_745 0x0745 -+#define PCI_DEVICE_ID_SI_746 0x0746 -+#define PCI_DEVICE_ID_SI_748 0x0748 -+#define PCI_DEVICE_ID_SI_750 0x0750 -+#define PCI_DEVICE_ID_SI_751 0x0751 -+#define PCI_DEVICE_ID_SI_752 0x0752 -+#define PCI_DEVICE_ID_SI_755 0x0755 -+#define PCI_DEVICE_ID_SI_760 0x0760 -+#define PCI_DEVICE_ID_SI_900 0x0900 -+#define PCI_DEVICE_ID_SI_961 0x0961 -+#define PCI_DEVICE_ID_SI_962 0x0962 -+#define PCI_DEVICE_ID_SI_963 0x0963 -+#define PCI_DEVICE_ID_SI_5107 0x5107 -+#define PCI_DEVICE_ID_SI_5300 0x5300 -+#define PCI_DEVICE_ID_SI_5511 0x5511 -+#define PCI_DEVICE_ID_SI_5513 0x5513 -+#define PCI_DEVICE_ID_SI_5518 0x5518 -+#define PCI_DEVICE_ID_SI_5571 0x5571 -+#define PCI_DEVICE_ID_SI_5581 0x5581 -+#define PCI_DEVICE_ID_SI_5582 0x5582 -+#define PCI_DEVICE_ID_SI_5591 0x5591 -+#define PCI_DEVICE_ID_SI_5596 0x5596 -+#define PCI_DEVICE_ID_SI_5597 0x5597 -+#define PCI_DEVICE_ID_SI_5598 0x5598 -+#define PCI_DEVICE_ID_SI_5600 0x5600 -+#define PCI_DEVICE_ID_SI_6300 0x6300 -+#define PCI_DEVICE_ID_SI_6306 0x6306 -+#define PCI_DEVICE_ID_SI_6326 0x6326 -+#define PCI_DEVICE_ID_SI_7001 0x7001 -+#define PCI_DEVICE_ID_SI_7012 0x7012 -+#define PCI_DEVICE_ID_SI_7016 0x7016 -+ -+#define PCI_VENDOR_ID_HP 0x103c -+#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FX2 0x100a -+#define PCI_DEVICE_ID_HP_TACHYON 0x1028 -+#define PCI_DEVICE_ID_HP_TACHLITE 0x1029 -+#define PCI_DEVICE_ID_HP_J2585A 0x1030 -+#define PCI_DEVICE_ID_HP_J2585B 0x1031 -+#define PCI_DEVICE_ID_HP_J2973A 0x1040 -+#define PCI_DEVICE_ID_HP_J2970A 0x1042 -+#define PCI_DEVICE_ID_HP_DIVA 0x1048 -+#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049 -+#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A -+#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B -+#define PCI_DEVICE_ID_HP_PCI_LBA 0x1054 -+#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0 -+#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 -+#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b -+#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223 -+#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226 -+#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227 -+#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229 -+#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a -+#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e -+#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c -+#define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282 -+#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290 -+#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301 -+#define PCI_DEVICE_ID_HP_CISSA 0x3220 -+#define PCI_DEVICE_ID_HP_CISSB 0x3230 -+#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 -+ -+#define PCI_VENDOR_ID_PCTECH 0x1042 -+#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 -+#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 -+#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 -+#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 -+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 -+ -+#define PCI_VENDOR_ID_ASUSTEK 0x1043 -+#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 -+ -+#define PCI_VENDOR_ID_DPT 0x1044 -+#define PCI_DEVICE_ID_DPT 0xa400 -+ -+#define PCI_VENDOR_ID_OPTI 0x1045 -+#define PCI_DEVICE_ID_OPTI_92C178 0xc178 -+#define PCI_DEVICE_ID_OPTI_82C557 0xc557 -+#define PCI_DEVICE_ID_OPTI_82C558 0xc558 -+#define PCI_DEVICE_ID_OPTI_82C621 0xc621 -+#define PCI_DEVICE_ID_OPTI_82C700 0xc700 -+#define PCI_DEVICE_ID_OPTI_82C701 0xc701 -+#define PCI_DEVICE_ID_OPTI_82C814 0xc814 -+#define PCI_DEVICE_ID_OPTI_82C822 0xc822 -+#define PCI_DEVICE_ID_OPTI_82C861 0xc861 -+#define PCI_DEVICE_ID_OPTI_82C825 0xd568 -+ -+#define PCI_VENDOR_ID_ELSA 0x1048 -+#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 -+#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 -+ -+#define PCI_VENDOR_ID_SGS 0x104a -+#define PCI_DEVICE_ID_SGS_2000 0x0008 -+#define PCI_DEVICE_ID_SGS_1764 0x0009 -+ -+#define PCI_VENDOR_ID_BUSLOGIC 0x104B -+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 -+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 -+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 -+ -+#define PCI_VENDOR_ID_TI 0x104c -+#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 -+#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 -+#define PCI_DEVICE_ID_TI_4450 0x8011 -+#define PCI_DEVICE_ID_TI_1130 0xac12 -+#define PCI_DEVICE_ID_TI_1031 0xac13 -+#define PCI_DEVICE_ID_TI_1131 0xac15 -+#define PCI_DEVICE_ID_TI_1250 0xac16 -+#define PCI_DEVICE_ID_TI_1220 0xac17 -+#define PCI_DEVICE_ID_TI_1221 0xac19 -+#define PCI_DEVICE_ID_TI_1210 0xac1a -+#define PCI_DEVICE_ID_TI_1450 0xac1b -+#define PCI_DEVICE_ID_TI_1225 0xac1c -+#define PCI_DEVICE_ID_TI_1251A 0xac1d -+#define PCI_DEVICE_ID_TI_1211 0xac1e -+#define PCI_DEVICE_ID_TI_1251B 0xac1f -+#define PCI_DEVICE_ID_TI_4410 0xac41 -+#define PCI_DEVICE_ID_TI_4451 0xac42 -+#define PCI_DEVICE_ID_TI_4510 0xac44 -+#define PCI_DEVICE_ID_TI_4520 0xac46 -+#define PCI_DEVICE_ID_TI_1410 0xac50 -+#define PCI_DEVICE_ID_TI_1420 0xac51 -+#define PCI_DEVICE_ID_TI_1451A 0xac52 -+#define PCI_DEVICE_ID_TI_1620 0xac54 -+#define PCI_DEVICE_ID_TI_1520 0xac55 -+#define PCI_DEVICE_ID_TI_1510 0xac56 -+ -+#define PCI_VENDOR_ID_SONY 0x104d -+#define PCI_DEVICE_ID_SONY_CXD3222 0x8039 -+ -+#define PCI_VENDOR_ID_OAK 0x104e -+#define PCI_DEVICE_ID_OAK_OTI107 0x0107 -+ -+/* Winbond have two vendor IDs! See 0x10ad as well */ -+#define PCI_VENDOR_ID_WINBOND2 0x1050 -+#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 -+#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a -+#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 -+ -+#define PCI_VENDOR_ID_ANIGMA 0x1051 -+#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 -+ -+#define PCI_VENDOR_ID_EFAR 0x1055 -+#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 -+#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 -+#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462 -+#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 -+ -+#define PCI_VENDOR_ID_MOTOROLA 0x1057 -+#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 -+#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 -+#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 -+#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 -+#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 -+#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 -+#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 -+#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 -+#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b -+#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803 -+ -+#define PCI_VENDOR_ID_PROMISE 0x105a -+#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 -+#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 -+#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 -+#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 -+#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 -+#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 -+#define PCI_DEVICE_ID_PROMISE_20268R 0x6268 -+#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 -+#define PCI_DEVICE_ID_PROMISE_20270 0x6268 -+#define PCI_DEVICE_ID_PROMISE_20271 0x6269 -+#define PCI_DEVICE_ID_PROMISE_20275 0x1275 -+#define PCI_DEVICE_ID_PROMISE_20276 0x5275 -+#define PCI_DEVICE_ID_PROMISE_20277 0x7275 -+#define PCI_DEVICE_ID_PROMISE_5300 0x5300 -+ -+#define PCI_VENDOR_ID_N9 0x105d -+#define PCI_DEVICE_ID_N9_I128 0x2309 -+#define PCI_DEVICE_ID_N9_I128_2 0x2339 -+#define PCI_DEVICE_ID_N9_I128_T2R 0x493d -+ -+#define PCI_VENDOR_ID_UMC 0x1060 -+#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 -+#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 -+#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a -+#define PCI_DEVICE_ID_UMC_UM8886A 0x886a -+#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 -+#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 -+#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 -+#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 -+#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 -+ -+#define PCI_VENDOR_ID_X 0x1061 -+#define PCI_DEVICE_ID_X_AGX016 0x0001 -+ -+#define PCI_VENDOR_ID_MYLEX 0x1069 -+#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 -+#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 -+#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 -+#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 -+#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 -+#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 -+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 -+ -+#define PCI_VENDOR_ID_PICOP 0x1066 -+#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 -+#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 -+ -+#define PCI_VENDOR_ID_APPLE 0x106b -+#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 -+#define PCI_DEVICE_ID_APPLE_GC 0x0002 -+#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e -+#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 -+#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 -+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 -+#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022 -+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 -+#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025 -+#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d -+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e -+#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 -+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032 -+#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA 0x0033 -+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034 -+#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b -+#define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e -+#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043 -+#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b -+#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c -+#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050 -+#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051 -+#define PCI_DEVICE_ID_APPLE_SH_FW 0x0052 -+#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058 -+#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059 -+#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 -+ -+#define PCI_VENDOR_ID_YAMAHA 0x1073 -+#define PCI_DEVICE_ID_YAMAHA_724 0x0004 -+#define PCI_DEVICE_ID_YAMAHA_724F 0x000d -+#define PCI_DEVICE_ID_YAMAHA_740 0x000a -+#define PCI_DEVICE_ID_YAMAHA_740C 0x000c -+#define PCI_DEVICE_ID_YAMAHA_744 0x0010 -+#define PCI_DEVICE_ID_YAMAHA_754 0x0012 -+ -+#define PCI_VENDOR_ID_NEXGEN 0x1074 -+#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 -+ -+#define PCI_VENDOR_ID_QLOGIC 0x1077 -+#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 -+#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 -+#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 -+#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 -+ -+#define PCI_VENDOR_ID_CYRIX 0x1078 -+#define PCI_DEVICE_ID_CYRIX_5510 0x0000 -+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 -+#define PCI_DEVICE_ID_CYRIX_5520 0x0002 -+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 -+#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 -+#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 -+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 -+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 -+ -+#define PCI_VENDOR_ID_LEADTEK 0x107d -+#define PCI_DEVICE_ID_LEADTEK_805 0x0000 -+ -+#define PCI_VENDOR_ID_INTERPHASE 0x107e -+#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 -+#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 -+#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008 -+ -+#define PCI_VENDOR_ID_CONTAQ 0x1080 -+#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 -+#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 -+ -+#define PCI_VENDOR_ID_FOREX 0x1083 -+ -+#define PCI_VENDOR_ID_OLICOM 0x108d -+#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 -+#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 -+#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 -+#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 -+#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 -+#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 -+ -+#define PCI_VENDOR_ID_SUN 0x108e -+#define PCI_DEVICE_ID_SUN_EBUS 0x1000 -+#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 -+#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100 -+#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101 -+#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102 -+#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103 -+#define PCI_DEVICE_ID_SUN_GEM 0x2bad -+#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 -+#define PCI_DEVICE_ID_SUN_PBM 0x8000 -+#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001 -+#define PCI_DEVICE_ID_SUN_SABRE 0xa000 -+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001 -+#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801 -+ -+#define PCI_VENDOR_ID_CMD 0x1095 -+#define PCI_DEVICE_ID_CMD_640 0x0640 -+#define PCI_DEVICE_ID_CMD_643 0x0643 -+#define PCI_DEVICE_ID_CMD_646 0x0646 -+#define PCI_DEVICE_ID_CMD_647 0x0647 -+#define PCI_DEVICE_ID_CMD_648 0x0648 -+#define PCI_DEVICE_ID_CMD_649 0x0649 -+#define PCI_DEVICE_ID_CMD_670 0x0670 -+#define PCI_DEVICE_ID_CMD_680 0x0680 -+ -+#define PCI_DEVICE_ID_SII_680 0x0680 -+#define PCI_DEVICE_ID_SII_3112 0x3112 -+#define PCI_DEVICE_ID_SII_1210SA 0x0240 -+ -+#define PCI_VENDOR_ID_VISION 0x1098 -+#define PCI_DEVICE_ID_VISION_QD8500 0x0001 -+#define PCI_DEVICE_ID_VISION_QD8580 0x0002 -+ -+#define PCI_VENDOR_ID_BROOKTREE 0x109e -+#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 -+#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 -+#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e -+#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 -+#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 -+ -+#define PCI_VENDOR_ID_SIERRA 0x10a8 -+#define PCI_DEVICE_ID_SIERRA_STB 0x0000 -+ -+#define PCI_VENDOR_ID_SGI 0x10a9 -+#define PCI_DEVICE_ID_SGI_IOC3 0x0003 -+#define PCI_DEVICE_ID_SGI_IOC4 0x100a -+#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 -+ -+#define PCI_VENDOR_ID_ACC 0x10aa -+#define PCI_DEVICE_ID_ACC_2056 0x0000 -+ -+#define PCI_VENDOR_ID_WINBOND 0x10ad -+#define PCI_DEVICE_ID_WINBOND_83769 0x0001 -+#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 -+#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 -+ -+#define PCI_VENDOR_ID_DATABOOK 0x10b3 -+#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 -+ -+#define PCI_VENDOR_ID_PLX 0x10b5 -+#define PCI_DEVICE_ID_PLX_R685 0x1030 -+#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a -+#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 -+#define PCI_DEVICE_ID_PLX_1077 0x1077 -+#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 -+#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 -+#define PCI_DEVICE_ID_PLX_R753 0x1152 -+#define PCI_DEVICE_ID_PLX_9030 0x9030 -+#define PCI_DEVICE_ID_PLX_9050 0x9050 -+#define PCI_DEVICE_ID_PLX_9060 0x9060 -+#define PCI_DEVICE_ID_PLX_9060ES 0x906E -+#define PCI_DEVICE_ID_PLX_9060SD 0x906D -+#define PCI_DEVICE_ID_PLX_9080 0x9080 -+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 -+ -+#define PCI_VENDOR_ID_MADGE 0x10b6 -+#define PCI_DEVICE_ID_MADGE_MK2 0x0002 -+#define PCI_DEVICE_ID_MADGE_C155S 0x1001 -+ -+#define PCI_VENDOR_ID_3COM 0x10b7 -+#define PCI_DEVICE_ID_3COM_3C985 0x0001 -+#define PCI_DEVICE_ID_3COM_3C940 0x1700 -+#define PCI_DEVICE_ID_3COM_3C339 0x3390 -+#define PCI_DEVICE_ID_3COM_3C359 0x3590 -+#define PCI_DEVICE_ID_3COM_3C590 0x5900 -+#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 -+#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 -+#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 -+#define PCI_DEVICE_ID_3COM_3C940B 0x80eb -+#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 -+#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 -+#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 -+#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 -+#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 -+#define PCI_DEVICE_ID_3COM_3CR990 0x9900 -+#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 -+#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 -+#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 -+#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 -+#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 -+#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 -+#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a -+ -+#define PCI_VENDOR_ID_SMC 0x10b8 -+#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 -+ -+#define PCI_VENDOR_ID_AL 0x10b9 -+#define PCI_DEVICE_ID_AL_M1445 0x1445 -+#define PCI_DEVICE_ID_AL_M1449 0x1449 -+#define PCI_DEVICE_ID_AL_M1451 0x1451 -+#define PCI_DEVICE_ID_AL_M1461 0x1461 -+#define PCI_DEVICE_ID_AL_M1489 0x1489 -+#define PCI_DEVICE_ID_AL_M1511 0x1511 -+#define PCI_DEVICE_ID_AL_M1513 0x1513 -+#define PCI_DEVICE_ID_AL_M1521 0x1521 -+#define PCI_DEVICE_ID_AL_M1523 0x1523 -+#define PCI_DEVICE_ID_AL_M1531 0x1531 -+#define PCI_DEVICE_ID_AL_M1533 0x1533 -+#define PCI_DEVICE_ID_AL_M1535 0x1535 -+#define PCI_DEVICE_ID_AL_M1541 0x1541 -+#define PCI_DEVICE_ID_AL_M1543 0x1543 -+#define PCI_DEVICE_ID_AL_M1563 0x1563 -+#define PCI_DEVICE_ID_AL_M1621 0x1621 -+#define PCI_DEVICE_ID_AL_M1631 0x1631 -+#define PCI_DEVICE_ID_AL_M1632 0x1632 -+#define PCI_DEVICE_ID_AL_M1641 0x1641 -+#define PCI_DEVICE_ID_AL_M1644 0x1644 -+#define PCI_DEVICE_ID_AL_M1647 0x1647 -+#define PCI_DEVICE_ID_AL_M1651 0x1651 -+#define PCI_DEVICE_ID_AL_M1671 0x1671 -+#define PCI_DEVICE_ID_AL_M1681 0x1681 -+#define PCI_DEVICE_ID_AL_M1683 0x1683 -+#define PCI_DEVICE_ID_AL_M1689 0x1689 -+#define PCI_DEVICE_ID_AL_M3307 0x3307 -+#define PCI_DEVICE_ID_AL_M4803 0x5215 -+#define PCI_DEVICE_ID_AL_M5219 0x5219 -+#define PCI_DEVICE_ID_AL_M5228 0x5228 -+#define PCI_DEVICE_ID_AL_M5229 0x5229 -+#define PCI_DEVICE_ID_AL_M5237 0x5237 -+#define PCI_DEVICE_ID_AL_M5243 0x5243 -+#define PCI_DEVICE_ID_AL_M5451 0x5451 -+#define PCI_DEVICE_ID_AL_M7101 0x7101 -+ -+#define PCI_VENDOR_ID_MITSUBISHI 0x10ba -+ -+#define PCI_VENDOR_ID_SURECOM 0x10bd -+#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 -+ -+#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 -+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 -+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 -+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 -+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 -+#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 -+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 -+ -+#define PCI_VENDOR_ID_ASP 0x10cd -+#define PCI_DEVICE_ID_ASP_ABP940 0x1200 -+#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 -+#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 -+ -+#define PCI_VENDOR_ID_MACRONIX 0x10d9 -+#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 -+#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 -+ -+#define PCI_VENDOR_ID_TCONRAD 0x10da -+#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 -+ -+#define PCI_VENDOR_ID_CERN 0x10dc -+#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 -+#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 -+#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 -+#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 -+ -+#define PCI_VENDOR_ID_NVIDIA 0x10de -+#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 -+#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 -+#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 -+#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN 0x002a -+#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C -+#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE 0x0035 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA 0x0036 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2 0x003e -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800 0x0041 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE 0x0042 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x0045 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000 0x004E -+#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS 0x0052 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE 0x0053 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA 0x0054 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2 0x0055 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057 -+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS 0x0064 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066 -+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS 0x0084 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e -+#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 -+#define PCI_DEVICE_ID_GEFORCE_6800A 0x00c1 -+#define PCI_DEVICE_ID_GEFORCE_6800A_LE 0x00c2 -+#define PCI_DEVICE_ID_GEFORCE_GO_6800 0x00c8 -+#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA 0x00c9 -+#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc -+#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 -+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6 -+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da -+#define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS 0x00e4 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT 0x0140 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600 0x0141 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL 0x0145 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540 0x014E -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200 0x014F -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200 0x0164 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250 0x0166 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1 0x0167 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1 0x0168 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE 0x0173 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO 0x0177 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC 0x0189 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B -+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4 -+#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 0x01b1 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS 0x01b4 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc -+#define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B 0x0211 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE 0x0212 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT 0x0215 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600 0x0250 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400 0x0251 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200 0x0253 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE 0x0265 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266 -+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 -+#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 -+#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO 0x026B -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO 0x0286 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL 0x0288 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL 0x0289 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL 0x028C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA 0x0301 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA 0x0311 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA 0x0321 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1 0x0322 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500 0x0326 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100 0x0327 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32 0x0328 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200 0x0329 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA 0x0330 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA 0x0333 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT 0x0334 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700 0x033F -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA 0x0341 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1 0x0347 -+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2 0x0348 -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C -+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E -+ -+#define PCI_VENDOR_ID_IMS 0x10e0 -+#define PCI_DEVICE_ID_IMS_8849 0x8849 -+#define PCI_DEVICE_ID_IMS_TT128 0x9128 -+#define PCI_DEVICE_ID_IMS_TT3D 0x9135 -+ -+#define PCI_VENDOR_ID_TEKRAM2 0x10e1 -+#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c -+ -+#define PCI_VENDOR_ID_TUNDRA 0x10e3 -+#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 -+ -+#define PCI_VENDOR_ID_AMCC 0x10e8 -+#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 -+#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 -+#define PCI_DEVICE_ID_AMCC_S5933 0x807d -+#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c -+ -+#define PCI_VENDOR_ID_INTERG 0x10ea -+#define PCI_DEVICE_ID_INTERG_1680 0x1680 -+#define PCI_DEVICE_ID_INTERG_1682 0x1682 -+#define PCI_DEVICE_ID_INTERG_2000 0x2000 -+#define PCI_DEVICE_ID_INTERG_2010 0x2010 -+#define PCI_DEVICE_ID_INTERG_5000 0x5000 -+#define PCI_DEVICE_ID_INTERG_5050 0x5050 -+ -+#define PCI_VENDOR_ID_REALTEK 0x10ec -+#define PCI_DEVICE_ID_REALTEK_8029 0x8029 -+#define PCI_DEVICE_ID_REALTEK_8129 0x8129 -+#define PCI_DEVICE_ID_REALTEK_8139 0x8139 -+#define PCI_DEVICE_ID_REALTEK_8169 0x8169 -+ -+#define PCI_VENDOR_ID_XILINX 0x10ee -+#define PCI_DEVICE_ID_TURBOPAM 0x4020 -+ -+#define PCI_VENDOR_ID_TRUEVISION 0x10fa -+#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c -+ -+#define PCI_VENDOR_ID_INIT 0x1101 -+#define PCI_DEVICE_ID_INIT_320P 0x9100 -+#define PCI_DEVICE_ID_INIT_360P 0x9500 -+ -+#define PCI_VENDOR_ID_CREATIVE 0x1102 // duplicate: ECTIVA -+#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 -+ -+#define PCI_VENDOR_ID_ECTIVA 0x1102 // duplicate: CREATIVE -+#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 -+ -+#define PCI_VENDOR_ID_TTI 0x1103 -+#define PCI_DEVICE_ID_TTI_HPT343 0x0003 -+#define PCI_DEVICE_ID_TTI_HPT366 0x0004 -+#define PCI_DEVICE_ID_TTI_HPT372 0x0005 -+#define PCI_DEVICE_ID_TTI_HPT302 0x0006 -+#define PCI_DEVICE_ID_TTI_HPT371 0x0007 -+#define PCI_DEVICE_ID_TTI_HPT374 0x0008 -+#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 // apparently a 372N variant? -+ -+#define PCI_VENDOR_ID_VIA 0x1106 -+#define PCI_DEVICE_ID_VIA_8763_0 0x0198 -+#define PCI_DEVICE_ID_VIA_8380_0 0x0204 -+#define PCI_DEVICE_ID_VIA_3238_0 0x0238 -+#define PCI_DEVICE_ID_VIA_PT880 0x0258 -+#define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259 -+#define PCI_DEVICE_ID_VIA_3269_0 0x0269 -+#define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282 -+#define PCI_DEVICE_ID_VIA_8363_0 0x0305 -+#define PCI_DEVICE_ID_VIA_8371_0 0x0391 -+#define PCI_DEVICE_ID_VIA_8501_0 0x0501 -+#define PCI_DEVICE_ID_VIA_82C505 0x0505 -+#define PCI_DEVICE_ID_VIA_82C561 0x0561 -+#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 -+#define PCI_DEVICE_ID_VIA_82C576 0x0576 -+#define PCI_DEVICE_ID_VIA_82C585 0x0585 -+#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 -+#define PCI_DEVICE_ID_VIA_82C595 0x0595 -+#define PCI_DEVICE_ID_VIA_82C596 0x0596 -+#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 -+#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 -+#define PCI_DEVICE_ID_VIA_8601_0 0x0601 -+#define PCI_DEVICE_ID_VIA_8605_0 0x0605 -+#define PCI_DEVICE_ID_VIA_82C680 0x0680 -+#define PCI_DEVICE_ID_VIA_82C686 0x0686 -+#define PCI_DEVICE_ID_VIA_82C691_0 0x0691 -+#define PCI_DEVICE_ID_VIA_82C693 0x0693 -+#define PCI_DEVICE_ID_VIA_82C693_1 0x0698 -+#define PCI_DEVICE_ID_VIA_82C926 0x0926 -+#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 -+#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 -+#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 -+#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 -+#define PCI_DEVICE_ID_VIA_6305 0x3044 -+#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 -+#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 -+#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 -+#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 -+#define PCI_DEVICE_ID_VIA_8233_5 0x3059 -+#define PCI_DEVICE_ID_VIA_8233_7 0x3065 -+#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 -+#define PCI_DEVICE_ID_VIA_8233_0 0x3074 -+#define PCI_DEVICE_ID_VIA_8633_0 0x3091 -+#define PCI_DEVICE_ID_VIA_8367_0 0x3099 -+#define PCI_DEVICE_ID_VIA_8653_0 0x3101 -+#define PCI_DEVICE_ID_VIA_8622 0x3102 -+#define PCI_DEVICE_ID_VIA_8233C_0 0x3109 -+#define PCI_DEVICE_ID_VIA_8361 0x3112 -+#define PCI_DEVICE_ID_VIA_XM266 0x3116 -+#define PCI_DEVICE_ID_VIA_612X 0x3119 -+#define PCI_DEVICE_ID_VIA_862X_0 0x3123 -+#define PCI_DEVICE_ID_VIA_8753_0 0x3128 -+#define PCI_DEVICE_ID_VIA_8233A 0x3147 -+#define PCI_DEVICE_ID_VIA_8703_51_0 0x3148 -+#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149 -+#define PCI_DEVICE_ID_VIA_XN266 0x3156 -+#define PCI_DEVICE_ID_VIA_8754C_0 0x3168 -+#define PCI_DEVICE_ID_VIA_8235 0x3177 -+#define PCI_DEVICE_ID_VIA_P4N333 0x3178 -+#define PCI_DEVICE_ID_VIA_8385_0 0x3188 -+#define PCI_DEVICE_ID_VIA_8377_0 0x3189 -+#define PCI_DEVICE_ID_VIA_8378_0 0x3205 -+#define PCI_DEVICE_ID_VIA_8783_0 0x3208 -+#define PCI_DEVICE_ID_VIA_P4M400 0x3209 -+#define PCI_DEVICE_ID_VIA_8237 0x3227 -+#define PCI_DEVICE_ID_VIA_3296_0 0x0296 -+#define PCI_DEVICE_ID_VIA_86C100A 0x6100 -+#define PCI_DEVICE_ID_VIA_8231 0x8231 -+#define PCI_DEVICE_ID_VIA_8231_4 0x8235 -+#define PCI_DEVICE_ID_VIA_8365_1 0x8305 -+#define PCI_DEVICE_ID_VIA_8371_1 0x8391 -+#define PCI_DEVICE_ID_VIA_8501_1 0x8501 -+#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 -+#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 -+#define PCI_DEVICE_ID_VIA_8601_1 0x8601 -+#define PCI_DEVICE_ID_VIA_8505_1 0x8605 -+#define PCI_DEVICE_ID_VIA_8633_1 0xB091 -+#define PCI_DEVICE_ID_VIA_8367_1 0xB099 -+#define PCI_DEVICE_ID_VIA_P4X266_1 0xB101 -+#define PCI_DEVICE_ID_VIA_8615_1 0xB103 -+#define PCI_DEVICE_ID_VIA_8361_1 0xB112 -+#define PCI_DEVICE_ID_VIA_8235_1 0xB168 -+#define PCI_DEVICE_ID_VIA_838X_1 0xB188 -+#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198 -+ -+#define PCI_VENDOR_ID_SIEMENS 0x110A -+#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 -+ -+#define PCI_VENDOR_ID_SMC2 0x1113 -+#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 -+ -+#define PCI_VENDOR_ID_VORTEX 0x1119 -+#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 -+#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 -+#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 -+#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 -+#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 -+#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 -+#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 -+#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 -+#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 -+#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 -+#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a -+#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b -+#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c -+#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d -+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 -+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 -+#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 -+#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 -+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 -+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 -+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 -+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 -+#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 -+#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 -+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 -+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 -+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 -+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 -+#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 -+#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 -+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 -+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 -+ -+#define PCI_VENDOR_ID_EF 0x111a -+#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 -+#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 -+#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003 -+#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005 -+ -+#define PCI_VENDOR_ID_IDT 0x111d -+#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 -+ -+#define PCI_VENDOR_ID_FORE 0x1127 -+#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 -+#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 -+ -+#define PCI_VENDOR_ID_IMAGINGTECH 0x112f -+#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 -+ -+#define PCI_VENDOR_ID_PHILIPS 0x1131 -+#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 -+#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 -+#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 -+ -+#define PCI_VENDOR_ID_EICON 0x1133 -+#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001 -+#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 -+#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003 -+#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 -+#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 -+#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b -+#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 -+#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 -+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 -+#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 -+ -+#define PCI_VENDOR_ID_ZIATECH 0x1138 -+#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 -+ -+#define PCI_VENDOR_ID_CYCLONE 0x113c -+#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 -+ -+#define PCI_VENDOR_ID_ALLIANCE 0x1142 -+#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 -+#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 -+#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 -+#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d -+ -+#define PCI_VENDOR_ID_SYSKONNECT 0x1148 -+#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000 -+#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 -+#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 -+#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 -+#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 -+#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 -+ -+#define PCI_VENDOR_ID_VMIC 0x114a -+#define PCI_DEVICE_ID_VMIC_VME 0x7587 -+ -+#define PCI_VENDOR_ID_DIGI 0x114f -+#define PCI_DEVICE_ID_DIGI_EPC 0x0002 -+#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 -+#define PCI_DEVICE_ID_DIGI_XEM 0x0004 -+#define PCI_DEVICE_ID_DIGI_XR 0x0005 -+#define PCI_DEVICE_ID_DIGI_CX 0x0006 -+#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 -+#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a -+#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 -+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 -+#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 -+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 -+#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 -+#define PCI_DEVICE_ID_NEO_2DB9 0x00C8 -+#define PCI_DEVICE_ID_NEO_2DB9PRI 0x00C9 -+#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA -+#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB -+ -+#define PCI_VENDOR_ID_MUTECH 0x1159 -+#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 -+ -+#define PCI_VENDOR_ID_XIRCOM 0x115d -+#define PCI_DEVICE_ID_XIRCOM_X3201_ETH 0x0003 -+#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 -+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 -+ -+#define PCI_VENDOR_ID_RENDITION 0x1163 -+#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 -+#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 -+ -+#define PCI_VENDOR_ID_SERVERWORKS 0x1166 -+#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 -+#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 -+#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 -+#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 -+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 -+#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 -+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 -+#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB -+#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 -+#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 -+#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 -+#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230 -+ -+#define PCI_VENDOR_ID_SBE 0x1176 -+#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 -+#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 -+#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 -+ -+#define PCI_VENDOR_ID_TOSHIBA 0x1179 -+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102 -+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0103 -+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0105 -+#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_A 0x0603 -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_B 0x060a -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f -+#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617 -+ -+#define PCI_VENDOR_ID_TOSHIBA_2 0x102f -+#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a -+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 -+#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180 -+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108 -+ -+#define PCI_VENDOR_ID_RICOH 0x1180 -+#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 -+#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 -+#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 -+#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 -+#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 -+ -+#define PCI_VENDOR_ID_DLINK 0x1186 -+#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00 -+ -+#define PCI_VENDOR_ID_ARTOP 0x1191 -+#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 -+#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 -+#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 -+#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 -+#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 -+#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 -+#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 -+#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 -+#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 -+#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 -+#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 -+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 -+#define PCI_DEVICE_ID_ARTOP_8060 0x8060 -+#define PCI_DEVICE_ID_ARTOP_AEC67160 0x8080 -+#define PCI_DEVICE_ID_ARTOP_AEC67160_2 0x8081 -+#define PCI_DEVICE_ID_ARTOP_AEC67162 0x808a -+ -+#define PCI_VENDOR_ID_ZEITNET 0x1193 -+#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 -+#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 -+ -+#define PCI_VENDOR_ID_OMEGA 0x119b -+#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 -+ -+#define PCI_VENDOR_ID_FUJITSU_ME 0x119e -+#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 -+#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 -+ -+#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 -+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 -+ -+#define PCI_VENDOR_ID_MARVELL 0x11ab -+#define PCI_DEVICE_ID_MARVELL_GT64011 0x4146 -+#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146 -+#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430 -+#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460 -+#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480 -+#define PCI_DEVICE_ID_MARVELL_GT96100 0x9652 -+#define PCI_DEVICE_ID_MARVELL_GT96100A 0x9653 -+ -+#define PCI_VENDOR_ID_LITEON 0x11ad -+#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 -+ -+#define PCI_VENDOR_ID_V3 0x11b0 -+#define PCI_DEVICE_ID_V3_V960 0x0001 -+#define PCI_DEVICE_ID_V3_V350 0x0001 -+#define PCI_DEVICE_ID_V3_V961 0x0002 -+#define PCI_DEVICE_ID_V3_V351 0x0002 -+ -+#define PCI_VENDOR_ID_NP 0x11bc -+#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 -+ -+#define PCI_VENDOR_ID_ATT 0x11c1 -+#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 -+#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 -+ -+#define PCI_VENDOR_ID_NEC2 0x11c3 /* NEC (2nd) */ -+ -+#define PCI_VENDOR_ID_SPECIALIX 0x11cb -+#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 -+#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 -+#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 -+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 -+ -+#define PCI_VENDOR_ID_AURAVISION 0x11d1 -+#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 -+ -+#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 -+#define PCI_DEVICE_ID_AD1889JS 0x1889 -+ -+#define PCI_VENDOR_ID_IKON 0x11d5 -+#define PCI_DEVICE_ID_IKON_10115 0x0115 -+#define PCI_DEVICE_ID_IKON_10117 0x0117 -+ -+#define PCI_VENDOR_ID_SEGA 0x11db -+#define PCI_DEVICE_ID_SEGA_BBA 0x1234 -+ -+#define PCI_VENDOR_ID_ZORAN 0x11de -+#define PCI_DEVICE_ID_ZORAN_36057 0x6057 -+#define PCI_DEVICE_ID_ZORAN_36120 0x6120 -+ -+#define PCI_VENDOR_ID_KINETIC 0x11f4 -+#define PCI_DEVICE_ID_KINETIC_2915 0x2915 -+ -+#define PCI_VENDOR_ID_COMPEX 0x11f6 -+#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 -+#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 -+ -+#define PCI_VENDOR_ID_RP 0x11fe -+#define PCI_DEVICE_ID_RP32INTF 0x0001 -+#define PCI_DEVICE_ID_RP8INTF 0x0002 -+#define PCI_DEVICE_ID_RP16INTF 0x0003 -+#define PCI_DEVICE_ID_RP4QUAD 0x0004 -+#define PCI_DEVICE_ID_RP8OCTA 0x0005 -+#define PCI_DEVICE_ID_RP8J 0x0006 -+#define PCI_DEVICE_ID_RP4J 0x0007 -+#define PCI_DEVICE_ID_RP8SNI 0x0008 -+#define PCI_DEVICE_ID_RP16SNI 0x0009 -+#define PCI_DEVICE_ID_RPP4 0x000A -+#define PCI_DEVICE_ID_RPP8 0x000B -+#define PCI_DEVICE_ID_RP8M 0x000C -+#define PCI_DEVICE_ID_RP4M 0x000D -+#define PCI_DEVICE_ID_RP2_232 0x000E -+#define PCI_DEVICE_ID_RP2_422 0x000F -+#define PCI_DEVICE_ID_URP32INTF 0x0801 -+#define PCI_DEVICE_ID_URP8INTF 0x0802 -+#define PCI_DEVICE_ID_URP16INTF 0x0803 -+#define PCI_DEVICE_ID_URP8OCTA 0x0805 -+#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C -+#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D -+#define PCI_DEVICE_ID_CRP16INTF 0x0903 -+ -+#define PCI_VENDOR_ID_CYCLADES 0x120e -+#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 -+#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 -+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 -+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 -+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 -+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 -+#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 -+#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 -+#define PCI_DEVICE_ID_PC300_RX_2 0x0300 -+#define PCI_DEVICE_ID_PC300_RX_1 0x0301 -+#define PCI_DEVICE_ID_PC300_TE_2 0x0310 -+#define PCI_DEVICE_ID_PC300_TE_1 0x0311 -+#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320 -+#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321 -+ -+/* Allied Telesyn */ -+#define PCI_VENDOR_ID_AT 0x1259 -+#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703 -+ -+#define PCI_VENDOR_ID_ESSENTIAL 0x120f -+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 -+ -+#define PCI_VENDOR_ID_O2 0x1217 -+#define PCI_DEVICE_ID_O2_6729 0x6729 -+#define PCI_DEVICE_ID_O2_6730 0x673a -+#define PCI_DEVICE_ID_O2_6832 0x6832 -+#define PCI_DEVICE_ID_O2_6836 0x6836 -+ -+#define PCI_VENDOR_ID_3DFX 0x121a -+#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 -+#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 -+#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 -+#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 -+#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 -+ -+#define PCI_VENDOR_ID_SIGMADES 0x1236 -+#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 -+ -+#define PCI_VENDOR_ID_CCUBE 0x123f -+ -+#define PCI_VENDOR_ID_AVM 0x1244 -+#define PCI_DEVICE_ID_AVM_B1 0x0700 -+#define PCI_DEVICE_ID_AVM_C4 0x0800 -+#define PCI_DEVICE_ID_AVM_A1 0x0a00 -+#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00 -+#define PCI_DEVICE_ID_AVM_C2 0x1100 -+#define PCI_DEVICE_ID_AVM_T1 0x1200 -+ -+#define PCI_VENDOR_ID_DIPIX 0x1246 -+ -+#define PCI_VENDOR_ID_STALLION 0x124d -+#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 -+#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 -+#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 -+ -+#define PCI_VENDOR_ID_OPTIBASE 0x1255 -+#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 -+#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 -+#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 -+#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 -+#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 -+ -+/* Allied Telesyn */ -+#define PCI_VENDOR_ID_AT 0x1259 -+#define PCI_SUBDEVICE_ID_AT_2700FX 0x2701 -+#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703 -+ -+#define PCI_VENDOR_ID_ESS 0x125d -+#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 -+#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 -+#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 -+ -+#define PCI_VENDOR_ID_SATSAGEM 0x1267 -+#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 -+#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 -+#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b -+ -+#define PCI_VENDOR_ID_HUGHES 0x1273 -+#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 -+ -+#define PCI_VENDOR_ID_ENSONIQ 0x1274 -+#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 -+#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 -+#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 -+ -+#define PCI_VENDOR_ID_TRANSMETA 0x1279 -+#define PCI_DEVICE_ID_EFFICEON 0x0060 -+ -+#define PCI_VENDOR_ID_ROCKWELL 0x127A -+ -+#define PCI_VENDOR_ID_ITE 0x1283 -+#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 -+#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 -+#define PCI_DEVICE_ID_ITE_8872 0x8872 -+#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 -+ -+/* formerly Platform Tech */ -+#define PCI_VENDOR_ID_ESS_OLD 0x1285 -+#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 -+ -+#define PCI_VENDOR_ID_ALTEON 0x12ae -+#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 -+ -+#define PCI_VENDOR_ID_USR 0x12B9 -+ -+#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A -+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B -+ -+#define PCI_VENDOR_ID_PICTUREL 0x12c5 -+#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 -+ -+#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 -+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 -+ -+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 -+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 -+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D -+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 -+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 -+ -+#define PCI_VENDOR_ID_AUREAL 0x12eb -+#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 -+#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 -+#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003 -+ -+#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8 -+#define PCI_DEVICE_ID_LML_33R10 0x8a02 -+ -+#define PCI_VENDOR_ID_CBOARDS 0x1307 -+#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 -+ -+#define PCI_VENDOR_ID_SIIG 0x131f -+#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 -+#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 -+#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 -+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 -+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 -+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 -+#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 -+#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 -+#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 -+#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 -+#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 -+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 -+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 -+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 -+#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 -+#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 -+#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 -+#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 -+#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 -+#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 -+#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 -+#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 -+#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 -+#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 -+#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 -+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 -+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 -+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 -+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 -+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 -+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 -+#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 -+#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 -+#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 -+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 -+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 -+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 -+ -+#define PCI_VENDOR_ID_RADISYS 0x1331 -+#define PCI_DEVICE_ID_RADISYS_ENP2611 0x0030 -+ -+#define PCI_VENDOR_ID_DOMEX 0x134a -+#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 -+ -+#define PCI_VENDOR_ID_QUATECH 0x135C -+#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 -+#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 -+#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 -+#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 -+#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 -+#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 -+ -+#define PCI_VENDOR_ID_SEALEVEL 0x135e -+#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 -+#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 -+#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 -+#define PCI_DEVICE_ID_SEALEVEL_UCOMM8 0x7804 -+ -+#define PCI_VENDOR_ID_HYPERCOPE 0x1365 -+#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 -+#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109 -+ -+#define PCI_VENDOR_ID_KAWASAKI 0x136b -+#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 -+ -+#define PCI_VENDOR_ID_CNET 0x1371 -+#define PCI_DEVICE_ID_CNET_GIGACARD 0x434e -+ -+#define PCI_VENDOR_ID_LMC 0x1376 -+#define PCI_DEVICE_ID_LMC_HSSI 0x0003 -+#define PCI_DEVICE_ID_LMC_DS3 0x0004 -+#define PCI_DEVICE_ID_LMC_SSI 0x0005 -+#define PCI_DEVICE_ID_LMC_T1 0x0006 -+ -+#define PCI_VENDOR_ID_NETGEAR 0x1385 -+#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a -+#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a -+ -+#define PCI_VENDOR_ID_APPLICOM 0x1389 -+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 -+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 -+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 -+ -+#define PCI_VENDOR_ID_MOXA 0x1393 -+#define PCI_DEVICE_ID_MOXA_RC7000 0x0001 -+#define PCI_DEVICE_ID_MOXA_CP102 0x1020 -+#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 -+#define PCI_DEVICE_ID_MOXA_CP102U 0x1022 -+#define PCI_DEVICE_ID_MOXA_C104 0x1040 -+#define PCI_DEVICE_ID_MOXA_CP104U 0x1041 -+#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 -+#define PCI_DEVICE_ID_MOXA_CT114 0x1140 -+#define PCI_DEVICE_ID_MOXA_CP114 0x1141 -+#define PCI_DEVICE_ID_MOXA_CP118U 0x1180 -+#define PCI_DEVICE_ID_MOXA_CP132 0x1320 -+#define PCI_DEVICE_ID_MOXA_CP132U 0x1321 -+#define PCI_DEVICE_ID_MOXA_CP134U 0x1340 -+#define PCI_DEVICE_ID_MOXA_C168 0x1680 -+#define PCI_DEVICE_ID_MOXA_CP168U 0x1681 -+#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 -+#define PCI_DEVICE_ID_MOXA_C218 0x2180 -+#define PCI_DEVICE_ID_MOXA_C320 0x3200 -+ -+#define PCI_VENDOR_ID_CCD 0x1397 -+#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 -+#define PCI_DEVICE_ID_CCD_B000 0xb000 -+#define PCI_DEVICE_ID_CCD_B006 0xb006 -+#define PCI_DEVICE_ID_CCD_B007 0xb007 -+#define PCI_DEVICE_ID_CCD_B008 0xb008 -+#define PCI_DEVICE_ID_CCD_B009 0xb009 -+#define PCI_DEVICE_ID_CCD_B00A 0xb00a -+#define PCI_DEVICE_ID_CCD_B00B 0xb00b -+#define PCI_DEVICE_ID_CCD_B00C 0xb00c -+#define PCI_DEVICE_ID_CCD_B100 0xb100 -+ -+#define PCI_VENDOR_ID_EXAR 0x13a8 -+#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152 -+#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154 -+#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158 -+ -+#define PCI_VENDOR_ID_MICROGATE 0x13c0 -+#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 -+#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020 -+#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 -+#define PCI_DEVICE_ID_MICROGATE_USC2 0x0210 -+ -+#define PCI_VENDOR_ID_3WARE 0x13C1 -+#define PCI_DEVICE_ID_3WARE_1000 0x1000 -+#define PCI_DEVICE_ID_3WARE_7000 0x1001 -+#define PCI_DEVICE_ID_3WARE_9000 0x1002 -+ -+#define PCI_VENDOR_ID_IOMEGA 0x13ca -+#define PCI_DEVICE_ID_IOMEGA_BUZ 0x4231 -+ -+#define PCI_VENDOR_ID_ABOCOM 0x13D1 -+#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 -+ -+#define PCI_VENDOR_ID_CMEDIA 0x13f6 -+#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 -+#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 -+#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 -+#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 -+ -+#define PCI_VENDOR_ID_LAVA 0x1407 -+#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ -+#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ -+#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ -+#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ -+#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ -+#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ -+#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ -+#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 -+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ -+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ -+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 -+ -+#define PCI_VENDOR_ID_TIMEDIA 0x1409 -+#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 -+ -+#define PCI_VENDOR_ID_OXSEMI 0x1415 -+#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 -+#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 -+#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 -+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 -+#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 -+ -+#define PCI_VENDOR_ID_SAMSUNG 0x144d -+ -+#define PCI_VENDOR_ID_AIRONET 0x14b9 -+#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001 -+#define PCI_DEVICE_ID_AIRONET_4800 0x4500 // values switched? see -+#define PCI_DEVICE_ID_AIRONET_4500 0x4800 // drivers/net/aironet4500_card.c -+ -+#define PCI_VENDOR_ID_TITAN 0x14D2 -+#define PCI_DEVICE_ID_TITAN_010L 0x8001 -+#define PCI_DEVICE_ID_TITAN_100L 0x8010 -+#define PCI_DEVICE_ID_TITAN_110L 0x8011 -+#define PCI_DEVICE_ID_TITAN_200L 0x8020 -+#define PCI_DEVICE_ID_TITAN_210L 0x8021 -+#define PCI_DEVICE_ID_TITAN_400L 0x8040 -+#define PCI_DEVICE_ID_TITAN_800L 0x8080 -+#define PCI_DEVICE_ID_TITAN_100 0xA001 -+#define PCI_DEVICE_ID_TITAN_200 0xA005 -+#define PCI_DEVICE_ID_TITAN_400 0xA003 -+#define PCI_DEVICE_ID_TITAN_800B 0xA004 -+ -+#define PCI_VENDOR_ID_PANACOM 0x14d4 -+#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 -+#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 -+ -+#define PCI_VENDOR_ID_SIPACKETS 0x14d9 -+#define PCI_DEVICE_ID_SP_HT 0x0010 -+ -+#define PCI_VENDOR_ID_AFAVLAB 0x14db -+#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 -+#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 -+ -+#define PCI_VENDOR_ID_BROADCOM 0x14e4 -+#define PCI_DEVICE_ID_TIGON3_5752 0x1600 -+#define PCI_DEVICE_ID_TIGON3_5752M 0x1601 -+#define PCI_DEVICE_ID_TIGON3_5700 0x1644 -+#define PCI_DEVICE_ID_TIGON3_5701 0x1645 -+#define PCI_DEVICE_ID_TIGON3_5702 0x1646 -+#define PCI_DEVICE_ID_TIGON3_5703 0x1647 -+#define PCI_DEVICE_ID_TIGON3_5704 0x1648 -+#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 -+#define PCI_DEVICE_ID_NX2_5706 0x164a -+#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d -+#define PCI_DEVICE_ID_TIGON3_5705 0x1653 -+#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 -+#define PCI_DEVICE_ID_TIGON3_5720 0x1658 -+#define PCI_DEVICE_ID_TIGON3_5721 0x1659 -+#define PCI_DEVICE_ID_TIGON3_5705M 0x165d -+#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e -+#define PCI_DEVICE_ID_TIGON3_5705F 0x166e -+#define PCI_DEVICE_ID_TIGON3_5750 0x1676 -+#define PCI_DEVICE_ID_TIGON3_5751 0x1677 -+#define PCI_DEVICE_ID_TIGON3_5750M 0x167c -+#define PCI_DEVICE_ID_TIGON3_5751M 0x167d -+#define PCI_DEVICE_ID_TIGON3_5751F 0x167e -+#define PCI_DEVICE_ID_TIGON3_5782 0x1696 -+#define PCI_DEVICE_ID_TIGON3_5788 0x169c -+#define PCI_DEVICE_ID_TIGON3_5789 0x169d -+#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 -+#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 -+#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 -+#define PCI_DEVICE_ID_NX2_5706S 0x16aa -+#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 -+#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 -+#define PCI_DEVICE_ID_TIGON3_5781 0x16dd -+#define PCI_DEVICE_ID_TIGON3_5753 0x16f7 -+#define PCI_DEVICE_ID_TIGON3_5753M 0x16fd -+#define PCI_DEVICE_ID_TIGON3_5753F 0x16fe -+#define PCI_DEVICE_ID_TIGON3_5901 0x170d -+#define PCI_DEVICE_ID_BCM4401B1 0x170c -+#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e -+#define PCI_DEVICE_ID_BCM4401 0x4401 -+#define PCI_DEVICE_ID_BCM4401B0 0x4402 -+ -+#define PCI_VENDOR_ID_TOPIC 0x151f -+#define PCI_DEVICE_ID_TOPIC_TP560 0x0000 -+ -+#define PCI_VENDOR_ID_ENE 0x1524 -+#define PCI_DEVICE_ID_ENE_1211 0x1211 -+#define PCI_DEVICE_ID_ENE_1225 0x1225 -+#define PCI_DEVICE_ID_ENE_1410 0x1410 -+#define PCI_DEVICE_ID_ENE_1420 0x1420 -+ -+#define PCI_VENDOR_ID_SYBA 0x1592 -+#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 -+#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 -+ -+#define PCI_VENDOR_ID_MORETON 0x15aa -+#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 -+ -+#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 -+#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 -+ -+#define PCI_VENDOR_ID_MELLANOX 0x15b3 -+#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 -+#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 -+#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 -+#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c -+#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 -+ -+#define PCI_VENDOR_ID_PDC 0x15e9 -+#define PCI_DEVICE_ID_PDC_1841 0x1841 -+ -+#define PCI_VENDOR_ID_MACROLINK 0x15ed -+#define PCI_DEVICE_ID_MACROLINK_MCCS8 0x1000 -+#define PCI_DEVICE_ID_MACROLINK_MCCS 0x1001 -+#define PCI_DEVICE_ID_MACROLINK_MCCS8H 0x1002 -+#define PCI_DEVICE_ID_MACROLINK_MCCSH 0x1003 -+#define PCI_DEVICE_ID_MACROLINK_MCCR8 0x2000 -+#define PCI_DEVICE_ID_MACROLINK_MCCR 0x2001 -+ -+#define PCI_VENDOR_ID_FARSITE 0x1619 -+#define PCI_DEVICE_ID_FARSITE_T2P 0x0400 -+#define PCI_DEVICE_ID_FARSITE_T4P 0x0440 -+#define PCI_DEVICE_ID_FARSITE_T1U 0x0610 -+#define PCI_DEVICE_ID_FARSITE_T2U 0x0620 -+#define PCI_DEVICE_ID_FARSITE_T4U 0x0640 -+#define PCI_DEVICE_ID_FARSITE_TE1 0x1610 -+#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 -+ -+#define PCI_VENDOR_ID_SIBYTE 0x166d -+#define PCI_DEVICE_ID_BCM1250_HT 0x0002 -+ -+#define PCI_VENDOR_ID_LINKSYS 0x1737 -+#define PCI_DEVICE_ID_LINKSYS_EG1032 0x1032 -+#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 -+ -+#define PCI_VENDOR_ID_ALTIMA 0x173b -+#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 -+#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9 -+#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea -+#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb -+ -+#define PCI_VENDOR_ID_S2IO 0x17d5 -+#define PCI_DEVICE_ID_S2IO_WIN 0x5731 -+#define PCI_DEVICE_ID_S2IO_UNI 0x5831 -+#define PCI_DEVICE_ID_HERC_WIN 0x5732 -+#define PCI_DEVICE_ID_HERC_UNI 0x5832 -+ -+#define PCI_VENDOR_ID_INFINICON 0x1820 -+ -+#define PCI_VENDOR_ID_TOPSPIN 0x1867 -+ -+#define PCI_VENDOR_ID_TDI 0x192E -+#define PCI_DEVICE_ID_TDI_EHCI 0x0101 -+ -+#define PCI_VENDOR_ID_SYMPHONY 0x1c1c -+#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 -+ -+#define PCI_VENDOR_ID_TEKRAM 0x1de1 -+#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 -+ -+#define PCI_VENDOR_ID_HINT 0x3388 -+#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 -+ -+#define PCI_VENDOR_ID_3DLABS 0x3d3d -+#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 -+#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 -+#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 -+#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 -+#define PCI_DEVICE_ID_3DLABS_MX 0x0006 -+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 -+#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008 -+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 -+ -+#define PCI_VENDOR_ID_AVANCE 0x4005 -+#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 -+#define PCI_DEVICE_ID_AVANCE_2302 0x2302 -+ -+#define PCI_VENDOR_ID_AKS 0x416c -+#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 -+#define PCI_DEVICE_ID_AKS_CPC 0x0200 -+ -+#define PCI_VENDOR_ID_REDCREEK 0x4916 -+#define PCI_DEVICE_ID_RC45 0x1960 -+ -+#define PCI_VENDOR_ID_NETVIN 0x4a14 -+#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 -+ -+#define PCI_VENDOR_ID_S3 0x5333 -+#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 -+#define PCI_DEVICE_ID_S3_ViRGE 0x5631 -+#define PCI_DEVICE_ID_S3_TRIO 0x8811 -+#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 -+#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 -+#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d -+#define PCI_DEVICE_ID_S3_868 0x8880 -+#define PCI_DEVICE_ID_S3_928 0x88b0 -+#define PCI_DEVICE_ID_S3_864_1 0x88c0 -+#define PCI_DEVICE_ID_S3_864_2 0x88c1 -+#define PCI_DEVICE_ID_S3_964_1 0x88d0 -+#define PCI_DEVICE_ID_S3_964_2 0x88d1 -+#define PCI_DEVICE_ID_S3_968 0x88f0 -+#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 -+#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 -+#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 -+#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 -+#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25 -+#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 -+#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 -+#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 -+#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04 -+#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 -+ -+#define PCI_VENDOR_ID_DUNORD 0x5544 -+#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 -+ -+#define PCI_VENDOR_ID_DCI 0x6666 -+#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 -+#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 -+ -+#define PCI_VENDOR_ID_DUNORD 0x5544 -+#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 -+ -+#define PCI_VENDOR_ID_GENROCO 0x5555 -+#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 -+ -+#define PCI_VENDOR_ID_INTEL 0x8086 -+#define PCI_DEVICE_ID_INTEL_EESSC 0x0008 -+#define PCI_DEVICE_ID_INTEL_21145 0x0039 -+#define PCI_DEVICE_ID_INTEL_82375 0x0482 -+#define PCI_DEVICE_ID_INTEL_82424 0x0483 -+#define PCI_DEVICE_ID_INTEL_82378 0x0484 -+#define PCI_DEVICE_ID_INTEL_82430 0x0486 -+#define PCI_DEVICE_ID_INTEL_82434 0x04a3 -+#define PCI_DEVICE_ID_INTEL_I960 0x0960 -+#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 -+#define PCI_DEVICE_ID_INTEL_82562ET 0x1031 -+#define PCI_DEVICE_ID_INTEL_82801CAM 0x1038 -+#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 -+#define PCI_DEVICE_ID_INTEL_82815_AB 0x1131 -+#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132 -+#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 -+#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 -+#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 -+#define PCI_DEVICE_ID_INTEL_7116 0x1223 -+#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 -+#define PCI_DEVICE_ID_INTEL_7505_1 0x2552 -+#define PCI_DEVICE_ID_INTEL_7205_0 0x255d -+#define PCI_DEVICE_ID_INTEL_82596 0x1226 -+#define PCI_DEVICE_ID_INTEL_82865 0x1227 -+#define PCI_DEVICE_ID_INTEL_82557 0x1229 -+#define PCI_DEVICE_ID_INTEL_82437 0x122d -+#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e -+#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 -+#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 -+#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 -+#define PCI_DEVICE_ID_INTEL_82441 0x1237 -+#define PCI_DEVICE_ID_INTEL_82380FB 0x124b -+#define PCI_DEVICE_ID_INTEL_82439 0x1250 -+#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 -+#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 -+#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 -+#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 -+#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 -+#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412 -+#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 -+#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 -+#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 -+#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 -+#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 -+#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 -+#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422 -+#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 -+#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 -+#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 -+#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 -+#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 -+#define PCI_DEVICE_ID_INTEL_82801BA_1 0x2442 -+#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 -+#define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444 -+#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 -+#define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446 -+#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 -+#define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449 -+#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a -+#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b -+#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c -+#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e -+#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 -+#define PCI_DEVICE_ID_INTEL_82801E_2 0x2452 -+#define PCI_DEVICE_ID_INTEL_82801E_3 0x2453 -+#define PCI_DEVICE_ID_INTEL_82801E_9 0x2459 -+#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b -+#define PCI_DEVICE_ID_INTEL_82801E_13 0x245d -+#define PCI_DEVICE_ID_INTEL_82801E_14 0x245e -+#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 -+#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482 -+#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 -+#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484 -+#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 -+#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 -+#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487 -+#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a -+#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b -+#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c -+#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 -+#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1 -+#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2 -+#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 -+#define PCI_DEVICE_ID_INTEL_82801DB_4 0x24c4 -+#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 -+#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 -+#define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7 -+#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9 -+#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca -+#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb -+#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc -+#define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd -+#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 -+#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 -+#define PCI_DEVICE_ID_INTEL_82801EB_2 0x24d2 -+#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 -+#define PCI_DEVICE_ID_INTEL_82801EB_4 0x24d4 -+#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 -+#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 -+#define PCI_DEVICE_ID_INTEL_82801EB_7 0x24d7 -+#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db -+#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd -+#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 -+#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 -+#define PCI_DEVICE_ID_INTEL_ESB_3 0x25a3 -+#define PCI_DEVICE_ID_INTEL_ESB_31 0x25b0 -+#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 -+#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 -+#define PCI_DEVICE_ID_INTEL_ESB_6 0x25a7 -+#define PCI_DEVICE_ID_INTEL_ESB_7 0x25a9 -+#define PCI_DEVICE_ID_INTEL_ESB_8 0x25aa -+#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab -+#define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac -+#define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad -+#define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae -+#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500 -+#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501 -+#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 -+#define PCI_DEVICE_ID_INTEL_82860_HB 0x2531 -+#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 -+#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 -+#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570 -+#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 -+#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578 -+#define PCI_DEVICE_ID_INTEL_82875_IG 0x257b -+#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580 -+#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 -+#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590 -+#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 -+#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770 -+#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 -+#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 -+#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 -+#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642 -+#define PCI_DEVICE_ID_INTEL_ICH6_3 0x2651 -+#define PCI_DEVICE_ID_INTEL_ICH6_4 0x2652 -+#define PCI_DEVICE_ID_INTEL_ICH6_5 0x2653 -+#define PCI_DEVICE_ID_INTEL_ICH6_6 0x2658 -+#define PCI_DEVICE_ID_INTEL_ICH6_7 0x2659 -+#define PCI_DEVICE_ID_INTEL_ICH6_8 0x265a -+#define PCI_DEVICE_ID_INTEL_ICH6_9 0x265b -+#define PCI_DEVICE_ID_INTEL_ICH6_10 0x265c -+#define PCI_DEVICE_ID_INTEL_ICH6_11 0x2660 -+#define PCI_DEVICE_ID_INTEL_ICH6_12 0x2662 -+#define PCI_DEVICE_ID_INTEL_ICH6_13 0x2664 -+#define PCI_DEVICE_ID_INTEL_ICH6_14 0x2666 -+#define PCI_DEVICE_ID_INTEL_ICH6_15 0x2668 -+#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a -+#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d -+#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e -+#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f -+#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670 -+#define PCI_DEVICE_ID_INTEL_ESB2_1 0x2680 -+#define PCI_DEVICE_ID_INTEL_ESB2_2 0x2681 -+#define PCI_DEVICE_ID_INTEL_ESB2_3 0x2682 -+#define PCI_DEVICE_ID_INTEL_ESB2_4 0x2683 -+#define PCI_DEVICE_ID_INTEL_ESB2_5 0x2688 -+#define PCI_DEVICE_ID_INTEL_ESB2_6 0x2689 -+#define PCI_DEVICE_ID_INTEL_ESB2_7 0x268a -+#define PCI_DEVICE_ID_INTEL_ESB2_8 0x268b -+#define PCI_DEVICE_ID_INTEL_ESB2_9 0x268c -+#define PCI_DEVICE_ID_INTEL_ESB2_10 0x2690 -+#define PCI_DEVICE_ID_INTEL_ESB2_11 0x2692 -+#define PCI_DEVICE_ID_INTEL_ESB2_12 0x2694 -+#define PCI_DEVICE_ID_INTEL_ESB2_13 0x2696 -+#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698 -+#define PCI_DEVICE_ID_INTEL_ESB2_15 0x2699 -+#define PCI_DEVICE_ID_INTEL_ESB2_16 0x269a -+#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b -+#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e -+#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 -+#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 -+#define PCI_DEVICE_ID_INTEL_ICH7_2 0x27c0 -+#define PCI_DEVICE_ID_INTEL_ICH7_3 0x27c1 -+#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 -+#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd -+#define PCI_DEVICE_ID_INTEL_ICH7_5 0x27c4 -+#define PCI_DEVICE_ID_INTEL_ICH7_6 0x27c5 -+#define PCI_DEVICE_ID_INTEL_ICH7_7 0x27c8 -+#define PCI_DEVICE_ID_INTEL_ICH7_8 0x27c9 -+#define PCI_DEVICE_ID_INTEL_ICH7_9 0x27ca -+#define PCI_DEVICE_ID_INTEL_ICH7_10 0x27cb -+#define PCI_DEVICE_ID_INTEL_ICH7_11 0x27cc -+#define PCI_DEVICE_ID_INTEL_ICH7_12 0x27d0 -+#define PCI_DEVICE_ID_INTEL_ICH7_13 0x27d2 -+#define PCI_DEVICE_ID_INTEL_ICH7_14 0x27d4 -+#define PCI_DEVICE_ID_INTEL_ICH7_15 0x27d6 -+#define PCI_DEVICE_ID_INTEL_ICH7_16 0x27d8 -+#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da -+#define PCI_DEVICE_ID_INTEL_ICH7_18 0x27dc -+#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd -+#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de -+#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df -+#define PCI_DEVICE_ID_INTEL_ICH7_22 0x27e0 -+#define PCI_DEVICE_ID_INTEL_ICH7_23 0x27e2 -+#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 -+#define PCI_DEVICE_ID_INTEL_ESB2_19 0x3500 -+#define PCI_DEVICE_ID_INTEL_ESB2_20 0x3501 -+#define PCI_DEVICE_ID_INTEL_ESB2_21 0x3504 -+#define PCI_DEVICE_ID_INTEL_ESB2_22 0x3505 -+#define PCI_DEVICE_ID_INTEL_ESB2_23 0x350c -+#define PCI_DEVICE_ID_INTEL_ESB2_24 0x350d -+#define PCI_DEVICE_ID_INTEL_ESB2_25 0x3510 -+#define PCI_DEVICE_ID_INTEL_ESB2_26 0x3511 -+#define PCI_DEVICE_ID_INTEL_ESB2_27 0x3514 -+#define PCI_DEVICE_ID_INTEL_ESB2_28 0x3515 -+#define PCI_DEVICE_ID_INTEL_ESB2_29 0x3518 -+#define PCI_DEVICE_ID_INTEL_ESB2_30 0x3519 -+#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 -+#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 -+#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580 -+#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 -+#define PCI_DEVICE_ID_INTEL_E7520_MCH 0x3590 -+#define PCI_DEVICE_ID_INTEL_E7320_MCH 0x3592 -+#define PCI_DEVICE_ID_INTEL_MCH_PA 0x3595 -+#define PCI_DEVICE_ID_INTEL_MCH_PA1 0x3596 -+#define PCI_DEVICE_ID_INTEL_MCH_PB 0x3597 -+#define PCI_DEVICE_ID_INTEL_MCH_PB1 0x3598 -+#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599 -+#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a -+#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e -+#define PCI_DEVICE_ID_INTEL_80310 0x530d -+#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 -+#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 -+#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 -+#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 -+#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 -+#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 -+#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 -+#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 -+#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 -+#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 -+#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 -+#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 -+#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 -+#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124 -+#define PCI_DEVICE_ID_INTEL_82810E_IG 0x7125 -+#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 -+#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 -+#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 -+#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 -+#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 -+#define PCI_DEVICE_ID_INTEL_440MX 0x7195 -+#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 -+#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 -+#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a -+#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b -+#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 -+#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 -+#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 -+#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600 -+#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 -+#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602 -+#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603 -+#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 -+#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 -+#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca -+#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb -+#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea -+#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 -+#define PCI_DEVICE_ID_INTEL_IXP2400 0x9001 -+#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 -+#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 -+ -+#define PCI_VENDOR_ID_COMPUTONE 0x8e0e -+#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 -+#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 -+#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e -+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 -+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 -+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 -+ -+#define PCI_VENDOR_ID_KTI 0x8e2e -+#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 -+ -+#define PCI_VENDOR_ID_ADAPTEC 0x9004 -+#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 -+#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 -+#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 -+#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 -+#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 -+#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 -+#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 -+#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 -+#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 -+#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 -+#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 -+#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 -+#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 -+#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 -+#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 -+#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 -+#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 -+#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 -+#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 -+#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 -+#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 -+#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 -+#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 -+#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 -+#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 -+#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 -+ -+#define PCI_VENDOR_ID_ADAPTEC2 0x9005 -+#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 -+#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 -+#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 -+#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f -+#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 -+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 -+#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f -+#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 -+#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 -+#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 -+#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f -+#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 -+#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 -+#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 -+#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf -+#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 -+ -+#define PCI_VENDOR_ID_ATRONICS 0x907f -+#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 -+ -+#define PCI_VENDOR_ID_HOLTEK 0x9412 -+#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 -+ -+#define PCI_VENDOR_ID_NETMOS 0x9710 -+#define PCI_DEVICE_ID_NETMOS_9705 0x9705 -+#define PCI_DEVICE_ID_NETMOS_9715 0x9715 -+#define PCI_DEVICE_ID_NETMOS_9735 0x9735 -+#define PCI_DEVICE_ID_NETMOS_9745 0x9745 -+#define PCI_DEVICE_ID_NETMOS_9755 0x9755 -+#define PCI_DEVICE_ID_NETMOS_9805 0x9805 -+#define PCI_DEVICE_ID_NETMOS_9815 0x9815 -+#define PCI_DEVICE_ID_NETMOS_9835 0x9835 -+#define PCI_DEVICE_ID_NETMOS_9845 0x9845 -+#define PCI_DEVICE_ID_NETMOS_9855 0x9855 -+ -+#define PCI_SUBVENDOR_ID_EXSYS 0xd84d -+#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 -+ -+#define PCI_VENDOR_ID_TIGERJET 0xe159 -+#define PCI_DEVICE_ID_TIGERJET_300 0x0001 -+#define PCI_DEVICE_ID_TIGERJET_100 0x0002 -+ -+#define PCI_VENDOR_ID_TTTECH 0x0357 -+#define PCI_DEVICE_ID_TTTECH_MC322 0x000A -+ -+#define PCI_VENDOR_ID_ARK 0xedd8 -+#define PCI_DEVICE_ID_ARK_STING 0xa091 -+#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 -+#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 |