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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-11-02 20:07:26 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-11-02 20:07:26 +0000
commit4f2c17075b25162d8becfd90de751556f425d5dc (patch)
treefc4edc4564190051908bdd3c9288202017930495 /target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch
parent1048c7b452f060c290d973d8a50ec4d178c937e6 (diff)
[lantiq] adds 3.6 files, patches and config
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch')
-rw-r--r--target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch27
1 files changed, 27 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch b/target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch
new file mode 100644
index 000000000..e8a24051c
--- /dev/null
+++ b/target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch
@@ -0,0 +1,27 @@
+From 50b5073dd266721a690323519fb906a56daa09d7 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 1 Nov 2012 20:39:43 +0100
+Subject: [PATCH 101/113] MIPS: lantiq: bootsel bits are wrong
+
+---
+ arch/mips/lantiq/xway/reset.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
+index 22c55f7..a89d1a3 100644
+--- a/arch/mips/lantiq/xway/reset.c
++++ b/arch/mips/lantiq/xway/reset.c
+@@ -34,8 +34,8 @@
+ /* reset cause */
+ #define RCU_STAT_SHIFT 26
+ /* boot selection */
+-#define RCU_BOOT_SEL_SHIFT 26
+-#define RCU_BOOT_SEL_MASK 0x7
++#define RCU_BOOT_SEL_SHIFT 17
++#define RCU_BOOT_SEL_MASK 0xf
+
+ /* remapped base addr of the reset control unit */
+ static void __iomem *ltq_rcu_membase;
+--
+1.7.10.4
+