[lantiq] 3.2 R.I.P.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31911 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 51 deletions

diff --git a/target/linux/lantiq/patches-3.2/0070-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch b/target/linux/lantiq/patches-3.2/0070-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch
deleted file mode 100644
index 40885c8a8..000000000
--- a/target/linux/lantiq/patches-3.2/0070-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 6c2374c768e0eacba197e242e8793d93846dc762 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 11 Apr 2012 18:43:50 +0200
-Subject: [PATCH 70/73] MIPS: lantiq: fix dwc_otg usb for ase
-
-changed irq number and pmu settings. little bit of fiddling to get the now variable
-irq into resources.
-
-Signed-off-by: Conor O'Gorman <i@conorogorman.net>
----
- .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h |    1 +
- drivers/usb/dwc_otg/dwc_otg_driver.c               |    3 +++
- drivers/usb/dwc_otg/dwc_otg_ifx.c                  |    5 ++++-
- 3 files changed, 8 insertions(+), 1 deletions(-)
-
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-@@ -36,6 +36,7 @@
- 
- #define LTQ_TIMER6_INT		(INT_NUM_IM1_IRL0 + 23)
- #define LTQ_USB_INT		(INT_NUM_IM1_IRL0 + 22)
-+#define LTQ_USB_ASE_INT		(INT_NUM_IM0_IRL0 + 31)
- #define LTQ_USB_OC_INT		(INT_NUM_IM4_IRL0 + 23)
- 
- #define MIPS_CPU_TIMER_IRQ		7
---- a/drivers/usb/dwc_otg/dwc_otg_driver.c
-+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
-@@ -860,6 +860,9 @@ static int __init dwc_otg_init(void)
- 
-     printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
- 
-+    if (ltq_is_ase())
-+        dwc_irq = LTQ_USB_ASE_INT;
-+
- 	// ifxmips setup
-     retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
-     if (retval < 0)
---- a/drivers/usb/dwc_otg/dwc_otg_ifx.c
-+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
-@@ -61,7 +61,10 @@ void dwc_otg_power_on (void)
- 	// clear power
- 	writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
- 	// set clock gating
--	writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
-+	if (ltq_is_ase())
-+		writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
-+	else
-+		writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
- 	// set power
- 	writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
- 	writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);