diff options
author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-05-09 12:52:19 +0000 |
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committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-05-09 12:52:19 +0000 |
commit | dcc5e22d87eb62d455f31e8ac36a81f33338f2ab (patch) | |
tree | 81c8801b4ca78a10d166ed2a66fc11ece75b5940 /target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch | |
parent | ee96308b09e5614d8c13237d47da955090d15798 (diff) |
[lantiq] Drop 2.6.32 support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31670 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch')
-rw-r--r-- | target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch | 546 |
1 files changed, 0 insertions, 546 deletions
diff --git a/target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch b/target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch deleted file mode 100644 index 1757266f9..000000000 --- a/target/linux/lantiq/patches-2.6.32/0003-MIPS-Lantiq-Add-PCI-controller-support.patch +++ /dev/null @@ -1,546 +0,0 @@ -From 08127ed36bad367903591bbf0f244179683ccb28 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Wed, 30 Mar 2011 09:27:49 +0200 -Subject: [PATCH 03/13] MIPS: Lantiq: Add PCI controller support. - -The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds -the driver that allows us to use the EBU as a PCI controller. In order for -PCI to work the EBU is set to endianess swap all the data. In addition we -need to make use of SWAP_IO_SPACE for device->host DMA to work. - -The clock of the PCI works in several modes (internal/external). If this -is not configured correctly the SoC will hang. - -Signed-off-by: John Crispin <blogic@openwrt.org> -Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/2250/ -Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---- - .../mips/include/asm/mach-lantiq/lantiq_platform.h | 46 +++ - arch/mips/pci/Makefile | 1 + - arch/mips/pci/ops-lantiq.c | 116 ++++++++ - arch/mips/pci/pci-lantiq.c | 297 ++++++++++++++++++++ - arch/mips/pci/pci-lantiq.h | 18 ++ - 5 files changed, 478 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_platform.h - create mode 100644 arch/mips/pci/ops-lantiq.c - create mode 100644 arch/mips/pci/pci-lantiq.c - create mode 100644 arch/mips/pci/pci-lantiq.h - -diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h -new file mode 100644 -index 0000000..1f1dba6 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h -@@ -0,0 +1,46 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> -+ */ -+ -+#ifndef _LANTIQ_PLATFORM_H__ -+#define _LANTIQ_PLATFORM_H__ -+ -+#include <linux/mtd/partitions.h> -+ -+/* struct used to pass info to the pci core */ -+enum { -+ PCI_CLOCK_INT = 0, -+ PCI_CLOCK_EXT -+}; -+ -+#define PCI_EXIN0 0x0001 -+#define PCI_EXIN1 0x0002 -+#define PCI_EXIN2 0x0004 -+#define PCI_EXIN3 0x0008 -+#define PCI_EXIN4 0x0010 -+#define PCI_EXIN5 0x0020 -+#define PCI_EXIN_MAX 6 -+ -+#define PCI_GNT1 0x0040 -+#define PCI_GNT2 0x0080 -+#define PCI_GNT3 0x0100 -+#define PCI_GNT4 0x0200 -+ -+#define PCI_REQ1 0x0400 -+#define PCI_REQ2 0x0800 -+#define PCI_REQ3 0x1000 -+#define PCI_REQ4 0x2000 -+#define PCI_REQ_SHIFT 10 -+#define PCI_REQ_MASK 0xf -+ -+struct ltq_pci_data { -+ int clock; -+ int gpio; -+ int irq[16]; -+}; -+ -+#endif -diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile -index f0d5329..4df8799 100644 ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o - obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o - obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o - obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o -+obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o - obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o -diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c -new file mode 100644 -index 0000000..1f2afb5 ---- /dev/null -+++ b/arch/mips/pci/ops-lantiq.c -@@ -0,0 +1,116 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> -+ */ -+ -+#include <linux/types.h> -+#include <linux/pci.h> -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/delay.h> -+#include <linux/mm.h> -+#include <asm/addrspace.h> -+#include <linux/vmalloc.h> -+ -+#include <lantiq_soc.h> -+ -+#include "pci-lantiq.h" -+ -+#define LTQ_PCI_CFG_BUSNUM_SHF 16 -+#define LTQ_PCI_CFG_DEVNUM_SHF 11 -+#define LTQ_PCI_CFG_FUNNUM_SHF 8 -+ -+#define PCI_ACCESS_READ 0 -+#define PCI_ACCESS_WRITE 1 -+ -+static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, -+ unsigned int devfn, unsigned int where, u32 *data) -+{ -+ unsigned long cfg_base; -+ unsigned long flags; -+ u32 temp; -+ -+ /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the -+ SoC itself */ -+ if ((bus->number != 0) || ((devfn & 0xf8) > 0x78) -+ || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) -+ return 1; -+ -+ spin_lock_irqsave(&ebu_lock, flags); -+ -+ cfg_base = (unsigned long) ltq_pci_mapped_cfg; -+ cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << -+ LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); -+ -+ /* Perform access */ -+ if (access_type == PCI_ACCESS_WRITE) { -+ ltq_w32(swab32(*data), ((u32 *)cfg_base)); -+ } else { -+ *data = ltq_r32(((u32 *)(cfg_base))); -+ *data = swab32(*data); -+ } -+ wmb(); -+ -+ /* clean possible Master abort */ -+ cfg_base = (unsigned long) ltq_pci_mapped_cfg; -+ cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; -+ temp = ltq_r32(((u32 *)(cfg_base))); -+ temp = swab32(temp); -+ cfg_base = (unsigned long) ltq_pci_mapped_cfg; -+ cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; -+ ltq_w32(temp, ((u32 *)cfg_base)); -+ -+ spin_unlock_irqrestore(&ebu_lock, flags); -+ -+ if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ)) -+ return 1; -+ -+ return 0; -+} -+ -+int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *val) -+{ -+ u32 data = 0; -+ -+ if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ if (size == 1) -+ *val = (data >> ((where & 3) << 3)) & 0xff; -+ else if (size == 2) -+ *val = (data >> ((where & 3) << 3)) & 0xffff; -+ else -+ *val = data; -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 val) -+{ -+ u32 data = 0; -+ -+ if (size == 4) { -+ data = val; -+ } else { -+ if (ltq_pci_config_access(PCI_ACCESS_READ, bus, -+ devfn, where, &data)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ if (size == 1) -+ data = (data & ~(0xff << ((where & 3) << 3))) | -+ (val << ((where & 3) << 3)); -+ else if (size == 2) -+ data = (data & ~(0xffff << ((where & 3) << 3))) | -+ (val << ((where & 3) << 3)); -+ } -+ -+ if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ return PCIBIOS_SUCCESSFUL; -+} -diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c -new file mode 100644 -index 0000000..603d749 ---- /dev/null -+++ b/arch/mips/pci/pci-lantiq.c -@@ -0,0 +1,297 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> -+ */ -+ -+#include <linux/types.h> -+#include <linux/pci.h> -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/delay.h> -+#include <linux/mm.h> -+#include <linux/vmalloc.h> -+#include <linux/platform_device.h> -+ -+#include <asm/pci.h> -+#include <asm/gpio.h> -+#include <asm/addrspace.h> -+ -+#include <lantiq_soc.h> -+#include <lantiq_irq.h> -+#include <lantiq_platform.h> -+ -+#include "pci-lantiq.h" -+ -+#define LTQ_PCI_CFG_BASE 0x17000000 -+#define LTQ_PCI_CFG_SIZE 0x00008000 -+#define LTQ_PCI_MEM_BASE 0x18000000 -+#define LTQ_PCI_MEM_SIZE 0x02000000 -+#define LTQ_PCI_IO_BASE 0x1AE00000 -+#define LTQ_PCI_IO_SIZE 0x00200000 -+ -+#define PCI_CR_FCI_ADDR_MAP0 0x00C0 -+#define PCI_CR_FCI_ADDR_MAP1 0x00C4 -+#define PCI_CR_FCI_ADDR_MAP2 0x00C8 -+#define PCI_CR_FCI_ADDR_MAP3 0x00CC -+#define PCI_CR_FCI_ADDR_MAP4 0x00D0 -+#define PCI_CR_FCI_ADDR_MAP5 0x00D4 -+#define PCI_CR_FCI_ADDR_MAP6 0x00D8 -+#define PCI_CR_FCI_ADDR_MAP7 0x00DC -+#define PCI_CR_CLK_CTRL 0x0000 -+#define PCI_CR_PCI_MOD 0x0030 -+#define PCI_CR_PC_ARB 0x0080 -+#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4 -+#define PCI_CR_BAR11MASK 0x0044 -+#define PCI_CR_BAR12MASK 0x0048 -+#define PCI_CR_BAR13MASK 0x004C -+#define PCI_CS_BASE_ADDR1 0x0010 -+#define PCI_CR_PCI_ADDR_MAP11 0x0064 -+#define PCI_CR_FCI_BURST_LENGTH 0x00E8 -+#define PCI_CR_PCI_EOI 0x002C -+#define PCI_CS_STS_CMD 0x0004 -+ -+#define PCI_MASTER0_REQ_MASK_2BITS 8 -+#define PCI_MASTER1_REQ_MASK_2BITS 10 -+#define PCI_MASTER2_REQ_MASK_2BITS 12 -+#define INTERNAL_ARB_ENABLE_BIT 0 -+ -+#define LTQ_CGU_IFCCR 0x0018 -+#define LTQ_CGU_PCICR 0x0034 -+ -+#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) -+#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) -+ -+#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) -+#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) -+ -+struct ltq_pci_gpio_map { -+ int pin; -+ int alt0; -+ int alt1; -+ int dir; -+ char *name; -+}; -+ -+/* the pci core can make use of the following gpios */ -+static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { -+ { 0, 1, 0, 0, "pci-exin0" }, -+ { 1, 1, 0, 0, "pci-exin1" }, -+ { 2, 1, 0, 0, "pci-exin2" }, -+ { 39, 1, 0, 0, "pci-exin3" }, -+ { 10, 1, 0, 0, "pci-exin4" }, -+ { 9, 1, 0, 0, "pci-exin5" }, -+ { 30, 1, 0, 1, "pci-gnt1" }, -+ { 23, 1, 0, 1, "pci-gnt2" }, -+ { 19, 1, 0, 1, "pci-gnt3" }, -+ { 38, 1, 0, 1, "pci-gnt4" }, -+ { 29, 1, 0, 0, "pci-req1" }, -+ { 31, 1, 0, 0, "pci-req2" }, -+ { 3, 1, 0, 0, "pci-req3" }, -+ { 37, 1, 0, 0, "pci-req4" }, -+}; -+ -+__iomem void *ltq_pci_mapped_cfg; -+static __iomem void *ltq_pci_membase; -+ -+int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; -+ -+/* Since the PCI REQ pins can be reused for other functionality, make it -+ possible to exclude those from interpretation by the PCI controller */ -+static int ltq_pci_req_mask = 0xf; -+ -+static int *ltq_pci_irq_map; -+ -+struct pci_ops ltq_pci_ops = { -+ .read = ltq_pci_read_config_dword, -+ .write = ltq_pci_write_config_dword -+}; -+ -+static struct resource pci_io_resource = { -+ .name = "pci io space", -+ .start = LTQ_PCI_IO_BASE, -+ .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1, -+ .flags = IORESOURCE_IO -+}; -+ -+static struct resource pci_mem_resource = { -+ .name = "pci memory space", -+ .start = LTQ_PCI_MEM_BASE, -+ .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ltq_pci_controller = { -+ .pci_ops = <q_pci_ops, -+ .mem_resource = &pci_mem_resource, -+ .mem_offset = 0x00000000UL, -+ .io_resource = &pci_io_resource, -+ .io_offset = 0x00000000UL, -+}; -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ if (ltqpci_plat_dev_init) -+ return ltqpci_plat_dev_init(dev); -+ -+ return 0; -+} -+ -+static u32 ltq_calc_bar11mask(void) -+{ -+ u32 mem, bar11mask; -+ -+ /* BAR11MASK value depends on available memory on system. */ -+ mem = num_physpages * PAGE_SIZE; -+ bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; -+ -+ return bar11mask; -+} -+ -+static void ltq_pci_setup_gpio(int gpio) -+{ -+ int i; -+ for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { -+ if (gpio & (1 << i)) { -+ ltq_gpio_request(ltq_pci_gpio_map[i].pin, -+ ltq_pci_gpio_map[i].alt0, -+ ltq_pci_gpio_map[i].alt1, -+ ltq_pci_gpio_map[i].dir, -+ ltq_pci_gpio_map[i].name); -+ } -+ } -+ ltq_gpio_request(21, 0, 0, 1, "pci-reset"); -+ ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; -+} -+ -+static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) -+{ -+ u32 temp_buffer; -+ -+ /* set clock to 33Mhz */ -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); -+ -+ /* external or internal clock ? */ -+ if (conf->clock) { -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16), -+ LTQ_CGU_IFCCR); -+ ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR); -+ } else { -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16), -+ LTQ_CGU_IFCCR); -+ ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR); -+ } -+ -+ /* setup pci clock and gpis used by pci */ -+ ltq_pci_setup_gpio(conf->gpio); -+ -+ /* enable auto-switching between PCI and EBU */ -+ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); -+ -+ /* busy, i.e. configuration is not done, PCI access has to be retried */ -+ ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); -+ wmb(); -+ /* BUS Master/IO/MEM access */ -+ ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); -+ -+ /* enable external 2 PCI masters */ -+ temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB); -+ temp_buffer &= (~(ltq_pci_req_mask << 16)); -+ /* enable internal arbiter */ -+ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); -+ /* enable internal PCI master reqest */ -+ temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); -+ -+ /* enable EBU request */ -+ temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); -+ -+ /* enable all external masters request */ -+ temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); -+ ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB); -+ wmb(); -+ -+ /* setup BAR memory regions */ -+ ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); -+ ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); -+ ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); -+ ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); -+ ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); -+ ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); -+ ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); -+ ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); -+ ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); -+ ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK); -+ ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11); -+ ltq_pci_w32(0, PCI_CS_BASE_ADDR1); -+ /* both TX and RX endian swap are enabled */ -+ ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); -+ wmb(); -+ ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000, -+ PCI_CR_BAR12MASK); -+ ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000, -+ PCI_CR_BAR13MASK); -+ /*use 8 dw burst length */ -+ ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH); -+ ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); -+ wmb(); -+ -+ /* setup irq line */ -+ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON); -+ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); -+ -+ /* toggle reset pin */ -+ __gpio_set_value(21, 0); -+ wmb(); -+ mdelay(1); -+ __gpio_set_value(21, 1); -+ return 0; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ if (ltq_pci_irq_map[slot]) -+ return ltq_pci_irq_map[slot]; -+ printk(KERN_ERR "ltq_pci: trying to map irq for unknown slot %d\n", -+ slot); -+ -+ return 0; -+} -+ -+static int __devinit ltq_pci_probe(struct platform_device *pdev) -+{ -+ struct ltq_pci_data *ltq_pci_data = -+ (struct ltq_pci_data *) pdev->dev.platform_data; -+ pci_probe_only = 0; -+ ltq_pci_irq_map = ltq_pci_data->irq; -+ ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); -+ ltq_pci_mapped_cfg = -+ ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); -+ ltq_pci_controller.io_map_base = -+ (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); -+ ltq_pci_startup(ltq_pci_data); -+ register_pci_controller(<q_pci_controller); -+ -+ return 0; -+} -+ -+static struct platform_driver -+ltq_pci_driver = { -+ .probe = ltq_pci_probe, -+ .driver = { -+ .name = "ltq_pci", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init pcibios_init(void) -+{ -+ int ret = platform_driver_register(<q_pci_driver); -+ if (ret) -+ printk(KERN_INFO "ltq_pci: Error registering platfom driver!"); -+ return ret; -+} -+ -+arch_initcall(pcibios_init); -diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h -new file mode 100644 -index 0000000..66bf6cd ---- /dev/null -+++ b/arch/mips/pci/pci-lantiq.h -@@ -0,0 +1,18 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> -+ */ -+ -+#ifndef _LTQ_PCI_H__ -+#define _LTQ_PCI_H__ -+ -+extern __iomem void *ltq_pci_mapped_cfg; -+extern int ltq_pci_read_config_dword(struct pci_bus *bus, -+ unsigned int devfn, int where, int size, u32 *val); -+extern int ltq_pci_write_config_dword(struct pci_bus *bus, -+ unsigned int devfn, int where, int size, u32 val); -+ -+#endif --- -1.7.2.3 - |