bump ifxmips to .30

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17817 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 35 insertions, 0 deletions

diff --git a/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch
new file mode 100644
index 000000000..49ff66310
--- /dev/null
+++ b/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch
@@ -0,0 +1,35 @@
+Index: linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c
+===================================================================
+--- linux-2.6.30.5.orig/arch/mips/kernel/cevt-r4k.c	2009-08-16 23:19:38.000000000 +0200
++++ linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c	2009-09-02 18:26:26.000000000 +0200
+@@ -21,6 +21,22 @@
+ 
+ #ifndef CONFIG_MIPS_MT_SMTC
+ 
++/*
++ * Compare interrupt can be routed and latched outside the core,
++ * so a single execution hazard barrier may not be enough to give
++ * it time to clear as seen in the Cause register.  4 time the
++ * pipeline depth seems reasonably conservative, and empirically
++ * works better in configurations with high CPU/bus clock ratios.
++ */
++
++#define compare_change_hazard() \
++	do { \
++		irq_disable_hazard(); \
++		irq_disable_hazard(); \
++		irq_disable_hazard(); \
++		irq_disable_hazard(); \
++	} while (0)
++
+ static int mips_next_event(unsigned long delta,
+                            struct clock_event_device *evt)
+ {
+@@ -30,6 +46,7 @@
+ 	cnt = read_c0_count();
+ 	cnt += delta;
+ 	write_c0_compare(cnt);
++	compare_change_hazard();
+ 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
+ 	return res;
+ }