diff options
author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-05-11 14:13:15 +0000 |
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committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-05-11 14:13:15 +0000 |
commit | 9a24ac5b8c947665253a616bfc273e0ccb141e41 (patch) | |
tree | 0657d1101a95896275d2f9cb22d757cd7b794fb8 /target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/ifx_start.S | |
parent | e43a5d11b511501338787c90c209606c37816cb4 (diff) |
add u-boot sources for danube
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11108 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/ifx_start.S')
-rw-r--r-- | target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/ifx_start.S | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/ifx_start.S b/target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/ifx_start.S new file mode 100644 index 000000000..17c0b0ae5 --- /dev/null +++ b/target/linux/ifxmips/image/u-boot/files/cpu/mips/danube/ifx_start.S @@ -0,0 +1,51 @@ +/* + * IFX Platform Dependent CPU Initializations + * - for Danube + */ + +#define IFX_EBU_BOOTCFG_DWORD \ + .word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */ \ + .word 0x00000000; /* phases of the flash */ + +#define IFX_MORE_RESERVED_VECTORS \ + XVECENT(romExcHandle,0x400); /* Int, CauseIV=1 */ \ + RVECENT(romReserved,129); \ + RVECENT(romReserved,130); \ + RVECENT(romReserved,131); \ + RVECENT(romReserved,132); \ + RVECENT(romReserved,133); \ + RVECENT(romReserved,134); \ + RVECENT(romReserved,135); \ + RVECENT(romReserved,136); \ + RVECENT(romReserved,137); \ + RVECENT(romReserved,138); \ + RVECENT(romReserved,139); \ + RVECENT(romReserved,140); \ + RVECENT(romReserved,141); \ + RVECENT(romReserved,142); \ + RVECENT(romReserved,143); \ + RVECENT(romExcHandle,0x480); /* EJTAG debug exception */ + +#define IFX_RESET_PRECHECK \ + mfc0 k0, CP0_EBASE; \ + and k0, EBASEF_CPUNUM; \ + bne k0, zero, ifx_mips_handler_1; \ + nop; + +#define IFX_CPU_EXTRA_INIT \ + mfc0 k0, CP0_CONFIG, 7; \ + li k1, 0x04; \ + or k0, k1; \ + mtc0 k0, CP0_CONFIG, 7; + +#define IFX_CACHE_OPER_MODE \ + li t0, CONF_CM_CACHABLE_NO_WA; + +/* + * Stop VCPU + */ +#define IFX_MIPS_HANDLER_1 \ + wait; \ + b ifx_mips_handler_1; \ + nop; + |