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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-22 20:57:09 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-22 20:57:09 +0000
commit664450823b22d9036d099c72cce1e63954838fdd (patch)
tree37abf723731c5d69952adc835c1112e3a284875e /target/linux/ifxmips/files/include
parentf570d01618e0d40623931bbe47dcf8a8cbb76c2f (diff)
fix whitespaces
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9846 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ifxmips/files/include')
-rw-r--r--target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h39
1 files changed, 20 insertions, 19 deletions
diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
index 5b420b8be..43bdfb848 100644
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
@@ -351,24 +351,25 @@
#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
-#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
-#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
-#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
-#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
-#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
-#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
-#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
-#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
-#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
-#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
-#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
-#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
-#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
-#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
-#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
-#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
-#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
-#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
-#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
+#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
+#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
+#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
+#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
+#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
+#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
+#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
+#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
+#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
+#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
+#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
+#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
+#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
+#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
+#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
+#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
+#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
+#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
+#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
+#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
#endif