danube to ifxmips transition

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9825 3c298f89-4303-0410-b956-a3cf2f4a3e73

9 files changed, 150 insertions, 156 deletions

diff --git a/target/linux/ifxmips/files/arch/mips/danube/Kconfig b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
index 03b53b8e4..3d8277ec3 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/Kconfig
+++ b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
@@ -1,35 +1,35 @@
 # copyright 2007 john crispin <blogic@openwrt.org>
 
-menu "Danube built-in"
+menu "IFXMips built-in"
 
 config IFXMIPS_ASC_UART
-	bool "Danube asc uart"
+	bool "IFXMips asc uart"
 	select SERIAL_CORE
 	select SERIAL_CORE_CONSOLE
 	default y
 
 config MTD_IFXMIPS
-	bool "Danube flash map"
+	bool "IFXMips flash map"
 	default y
 
 config IFXMIPS_WDT
-	bool "Danube watchdog"
+	bool "IFXMips watchdog"
 	default y
 
 config IFXMIPS_LED
-	bool "Danube led"
+	bool "IFXMips led"
 	default y
 
 config IFXMIPS_GPIO
-	bool "Danube gpio"
+	bool "IFXMips gpio"
 	default y
 
 config IFXMIPS_SSC
-	bool "Danube ssc"
+	bool "IFXMips ssc"
 	default y
 
 config IFXMIPS_EEPROM
-	bool "Danube eeprom"
+	bool "IFXMips eeprom"
 	default y
 
 endmenu
diff --git a/target/linux/ifxmips/files/arch/mips/danube/Makefile b/target/linux/ifxmips/files/arch/mips/danube/Makefile
index 0fc94ce11..eb2c892e8 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/Makefile
+++ b/target/linux/ifxmips/files/arch/mips/danube/Makefile
@@ -1,9 +1,3 @@
-#
-#  Copyright 2007 openwrt.org
-#       John Crispin <blogic@openwrt.org>
-#
-# Makefile for Infineon Danube
-#
 obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o
 
 obj-$(CONFIG_PCI) += pci.o
diff --git a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
index 11bc4be63..f2bbb3446 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
@@ -19,10 +19,10 @@
 #include <linux/errno.h>
 #include <asm/io.h>
 
-#include <asm/danube/danube.h>
-#include <asm/danube/danube_irq.h>
-#include <asm/danube/danube_dma.h>
-#include <asm/danube/danube_pmu.h>
+#include <asm/ifxmips/ifxmips.h>
+#include <asm/ifxmips/ifxmips_irq.h>
+#include <asm/ifxmips/ifxmips_dma.h>
+#include <asm/ifxmips/ifxmips_pmu.h>
 
 /*25 descriptors for each dma channel,4096/8/20=25.xx*/
 #define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
@@ -32,9 +32,9 @@
 #define DMA_INT_BUDGET      100	/*budget for interrupt handling */
 #define DMA_POLL_COUNTER    4	/*fix me, set the correct counter value here! */
 
-extern void mask_and_ack_danube_irq (unsigned int irq_nr);
-extern void enable_danube_irq (unsigned int irq_nr);
-extern void disable_danube_irq (unsigned int irq_nr);
+extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
+extern void enable_ifxmips_irq (unsigned int irq_nr);
+extern void disable_ifxmips_irq (unsigned int irq_nr);
 
 u64 *g_desc_list;
 _dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
@@ -67,8 +67,8 @@ _dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
 };
 
 _dma_chan_map *chan_map = default_dma_map;
-volatile u32 g_danube_dma_int_status = 0;
-volatile int g_danube_dma_in_process = 0;/*0=not in process,1=in process*/
+volatile u32 g_ifxmips_dma_int_status = 0;
+volatile int g_ifxmips_dma_in_process = 0;/*0=not in process,1=in process*/
 
 void do_dma_tasklet (unsigned long);
 DECLARE_TASKLET (dma_tasklet, do_dma_tasklet, 0);
@@ -101,7 +101,7 @@ enable_ch_irq (_dma_channel_info *pCh)
 	writel(0x4a, IFXMIPS_DMA_CIE);
 	writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
 	local_irq_restore(flag);
-	enable_danube_irq(pCh->irq);
+	enable_ifxmips_irq(pCh->irq);
 }
 
 void
@@ -111,12 +111,12 @@ disable_ch_irq (_dma_channel_info *pCh)
 	int chan_no = (int) (pCh - dma_chan);
 
 	local_irq_save(flag);
-	g_danube_dma_int_status &= ~(1 << chan_no);
+	g_ifxmips_dma_int_status &= ~(1 << chan_no);
 	writel(chan_no, IFXMIPS_DMA_CS);
 	writel(0, IFXMIPS_DMA_CIE);
 	writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
 	local_irq_restore(flag);
-	mask_and_ack_danube_irq(pCh->irq);
+	mask_and_ack_ifxmips_irq(pCh->irq);
 }
 
 void
@@ -180,9 +180,9 @@ rx_chan_intr_handler (int chan_no)
 		writel(chan_no, IFXMIPS_DMA_CS);
 		writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
 		writel(tmp, IFXMIPS_DMA_CS);
-		g_danube_dma_int_status &= ~(1 << chan_no);
+		g_ifxmips_dma_int_status &= ~(1 << chan_no);
 		local_irq_restore(flag);
-		enable_danube_irq(dma_chan[chan_no].irq);
+		enable_ifxmips_irq(dma_chan[chan_no].irq);
 	}
 }
 
@@ -199,7 +199,7 @@ tx_chan_intr_handler (int chan_no)
     writel(chan_no, IFXMIPS_DMA_CS);
     writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
     writel(tmp, IFXMIPS_DMA_CS);
-    g_danube_dma_int_status &= ~(1 << chan_no);
+    g_ifxmips_dma_int_status &= ~(1 << chan_no);
     local_irq_restore(flag);
 	pDev->current_tx_chan = pCh->rel_chan_no;
 	if (pDev->intr_handler)
@@ -215,7 +215,7 @@ do_dma_tasklet (unsigned long unused)
 	int weight = 0;
     int flag;
 
-	while (g_danube_dma_int_status)
+	while (g_ifxmips_dma_int_status)
 	{
 		if (budget-- < 0)
 		{
@@ -226,7 +226,7 @@ do_dma_tasklet (unsigned long unused)
 		weight = 0;
 		for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
 		{
-			if ((g_danube_dma_int_status & (1 << i)) && dma_chan[i].weight > 0)
+			if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0)
 			{
 				if (dma_chan[i].weight > weight)
 				{
@@ -251,10 +251,10 @@ do_dma_tasklet (unsigned long unused)
 	}
 
     local_irq_save(flag);
-	g_danube_dma_in_process = 0;
-    if (g_danube_dma_int_status)
+	g_ifxmips_dma_in_process = 0;
+    if (g_ifxmips_dma_int_status)
 	{
-        g_danube_dma_in_process = 1;
+        g_ifxmips_dma_in_process = 1;
         tasklet_schedule(&dma_tasklet);
     }
     local_irq_restore(flag);
@@ -274,13 +274,13 @@ dma_interrupt (int irq, void *dev_id)
 
 	tmp = readl(IFXMIPS_DMA_IRNEN);
 	writel(0, IFXMIPS_DMA_IRNEN);
-	g_danube_dma_int_status |= 1 << chan_no;
+	g_ifxmips_dma_int_status |= 1 << chan_no;
 	writel(tmp, IFXMIPS_DMA_IRNEN);
-	mask_and_ack_danube_irq(irq);
+	mask_and_ack_ifxmips_irq(irq);
 
-    if (!g_danube_dma_in_process)
+    if (!g_ifxmips_dma_in_process)
 	{
-        g_danube_dma_in_process = 1;
+        g_ifxmips_dma_in_process = 1;
         tasklet_schedule(&dma_tasklet);
     }
 
@@ -387,7 +387,7 @@ dma_device_register(_dma_device_info *dev)
 			writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
 			writel(0x30000, IFXMIPS_DMA_CCTRL);
 			local_irq_restore(flag);
-			enable_danube_irq(dma_chan[chan_no].irq);
+			enable_ifxmips_irq(dma_chan[chan_no].irq);
 		}
 	}
 }
@@ -438,10 +438,10 @@ dma_device_unregister (_dma_device_info *dev)
 	{
 		pCh = dev->rx_chan[i];
 		chan_no = (int)(dev->rx_chan[i] - dma_chan);
-		disable_danube_irq(pCh->irq);
+		disable_ifxmips_irq(pCh->irq);
 
 		local_irq_save(flag);
-		g_danube_dma_int_status &= ~(1 << chan_no);
+		g_ifxmips_dma_int_status &= ~(1 << chan_no);
 		pCh->curr_desc = 0;
 		pCh->prev_desc = 0;
 		pCh->control = IFXMIPS_DMA_CH_OFF;
@@ -685,7 +685,7 @@ dma_chip_init(void)
 	int i;
 
 	// enable DMA from PMU
-	danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
+	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
 
 	// reset DMA
 	writel(readl(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
@@ -704,7 +704,7 @@ dma_chip_init(void)
 }
 
 int
-danube_dma_init (void)
+ifxmips_dma_init (void)
 {
 	int i;
 
@@ -736,7 +736,7 @@ danube_dma_init (void)
 	return 0;
 }
 
-arch_initcall(danube_dma_init);
+arch_initcall(ifxmips_dma_init);
 
 void
 dma_cleanup(void)
diff --git a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
index 163980049..32ecaa023 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
@@ -1,5 +1,5 @@
 /*
- *   arch/mips/danube/interrupt.c
+ *   arch/mips/ifxmips/interrupt.c
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -17,7 +17,7 @@
  *
  *   Copyright (C) 2005 Wu Qi Ming infineon
  *
- *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   Rewrite of Infineon IFXMips code, thanks to infineon for the support,
  *   software and hardware
  *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
@@ -33,97 +33,97 @@
 
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
-#include <asm/danube/danube.h>
-#include <asm/danube/danube_irq.h>
+#include <asm/ifxmips/ifxmips.h>
+#include <asm/ifxmips/ifxmips_irq.h>
 #include <asm/irq_cpu.h>
 
 
 void
-disable_danube_irq (unsigned int irq_nr)
+disable_ifxmips_irq (unsigned int irq_nr)
 {
 	int i;
-	u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
+	u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
 
 	irq_nr -= INT_NUM_IRQ0;
 	for (i = 0; i <= 4; i++)
 	{
 		if (irq_nr < INT_NUM_IM_OFFSET){
-			writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
+			writel(readl(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
 			return;
 		}
-		danube_ier += IFXMIPS_ICU_OFFSET;
+		ifxmips_ier += IFXMIPS_ICU_OFFSET;
 		irq_nr -= INT_NUM_IM_OFFSET;
 	}
 }
-EXPORT_SYMBOL (disable_danube_irq);
+EXPORT_SYMBOL (disable_ifxmips_irq);
 
 void
-mask_and_ack_danube_irq (unsigned int irq_nr)
+mask_and_ack_ifxmips_irq (unsigned int irq_nr)
 {
 	int i;
-	u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
-	u32 *danube_isr = IFXMIPS_ICU_IM0_ISR;
+	u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
+	u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR;
 
 	irq_nr -= INT_NUM_IRQ0;
 	for (i = 0; i <= 4; i++)
 	{
 		if (irq_nr < INT_NUM_IM_OFFSET)
 		{
-			writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
-			writel((1 << irq_nr ), danube_isr);
+			writel(readl(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
+			writel((1 << irq_nr ), ifxmips_isr);
 			return;
 		}
-		danube_ier += IFXMIPS_ICU_OFFSET;
-		danube_isr += IFXMIPS_ICU_OFFSET;
+		ifxmips_ier += IFXMIPS_ICU_OFFSET;
+		ifxmips_isr += IFXMIPS_ICU_OFFSET;
 		irq_nr -= INT_NUM_IM_OFFSET;
 	}
 }
-EXPORT_SYMBOL (mask_and_ack_danube_irq);
+EXPORT_SYMBOL (mask_and_ack_ifxmips_irq);
 
 void
-enable_danube_irq (unsigned int irq_nr)
+enable_ifxmips_irq (unsigned int irq_nr)
 {
 	int i;
-	u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
+	u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
 
 	irq_nr -= INT_NUM_IRQ0;
 	for (i = 0; i <= 4; i++)
 	{
 		if (irq_nr < INT_NUM_IM_OFFSET)
 		{
-			writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
+			writel(readl(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
 			return;
 		}
-		danube_ier += IFXMIPS_ICU_OFFSET;
+		ifxmips_ier += IFXMIPS_ICU_OFFSET;
 		irq_nr -= INT_NUM_IM_OFFSET;
 	}
 }
-EXPORT_SYMBOL (enable_danube_irq);
+EXPORT_SYMBOL (enable_ifxmips_irq);
 
 static unsigned int
-startup_danube_irq (unsigned int irq)
+startup_ifxmips_irq (unsigned int irq)
 {
-	enable_danube_irq (irq);
+	enable_ifxmips_irq (irq);
 	return 0;
 }
 
 static void
-end_danube_irq (unsigned int irq)
+end_ifxmips_irq (unsigned int irq)
 {
 	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-		enable_danube_irq (irq);
+		enable_ifxmips_irq (irq);
 }
 
-static struct hw_interrupt_type danube_irq_type = {
+static struct hw_interrupt_type ifxmips_irq_type = {
 	"IFXMIPS",
-	.startup = startup_danube_irq,
-	.enable = enable_danube_irq,
-	.disable = disable_danube_irq,
-	.unmask = enable_danube_irq,
-	.ack = end_danube_irq,
-	.mask = disable_danube_irq,
-	.mask_ack = mask_and_ack_danube_irq,
-	.end = end_danube_irq,
+	.startup = startup_ifxmips_irq,
+	.enable = enable_ifxmips_irq,
+	.disable = disable_ifxmips_irq,
+	.unmask = enable_ifxmips_irq,
+	.ack = end_ifxmips_irq,
+	.mask = disable_ifxmips_irq,
+	.mask_ack = mask_and_ack_ifxmips_irq,
+	.end = end_ifxmips_irq,
 };
 
 static inline int
@@ -141,7 +141,7 @@ ls1bit32(unsigned long x)
 }
 
 void
-danube_hw_irqdispatch (int module)
+ifxmips_hw_irqdispatch (int module)
 {
 	u32 irq;
 
@@ -171,7 +171,7 @@ plat_irq_dispatch (void)
 		{
 			if (pending & (CAUSEF_IP2 << i))
 			{
-				danube_hw_irqdispatch(i);
+				ifxmips_hw_irqdispatch(i);
 				goto out;
 			}
 		}
@@ -212,7 +212,7 @@ arch_init_irq(void)
 		irq_desc[i].action = NULL;
 		irq_desc[i].depth = 1;
 #endif
-		set_irq_chip_and_handler(i, &danube_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &ifxmips_irq_type, handle_level_irq);
 	}
 
 	set_c0_status (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pci.c b/target/linux/ifxmips/files/arch/mips/danube/pci.c
index 81727805a..3032d87c2 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/pci.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/pci.c
@@ -4,8 +4,8 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
-#include <asm/danube/danube.h>
-#include <asm/danube/danube_irq.h>
+#include <asm/ifxmips/ifxmips.h>
+#include <asm/ifxmips/ifxmips_irq.h>
 #include <asm/addrspace.h>
 #include <linux/vmalloc.h>
 
@@ -21,12 +21,12 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
-static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
+static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
+static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
 
-struct pci_ops danube_pci_ops = {
-	.read = danube_pci_read_config_dword,
-	.write = danube_pci_write_config_dword
+struct pci_ops ifxmips_pci_ops = {
+	.read = ifxmips_pci_read_config_dword,
+	.write = ifxmips_pci_write_config_dword
 };
 
 static struct resource pci_io_resource = {
@@ -43,18 +43,18 @@ static struct resource pci_mem_resource = {
 	.flags = IORESOURCE_MEM
 };
 
-static struct pci_controller danube_pci_controller = {
-	.pci_ops = &danube_pci_ops,
+static struct pci_controller ifxmips_pci_controller = {
+	.pci_ops = &ifxmips_pci_ops,
 	.mem_resource = &pci_mem_resource,
 	.mem_offset	= 0x00000000UL,
 	.io_resource = &pci_io_resource,
 	.io_offset	= 0x00000000UL,
 };
 
-static u32 danube_pci_mapped_cfg;
+static u32 ifxmips_pci_mapped_cfg;
 
 static int
-danube_pci_config_access(unsigned char access_type,
+ifxmips_pci_config_access(unsigned char access_type,
 		struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
 {
 	unsigned long cfg_base;
@@ -62,15 +62,15 @@ danube_pci_config_access(unsigned char access_type,
 
 	u32 temp;
 
-	/* Danube support slot from 0 to 15 */
-	/* dev_fn 0&0x68 (AD29) is danube itself */
+	/* IFXMips support slot from 0 to 15 */
+	/* dev_fn 0&0x68 (AD29) is ifxmips itself */
 	if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
 			|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
 		return 1;
 
 	local_irq_save(flags);
 
-	cfg_base = danube_pci_mapped_cfg;
+	cfg_base = ifxmips_pci_mapped_cfg;
 	cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
 			IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
 
@@ -91,12 +91,12 @@ danube_pci_config_access(unsigned char access_type,
 	wmb();
 
 	/* clean possible Master abort */
-	cfg_base = (danube_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
+	cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
 	temp = readl(((u32*)(cfg_base)));
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
 	temp = swab32 (temp);
 #endif
-	cfg_base = (danube_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
+	cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
 	writel(temp, ((u32*)cfg_base));
 
 	local_irq_restore(flags);
@@ -107,12 +107,12 @@ danube_pci_config_access(unsigned char access_type,
 	return 0;
 }
 
-static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
+static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
 		int where, int size, u32 * val)
 {
 	u32 data = 0;
 
-	if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+	if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	if (size == 1)
@@ -125,7 +125,7 @@ static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
+static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
 		int where, int size, u32 val)
 {
 	u32 data = 0;
@@ -134,7 +134,7 @@ static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn
 	{
 		data = val;
 	} else {
-		if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+		if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 			return PCIBIOS_DEVICE_NOT_FOUND;
 
 		if (size == 1)
@@ -145,7 +145,7 @@ static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn
 				(val << ((where & 3) << 3));
 	}
 
-	if (danube_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+	if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	return PCIBIOS_SUCCESSFUL;
@@ -178,8 +178,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
 	return 0;
 }
 
-static void __init danube_pci_startup (void){
-	/*initialize the first PCI device--danube itself */
+static void __init ifxmips_pci_startup (void){
+	/*initialize the first PCI device--ifxmips itself */
 	u32 temp_buffer;
 	/*TODO: trigger reset */
 	writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
@@ -301,17 +301,17 @@ int pcibios_init(void){
 	pci_probe_only = 0;
 	printk ("PCI: Probing PCI hardware on host bus 0.\n");
 
-	danube_pci_startup ();
+	ifxmips_pci_startup ();
 
 	//	IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
-	danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
-	printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
+	ifxmips_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
+	printk("IFXMips PCI mapped to 0x%08X\n", (unsigned long)ifxmips_pci_mapped_cfg);
 
-	danube_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
+	ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
 
-	printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
+	printk("IFXMips PCI I/O mapped to 0x%08X\n", (unsigned long)ifxmips_pci_controller.io_map_base);
 
-	register_pci_controller(&danube_pci_controller);
+	register_pci_controller(&ifxmips_pci_controller);
 
 	return 0;
 }
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pmu.c b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
index b96cfdc57..296dd5c7a 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/pmu.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
@@ -1,5 +1,5 @@
 /*
- *   arch/mips/danube/pmu.c
+ *   arch/mips/ifxmips/pmu.c
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -22,10 +22,10 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/version.h>
-#include <asm/danube/danube.h>
+#include <asm/ifxmips/ifxmips.h>
 
 void
-danube_pmu_enable (unsigned int module)
+ifxmips_pmu_enable (unsigned int module)
 {
 	int err = 1000000;
 
@@ -35,11 +35,11 @@ danube_pmu_enable (unsigned int module)
 	if (!err)
 		panic("activating PMU module failed!");
 }
-EXPORT_SYMBOL(danube_pmu_enable);
+EXPORT_SYMBOL(ifxmips_pmu_enable);
 
 void
-danube_pmu_disable (unsigned int module)
+ifxmips_pmu_disable (unsigned int module)
 {
 	writel(readl(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
 }
-EXPORT_SYMBOL(danube_pmu_disable);
+EXPORT_SYMBOL(ifxmips_pmu_disable);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/prom.c b/target/linux/ifxmips/files/arch/mips/danube/prom.c
index 9933d419c..317a23ca4 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/prom.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/prom.c
@@ -1,5 +1,5 @@
 /*
- *   arch/mips/danube/prom.c
+ *   arch/mips/ifxmips/prom.c
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -17,7 +17,7 @@
  *
  *   Copyright (C) 2005 Wu Qi Ming infineon
  *
- *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   Rewrite of Infineon IFXMips code, thanks to infineon for the support,
  *   software and hardware
  *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 #include <linux/bootmem.h>
 #include <asm/bootinfo.h>
-#include <asm/danube/danube.h>
+#include <asm/ifxmips/ifxmips.h>
 
 static char buf[1024];
 
diff --git a/target/linux/ifxmips/files/arch/mips/danube/reset.c b/target/linux/ifxmips/files/arch/mips/danube/reset.c
index 333c29d46..a1f7a464b 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/reset.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/reset.c
@@ -1,5 +1,5 @@
 /*
- *   arch/mips/danube/prom.c
+ *   arch/mips/ifxmips/prom.c
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -17,7 +17,7 @@
  *
  *   Copyright (C) 2005 infineon
  *
- *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   Rewrite of Infineon IFXMips code, thanks to infineon for the support,
  *   software and hardware
  *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
@@ -29,10 +29,10 @@
 #include <asm/reboot.h>
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/danube/danube.h>
+#include <asm/ifxmips/ifxmips.h>
 
 static void
-danube_machine_restart (char *command)
+ifxmips_machine_restart (char *command)
 {
 	printk (KERN_NOTICE "System restart\n");
 	local_irq_disable ();
@@ -42,7 +42,7 @@ danube_machine_restart (char *command)
 }
 
 static void
-danube_machine_halt (void)
+ifxmips_machine_halt (void)
 {
 	printk (KERN_NOTICE "System halted.\n");
 	local_irq_disable ();
@@ -50,7 +50,7 @@ danube_machine_halt (void)
 }
 
 static void
-danube_machine_power_off (void)
+ifxmips_machine_power_off (void)
 {
 	printk (KERN_NOTICE "Please turn off the power now.\n");
 	local_irq_disable ();
@@ -58,9 +58,9 @@ danube_machine_power_off (void)
 }
 
 void
-danube_reboot_setup (void)
+ifxmips_reboot_setup (void)
 {
-	_machine_restart = danube_machine_restart;
-	_machine_halt = danube_machine_halt;
-	pm_power_off = danube_machine_power_off;
+	_machine_restart = ifxmips_machine_restart;
+	_machine_halt = ifxmips_machine_halt;
+	pm_power_off = ifxmips_machine_power_off;
 }
diff --git a/target/linux/ifxmips/files/arch/mips/danube/setup.c b/target/linux/ifxmips/files/arch/mips/danube/setup.c
index 0abc5d3ec..8aac788d7 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/setup.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/setup.c
@@ -1,5 +1,5 @@
 /*
- *   arch/mips/danube/setup.c
+ *   arch/mips/ifxmips/setup.c
  *
  *   This program is free software; you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -17,7 +17,7 @@
  *
  *   Copyright (C) 2004 peng.liu@infineon.com 
  *
- *   Rewrite of Infineon Danube code, thanks to infineon for the support,
+ *   Rewrite of Infineon IFXMips code, thanks to infineon for the support,
  *   software and hardware
  *
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
@@ -30,14 +30,14 @@
 #include <asm/traps.h>
 #include <asm/cpu.h>
 #include <asm/irq.h>
-#include <asm/danube/danube.h>
-#include <asm/danube/danube_irq.h>
-#include <asm/danube/danube_pmu.h>
+#include <asm/ifxmips/ifxmips.h>
+#include <asm/ifxmips/ifxmips_irq.h>
+#include <asm/ifxmips/ifxmips_pmu.h>
 
 static unsigned int r4k_offset; /* Amount to increment compare reg each time */
 static unsigned int r4k_cur;    /* What counter should be at next timer irq */
 
-extern void danube_reboot_setup (void);
+extern void ifxmips_reboot_setup (void);
 void prom_printf (const char * fmt, ...);
 
 void
@@ -47,7 +47,7 @@ __init bus_error_init (void)
 }
 
 unsigned int
-danube_get_ddr_hz (void)
+ifxmips_get_ddr_hz (void)
 {
 	switch (readl(IFXMIPS_CGU_SYS) & 0x3)
 	{
@@ -60,12 +60,12 @@ danube_get_ddr_hz (void)
 	}
 	return CLOCK_83M;
 }
-EXPORT_SYMBOL(danube_get_ddr_hz);
+EXPORT_SYMBOL(ifxmips_get_ddr_hz);
 
 unsigned int
-danube_get_cpu_hz (void)
+ifxmips_get_cpu_hz (void)
 {
-	unsigned int ddr_clock = danube_get_ddr_hz();
+	unsigned int ddr_clock = ifxmips_get_ddr_hz();
 	switch (readl(IFXMIPS_CGU_SYS) & 0xc)
 	{
 	case 0:
@@ -75,38 +75,38 @@ danube_get_cpu_hz (void)
 	}
 	return ddr_clock << 1;
 }
-EXPORT_SYMBOL(danube_get_cpu_hz);
+EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 
 unsigned int
-danube_get_fpi_hz (void)
+ifxmips_get_fpi_hz (void)
 {
-	unsigned int ddr_clock = danube_get_ddr_hz();
+	unsigned int ddr_clock = ifxmips_get_ddr_hz();
 	if (readl(IFXMIPS_CGU_SYS) & 0x40)
 	{
 		return ddr_clock >> 1;
 	}
 	return ddr_clock;
 }
-EXPORT_SYMBOL(danube_get_fpi_hz);
+EXPORT_SYMBOL(ifxmips_get_fpi_hz);
 
 unsigned int
-danube_get_cpu_ver (void)
+ifxmips_get_cpu_ver (void)
 {
 	return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
 }
-EXPORT_SYMBOL(danube_get_cpu_ver);
+EXPORT_SYMBOL(ifxmips_get_cpu_ver);
 
 void
-danube_time_init (void)
+ifxmips_time_init (void)
 {
-	mips_hpt_frequency = danube_get_cpu_hz() / 2;
+	mips_hpt_frequency = ifxmips_get_cpu_hz() / 2;
 	r4k_offset = mips_hpt_frequency / HZ;
 	printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
 	printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
 }
 
 int
-danube_be_handler(struct pt_regs *regs, int is_fixup)
+ifxmips_be_handler(struct pt_regs *regs, int is_fixup)
 {
 	/*TODO*/
 	printk(KERN_ERR "TODO: BUS error\n");
@@ -116,7 +116,7 @@ danube_be_handler(struct pt_regs *regs, int is_fixup)
 
 /* ISR GPTU Timer 6 for high resolution timer */
 static irqreturn_t
-danube_timer6_interrupt(int irq, void *dev_id)
+ifxmips_timer6_interrupt(int irq, void *dev_id)
 {
 	timer_interrupt(IFXMIPS_TIMER6_INT, NULL);
 
@@ -124,7 +124,7 @@ danube_timer6_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction hrt_irqaction = {
-	.handler = danube_timer6_interrupt,
+	.handler = ifxmips_timer6_interrupt,
 	.flags = IRQF_DISABLED,
 	.name = "hrt",
 };
@@ -139,7 +139,7 @@ plat_timer_setup (struct irqaction *irq)
 	r4k_cur = (read_c0_count() + r4k_offset);
 	write_c0_compare(r4k_cur);
 
-	danube_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
+	ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
 
 	writel(0x100, IFXMIPS_GPTU_GPT_CLC);
 
@@ -158,7 +158,7 @@ void __init
 plat_mem_setup (void)
 {
 	u32 status;
-	prom_printf("This %s has a cpu rev of 0x%X\n", BOARD_SYSTEM_TYPE, danube_get_cpu_ver());
+	prom_printf("This %s has a cpu rev of 0x%X\n", BOARD_SYSTEM_TYPE, ifxmips_get_cpu_ver());
 
 	//TODO WHY ???
 	/* clear RE bit*/
@@ -166,9 +166,9 @@ plat_mem_setup (void)
 	status &= (~(1<<25));
 	write_c0_status(status);
 
-	danube_reboot_setup();
-	board_time_init = danube_time_init;
-	board_be_handler = &danube_be_handler;
+	ifxmips_reboot_setup();
+	board_time_init = ifxmips_time_init;
+	board_be_handler = &ifxmips_be_handler;
 
 	ioport_resource.start = IOPORT_RESOURCE_START;
 	ioport_resource.end = IOPORT_RESOURCE_END;