change danube 2 ifxmips

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9821 3c298f89-4303-0410-b956-a3cf2f4a3e73

9 files changed, 182 insertions, 182 deletions

diff --git a/target/linux/ifxmips/files/arch/mips/danube/Kconfig b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
index 1c5ad72ca..03b53b8e4 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/Kconfig
+++ b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
@@ -2,33 +2,33 @@
 
 menu "Danube built-in"
 
-config DANUBE_ASC_UART
+config IFXMIPS_ASC_UART
 	bool "Danube asc uart"
 	select SERIAL_CORE
 	select SERIAL_CORE_CONSOLE
 	default y
 
-config MTD_DANUBE
+config MTD_IFXMIPS
 	bool "Danube flash map"
 	default y
 
-config DANUBE_WDT
+config IFXMIPS_WDT
 	bool "Danube watchdog"
 	default y
 
-config DANUBE_LED
+config IFXMIPS_LED
 	bool "Danube led"
 	default y
 
-config DANUBE_GPIO
+config IFXMIPS_GPIO
 	bool "Danube gpio"
 	default y
 
-config DANUBE_SSC
+config IFXMIPS_SSC
 	bool "Danube ssc"
 	default y
 
-config DANUBE_EEPROM
+config IFXMIPS_EEPROM
 	bool "Danube eeprom"
 	default y
 
diff --git a/target/linux/ifxmips/files/arch/mips/danube/Makefile b/target/linux/ifxmips/files/arch/mips/danube/Makefile
index fed8f2f45..0fc94ce11 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/Makefile
+++ b/target/linux/ifxmips/files/arch/mips/danube/Makefile
@@ -4,7 +4,7 @@
 #
 # Makefile for Infineon Danube
 #
-obj-y := reset.o prom.o setup.o interrupt.o dma-core.o
+obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o
 
 obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_KGDB) += kgdb_serial.o
diff --git a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
index 7d29dbdc0..11bc4be63 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
@@ -25,7 +25,7 @@
 #include <asm/danube/danube_pmu.h>
 
 /*25 descriptors for each dma channel,4096/8/20=25.xx*/
-#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
+#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
 
 #define MAX_DMA_DEVICE_NUM  6	/*max ports connecting to dma */
 #define MAX_DMA_CHANNEL_NUM 20	/*max dma channels */
@@ -44,26 +44,26 @@ char global_device_name[MAX_DMA_DEVICE_NUM][20] =
 	{ {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} };
 
 _dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
-	{"PPE", DANUBE_DMA_RX, 0, DANUBE_DMA_CH0_INT, 0},
-	{"PPE", DANUBE_DMA_TX, 0, DANUBE_DMA_CH1_INT, 0},
-	{"PPE", DANUBE_DMA_RX, 1, DANUBE_DMA_CH2_INT, 1},
-	{"PPE", DANUBE_DMA_TX, 1, DANUBE_DMA_CH3_INT, 1},
-	{"PPE", DANUBE_DMA_RX, 2, DANUBE_DMA_CH4_INT, 2},
-	{"PPE", DANUBE_DMA_TX, 2, DANUBE_DMA_CH5_INT, 2},
-	{"PPE", DANUBE_DMA_RX, 3, DANUBE_DMA_CH6_INT, 3},
-	{"PPE", DANUBE_DMA_TX, 3, DANUBE_DMA_CH7_INT, 3},
-	{"DEU", DANUBE_DMA_RX, 0, DANUBE_DMA_CH8_INT, 0},
-	{"DEU", DANUBE_DMA_TX, 0, DANUBE_DMA_CH9_INT, 0},
-	{"DEU", DANUBE_DMA_RX, 1, DANUBE_DMA_CH10_INT, 1},
-	{"DEU", DANUBE_DMA_TX, 1, DANUBE_DMA_CH11_INT, 1},
-	{"SPI", DANUBE_DMA_RX, 0, DANUBE_DMA_CH12_INT, 0},
-	{"SPI", DANUBE_DMA_TX, 0, DANUBE_DMA_CH13_INT, 0},
-	{"SDIO", DANUBE_DMA_RX, 0, DANUBE_DMA_CH14_INT, 0},
-	{"SDIO", DANUBE_DMA_TX, 0, DANUBE_DMA_CH15_INT, 0},
-	{"MCTRL0", DANUBE_DMA_RX, 0, DANUBE_DMA_CH16_INT, 0},
-	{"MCTRL0", DANUBE_DMA_TX, 0, DANUBE_DMA_CH17_INT, 0},
-	{"MCTRL1", DANUBE_DMA_RX, 1, DANUBE_DMA_CH18_INT, 1},
-	{"MCTRL1", DANUBE_DMA_TX, 1, DANUBE_DMA_CH19_INT, 1}
+	{"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
+	{"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
+	{"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
+	{"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
+	{"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
+	{"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
+	{"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
+	{"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
+	{"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
+	{"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
+	{"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
+	{"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
+	{"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
+	{"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
+	{"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
+	{"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
+	{"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
+	{"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
+	{"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
+	{"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
 };
 
 _dma_chan_map *chan_map = default_dma_map;
@@ -97,9 +97,9 @@ enable_ch_irq (_dma_channel_info *pCh)
 	int flag;
 
 	local_irq_save(flag);
-	writel(chan_no, DANUBE_DMA_CS);
-	writel(0x4a, DANUBE_DMA_CIE);
-	writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
+	writel(chan_no, IFXMIPS_DMA_CS);
+	writel(0x4a, IFXMIPS_DMA_CIE);
+	writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
 	local_irq_restore(flag);
 	enable_danube_irq(pCh->irq);
 }
@@ -112,9 +112,9 @@ disable_ch_irq (_dma_channel_info *pCh)
 
 	local_irq_save(flag);
 	g_danube_dma_int_status &= ~(1 << chan_no);
-	writel(chan_no, DANUBE_DMA_CS);
-	writel(0, DANUBE_DMA_CIE);
-	writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);
+	writel(chan_no, IFXMIPS_DMA_CS);
+	writel(0, IFXMIPS_DMA_CIE);
+	writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
 	local_irq_restore(flag);
 	mask_and_ack_danube_irq(pCh->irq);
 }
@@ -126,9 +126,9 @@ open_chan (_dma_channel_info *pCh)
 	int chan_no = (int)(pCh - dma_chan);
 
 	local_irq_save(flag);
-	writel(chan_no, DANUBE_DMA_CS);
-	writel(readl(DANUBE_DMA_CCTRL) | 1, DANUBE_DMA_CCTRL);
-	if(pCh->dir == DANUBE_DMA_RX)
+	writel(chan_no, IFXMIPS_DMA_CS);
+	writel(readl(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
+	if(pCh->dir == IFXMIPS_DMA_RX)
 		enable_ch_irq(pCh);
 	local_irq_restore(flag);
 }
@@ -140,8 +140,8 @@ close_chan(_dma_channel_info *pCh)
 	int chan_no = (int) (pCh - dma_chan);
 
 	local_irq_save(flag);
-	writel(chan_no, DANUBE_DMA_CS);
-	writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+	writel(chan_no, IFXMIPS_DMA_CS);
+	writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
 	disable_ch_irq(pCh);
 	local_irq_restore(flag);
 }
@@ -151,8 +151,8 @@ reset_chan (_dma_channel_info *pCh)
 {
 	int chan_no = (int) (pCh - dma_chan);
 
-	writel(chan_no, DANUBE_DMA_CS);
-	writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
+	writel(chan_no, IFXMIPS_DMA_CS);
+	writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
 }
 
 void
@@ -176,10 +176,10 @@ rx_chan_intr_handler (int chan_no)
 		pCh->weight--;
 	} else {
 		local_irq_save(flag);
-		tmp = readl(DANUBE_DMA_CS);
-		writel(chan_no, DANUBE_DMA_CS);
-		writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
-		writel(tmp, DANUBE_DMA_CS);
+		tmp = readl(IFXMIPS_DMA_CS);
+		writel(chan_no, IFXMIPS_DMA_CS);
+		writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+		writel(tmp, IFXMIPS_DMA_CS);
 		g_danube_dma_int_status &= ~(1 << chan_no);
 		local_irq_restore(flag);
 		enable_danube_irq(dma_chan[chan_no].irq);
@@ -195,10 +195,10 @@ tx_chan_intr_handler (int chan_no)
     int flag;
 
     local_irq_save(flag);
-    tmp = readl(DANUBE_DMA_CS);
-    writel(chan_no, DANUBE_DMA_CS);
-    writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
-    writel(tmp, DANUBE_DMA_CS);
+    tmp = readl(IFXMIPS_DMA_CS);
+    writel(chan_no, IFXMIPS_DMA_CS);
+    writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+    writel(tmp, IFXMIPS_DMA_CS);
     g_danube_dma_int_status &= ~(1 << chan_no);
     local_irq_restore(flag);
 	pDev->current_tx_chan = pCh->rel_chan_no;
@@ -238,7 +238,7 @@ do_dma_tasklet (unsigned long unused)
 
 		if (chan_no >= 0)
 		{
-			if (chan_map[chan_no].dir == DANUBE_DMA_RX)
+			if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
 				rx_chan_intr_handler(chan_no);
 			else
 				tx_chan_intr_handler(chan_no);
@@ -272,10 +272,10 @@ dma_interrupt (int irq, void *dev_id)
 	if (chan_no < 0 || chan_no > 19)
 		BUG();
 
-	tmp = readl(DANUBE_DMA_IRNEN);
-	writel(0, DANUBE_DMA_IRNEN);
+	tmp = readl(IFXMIPS_DMA_IRNEN);
+	writel(0, IFXMIPS_DMA_IRNEN);
 	g_danube_dma_int_status |= 1 << chan_no;
-	writel(tmp, DANUBE_DMA_IRNEN);
+	writel(tmp, IFXMIPS_DMA_IRNEN);
 	mask_and_ack_danube_irq(irq);
 
     if (!g_danube_dma_in_process)
@@ -328,7 +328,7 @@ dma_device_register(_dma_device_info *dev)
 	for (i = 0; i < dev->max_tx_chan_num; i++)
 	{
 		pCh = dev->tx_chan[i];
-		if (pCh->control == DANUBE_DMA_CH_ON)
+		if (pCh->control == IFXMIPS_DMA_CH_ON)
 		{
 			chan_no = (int)(pCh - dma_chan);
 			for (j = 0; j < pCh->desc_len; j++)
@@ -337,16 +337,16 @@ dma_device_register(_dma_device_info *dev)
 				memset(tx_desc_p, 0, sizeof(struct tx_desc));
 			}
 			local_irq_save(flag);
-			writel(chan_no, DANUBE_DMA_CS);
+			writel(chan_no, IFXMIPS_DMA_CS);
 			/*check if the descriptor length is changed */
-			if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
-				writel(pCh->desc_len, DANUBE_DMA_CDLEN);
-
-			writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
-			writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
-			while (readl(DANUBE_DMA_CCTRL) & 2){};
-			writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
-			writel(0x30100, DANUBE_DMA_CCTRL);	/*reset and enable channel,enable channel later */
+			if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+				writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+
+			writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+			while (readl(IFXMIPS_DMA_CCTRL) & 2){};
+			writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+			writel(0x30100, IFXMIPS_DMA_CCTRL);	/*reset and enable channel,enable channel later */
 			local_irq_restore(flag);
 		}
 	}
@@ -354,7 +354,7 @@ dma_device_register(_dma_device_info *dev)
 	for (i = 0; i < dev->max_rx_chan_num; i++)
 	{
 		pCh = dev->rx_chan[i];
-		if (pCh->control == DANUBE_DMA_CH_ON)
+		if (pCh->control == IFXMIPS_DMA_CH_ON)
 		{
 			chan_no = (int)(pCh - dma_chan);
 
@@ -376,16 +376,16 @@ dma_device_register(_dma_device_info *dev)
 			}
 
 			local_irq_save(flag);
-			writel(chan_no, DANUBE_DMA_CS);
+			writel(chan_no, IFXMIPS_DMA_CS);
 			/*check if the descriptor length is changed */
-			if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
-				writel(pCh->desc_len, DANUBE_DMA_CDLEN);
-			writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
-			writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
-			while (readl(DANUBE_DMA_CCTRL) & 2){};
-			writel(0x0a, DANUBE_DMA_CIE);	/*fix me, should enable all the interrupts here? */
-			writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
-			writel(0x30000, DANUBE_DMA_CCTRL);
+			if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+				writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+			writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+			while (readl(IFXMIPS_DMA_CCTRL) & 2){};
+			writel(0x0a, IFXMIPS_DMA_CIE);	/*fix me, should enable all the interrupts here? */
+			writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+			writel(0x30000, IFXMIPS_DMA_CCTRL);
 			local_irq_restore(flag);
 			enable_danube_irq(dma_chan[chan_no].irq);
 		}
@@ -405,18 +405,18 @@ dma_device_unregister (_dma_device_info *dev)
 	for (i = 0; i < dev->max_tx_chan_num; i++)
 	{
 		pCh = dev->tx_chan[i];
-		if (pCh->control == DANUBE_DMA_CH_ON)
+		if (pCh->control == IFXMIPS_DMA_CH_ON)
 		{
 			chan_no = (int)(dev->tx_chan[i] - dma_chan);
 			local_irq_save (flag);
-			writel(chan_no, DANUBE_DMA_CS);
+			writel(chan_no, IFXMIPS_DMA_CS);
 			pCh->curr_desc = 0;
 			pCh->prev_desc = 0;
-			pCh->control = DANUBE_DMA_CH_OFF;
-			writel(0, DANUBE_DMA_CIE);	/*fix me, should disable all the interrupts here? */
-			writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);	/*disable interrupts */
-			writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
-			while (readl(DANUBE_DMA_CCTRL) & 1) {};
+			pCh->control = IFXMIPS_DMA_CH_OFF;
+			writel(0, IFXMIPS_DMA_CIE);	/*fix me, should disable all the interrupts here? */
+			writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);	/*disable interrupts */
+			writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+			while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
 			local_irq_restore (flag);
 
 			for (j = 0; j < pCh->desc_len; j++)
@@ -444,13 +444,13 @@ dma_device_unregister (_dma_device_info *dev)
 		g_danube_dma_int_status &= ~(1 << chan_no);
 		pCh->curr_desc = 0;
 		pCh->prev_desc = 0;
-		pCh->control = DANUBE_DMA_CH_OFF;
+		pCh->control = IFXMIPS_DMA_CH_OFF;
 
-		writel(chan_no, DANUBE_DMA_CS);
-		writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
-		writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);	/*disable interrupts */
-		writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
-		while (readl(DANUBE_DMA_CCTRL) & 1) {};
+		writel(chan_no, IFXMIPS_DMA_CS);
+		writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
+		writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);	/*disable interrupts */
+		writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+		while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
 
 		local_irq_restore (flag);
 		for (j = 0; j < pCh->desc_len; j++)
@@ -577,8 +577,8 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *
 		dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
 	}
 
-	writel(chan_no, DANUBE_DMA_CS);
-	tmp = readl(DANUBE_DMA_CCTRL);
+	writel(chan_no, IFXMIPS_DMA_CS);
+	tmp = readl(IFXMIPS_DMA_CCTRL);
 
 	if (!(tmp & 1))
 		pCh->open (pCh);
@@ -625,14 +625,14 @@ map_dma_chan(_dma_chan_map *map)
 		dma_devs[i].rx_burst_len = 4;
 		if (i == 0)
 		{
-			writel(0, DANUBE_DMA_PS);
-			writel(readl(DANUBE_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), DANUBE_DMA_PCTRL);	/*enable dma drop */
+			writel(0, IFXMIPS_DMA_PS);
+			writel(readl(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL);	/*enable dma drop */
 		}
 
 		if (i == 1)
 		{
-			writel(1, DANUBE_DMA_PS);
-			writel(0x14, DANUBE_DMA_PCTRL);	/*deu port setting */
+			writel(1, IFXMIPS_DMA_PS);
+			writel(0x14, IFXMIPS_DMA_PCTRL);	/*deu port setting */
 		}
 
 		for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
@@ -644,8 +644,8 @@ map_dma_chan(_dma_chan_map *map)
 			dma_chan[j].enable_irq = &enable_ch_irq;
 			dma_chan[j].disable_irq = &disable_ch_irq;
 			dma_chan[j].rel_chan_no = map[j].rel_chan_no;
-			dma_chan[j].control = DANUBE_DMA_CH_OFF;
-			dma_chan[j].default_weight = DANUBE_DMA_CH_DEFAULT_WEIGHT;
+			dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
+			dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
 			dma_chan[j].weight = dma_chan[j].default_weight;
 			dma_chan[j].curr_desc = 0;
 			dma_chan[j].prev_desc = 0;
@@ -655,16 +655,16 @@ map_dma_chan(_dma_chan_map *map)
 		{
 			if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0)
 			{
-				if (map[j].dir == DANUBE_DMA_RX)
+				if (map[j].dir == IFXMIPS_DMA_RX)
 				{
-					dma_chan[j].dir = DANUBE_DMA_RX;
+					dma_chan[j].dir = IFXMIPS_DMA_RX;
 					dma_devs[i].max_rx_chan_num++;
 					dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
 					dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
 					dma_chan[j].dma_dev = (void*)&dma_devs[i];
-				} else if(map[j].dir == DANUBE_DMA_TX)
+				} else if(map[j].dir == IFXMIPS_DMA_TX)
 				{ /*TX direction */
-					dma_chan[j].dir = DANUBE_DMA_TX;
+					dma_chan[j].dir = IFXMIPS_DMA_TX;
 					dma_devs[i].max_tx_chan_num++;
 					dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
 					dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
@@ -685,20 +685,20 @@ dma_chip_init(void)
 	int i;
 
 	// enable DMA from PMU
-	danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
+	danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
 
 	// reset DMA
-	writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
+	writel(readl(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
 
 	// diable all interrupts
-	writel(0, DANUBE_DMA_IRNEN);
+	writel(0, IFXMIPS_DMA_IRNEN);
 
 	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
 	{
-		writel(i, DANUBE_DMA_CS);
-		writel(0x2, DANUBE_DMA_CCTRL);
-		writel(0x80000040, DANUBE_DMA_CPOLL);
-		writel(readl(DANUBE_DMA_CCTRL) & ~0x1, DANUBE_DMA_CCTRL);
+		writel(i, IFXMIPS_DMA_CS);
+		writel(0x2, IFXMIPS_DMA_CCTRL);
+		writel(0x80000040, IFXMIPS_DMA_CPOLL);
+		writel(readl(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
 
 	}
 }
@@ -724,13 +724,13 @@ danube_dma_init (void)
 
 	for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
 	{
-		dma_chan[i].desc_base = (u32)g_desc_list + i * DANUBE_DMA_DESCRIPTOR_OFFSET * 8;
+		dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
 		dma_chan[i].curr_desc = 0;
-		dma_chan[i].desc_len = DANUBE_DMA_DESCRIPTOR_OFFSET;
+		dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
 
-		writel(i, DANUBE_DMA_CS);
-		writel((u32)CPHYSADDR(dma_chan[i].desc_base), DANUBE_DMA_CDBA);
-		writel(dma_chan[i].desc_len, DANUBE_DMA_CDLEN);
+		writel(i, IFXMIPS_DMA_CS);
+		writel((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
+		writel(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
 	}
 
 	return 0;
diff --git a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
index c266608ea..163980049 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
@@ -42,7 +42,7 @@ void
 disable_danube_irq (unsigned int irq_nr)
 {
 	int i;
-	u32 *danube_ier = DANUBE_ICU_IM0_IER;
+	u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
 
 	irq_nr -= INT_NUM_IRQ0;
 	for (i = 0; i <= 4; i++)
@@ -51,7 +51,7 @@ disable_danube_irq (unsigned int irq_nr)
 			writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
 			return;
 		}
-		danube_ier += DANUBE_ICU_OFFSET;
+		danube_ier += IFXMIPS_ICU_OFFSET;
 		irq_nr -= INT_NUM_IM_OFFSET;
 	}
 }
@@ -61,8 +61,8 @@ void
 mask_and_ack_danube_irq (unsigned int irq_nr)
 {
 	int i;
-	u32 *danube_ier = DANUBE_ICU_IM0_IER;
-	u32 *danube_isr = DANUBE_ICU_IM0_ISR;
+	u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
+	u32 *danube_isr = IFXMIPS_ICU_IM0_ISR;
 
 	irq_nr -= INT_NUM_IRQ0;
 	for (i = 0; i <= 4; i++)
@@ -73,8 +73,8 @@ mask_and_ack_danube_irq (unsigned int irq_nr)
 			writel((1 << irq_nr ), danube_isr);
 			return;
 		}
-		danube_ier += DANUBE_ICU_OFFSET;
-		danube_isr += DANUBE_ICU_OFFSET;
+		danube_ier += IFXMIPS_ICU_OFFSET;
+		danube_isr += IFXMIPS_ICU_OFFSET;
 		irq_nr -= INT_NUM_IM_OFFSET;
 	}
 }
@@ -84,7 +84,7 @@ void
 enable_danube_irq (unsigned int irq_nr)
 {
 	int i;
-	u32 *danube_ier = DANUBE_ICU_IM0_IER;
+	u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
 
 	irq_nr -= INT_NUM_IRQ0;
 	for (i = 0; i <= 4; i++)
@@ -94,7 +94,7 @@ enable_danube_irq (unsigned int irq_nr)
 			writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
 			return;
 		}
-		danube_ier += DANUBE_ICU_OFFSET;
+		danube_ier += IFXMIPS_ICU_OFFSET;
 		irq_nr -= INT_NUM_IM_OFFSET;
 	}
 }
@@ -115,7 +115,7 @@ end_danube_irq (unsigned int irq)
 }
 
 static struct hw_interrupt_type danube_irq_type = {
-	"DANUBE",
+	"IFXMIPS",
 	.startup = startup_danube_irq,
 	.enable = enable_danube_irq,
 	.disable = disable_danube_irq,
@@ -145,7 +145,7 @@ danube_hw_irqdispatch (int module)
 {
 	u32 irq;
 
-	irq = readl(DANUBE_ICU_IM0_IOSR + (module * DANUBE_ICU_OFFSET));
+	irq = readl(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
 	if (irq == 0)
 		return;
 
@@ -153,7 +153,7 @@ danube_hw_irqdispatch (int module)
 	do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 
 	if ((irq == 22) && (module == 0)){
-		writel(readl(DANUBE_EBU_PCC_ISTAT) | 0x10, DANUBE_EBU_PCC_ISTAT);
+		writel(readl(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
 	}
 }
 
@@ -195,7 +195,7 @@ arch_init_irq(void)
 
 	for (i = 0; i < 5; i++)
 	{
-		writel(0, DANUBE_ICU_IM0_IER + (i * DANUBE_ICU_OFFSET));
+		writel(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
 	}
 
 	mips_cpu_irq_init();
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pci.c b/target/linux/ifxmips/files/arch/mips/danube/pci.c
index 1896336d8..81727805a 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/pci.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/pci.c
@@ -9,14 +9,14 @@
 #include <asm/addrspace.h>
 #include <linux/vmalloc.h>
 
-#define DANUBE_PCI_MEM_BASE    0x18000000
-#define DANUBE_PCI_MEM_SIZE    0x02000000
-#define DANUBE_PCI_IO_BASE     0x1AE00000
-#define DANUBE_PCI_IO_SIZE     0x00200000
+#define IFXMIPS_PCI_MEM_BASE    0x18000000
+#define IFXMIPS_PCI_MEM_SIZE    0x02000000
+#define IFXMIPS_PCI_IO_BASE     0x1AE00000
+#define IFXMIPS_PCI_IO_SIZE     0x00200000
 
-#define DANUBE_PCI_CFG_BUSNUM_SHF 16
-#define DANUBE_PCI_CFG_DEVNUM_SHF 11
-#define DANUBE_PCI_CFG_FUNNUM_SHF 8
+#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
+#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
+#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
@@ -31,15 +31,15 @@ struct pci_ops danube_pci_ops = {
 
 static struct resource pci_io_resource = {
 	.name = "io pci IO space",
-	.start = DANUBE_PCI_IO_BASE,
-	.end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE - 1,
+	.start = IFXMIPS_PCI_IO_BASE,
+	.end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
 	.flags = IORESOURCE_IO
 };
 
 static struct resource pci_mem_resource = {
 	.name = "ext pci memory space",
-	.start = DANUBE_PCI_MEM_BASE,
-	.end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE - 1,
+	.start = IFXMIPS_PCI_MEM_BASE,
+	.end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
 	.flags = IORESOURCE_MEM
 };
 
@@ -71,32 +71,32 @@ danube_pci_config_access(unsigned char access_type,
 	local_irq_save(flags);
 
 	cfg_base = danube_pci_mapped_cfg;
-	cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
-			DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
+	cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
+			IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
 
 	/* Perform access */
 	if (access_type == PCI_ACCESS_WRITE)
 	{
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
 		writel(swab32(*data), ((u32*)cfg_base));
 #else
 		writel(*data, ((u32*)cfg_base));
 #endif
 	} else {
 		*data = readl(((u32*)(cfg_base)));
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
 		*data = swab32(*data);
 #endif
 	}
 	wmb();
 
 	/* clean possible Master abort */
-	cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
+	cfg_base = (danube_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
 	temp = readl(((u32*)(cfg_base)));
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
 	temp = swab32 (temp);
 #endif
-	cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
+	cfg_base = (danube_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
 	writel(temp, ((u32*)cfg_base));
 
 	local_irq_restore(flags);
@@ -163,8 +163,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
 		case 1:
 			//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
 			printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
-			writel(readl(DANUBE_EBU_PCC_CON) | 0xc, DANUBE_EBU_PCC_CON);
-			writel(readl(DANUBE_EBU_PCC_IEN) | 0x10, DANUBE_EBU_PCC_IEN);
+			writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
+			writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
 			break;
 		case 2:
 		case 3:
@@ -182,31 +182,31 @@ static void __init danube_pci_startup (void){
 	/*initialize the first PCI device--danube itself */
 	u32 temp_buffer;
 	/*TODO: trigger reset */
-	writel(readl(DANUBE_CGU_IFCCR) & ~0xf00000, DANUBE_CGU_IFCCR);
-	writel(readl(DANUBE_CGU_IFCCR) | 0x800000, DANUBE_CGU_IFCCR);
+	writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
+	writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
 	/* PCIS of IF_CLK of CGU   : 1 =>PCI Clock output
 	   0 =>clock input
 	   PADsel of PCI_CR of CGU : 1 =>From CGU
 	   : 0 =>From pad
 	 */
-	writel(readl(DANUBE_CGU_IFCCR) | (1 << 16), DANUBE_CGU_IFCCR);
-	writel((1 << 31) | (1 << 30), DANUBE_CGU_PCICR);
+	writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
+	writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 
 	/* prepare GPIO */
 	/* PCI_RST: P1.5 ALT 01 */
 	//pliu20060613: start
-	writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
-	writel(readl(DANUBE_GPIO_P1_OD) | (1 << 5), DANUBE_GPIO_P1_OD);
-	writel(readl(DANUBE_GPIO_P1_DIR) | (1 << 5), DANUBE_GPIO_P1_DIR);
-	writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL1);
-	writel(readl(DANUBE_GPIO_P1_ALTSEL0) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL0);
+	writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
+	writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
+	writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
+	writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
+	writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
 	//pliu20060613: end
 	/* PCI_REQ1: P1.13 ALT 01 */
 	/* PCI_GNT1: P1.14 ALT 01 */
-	writel(readl(DANUBE_GPIO_P1_DIR) & ~0x2000, DANUBE_GPIO_P1_DIR);
-	writel(readl(DANUBE_GPIO_P1_DIR) | 0x4000, DANUBE_GPIO_P1_DIR);
-	writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~0x6000, DANUBE_GPIO_P1_ALTSEL1);
-	writel(readl(DANUBE_GPIO_P1_ALTSEL0) | 0x6000, DANUBE_GPIO_P1_ALTSEL0);
+	writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
+	writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
+	writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
+	writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
 	/* PCI_REQ2: P1.15 ALT 10 */
 	/* PCI_GNT2: P1.7 ALT 10 */
 
@@ -260,9 +260,9 @@ static void __init danube_pci_startup (void){
 	writel(0x0e000008, PCI_CR_BAR11MASK);
 	writel(0, PCI_CR_PCI_ADDR_MAP11);
 	writel(0, PCI_CS_BASE_ADDR1);
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
 	/* both TX and RX endian swap are enabled */
-	DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
+	IFXMIPS_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
 	wmb ();
 #endif
 	/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
@@ -273,10 +273,10 @@ static void __init danube_pci_startup (void){
 
 	writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 	wmb();
-	writel(readl(DANUBE_GPIO_P1_OUT) & ~(1 << 5), DANUBE_GPIO_P1_OUT);
+	writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
 	wmb();
 	mdelay (1);
-	writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
+	writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
 }
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
@@ -303,11 +303,11 @@ int pcibios_init(void){
 
 	danube_pci_startup ();
 
-	//	DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
+	//	IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
 	danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
 	printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
 
-	danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE - 1);
+	danube_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
 
 	printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
 
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pmu.c b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
index 5bb66dbe5..b96cfdc57 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/pmu.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
@@ -29,8 +29,8 @@ danube_pmu_enable (unsigned int module)
 {
 	int err = 1000000;
 
-	writel(readl(DANUBE_PMU_PWDCR) & ~module, DANUBE_PMU_PWDCR);
-	while (--err && (readl(DANUBE_PMU_PWDSR) & module)) {}
+	writel(readl(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
+	while (--err && (readl(IFXMIPS_PMU_PWDSR) & module)) {}
 
 	if (!err)
 		panic("activating PMU module failed!");
@@ -40,6 +40,6 @@ EXPORT_SYMBOL(danube_pmu_enable);
 void
 danube_pmu_disable (unsigned int module)
 {
-	writel(readl(DANUBE_PMU_PWDCR) | module, DANUBE_PMU_PWDCR);
+	writel(readl(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
 }
 EXPORT_SYMBOL(danube_pmu_disable);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/prom.c b/target/linux/ifxmips/files/arch/mips/danube/prom.c
index efb06120e..9933d419c 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/prom.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/prom.c
@@ -45,11 +45,11 @@ get_system_type (void)
 void
 prom_putchar (char c)
 {
-	while ((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+	while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
 
 	if (c == '\n')
-		writel('\r', DANUBE_ASC1_TBUF);
-	writel(c, DANUBE_ASC1_TBUF);
+		writel('\r', IFXMIPS_ASC1_TBUF);
+	writel(c, IFXMIPS_ASC1_TBUF);
 }
 
 void
@@ -73,8 +73,8 @@ prom_printf (const char * fmt, ...)
 void __init
 prom_init(void)
 {
-	mips_machgroup = MACH_GROUP_DANUBE;
-	mips_machtype = MACH_INFINEON_DANUBE;
+	mips_machgroup = MACH_GROUP_IFXMIPS;
+	mips_machtype = MACH_INFINEON_IFXMIPS;
 
 	strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
 	add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/reset.c b/target/linux/ifxmips/files/arch/mips/danube/reset.c
index cb1793ca7..333c29d46 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/reset.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/reset.c
@@ -37,7 +37,7 @@ danube_machine_restart (char *command)
 	printk (KERN_NOTICE "System restart\n");
 	local_irq_disable ();
 
-	writel(readl(DANUBE_RCU_REQ) | DANUBE_RST_ALL, DANUBE_RCU_REQ);
+	writel(readl(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
 	for (;;);
 }
 
diff --git a/target/linux/ifxmips/files/arch/mips/danube/setup.c b/target/linux/ifxmips/files/arch/mips/danube/setup.c
index 60b0ce28e..0abc5d3ec 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/setup.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/setup.c
@@ -49,7 +49,7 @@ __init bus_error_init (void)
 unsigned int
 danube_get_ddr_hz (void)
 {
-	switch (readl(DANUBE_CGU_SYS) & 0x3)
+	switch (readl(IFXMIPS_CGU_SYS) & 0x3)
 	{
 	case 0:
 		return CLOCK_167M;
@@ -66,7 +66,7 @@ unsigned int
 danube_get_cpu_hz (void)
 {
 	unsigned int ddr_clock = danube_get_ddr_hz();
-	switch (readl(DANUBE_CGU_SYS) & 0xc)
+	switch (readl(IFXMIPS_CGU_SYS) & 0xc)
 	{
 	case 0:
 		return CLOCK_333M;
@@ -81,7 +81,7 @@ unsigned int
 danube_get_fpi_hz (void)
 {
 	unsigned int ddr_clock = danube_get_ddr_hz();
-	if (readl(DANUBE_CGU_SYS) & 0x40)
+	if (readl(IFXMIPS_CGU_SYS) & 0x40)
 	{
 		return ddr_clock >> 1;
 	}
@@ -92,7 +92,7 @@ EXPORT_SYMBOL(danube_get_fpi_hz);
 unsigned int
 danube_get_cpu_ver (void)
 {
-	return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
+	return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
 }
 EXPORT_SYMBOL(danube_get_cpu_ver);
 
@@ -118,7 +118,7 @@ danube_be_handler(struct pt_regs *regs, int is_fixup)
 static irqreturn_t
 danube_timer6_interrupt(int irq, void *dev_id)
 {
-	timer_interrupt(DANUBE_TIMER6_INT, NULL);
+	timer_interrupt(IFXMIPS_TIMER6_INT, NULL);
 
 	return IRQ_HANDLED;
 }
@@ -139,18 +139,18 @@ plat_timer_setup (struct irqaction *irq)
 	r4k_cur = (read_c0_count() + r4k_offset);
 	write_c0_compare(r4k_cur);
 
-	danube_pmu_enable(DANUBE_PMU_PWDCR_GPT | DANUBE_PMU_PWDCR_FPI);
+	danube_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
 
-	writel(0x100, DANUBE_GPTU_GPT_CLC);
+	writel(0x100, IFXMIPS_GPTU_GPT_CLC);
 
-	writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
-	writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
+	writel(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
+	writel(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
 
-	retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
+	retval = setup_irq(IFXMIPS_TIMER6_INT, &hrt_irqaction);
 
 	if (retval)
 	{
-		prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
+		prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", IFXMIPS_TIMER6_INT);
 	}
 }