kernel: update bcma and ssb for kernel 3.8+ to version from wireless-testing master-2013-04-26.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@36473 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 319 insertions, 10 deletions

diff --git a/target/linux/generic/patches-3.9/025-bcma_backport.patch b/target/linux/generic/patches-3.9/025-bcma_backport.patch
index 489dc2018..a1a1ebc0f 100644
--- a/target/linux/generic/patches-3.9/025-bcma_backport.patch
+++ b/target/linux/generic/patches-3.9/025-bcma_backport.patch
@@ -1,3 +1,234 @@
+--- a/drivers/bcma/core.c
++++ b/drivers/bcma/core.c
+@@ -104,7 +104,13 @@ void bcma_core_pll_ctl(struct bcma_devic
+ 		if (i)
+ 			bcma_err(core->bus, "PLL enable timeout\n");
+ 	} else {
+-		bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
++		/*
++		 * Mask the PLL but don't wait for it to be disabled. PLL may be
++		 * shared between cores and will be still up if there is another
++		 * core using it.
++		 */
++		bcma_mask32(core, BCMA_CLKCTLST, ~req);
++		bcma_read32(core, BCMA_CLKCTLST);
+ 	}
+ }
+ EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
+--- a/drivers/bcma/driver_chipcommon.c
++++ b/drivers/bcma/driver_chipcommon.c
+@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
+ 	return value;
+ }
+ 
+-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
++u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
+ {
+ 	if (cc->capabilities & BCMA_CC_CAP_PMU)
+ 		return bcma_pmu_get_alp_clock(cc);
+ 
+ 	return 20000000;
+ }
++EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
+ 
+ static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
+ {
+@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
+ 
+ 	return res;
+ }
++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
+ 
+ u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
+ {
+@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
+ 
+ 	return res;
+ }
++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
+ 
+ /*
+  * If the bit is set to 0, chipcommon controlls this GPIO,
+--- a/drivers/bcma/driver_chipcommon_pmu.c
++++ b/drivers/bcma/driver_chipcommon_pmu.c
+@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
+ 	struct bcma_bus *bus = cc->core->bus;
+ 
+ 	switch (bus->chipinfo.id) {
++	case BCMA_CHIP_ID_BCM4313:
++	case BCMA_CHIP_ID_BCM43224:
++	case BCMA_CHIP_ID_BCM43225:
++	case BCMA_CHIP_ID_BCM43227:
++	case BCMA_CHIP_ID_BCM43228:
++	case BCMA_CHIP_ID_BCM4331:
++	case BCMA_CHIP_ID_BCM43421:
++	case BCMA_CHIP_ID_BCM43428:
++	case BCMA_CHIP_ID_BCM43431:
+ 	case BCMA_CHIP_ID_BCM4716:
+-	case BCMA_CHIP_ID_BCM4748:
+ 	case BCMA_CHIP_ID_BCM47162:
+-	case BCMA_CHIP_ID_BCM4313:
+-	case BCMA_CHIP_ID_BCM5357:
++	case BCMA_CHIP_ID_BCM4748:
+ 	case BCMA_CHIP_ID_BCM4749:
++	case BCMA_CHIP_ID_BCM5357:
+ 	case BCMA_CHIP_ID_BCM53572:
++	case BCMA_CHIP_ID_BCM6362:
+ 		/* always 20Mhz */
+ 		return 20000 * 1000;
+-	case BCMA_CHIP_ID_BCM5356:
+ 	case BCMA_CHIP_ID_BCM4706:
++	case BCMA_CHIP_ID_BCM5356:
+ 		/* always 25Mhz */
+ 		return 25000 * 1000;
++	case BCMA_CHIP_ID_BCM43460:
++	case BCMA_CHIP_ID_BCM4352:
++	case BCMA_CHIP_ID_BCM4360:
++		if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
++			return 40000 * 1000;
++		else
++			return 20000 * 1000;
+ 	default:
+ 		bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
+ 			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
+@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 		tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
+ 		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
+ 
+-		tmp = 1 << 10;
++		tmp = BCMA_CC_PMU_CTL_PLL_UPD;
+ 		break;
+ 
+ 	case BCMA_CHIP_ID_BCM4331:
+@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
+ 						     0x03000a08);
+ 		}
+-		tmp = 1 << 10;
++		tmp = BCMA_CC_PMU_CTL_PLL_UPD;
+ 		break;
+ 
+ 	case BCMA_CHIP_ID_BCM43224:
+@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
+ 						     0x88888815);
+ 		}
+-		tmp = 1 << 10;
++		tmp = BCMA_CC_PMU_CTL_PLL_UPD;
+ 		break;
+ 
+ 	case BCMA_CHIP_ID_BCM4716:
+@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 						     0x88888815);
+ 		}
+ 
+-		tmp = 3 << 9;
++		tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
+ 		break;
+ 
+ 	case BCMA_CHIP_ID_BCM43227:
+@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
+ 			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
+ 						     0x88888815);
+ 		}
+-		tmp = 1 << 10;
++		tmp = BCMA_CC_PMU_CTL_PLL_UPD;
+ 		break;
+ 	default:
+ 		bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -120,6 +120,11 @@ static int bcma_register_cores(struct bc
+ 			continue;
+ 		}
+ 
++		/* Only first GMAC core on BCM4706 is connected and working */
++		if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
++		    core->core_unit > 0)
++			continue;
++
+ 		core->dev.release = bcma_release_core_dev;
+ 		core->dev.bus = &bcma_bus_type;
+ 		dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
+--- a/drivers/bcma/scan.c
++++ b/drivers/bcma/scan.c
+@@ -137,19 +137,19 @@ static void bcma_scan_switch_core(struct
+ 				       addr);
+ }
+ 
+-static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
++static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
+ {
+ 	u32 ent = readl(*eromptr);
+ 	(*eromptr)++;
+ 	return ent;
+ }
+ 
+-static void bcma_erom_push_ent(u32 **eromptr)
++static void bcma_erom_push_ent(u32 __iomem **eromptr)
+ {
+ 	(*eromptr)--;
+ }
+ 
+-static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
++static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
+ {
+ 	u32 ent = bcma_erom_get_ent(bus, eromptr);
+ 	if (!(ent & SCAN_ER_VALID))
+@@ -159,14 +159,14 @@ static s32 bcma_erom_get_ci(struct bcma_
+ 	return ent;
+ }
+ 
+-static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
++static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
+ {
+ 	u32 ent = bcma_erom_get_ent(bus, eromptr);
+ 	bcma_erom_push_ent(eromptr);
+ 	return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
+ }
+ 
+-static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
++static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
+ {
+ 	u32 ent = bcma_erom_get_ent(bus, eromptr);
+ 	bcma_erom_push_ent(eromptr);
+@@ -175,7 +175,7 @@ static bool bcma_erom_is_bridge(struct b
+ 		((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
+ }
+ 
+-static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
++static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
+ {
+ 	u32 ent;
+ 	while (1) {
+@@ -189,7 +189,7 @@ static void bcma_erom_skip_component(str
+ 	bcma_erom_push_ent(eromptr);
+ }
+ 
+-static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
++static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
+ {
+ 	u32 ent = bcma_erom_get_ent(bus, eromptr);
+ 	if (!(ent & SCAN_ER_VALID))
+@@ -199,7 +199,7 @@ static s32 bcma_erom_get_mst_port(struct
+ 	return ent;
+ }
+ 
+-static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
++static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
+ 				  u32 type, u8 port)
+ {
+ 	u32 addrl, addrh, sizel, sizeh = 0;
+--- a/drivers/bcma/sprom.c
++++ b/drivers/bcma/sprom.c
+@@ -217,6 +217,7 @@ static void bcma_sprom_extract_r8(struct
+ 	}
+ 
+ 	SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
+ 
+ 	SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
+ 	     SSB_SPROM4_TXPID2G0_SHIFT);
 --- a/include/linux/bcma/bcma.h
 +++ b/include/linux/bcma/bcma.h
 @@ -134,6 +134,7 @@ struct bcma_host_ops {
@@ -8,19 +239,78 @@
  #define BCMA_CORE_DEFAULT		0xFFF
  
  #define BCMA_MAX_NR_CORES		16
---- a/include/linux/bcma/bcma_regs.h
-+++ b/include/linux/bcma/bcma_regs.h
-@@ -37,6 +37,7 @@
- #define  BCMA_IOST_BIST_DONE		0x8000
- #define BCMA_RESET_CTL			0x0800
- #define  BCMA_RESET_CTL_RESET		0x0001
-+#define BCMA_RESET_ST			0x0804
+@@ -173,6 +174,60 @@ struct bcma_host_ops {
+ #define BCMA_CHIP_ID_BCM53572	53572
+ #define  BCMA_PKG_ID_BCM47188	9
  
- /* BCMA PCI config space registers. */
- #define BCMA_PCI_PMCSR			0x44
++/* Board types (on PCI usually equals to the subsystem dev id) */
++/* BCM4313 */
++#define BCMA_BOARD_TYPE_BCM94313BU	0X050F
++#define BCMA_BOARD_TYPE_BCM94313HM	0X0510
++#define BCMA_BOARD_TYPE_BCM94313EPA	0X0511
++#define BCMA_BOARD_TYPE_BCM94313HMG	0X051C
++/* BCM4716 */
++#define BCMA_BOARD_TYPE_BCM94716NR2	0X04CD
++/* BCM43224 */
++#define BCMA_BOARD_TYPE_BCM943224X21	0X056E
++#define BCMA_BOARD_TYPE_BCM943224X21_FCC	0X00D1
++#define BCMA_BOARD_TYPE_BCM943224X21B	0X00E9
++#define BCMA_BOARD_TYPE_BCM943224M93	0X008B
++#define BCMA_BOARD_TYPE_BCM943224M93A	0X0090
++#define BCMA_BOARD_TYPE_BCM943224X16	0X0093
++#define BCMA_BOARD_TYPE_BCM94322X9	0X008D
++#define BCMA_BOARD_TYPE_BCM94322M35E	0X008E
++/* BCM43228 */
++#define BCMA_BOARD_TYPE_BCM943228BU8	0X0540
++#define BCMA_BOARD_TYPE_BCM943228BU9	0X0541
++#define BCMA_BOARD_TYPE_BCM943228BU	0X0542
++#define BCMA_BOARD_TYPE_BCM943227HM4L	0X0543
++#define BCMA_BOARD_TYPE_BCM943227HMB	0X0544
++#define BCMA_BOARD_TYPE_BCM943228HM4L	0X0545
++#define BCMA_BOARD_TYPE_BCM943228SD	0X0573
++/* BCM4331 */
++#define BCMA_BOARD_TYPE_BCM94331X19	0X00D6
++#define BCMA_BOARD_TYPE_BCM94331X28	0X00E4
++#define BCMA_BOARD_TYPE_BCM94331X28B	0X010E
++#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX	0X00E4
++#define BCMA_BOARD_TYPE_BCM94331X12_2G	0X00EC
++#define BCMA_BOARD_TYPE_BCM94331X12_5G	0X00ED
++#define BCMA_BOARD_TYPE_BCM94331X29B	0X00EF
++#define BCMA_BOARD_TYPE_BCM94331CSAX	0X00EF
++#define BCMA_BOARD_TYPE_BCM94331X19C	0X00F5
++#define BCMA_BOARD_TYPE_BCM94331X33	0X00F4
++#define BCMA_BOARD_TYPE_BCM94331BU	0X0523
++#define BCMA_BOARD_TYPE_BCM94331S9BU	0X0524
++#define BCMA_BOARD_TYPE_BCM94331MC	0X0525
++#define BCMA_BOARD_TYPE_BCM94331MCI	0X0526
++#define BCMA_BOARD_TYPE_BCM94331PCIEBT4	0X0527
++#define BCMA_BOARD_TYPE_BCM94331HM	0X0574
++#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL	0X059B
++#define BCMA_BOARD_TYPE_BCM94331MCH5	0X05A9
++#define BCMA_BOARD_TYPE_BCM94331CS	0X05C6
++#define BCMA_BOARD_TYPE_BCM94331CD	0X05DA
++/* BCM53572 */
++#define BCMA_BOARD_TYPE_BCM953572BU	0X058D
++#define BCMA_BOARD_TYPE_BCM953572NR2	0X058E
++#define BCMA_BOARD_TYPE_BCM947188NR2	0X058F
++#define BCMA_BOARD_TYPE_BCM953572SDRNR2	0X0590
++/* BCM43142 */
++#define BCMA_BOARD_TYPE_BCM943142HM	0X05E0
++
+ struct bcma_device {
+ 	struct bcma_bus *bus;
+ 	struct bcma_device_id id;
 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -316,6 +316,9 @@
+@@ -104,6 +104,7 @@
+ #define  BCMA_CC_CHIPST_4706_MIPS_BENDIAN	BIT(3) /* 0: little, 1: big endian */
+ #define  BCMA_CC_CHIPST_4706_PCIE1_DISABLE	BIT(5) /* PCIE1 enable strap pin */
+ #define  BCMA_CC_CHIPST_5357_NAND_BOOT		BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
++#define  BCMA_CC_CHIPST_4360_XTAL_40MZ		0x00000001
+ #define BCMA_CC_JCMD			0x0030		/* Rev >= 10 only */
+ #define  BCMA_CC_JCMD_START		0x80000000
+ #define  BCMA_CC_JCMD_BUSY		0x80000000
+@@ -315,6 +316,9 @@
  #define BCMA_CC_PMU_CTL			0x0600 /* PMU control */
  #define  BCMA_CC_PMU_CTL_ILP_DIV	0xFFFF0000 /* ILP div mask */
  #define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT	16
@@ -30,3 +320,22 @@
  #define  BCMA_CC_PMU_CTL_PLL_UPD	0x00000400
  #define  BCMA_CC_PMU_CTL_NOILPONW	0x00000200 /* No ILP on wait */
  #define  BCMA_CC_PMU_CTL_HTREQEN	0x00000100 /* HT req enable */
+@@ -607,6 +611,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
+ 
+ extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
+ 
++extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
++
+ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+ 
+ u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
+--- a/include/linux/bcma/bcma_regs.h
++++ b/include/linux/bcma/bcma_regs.h
+@@ -37,6 +37,7 @@
+ #define  BCMA_IOST_BIST_DONE		0x8000
+ #define BCMA_RESET_CTL			0x0800
+ #define  BCMA_RESET_CTL_RESET		0x0001
++#define BCMA_RESET_ST			0x0804
+ 
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR			0x44