diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-12-13 21:27:12 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-12-13 21:27:12 +0000 |
| commit | b8cb4db65f0ab0055846afba02809c758a230908 (patch) | |
| tree | 8b988a165fe3985dda8e0142be7bf8c714f742ac /target/linux/danube/files/include/asm-mips | |
| parent | 90e9add59f05a5280f2517747029f44ddf4d2e32 (diff) | |
danube gpio cleanup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9740 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/danube/files/include/asm-mips')
| -rw-r--r-- | target/linux/danube/files/include/asm-mips/danube/danube.h | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/target/linux/danube/files/include/asm-mips/danube/danube.h b/target/linux/danube/files/include/asm-mips/danube/danube.h index 34feb88ca..512ec4930 100644 --- a/target/linux/danube/files/include/asm-mips/danube/danube.h +++ b/target/linux/danube/files/include/asm-mips/danube/danube.h @@ -275,17 +275,6 @@ #define INTERNAL_ARB_ENABLE_BIT 0 -/*------------ GPIO */ -#define DANUBE_GPIO_BASE_ADDR 0xBE100B00 - -#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040)) -#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054)) -#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C)) -#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020)) -#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050)) -#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048)) - - /*------------ WDT */ #define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000) @@ -314,9 +303,32 @@ #define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C)) #define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010)) - #define LED_CON0_SWU (1 << 31) #define LED_CON0_AD1 (1 << 25) #define LED_CON0_AD0 (1 << 24) + +/*------------ GPIO */ + +#define DANUBE_GPIO_BASE_ADDR (0xBE100B00) + +#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010)) +#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040)) +#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014)) +#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044)) +#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018)) +#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048)) +#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C)) +#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C)) +#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020)) +#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050)) +#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024)) +#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054)) +#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028)) +#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058)) +#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C)) +#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C)) +#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030)) +#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060)) + #endif |