diff options
| author | kaloz <kaloz@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2010-11-22 13:31:46 +0000 |
|---|---|---|
| committer | kaloz <kaloz@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2010-11-22 13:31:46 +0000 |
| commit | 02028358c7be16b3a798973bd88432ca68cfdfdf (patch) | |
| tree | a5e99f7798071ae6ca4b0fbd43d490c0987393db /target/linux/coldfire/patches/044-m547x_8x_initial.patch | |
| parent | 12a0868f9234d1b7cbf7141959276c809169819b (diff) | |
[coldfire]: remove 2.6.25 support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24088 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/coldfire/patches/044-m547x_8x_initial.patch')
| -rw-r--r-- | target/linux/coldfire/patches/044-m547x_8x_initial.patch | 3403 |
1 files changed, 0 insertions, 3403 deletions
diff --git a/target/linux/coldfire/patches/044-m547x_8x_initial.patch b/target/linux/coldfire/patches/044-m547x_8x_initial.patch deleted file mode 100644 index e313a3638..000000000 --- a/target/linux/coldfire/patches/044-m547x_8x_initial.patch +++ /dev/null @@ -1,3403 +0,0 @@ -From 5b8edb0ea5cafb522e21b2973eaff6298062dd81 Mon Sep 17 00:00:00 2001 -From: Kurt Mahan <kmahan@freescale.com> -Date: Thu, 28 Feb 2008 10:56:17 -0700 -Subject: [PATCH] Initial M547x/M548x port. - -LTIBName: m547x-8x-initial -Signed-off-by: Kurt Mahan <kmahan@freescale.com> ---- - arch/m68k/Kconfig | 84 ++++- - arch/m68k/Makefile | 4 + - arch/m68k/coldfire/config.c | 112 +++++- - arch/m68k/coldfire/head.S | 153 ++++++- - arch/m68k/coldfire/ints.c | 78 ++++- - arch/m68k/configs/m5485evb_defconfig | 777 ++++++++++++++++++++++++++++++++++ - drivers/serial/mcfserial.c | 45 ++- - include/asm-m68k/cf_pgalloc.h | 5 + - include/asm-m68k/cfcache.h | 28 ++- - include/asm-m68k/coldfire.h | 7 + - include/asm-m68k/m5485gpio.h | 694 ++++++++++++++++++++++++++++++ - include/asm-m68k/m5485gpt.h | 88 ++++ - include/asm-m68k/m5485psc.h | 474 +++++++++++++++++++++ - include/asm-m68k/m5485sim.h | 219 ++++++++++ - include/asm-m68k/mcfsim.h | 5 + - include/asm-m68k/mcfuart.h | 14 + - include/asm-m68k/mmu_context.h | 72 ++++ - include/asm-m68k/page_offset.h | 5 + - 18 files changed, 2824 insertions(+), 40 deletions(-) - create mode 100644 arch/m68k/configs/m5485evb_defconfig - create mode 100644 include/asm-m68k/m5485gpio.h - create mode 100644 include/asm-m68k/m5485gpt.h - create mode 100644 include/asm-m68k/m5485psc.h - create mode 100644 include/asm-m68k/m5485sim.h - ---- a/arch/m68k/Kconfig -+++ b/arch/m68k/Kconfig -@@ -56,7 +56,7 @@ config ARCH_MAY_HAVE_PC_FDC - default y - - config NO_IOPORT -- def_bool !M54455 -+ def_bool !(M54455 || M547X_8X) - - config NO_DMA - def_bool SUN3 -@@ -319,20 +319,80 @@ config M68060 - config M54455 - bool "MCF54455 support" - depends on COLDFIRE -- default y - help - This option will add support for the MCF54455 processor with mmu. - -+config M547X_8X -+ bool "MCF547x/MCF548x support" -+ depends on COLDFIRE -+ help -+ This option will add support for the MCF547x/MCF548x processor with mmu. -+ -+config M547X -+ bool -+ depends on M547X_8X -+ default n -+ -+config M548X -+ bool -+ depends on M547X_8X -+ default n -+ -+choice -+ prompt "Model" -+ depends on M547X_8X -+ default M5485CFE -+ config M5475AFE -+ bool "MCF5475AFE" -+ select M547X -+ config M5475BFE -+ bool "MCF5475BFE" -+ select M547X -+ config M5475CFE -+ bool "MCF5475CFE" -+ select M547X -+ config M5475DFE -+ bool "MCF5475DFE" -+ select M547X -+ config M5475EFE -+ bool "MCF5475EFE" -+ select M547X -+ config M5475FFE -+ bool "MCF5475FFE" -+ select M547X -+ -+ config M5485AFE -+ bool "MCF5485AFE" -+ select M548X -+ config M5485BFE -+ bool "MCF5485BFE" -+ select M548X -+ config M5485CFE -+ bool "MCF5485CFE" -+ select M548X -+ config M5485DFE -+ bool "MCF5485DFE" -+ select M548X -+ config M5485EFE -+ bool "MCF5485EFE" -+ select M548X -+ config M5485FFE -+ bool "MCF5485FFE" -+ select M548X -+ -+endchoice -+ - config MCFCLK -- int "M54455EVB System Clock" -- depends on M54455 -- default 266666666 -+ int -+ default 266666666 if M54455 -+ default 266000000 if M547X -+ default 200000000 if M548X - help -- System clock for EVB. Usually 266MHz for u-boot and 200MHz for dBUG. -+ Coldfire System clock. - - config MCF_USER_HALT - bool "Coldfire User Halt Enable" -- depends on M54455 -+ depends on M54455 || M547X_8X - default n - help - Enables the HALT instruction in User Mode. -@@ -350,13 +410,15 @@ config MMU_CFV4E - - config SDRAM_BASE - hex -- depends on M54455 -- default 0x40000000 -+ depends on COLDFIRE -+ default 0x40000000 if M54455 -+ default 0x00000000 if M547X_8X - - config SDRAM_SIZE - hex -- depends on M54455 -- default 0x0FFFFFFF -+ depends on COLDFIRE -+ default 0x0FFFFFFF if M54455 -+ default 0x04000000 if M547X_8X - - config NOR_FLASH_BASE - hex "NOR Flash Base Address" ---- a/arch/m68k/Makefile -+++ b/arch/m68k/Makefile -@@ -63,6 +63,10 @@ ifdef CONFIG_M54455 - KBUILD_CFLAGS += -march=isac -mcpu=54455 -msoft-float -g - KBUILD_AFLAGS += -march=isac -mcpu=54455 -msoft-float - endif -+ifdef CONFIG_M547X_8X -+KBUILD_CFLAGS += -mcfv4e -g -+KBUILD_AFLAGS += -mcfv4e -+endif - - ifdef CONFIG_KGDB - # If configured for kgdb support, include debugging infos and keep the ---- a/arch/m68k/coldfire/config.c -+++ b/arch/m68k/coldfire/config.c -@@ -1,8 +1,9 @@ - /* -- * linux/arch/m68k/coldifre/config.c -+ * linux/arch/m68k/coldfire/config.c - * -+ * Kurt Mahan kmahan@freescale.com - * Matt Waddel Matt.Waddel@freescale.com -- * Copyright Freescale Semiconductor, Inc. 2007 -+ * Copyright Freescale Semiconductor, Inc. 2007, 2008 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -32,11 +33,16 @@ - #include <asm/movs.h> - #include <asm/page.h> - #include <asm/pgalloc.h> -+ -+#include <asm/mcfsim.h> -+ -+#if 0 - #include <asm/mcf5445x_intc.h> - #include <asm/mcf5445x_sdramc.h> - #include <asm/mcf5445x_fbcs.h> - #include <asm/mcf5445x_dtim.h> - #include <asm/mcf5445x_xbs.h> -+#endif - - /* JKM -- testing */ - #include <linux/pfn.h> -@@ -85,15 +91,21 @@ int __init uboot_commandline(char *boota - { - int len = 0, cmd_line_len; - static struct uboot_record uboot_info; -+ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; - - extern unsigned long uboot_info_stk; - -- /* Add 0x80000000 to get post-remapped kernel memory location */ -- uboot_info.bd_info = (*(u32 *)(uboot_info_stk)) + 0x80000000; -- uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + 0x80000000; -- uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + 0x80000000; -- uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + 0x80000000; -- uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + 0x80000000; -+ /* validate address */ -+ if ((uboot_info_stk < PAGE_OFFSET_RAW) || -+ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE))) -+ return 0; -+ -+ /* Add offset to get post-remapped kernel memory location */ -+ uboot_info.bd_info = (*(u32 *)(uboot_info_stk)) + offset; -+ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset; -+ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset; -+ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset; -+ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset; - - cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start; - if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1)) -@@ -106,21 +118,36 @@ int __init uboot_commandline(char *boota - /* - * This routine does things not done in the bootloader. - */ -+#if defined(CONFIG_M54455) - #define DEFAULT_COMMAND_LINE "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" -+#elif defined(CONFIG_M547X_8X) -+#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ ip=172.27.155.85:172.27.155.1" -+#endif - asmlinkage void __init cf_early_init(void) - { - struct bi_record *record = (struct bi_record *) &_end; - - extern char _end; - -+#if defined(CONFIG_M54455) - SET_VBR((void *)MCF_RAMBAR1); -+#elif defined(CONFIG_M547X_8X) -+ SET_VBR((void *)MCF_RAMBAR0); -+#endif - - /* Mask all interrupts */ -+#if defined(CONFIG_M54455) - MCF_INTC0_IMRL = 0xFFFFFFFF; - MCF_INTC0_IMRH = 0xFFFFFFFF; - MCF_INTC1_IMRL = 0xFFFFFFFF; - MCF_INTC1_IMRH = 0xFFFFFFFF; -+#elif defined(CONFIG_M547X_8X) -+/* JKM -- ?? */ -+ MCF_IMRL = 0xFFFFFFFF; -+ MCF_IMRH = 0xFFFFFFFF; -+#endif - -+#if defined(CONFIG_M54455) - #if defined(CONFIG_NOR_FLASH_BASE) - MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE; - #else -@@ -131,9 +158,10 @@ asmlinkage void __init cf_early_init(voi - /* Init optional SDRAM chip select */ - MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B; - #endif -+#endif /* CONFIG_M54455 */ - -+#if defined(CONFIG_M54455) - /* Setup SDRAM crossbar(XBS) priorities */ --printk(KERN_INFO "Bumping USB Priority\n"); - MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | - MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | - MCF_XBS_PRS_M2(MCF_XBS_PRI_4) | -@@ -141,6 +169,7 @@ printk(KERN_INFO "Bumping USB Priority\n - MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | - MCF_XBS_PRS_M6(MCF_XBS_PRI_1) | - MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); -+#endif - - - m68k_machtype = MACH_CFMMU; -@@ -152,6 +181,7 @@ printk(KERN_INFO "Bumping USB Priority\n - m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; - m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE; - -+#if defined(CONFIG_M54455) - if (!uboot_commandline(m68k_command_line)) { - #if defined(CONFIG_BOOTPARAM) - strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1); -@@ -159,6 +189,10 @@ printk(KERN_INFO "Bumping USB Priority\n - strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); - #endif - } -+#else -+/* JKM -- hack until mappings get resolved */ -+ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE); -+#endif - - - #if defined(CONFIG_BLK_DEV_INITRD) -@@ -185,6 +219,7 @@ printk(KERN_INFO "Bumping USB Priority\n - cacr_set(CACHE_INITIAL_MODE); - } - -+#if defined(CONFIG_M54455) - void settimericr(unsigned int timer, unsigned int level) - { - volatile unsigned char *icrp; -@@ -202,6 +237,7 @@ void settimericr(unsigned int timer, uns - coldfire_enable_irq0(irq); - } - } -+#endif - - /* Assembler routines */ - asmlinkage void buserr(void); -@@ -214,7 +250,11 @@ void __init coldfire_trap_init(void) - int i = 0; - e_vector *vectors; - -+#if defined(CONFIG_M54455) - vectors = (e_vector *)MCF_RAMBAR1; -+#elif defined(CONFIG_M547X_8X) -+ vectors = (e_vector *)MCF_RAMBAR0; -+#endif - /* - * There is a common trap handler and common interrupt - * handler that handle almost every vector. We treat -@@ -235,6 +275,8 @@ void __init coldfire_trap_init(void) - vectors[32] = system_call; - } - -+#if defined(CONFIG_M54455) -+ - void coldfire_tick(void) - { - /* Reset the ColdFire timer */ -@@ -285,13 +327,49 @@ unsigned long coldfire_gettimeoffset(voi - return offset; - } - -+#elif defined(CONFIG_M547X_8X) -+ -+void coldfire_tick(void) -+{ -+ /* Reset the ColdFire timer */ -+ MCF_SSR(0) = MCF_SSR_ST; -+} -+ -+void __init coldfire_sched_init(irq_handler_t handler) -+{ -+ int irq = ISC_SLTn(0); -+ -+ MCF_SCR(0) = 0; -+ MCF_ICR(irq) = ILP_SLT0; -+ request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL); -+ MCF_SLTCNT(0) = MCF_BUSCLK / HZ; -+ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN; -+} -+ -+unsigned long coldfire_gettimeoffset(void) -+{ -+ volatile unsigned long trr, tcn, offset; -+ trr = MCF_SLTCNT(0); -+ tcn = MCF_SCNT(0); -+ -+ offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3); -+ if (MCF_SSR(0) & MCF_SSR_ST) -+ offset += 1000000 / HZ; -+ -+ return offset; -+} -+ -+#endif -+ - void coldfire_reboot(void) - { -+#if defined(CONFIG_M54455) - /* disable interrupts and do a software reset */ - asm("movew #0x2700, %%sr\n\t" - "moveb #0x80, %%d0\n\t" - "moveb %%d0, 0xfc0a0000\n\t" - : : : "%d0"); -+#endif - } - - /* int coldfire_hwclk(int i, struct rtc_time *t) -@@ -305,6 +383,7 @@ static void coldfire_get_model(char *mod - sprintf(model, "Version 4 ColdFire"); - } - -+/* JKM -- Why do we need these? */ - void coldfire_enable_irq(unsigned int vec) - { - unsigned long flags; -@@ -318,13 +397,21 @@ void coldfire_enable_irq(unsigned int ve - - local_irq_save(flags); - irq_enable[vec]++; -+#if defined(CONFIG_M54455) - if (vec < 32) - MCF_INTC0_IMRL &= ~(1 << vec); - else - MCF_INTC0_IMRH &= ~(1 << (vec - 32)); -+#elif defined(CONFIG_M547X_8X) -+ if (vec < 32) -+ MCF_IMRL &= ~(1 << vec); -+ else -+ MCF_IMRH &= ~(1 << (vec - 32)); -+#endif - local_irq_restore(flags); - } - -+/* JKM -- Why do we need these? */ - void coldfire_disable_irq(unsigned int vec) - { - unsigned long flags; -@@ -338,10 +425,17 @@ void coldfire_disable_irq(unsigned int v - - local_irq_save(flags); - if (--irq_enable[vec] == 0) { -+#if defined(CONFIG_M54455) - if (vec < 32) - MCF_INTC0_IMRL |= (1 << vec); - else - MCF_INTC0_IMRH |= (1 << (vec - 32)); -+#elif defined(CONFIG_M547X_8X) -+ if (vec < 32) -+ MCF_IMRL |= (1 << vec); -+ else -+ MCF_IMRH |= (1 << (vec - 32)); -+#endif - - } - local_irq_restore(flags); ---- a/arch/m68k/coldfire/head.S -+++ b/arch/m68k/coldfire/head.S -@@ -2,9 +2,9 @@ - * head.S is the MMU enabled ColdFire specific initial boot code - * - * Ported to ColdFire by -- * Matt Waddel Matt.Waddel@freescale.com -- * Kurt Mahan kmahan@freescale.com -- * Copyright Freescale Semiconductor, Inc. 2007 -+ * Matt Waddel Matt.Waddel@freescale.com -+ * Kurt Mahan kmahan@freescale.com -+ * Copyright Freescale Semiconductor, Inc. 2007, 2008 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -52,6 +52,7 @@ - #define __FINIT .previous - #endif - -+/* JKM -- REVISE DOCS FOR RIGO */ - /* - * Setup ACR mappings to provide the following memory map: - * Data -@@ -61,13 +62,20 @@ - * None currently (mapped via TLBs) - */ - -+#if defined(CONFIG_M54455) - #define ACR0_DEFAULT #0xA00FA048 /* ACR0 default value */ - #define ACR1_DEFAULT #0xF00FA040 /* ACR1 default value */ - #define ACR2_DEFAULT #0x00000000 /* ACR2 default value */ - #define ACR3_DEFAULT #0x00000000 /* ACR3 default value */ -- - /* ACR mapping for FPGA (maps 0) */ - #define ACR0_FPGA #0x000FA048 /* ACR0 enable FPGA */ -+#elif defined(CONFIG_M547X_8X) -+#define ACR0_DEFAULT #0xE000C040 /* ACR0 default value */ -+#define ACR1_DEFAULT #0x00000000 /* ACR1 default value */ -+#define ACR2_DEFAULT #0x00000000 /* ACR2 default value */ -+#define ACR3_DEFAULT #0x00000000 /* ACR3 default value */ -+#endif -+ - - /* Several macros to make the writing of subroutines easier: - * - func_start marks the beginning of the routine which setups the frame -@@ -227,7 +235,7 @@ ENTRY(_stext) - - .long BOOTINFOV_MAGIC - .long 0 --1: jmp __start-0x80000000 -+1: jmp __start-(0xc0000000-CONFIG_SDRAM_BASE) - - .equ kernel_pg_dir,_stext - .equ .,_stext+0x1000 -@@ -237,19 +245,40 @@ ENTRY(_start) - __INIT - ENTRY(__start) - -+/* JKM -- make sure Rigo handles UBOOT */ - /* Save the location of u-boot info - cmd line, bd_info, etc. */ - movel %a7,%a4 /* Don't use %a4 before cf_early_init */ -+/* JKM -- fix to use CONFIG_SDRAM_BASE) */ -+#if defined(CONFIG_M54455) - addl #0x80000004,%a4 /* 0x80000004= 1 stack push + high mem offset */ -+#elif defined(CONFIG_M547X_8X) -+ addl #0xc0000004,%a4 /* 0x80000004= 1 stack push + high mem offset */ -+#endif - -+/* JKM -- fix this to work off of CONFIG_SDRAM_BASE */ - /* Setup initial stack pointer */ -+#if defined(CONFIG_M54455) - movel #0x40001000,%sp -+#elif defined(CONFIG_M547X_8X) -+ movel #0x00001000,%sp -+#endif - - /* Setup usp */ - subl %a0,%a0 - movel %a0,%usp - -+#if defined(CONFIG_M54455) - movel #(MCF_RAMBAR1 + 0x221), %d0 - movec %d0, %rambar1 -+#elif defined(CONFIG_M547X_8X) -+ movel #MCF_MBAR, %d0 -+ movec %d0, %mbar -+ move.l #(MCF_RAMBAR0 + 0x21), %d0 -+ movec %d0, %rambar0 -+ move.l #(MCF_RAMBAR1 + 0x21), %d0 -+ movec %d0, %rambar1 -+#endif -+ - movew #0x2700,%sr - - /* reset cache */ -@@ -278,6 +307,7 @@ ENTRY(__start) - /* If you change the memory size to another value make a matching - change in paging_init(cf-mmu.c) to zones_size[]. */ - -+#if defined(CONFIG_M54455) - /* Map 256MB as code */ - mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \ - MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ -@@ -383,16 +413,104 @@ ENTRY(__start) - MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ - 0, MMUDR_LK, %d0 - -- /* Do unity mapping to enable the MMU. Map first 16 MB in place as -- code (delete TLBs after MMU is enabled and we are executing in high -- memory). */ -+#elif defined(CONFIG_M547X_8X) -+ -+ /* Map first 8 MB as code */ -+ mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ -+ MMUDR_LK, %d0 -+ -+ /* Map first 8 MB as data */ -+ mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+ mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, MMUDR_LK, %d0 -+#endif -+ /* -+ * Do unity mapping to enable the MMU. Map first chunk of memory -+ * in place as code/data. The TLBs will be deleted after the MMU is -+ * enabled and we are executing in high memory. -+ */ -+ -+#if defined(CONFIG_M54455) -+ /* Map first 16 MB as code */ - mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \ - MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC, MMUDR_SP, 0, \ - 0, MMUDR_X, 0, %d0 -- /* Map first 16 MB as data too. */ -+ /* Map first 16 MB as data too */ - mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \ - MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ - 0, 0, %d0 -+#elif defined(CONFIG_M547X_8X) -+ /* Map first 4 MB as code */ -+ mmu_map (0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ -+ MMUDR_X, 0, %d0 -+ mmu_map (1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ -+ MMUDR_X, 0, %d0 -+ mmu_map (2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ -+ MMUDR_X, 0, %d0 -+ mmu_map (3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ -+ MMUDR_X, 0, %d0 -+ -+ /* Map first 4 MB as data too */ -+ mmu_map (0*1024*1024), (0*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, 0, %d0 -+ mmu_map (1*1024*1024), (1*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, 0, %d0 -+ mmu_map (2*1024*1024), (2*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, 0, %d0 -+ mmu_map (3*1024*1024), (3*1024*1024), 0, 0, \ -+ MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ -+ MMUDR_W, 0, 0, %d0 -+#endif - - /* Turn on MMU */ - movel #(MMUCR_EN),%a0 -@@ -412,9 +530,20 @@ ENTRY(__running_high) - addl #PAGE_OFFSET,%a1 - movel %a1,%a0@ - -- /* Unmap first 16 MB, code and data. */ -+ /* Unmap unity mappings */ -+#if defined(CONFIG_M54455) - mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0 - mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0 -+#elif defined(CONFIG_M547X_8X) -+ mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0 -+ mmu_unmap (PHYS_OFFSET+1*0x1000000), MMUOR_ITLB, %d0 -+ mmu_unmap (PHYS_OFFSET+2*0x1000000), MMUOR_ITLB, %d0 -+ mmu_unmap (PHYS_OFFSET+3*0x1000000), MMUOR_ITLB, %d0 -+ mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0 -+ mmu_unmap (PHYS_OFFSET+1*0x1000000), 0, %d0 -+ mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0 -+ mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0 -+#endif - - /* Setup initial stack pointer */ - lea init_task,%a2 -@@ -438,8 +567,9 @@ func_start set_context,%d0,(1*4) - movec %d0,%asid - func_return set_context - -+#ifdef CONFIG_M54455 - /* -- * set_fpga(addr,val) -+ * set_fpga(addr,val) on the M54455EVB - * - * Map in 0x00000000 -> 0x0fffffff and then do the write. - */ -@@ -456,6 +586,7 @@ set_fpga: - nop - movew %d1,%sr - rts -+#endif - - .data - .align 4 ---- a/arch/m68k/coldfire/ints.c -+++ b/arch/m68k/coldfire/ints.c -@@ -5,9 +5,10 @@ - * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * Copyright (C) 2000 Lineo Inc. (www.lineo.com) -- * Matt Waddel Matt.Waddel@freescale.com -- * Copyright Freescale Semiconductor, Inc. 2007 -- * Kurt Mahan kmahan@freescale.com -+ * -+ * Copyright Freescale Semiconductor, Inc. 2007, 2008 -+ * Kurt Mahan kmahan@freescale.com -+ * Matt Waddel Matt.Waddel@freescale.com - * - * Based on: - * linux/arch/m68k/kernel/ints.c & -@@ -46,7 +47,7 @@ static int irq_depth[SYS_IRQS]; - /* - * IRQ Controller - */ --#ifdef CONFIG_M54455 -+#if defined(CONFIG_M54455) - void m5445x_irq_enable(unsigned int irq); - void m5445x_irq_disable(unsigned int irq); - static struct irq_controller m5445x_irq_controller = { -@@ -55,6 +56,17 @@ static struct irq_controller m5445x_irq_ - .enable = m5445x_irq_enable, - .disable = m5445x_irq_disable, - }; -+#elif defined(CONFIG_M547X_8X) -+void m547x_8x_irq_enable(unsigned int irq); -+void m547x_8x_irq_disable(unsigned int irq); -+static struct irq_controller m547x_8x_irq_controller = { -+ .name = "M547X_8X", -+ .lock = SPIN_LOCK_UNLOCKED, -+ .enable = m547x_8x_irq_enable, -+ .disable = m547x_8x_irq_disable, -+}; -+#else -+# error No IRQ controller defined - #endif - - #define POOL_SIZE SYS_IRQS -@@ -75,9 +87,12 @@ void __init init_IRQ(void) - { - int i; - --#ifdef CONFIG_M54455 -+#if defined(CONFIG_M54455) - for (i = 0; i < SYS_IRQS; i++) - irq_controller[i] = &m5445x_irq_controller; -+#elif defined(CONFIG_M547X_8X) -+ for (i = 0; i < SYS_IRQS; i++) -+ irq_controller[i] = &m547x_8x_irq_controller; - #endif - } - -@@ -381,4 +396,57 @@ void m5445x_irq_disable(unsigned int irq - MCF_INTC1_SIMR = irq; - } - } -+#elif defined(CONFIG_M547X_8X) -+/* -+ * M547X_8X Implementation -+ */ -+void m547x_8x_irq_enable(unsigned int irq) -+{ -+ /* enable the interrupt hardware */ -+ if (irq < 64) -+ return; -+ -+ /* adjust past non-hardware ints */ -+ irq -= 64; -+ -+/* JKM -- re-add EPORT later */ -+#if 0 -+ /* check for eport */ -+ if ((irq > 0) && (irq < 8)) { -+ /* enable eport */ -+ MCF_EPORT_EPPAR &= ~(3 << (irq*2)); /* level */ -+ MCF_EPORT_EPDDR &= ~(1 << irq); /* input */ -+ MCF_EPORT_EPIER |= 1 << irq; /* irq enabled */ -+ } -+#endif -+ -+ if (irq < 32) -+ MCF_IMRL &= ~(1 << irq); -+ else -+ MCF_IMRH &= ~(1 << (irq - 32)); -+} -+ -+void m547x_8x_irq_disable(unsigned int irq) -+{ -+ /* disable the interrupt hardware */ -+ if (irq < 64) -+ return; -+ -+ /* adjust past non-hardware ints */ -+ irq -= 64; -+ -+/* JKM -- re-add EPORT later */ -+#if 0 -+ /* check for eport */ -+ if ((irq > 0) && (irq < 8)) { -+ /* disable eport */ -+ MCF_EPORT_EPIER &= ~(1 << irq); -+ } -+#endif -+ -+ if (irq < 32) -+ MCF_IMRL |= (1 << irq); -+ else -+ MCF_IMRH |= (1 << (irq - 32)); -+} - #endif ---- /dev/null -+++ b/arch/m68k/configs/m5485evb_defconfig -@@ -0,0 +1,777 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.24 -+# Thu Feb 21 00:19:01 2008 -+# -+CONFIG_M68K=y -+CONFIG_MMU=y -+# CONFIG_GENERIC_TIME is not set -+# CONFIG_GENERIC_CLOCKEVENTS is not set -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+# CONFIG_ARCH_HAS_ILOG2_U32 is not set -+# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_TIME_LOW_RES=y -+CONFIG_GENERIC_IOMAP=y -+# CONFIG_NO_IOPORT is not set -+# CONFIG_NO_DMA is not set -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+ -+# -+# General setup -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+# CONFIG_BSD_PROCESS_ACCT is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_USER_NS is not set -+# CONFIG_PID_NS is not set -+# CONFIG_AUDIT is not set -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_LOG_BUF_SHIFT=17 -+# CONFIG_CGROUPS is not set -+CONFIG_FAIR_GROUP_SCHED=y -+CONFIG_FAIR_USER_SCHED=y -+# CONFIG_FAIR_CGROUP_SCHED is not set -+CONFIG_SYSFS_DEPRECATED=y -+# CONFIG_RELAY is not set -+# CONFIG_BLK_DEV_INITRD is not set -+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -+CONFIG_SYSCTL=y -+# CONFIG_EMBEDDED is not set -+CONFIG_UID16=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_ANON_INODES=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+CONFIG_SLABINFO=y -+CONFIG_RT_MUTEXES=y -+# CONFIG_TINY_SHMEM is not set -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+# CONFIG_MODVERSIONS is not set -+# CONFIG_MODULE_SRCVERSION_ALL is not set -+# CONFIG_KMOD is not set -+CONFIG_BLOCK=y -+CONFIG_LBD=y -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_LSF is not set -+# CONFIG_BLK_DEV_BSG is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_AS=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_AS is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+ -+# -+# Platform dependent setup -+# -+# CONFIG_SUN3 is not set -+CONFIG_COLDFIRE=y -+CONFIG_CFV4E=y -+# CONFIG_AMIGA is not set -+# CONFIG_ATARI is not set -+# CONFIG_MAC is not set -+# CONFIG_APOLLO is not set -+# CONFIG_VME is not set -+# CONFIG_HP300 is not set -+# CONFIG_SUN3X is not set -+# CONFIG_Q40 is not set -+ -+# -+# Processor type -+# -+# CONFIG_M68020 is not set -+# CONFIG_M68030 is not set -+# CONFIG_M68040 is not set -+# CONFIG_M68060 is not set -+# CONFIG_M54455 is not set -+CONFIG_M547X_8X=y -+# CONFIG_M547X is not set -+CONFIG_M548X=y -+# CONFIG_M5475AFE is not set -+# CONFIG_M5475BFE is not set -+# CONFIG_M5475CFE is not set -+# CONFIG_M5475DFE is not set -+# CONFIG_M5475EFE is not set -+# CONFIG_M5475FFE is not set -+# CONFIG_M5485AFE is not set -+# CONFIG_M5485BFE is not set -+CONFIG_M5485CFE=y -+# CONFIG_M5485DFE is not set -+# CONFIG_M5485EFE is not set -+# CONFIG_M5485FFE is not set -+CONFIG_MCFCLK=50000000 -+# CONFIG_MCF_USER_HALT is not set -+CONFIG_MMU_CFV4E=y -+CONFIG_SDRAM_BASE=0x00000000 -+CONFIG_SDRAM_SIZE=0x04000000 -+# CONFIG_M68KFPU_EMU is not set -+CONFIG_ADVANCED=y -+# CONFIG_RMW_INSNS is not set -+CONFIG_SINGLE_MEMORY_CHUNK=y -+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+CONFIG_NEED_MULTIPLE_NODES=y -+# CONFIG_SPARSEMEM_STATIC is not set -+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+# CONFIG_RESOURCES_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_BOUNCE=y -+CONFIG_VIRT_TO_BUS=y -+ -+# -+# General setup -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_BINFMT_AOUT is not set -+# CONFIG_BINFMT_MISC is not set -+CONFIG_PROC_HARDWARE=y -+CONFIG_ZONE_DMA=y -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+ -+# -+# Power management options -+# -+# CONFIG_PM is not set -+ -+# -+# Networking -+# -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+# CONFIG_PACKET_MMAP is not set -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+CONFIG_NET_KEY=y -+# CONFIG_NET_KEY_MIGRATE is not set -+CONFIG_INET=y -+# CONFIG_IP_MULTICAST is not set -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_ASK_IP_FIB_HASH=y -+# CONFIG_IP_FIB_TRIE is not set -+CONFIG_IP_FIB_HASH=y -+# CONFIG_IP_MULTIPLE_TABLES is not set -+# CONFIG_IP_ROUTE_MULTIPATH is not set -+# CONFIG_IP_ROUTE_VERBOSE is not set -+CONFIG_IP_PNP=y -+# CONFIG_IP_PNP_DHCP is not set -+# CONFIG_IP_PNP_BOOTP is not set -+# CONFIG_IP_PNP_RARP is not set -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+CONFIG_INET_AH=y -+CONFIG_INET_ESP=y -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_INET6_XFRM_TUNNEL is not set -+# CONFIG_INET6_TUNNEL is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+# CONFIG_NET_SCHED is not set -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_HAMRADIO is not set -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+ -+# -+# Wireless -+# -+# CONFIG_CFG80211 is not set -+# CONFIG_WIRELESS_EXT is not set -+# CONFIG_MAC80211 is not set -+# CONFIG_IEEE80211 is not set -+# CONFIG_RFKILL is not set -+# CONFIG_NET_9P is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+# CONFIG_STANDALONE is not set -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_CONNECTOR is not set -+# CONFIG_MTD is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=y -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+# CONFIG_BLK_DEV_NBD is not set -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=64000 -+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+CONFIG_MISC_DEVICES=y -+# CONFIG_EEPROM_93CX6 is not set -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+CONFIG_SCSI_PROC_FS=y -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+# CONFIG_BLK_DEV_SR is not set -+# CONFIG_CHR_DEV_SG is not set -+# CONFIG_CHR_DEV_SCH is not set -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+CONFIG_SCSI_MULTI_LUN=y -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+# CONFIG_SCSI_LOWLEVEL is not set -+# CONFIG_ATA is not set -+# CONFIG_MD is not set -+CONFIG_NETDEVICES=y -+# CONFIG_NETDEVICES_MULTIQUEUE is not set -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_MACVLAN is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+# CONFIG_VETH is not set -+# CONFIG_PHYLIB is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+# CONFIG_B44 is not set -+# CONFIG_NETDEV_1000 is not set -+# CONFIG_NETDEV_10000 is not set -+ -+# -+# Wireless LAN -+# -+# CONFIG_WLAN_PRE80211 is not set -+# CONFIG_WLAN_80211 is not set -+# CONFIG_WAN is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_SHAPER is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+# CONFIG_ISDN is not set -+# CONFIG_PHONE is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+# CONFIG_INPUT_JOYDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+# CONFIG_KEYBOARD_ATKBD is not set -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Hardware I/O ports -+# -+CONFIG_SERIO=y -+CONFIG_SERIO_SERPORT=y -+# CONFIG_SERIO_RAW is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+# CONFIG_SERIAL_8250 is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_COLDFIRE=y -+CONFIG_UNIX98_PTYS=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_IPMI_HANDLER is not set -+# CONFIG_HW_RANDOM is not set -+# CONFIG_GEN_RTC is not set -+# CONFIG_R3964 is not set -+# CONFIG_RAW_DRIVER is not set -+# CONFIG_TCG_TPM is not set -+# CONFIG_I2C is not set -+ -+# -+# SPI support -+# -+# CONFIG_SPI is not set -+# CONFIG_COLDFIRE_EDMA is not set -+# CONFIG_SPI_MASTER is not set -+# CONFIG_W1 is not set -+# CONFIG_POWER_SUPPLY is not set -+# CONFIG_HWMON is not set -+# CONFIG_WATCHDOG is not set -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB_POSSIBLE=y -+# CONFIG_SSB is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_SM501 is not set -+ -+# -+# Multimedia devices -+# -+# CONFIG_VIDEO_DEV is not set -+# CONFIG_DVB_CORE is not set -+CONFIG_DAB=y -+ -+# -+# Graphics support -+# -+# CONFIG_VGASTATE is not set -+CONFIG_VIDEO_OUTPUT_CONTROL=m -+# CONFIG_FB is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+ -+# -+# Console display driver support -+# -+CONFIG_DUMMY_CONSOLE=y -+ -+# -+# Sound -+# -+# CONFIG_SOUND is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+CONFIG_HID_DEBUG=y -+# CONFIG_HIDRAW is not set -+# CONFIG_USB_SUPPORT is not set -+# CONFIG_MMC is not set -+# CONFIG_NEW_LEDS is not set -+# CONFIG_RTC_CLASS is not set -+ -+# -+# Userspace I/O -+# -+# CONFIG_UIO is not set -+ -+# -+# Character devices -+# -+# CONFIG_SERIAL_CONSOLE is not set -+ -+# -+# File systems -+# -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_XATTR=y -+# CONFIG_EXT3_FS_POSIX_ACL is not set -+# CONFIG_EXT3_FS_SECURITY is not set -+# CONFIG_EXT4DEV_FS is not set -+CONFIG_JBD=y -+CONFIG_FS_MBCACHE=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+# CONFIG_XFS_FS is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+CONFIG_MINIX_FS=y -+# CONFIG_ROMFS_FS is not set -+# CONFIG_INOTIFY is not set -+# CONFIG_QUOTA is not set -+CONFIG_DNOTIFY=y -+# CONFIG_AUTOFS_FS is not set -+# CONFIG_AUTOFS4_FS is not set -+# CONFIG_FUSE_FS is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+# CONFIG_ISO9660_FS is not set -+# CONFIG_UDF_FS is not set -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+CONFIG_NTFS_FS=y -+# CONFIG_NTFS_DEBUG is not set -+CONFIG_NTFS_RW=y -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+# CONFIG_PROC_KCORE is not set -+CONFIG_PROC_SYSCTL=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+# CONFIG_HUGETLB_PAGE is not set -+# CONFIG_CONFIGFS_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+# CONFIG_CRAMFS is not set -+# CONFIG_VXFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+# CONFIG_NFS_V3 is not set -+# CONFIG_NFS_V4 is not set -+# CONFIG_NFS_DIRECTIO is not set -+# CONFIG_NFSD is not set -+CONFIG_ROOT_NFS=y -+CONFIG_LOCKD=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+# CONFIG_SUNRPC_BIND34 is not set -+# CONFIG_RPCSEC_GSS_KRB5 is not set -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+# CONFIG_NLS_CODEPAGE_850 is not set -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=y -+# CONFIG_NLS_ISO8859_2 is not set -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+CONFIG_NLS_UTF8=y -+# CONFIG_DLM is not set -+CONFIG_INSTRUMENTATION=y -+# CONFIG_PROFILING is not set -+# CONFIG_MARKERS is not set -+ -+# -+# Kernel hacking -+# -+# CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_WARN_DEPRECATED=y -+# CONFIG_ENABLE_MUST_CHECK is not set -+# CONFIG_MAGIC_SYSRQ is not set -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+CONFIG_DETECT_SOFTLOCKUP=y -+CONFIG_SCHED_DEBUG=y -+# CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set -+CONFIG_DEBUG_SLAB=y -+# CONFIG_DEBUG_SLAB_LEAK is not set -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+CONFIG_DEBUG_BUGVERBOSE=y -+CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_SG is not set -+# CONFIG_FRAME_POINTER is not set -+CONFIG_FORCED_INLINING=y -+# CONFIG_BOOT_PRINTK_DELAY is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_FAULT_INJECTION is not set -+# CONFIG_SAMPLES is not set -+CONFIG_BOOTPARAM=y -+CONFIG_BOOTPARAM_STRING="root=/dev/nfs rw nfsroot=172.27.163.2:/tftpboot/ltib ip=172.27.163.3:172.27.163.2:172.27.255.254:255.255.0.0::eth0:off mtdparts=phys_mapped_flash:16m(User)" -+ -+# -+# CodeTEST Setup -+# -+# CONFIG_CODETEST is not set -+ -+# -+# Security options -+# -+# CONFIG_KEYS is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITY_FILE_CAPABILITIES is not set -+CONFIG_CRYPTO=y -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_HMAC=y -+# CONFIG_CRYPTO_XCBC is not set -+# CONFIG_CRYPTO_NULL is not set -+# CONFIG_CRYPTO_MD4 is not set -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_SHA1=y -+# CONFIG_CRYPTO_SHA256 is not set -+# CONFIG_CRYPTO_SHA512 is not set -+# CONFIG_CRYPTO_WP512 is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_ECB is not set -+CONFIG_CRYPTO_CBC=y -+# CONFIG_CRYPTO_PCBC is not set -+# CONFIG_CRYPTO_LRW is not set -+# CONFIG_CRYPTO_XTS is not set -+# CONFIG_CRYPTO_CRYPTD is not set -+CONFIG_CRYPTO_DES=y -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_DEFLATE is not set -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_CRC32C is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+CONFIG_CRYPTO_TEST=m -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_HW is not set -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+CONFIG_CRC_CCITT=y -+CONFIG_CRC16=y -+# CONFIG_CRC_ITU_T is not set -+CONFIG_CRC32=y -+# CONFIG_CRC7 is not set -+CONFIG_LIBCRC32C=y -+CONFIG_PLIST=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y ---- a/drivers/serial/mcfserial.c -+++ b/drivers/serial/mcfserial.c -@@ -45,6 +45,11 @@ - #include <asm/coldfire.h> - #include <asm/mcfsim.h> - #include <asm/mcfuart.h> -+#if defined(CONFIG_M547X_8X) -+#include <asm/m5485sim.h> -+#include <asm/m5485psc.h> -+#include <asm/m5485gpio.h> -+#endif - #ifdef CONFIG_NETtel - #include <asm/nettel.h> - #endif -@@ -64,7 +69,7 @@ struct timer_list mcfrs_timer_struct; - #define DEFAULT_CBAUD B38400 - #elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || \ - defined(CONFIG_M5329EVB) || defined(CONFIG_GILBARCO) || \ -- defined(CONFIG_M54455) -+ defined(CONFIG_M54455) || defined(CONFIG_M547X_8X) - #define CONSOLE_BAUD_RATE 115200 - #define DEFAULT_CBAUD B115200 - #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \ -@@ -97,7 +102,8 @@ static struct tty_driver *mcfrs_serial_d - #undef SERIAL_DEBUG_FLOW - - #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ -- defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455) -+ defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455) || \ -+ defined(CONFIG_M547X_8X) - #define IRQBASE (MCFINT_VECBASE+MCFINT_UART0) - #else - #define IRQBASE 73 -@@ -117,7 +123,11 @@ static struct mcf_serial mcfrs_table[] = - { /* ttyS1 */ - .magic = 0, - .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE2), -+#if defined(CONFIG_M547X_8X) -+ .irq = IRQBASE-1, -+#else - .irq = IRQBASE+1, -+#endif - .flags = ASYNC_BOOT_AUTOCONF, - }, - #endif -@@ -125,7 +135,11 @@ static struct mcf_serial mcfrs_table[] = - { /* ttyS2 */ - .magic = 0, - .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE3), -+#if defined(CONFIG_M547X_8X) -+ .irq = IRQBASE-2, -+#else - .irq = IRQBASE+2, -+#endif - .flags = ASYNC_BOOT_AUTOCONF, - }, - #endif -@@ -133,7 +147,11 @@ static struct mcf_serial mcfrs_table[] = - { /* ttyS3 */ - .magic = 0, - .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE4), -+#if defined(CONFIG_M547X_8X) -+ .irq = IRQBASE-3, -+#else - .irq = IRQBASE+3, -+#endif - .flags = ASYNC_BOOT_AUTOCONF, - }, - #endif -@@ -412,7 +430,12 @@ irqreturn_t mcfrs_interrupt(int irq, voi - struct mcf_serial *info; - unsigned char isr; - -+/* JKM -- revisit! IRQ compute */ -+#if defined(CONFIG_M547X_8X) -+ info = &mcfrs_table[(IRQBASE - irq)]; -+#else - info = &mcfrs_table[(irq - IRQBASE)]; -+#endif - isr = info->addr[MCFUART_UISR] & info->imr; - - if (isr & MCFUART_UIR_RXREADY) -@@ -1621,6 +1644,22 @@ static void mcfrs_irqinit(struct mcf_ser - /* GPIOs also must be initalized, depends on board */ - break; - } -+#elif defined(CONFIG_M547X_8X) -+ volatile unsigned char *uartp; -+ uartp = (volatile unsigned char *)info->addr; -+ -+ if (info->line > 3) { -+ printk("SERIAL: don't know how to handle UART %d interrupt?\n", -+ info->line); -+ return; -+ } -+ -+ /* Set GPIO port register to enable PSC(port) signals */ -+ MCF_PAR_PSCn(info->line) = (0 -+ | MCF_PAR_PSC_TXD -+ | MCF_PAR_PSC_RXD); -+ -+ MCF_ICR(info->irq - 64) = ILP_PSCn(info->line); - #else - volatile unsigned char *icrp, *uartp; - -@@ -1983,7 +2022,7 @@ struct console mcfrs_console = { - - static int __init mcfrs_console_init(void) - { --#ifndef CONFIG_M54455 -+#if !(defined(CONFIG_M54455) || defined(CONFIG_M547X_8X)) - register_console(&mcfrs_console); - #endif - return 0; ---- a/include/asm-m68k/cf_pgalloc.h -+++ b/include/asm-m68k/cf_pgalloc.h -@@ -1,9 +1,14 @@ - #ifndef M68K_CF_PGALLOC_H - #define M68K_CF_PGALLOC_H - -+/* JKM -- added -- needed? */ -+#include <linux/highmem.h> -+ - #include <asm/coldfire.h> - #include <asm/page.h> - #include <asm/cf_tlbflush.h> -+/* JKM -- added -- needed? */ -+#include <asm/cf_cacheflush.h> - - extern inline void pte_free_kernel(pte_t *pte) - { ---- a/include/asm-m68k/cfcache.h -+++ b/include/asm-m68k/cfcache.h -@@ -70,7 +70,33 @@ - /* cache disabled for testing */ - #define CACHE_INITIAL_MODE (CF_CACR_EUSP) - #endif /* CONFIG_M5445X_DISABLE_CACHE */ --#endif /* CONFIG_M54455 */ -+ -+#elif defined(CONFIG_M547X_8X) -+/* -+ * M547x/M548x Cache Configuration -+ * - cache line size is 16 bytes -+ * - cache is 4-way set associative -+ * - each cache has 512 sets (128k / 16bytes / 4way) -+ * - I-Cache size is 32KB -+ * - D-Cache size is 32KB -+ */ -+#define ICACHE_SIZE 0x8000 /* instruction - 32k */ -+#define DCACHE_SIZE 0x8000 /* data - 32k */ -+ -+#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ -+#define CACHE_SETS 0x0200 /* 512 sets */ -+#define CACHE_WAYS 0x0004 /* 4 way */ -+ -+#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ -+ CF_CACR_BCINVA+ \ -+ CF_CACR_ICINVA) -+ -+#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ -+ CF_CACR_BEC+ \ -+ CF_CACR_IEC+ \ -+ CF_CACR_DESB+ \ -+ CF_CACR_EUSP) -+#endif /* CONFIG_M547X_8X */ - - #ifndef __ASSEMBLY__ - ---- a/include/asm-m68k/coldfire.h -+++ b/include/asm-m68k/coldfire.h -@@ -1,9 +1,16 @@ - #ifndef _COLDFIRE_H_ - #define _COLDFIRE_H_ - -+#if defined(CONFIG_M54455) - #define MCF_MBAR 0x0 - #define MCF_RAMBAR1 0x40000000 - #define MCF_SRAM 0x80000000 -+#elif defined(CONFIG_M547X_8X) -+#define MCF_MBAR 0xE0000000 -+#define MCF_RAMBAR0 0xE3000000 -+#define MCF_RAMBAR1 0xE3001000 -+#endif -+ - #define MCF_CLK CONFIG_MCFCLK - #define MCF_BUSCLK (CONFIG_MCFCLK/2) - ---- /dev/null -+++ b/include/asm-m68k/m5485gpio.h -@@ -0,0 +1,694 @@ -+/* -+ * File: mcf548x_gpio.h -+ * Purpose: Register and bit definitions for the MCF548X -+ * -+ * Notes: -+ * -+ */ -+ -+#ifndef _M5485GPIO_H_ -+#define _M5485GPIO_H_ -+ -+/********************************************************************* -+* -+* General Purpose I/O (GPIO) -+* -+*********************************************************************/ -+ -+/* Register read/write macros */ -+#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00) -+#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01) -+#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02) -+#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04) -+#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05) -+#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06) -+#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07) -+#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08) -+#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09) -+#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A) -+#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C) -+#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D) -+#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E) -+#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10) -+#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11) -+#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12) -+#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14) -+#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15) -+#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16) -+#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17) -+#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18) -+#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19) -+#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A) -+#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C) -+#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D) -+#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E) -+#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20) -+#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21) -+#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22) -+#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24) -+#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25) -+#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26) -+#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27) -+#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28) -+#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29) -+#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A) -+#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C) -+#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D) -+#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E) -+#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30) -+#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31) -+#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32) -+#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34) -+#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35) -+#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36) -+#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37) -+#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38) -+#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39) -+#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A) -+#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C) -+#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D) -+#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E) -+#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40) -+#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42) -+#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43) -+#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44) -+#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48) -+#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A) -+#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C) -+#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D) -+#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E) -+#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F) -+#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50) -+#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40) -+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ -+#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02) -+#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04) -+#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08) -+#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10) -+#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ -+#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01) -+#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02) -+#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04) -+#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40) -+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40) -+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40) -+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40) -+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01) -+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02) -+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04) -+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ -+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01) -+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02) -+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04) -+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08) -+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ -+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01) -+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02) -+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04) -+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08) -+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40) -+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40) -+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ -+#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01) -+#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02) -+#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04) -+#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08) -+#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10) -+#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20) -+#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40) -+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ -+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02) -+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04) -+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08) -+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10) -+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ -+#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01) -+#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02) -+#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04) -+#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40) -+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40) -+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40) -+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40) -+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01) -+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02) -+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04) -+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ -+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01) -+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02) -+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04) -+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08) -+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ -+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01) -+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02) -+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04) -+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08) -+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40) -+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40) -+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01) -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02) -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04) -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08) -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10) -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20) -+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40) -+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ -+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02) -+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04) -+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08) -+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10) -+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ -+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01) -+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02) -+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04) -+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40) -+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40) -+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40) -+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40) -+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01) -+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02) -+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04) -+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ -+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01) -+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02) -+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04) -+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08) -+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ -+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01) -+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02) -+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04) -+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08) -+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40) -+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40) -+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ -+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01) -+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02) -+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04) -+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08) -+#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10) -+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20) -+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40) -+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ -+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02) -+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04) -+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08) -+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10) -+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ -+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01) -+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02) -+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04) -+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40) -+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ -+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01) -+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02) -+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04) -+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08) -+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10) -+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20) -+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40) -+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ -+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01) -+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02) -+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04) -+#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08) -+#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10) -+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20) -+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40) -+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01) -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02) -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04) -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08) -+#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10) -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20) -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40) -+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -+#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01) -+#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02) -+#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04) -+#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ -+#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01) -+#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02) -+#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04) -+#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08) -+#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ -+#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01) -+#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02) -+#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04) -+#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08) -+#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ -+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40) -+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40) -+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80) -+ -+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01) -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02) -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04) -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08) -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10) -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20) -+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ -+#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) -+#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) -+#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010) -+#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) -+#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) -+#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) -+#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) -+#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) -+#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) -+#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) -+#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ -+#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) -+#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) -+#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) -+#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) -+#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ -+#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) -+#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) -+#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) -+#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) -+#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) -+#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) -+#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) -+#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) -+#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) -+#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) -+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ -+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) -+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) -+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) -+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) -+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ -+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) -+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) -+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) -+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) -+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ -+#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) -+#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) -+#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) -+#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) -+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) -+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) -+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) -+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) -+#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ -+#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) -+#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) -+#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) -+#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) -+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) -+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) -+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) -+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) -+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) -+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ -+#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) -+#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) -+#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) -+#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) -+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) -+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) -+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) -+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ -+#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) -+#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) -+#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) -+#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) -+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) -+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) -+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) -+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) -+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ -+#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) -+#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) -+#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) -+#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) -+#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) -+#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) -+#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) -+#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) -+#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) -+#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) -+#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) -+#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) -+#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) -+#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) -+#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) -+#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) -+#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) -+#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) -+#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) -+#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) -+#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) -+#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) -+#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) -+#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) -+#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) -+#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) -+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) -+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) -+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) -+ -+/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -+#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) -+#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) -+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) -+ -+/********************************************************************/ -+ -+#endif /* _M5485GPIO_H_ */ ---- /dev/null -+++ b/include/asm-m68k/m5485gpt.h -@@ -0,0 +1,88 @@ -+/* -+ * File: mcf548x_gpt.h -+ * Purpose: Register and bit definitions for the MCF548X -+ * -+ * Notes: -+ * -+ */ -+ -+#ifndef __MCF548X_GPT_H__ -+#define __MCF548X_GPT_H__ -+ -+/********************************************************************* -+* -+* General Purpose Timers (GPT) -+* -+*********************************************************************/ -+ -+/* Register read/write macros */ -+#define MCF_GPT_GMS0 MCF_REG32(0x000800) -+#define MCF_GPT_GCIR0 MCF_REG32(0x000804) -+#define MCF_GPT_GPWM0 MCF_REG32(0x000808) -+#define MCF_GPT_GSR0 MCF_REG32(0x00080C) -+#define MCF_GPT_GMS1 MCF_REG32(0x000810) -+#define MCF_GPT_GCIR1 MCF_REG32(0x000814) -+#define MCF_GPT_GPWM1 MCF_REG32(0x000818) -+#define MCF_GPT_GSR1 MCF_REG32(0x00081C) -+#define MCF_GPT_GMS2 MCF_REG32(0x000820) -+#define MCF_GPT_GCIR2 MCF_REG32(0x000824) -+#define MCF_GPT_GPWM2 MCF_REG32(0x000828) -+#define MCF_GPT_GSR2 MCF_REG32(0x00082C) -+#define MCF_GPT_GMS3 MCF_REG32(0x000830) -+#define MCF_GPT_GCIR3 MCF_REG32(0x000834) -+#define MCF_GPT_GPWM3 MCF_REG32(0x000838) -+#define MCF_GPT_GSR3 MCF_REG32(0x00083C) -+#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010)) -+#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010)) -+#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010)) -+#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010)) -+ -+/* Bit definitions and macros for MCF_GPT_GMS */ -+#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -+#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -+#define MCF_GPT_GMS_IEN (0x00000100) -+#define MCF_GPT_GMS_OD (0x00000200) -+#define MCF_GPT_GMS_SC (0x00000400) -+#define MCF_GPT_GMS_CE (0x00001000) -+#define MCF_GPT_GMS_WDEN (0x00008000) -+#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -+#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -+#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -+#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) -+#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) -+#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) -+#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) -+#define MCF_GPT_GMS_ICT_ANY (0x00000000) -+#define MCF_GPT_GMS_ICT_RISE (0x00010000) -+#define MCF_GPT_GMS_ICT_FALL (0x00020000) -+#define MCF_GPT_GMS_ICT_PULSE (0x00030000) -+#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) -+#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) -+#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) -+#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) -+#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) -+#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) -+#define MCF_GPT_GMS_TMS_PWM (0x00000003) -+#define MCF_GPT_GMS_TMS_GPIO (0x00000004) -+ -+/* Bit definitions and macros for MCF_GPT_GCIR */ -+#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -+#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) -+ -+/* Bit definitions and macros for MCF_GPT_GPWM */ -+#define MCF_GPT_GPWM_LOAD (0x00000001) -+#define MCF_GPT_GPWM_PWMOP (0x00000100) -+#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) -+ -+/* Bit definitions and macros for MCF_GPT_GSR */ -+#define MCF_GPT_GSR_CAPT (0x00000001) -+#define MCF_GPT_GSR_COMP (0x00000002) -+#define MCF_GPT_GSR_PWMP (0x00000004) -+#define MCF_GPT_GSR_TEXP (0x00000008) -+#define MCF_GPT_GSR_PIN (0x00000100) -+#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -+#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) -+ -+/********************************************************************/ -+ -+#endif /* __MCF548X_GPT_H__ */ ---- /dev/null -+++ b/include/asm-m68k/m5485psc.h -@@ -0,0 +1,474 @@ -+/* -+ * File: mcf548x_psc.h -+ * Purpose: Register and bit definitions for the MCF548X -+ * -+ * Notes: -+ * -+ */ -+ -+#ifndef __MCF548X_PSC_H__ -+#define __MCF548X_PSC_H__ -+ -+/********************************************************************* -+* -+* Programmable Serial Controller (PSC) -+* -+*********************************************************************/ -+ -+/* Register read/write macros */ -+#define MCF_PSC_MR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600)) -+#define MCF_PSC_SR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604)) -+#define MCF_PSC_CSR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604)) -+#define MCF_PSC_CR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608)) -+#define MCF_PSC_RB0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) -+#define MCF_PSC_TB0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) -+#define MCF_PSC_TB_8BIT0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) -+#define MCF_PSC_TB_16BIT0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) -+#define MCF_PSC_TB_AC970 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) -+#define MCF_PSC_IPCR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610)) -+#define MCF_PSC_ACR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610)) -+#define MCF_PSC_ISR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614)) -+#define MCF_PSC_IMR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614)) -+#define MCF_PSC_CTUR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618)) -+#define MCF_PSC_CTLR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C)) -+#define MCF_PSC_IP0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634)) -+#define MCF_PSC_OPSET0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638)) -+#define MCF_PSC_OPRESET0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C)) -+#define MCF_PSC_SICR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640)) -+#define MCF_PSC_IRCR10 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644)) -+#define MCF_PSC_IRCR20 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648)) -+#define MCF_PSC_IRSDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C)) -+#define MCF_PSC_IRMDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650)) -+#define MCF_PSC_IRFDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654)) -+#define MCF_PSC_RFCNT0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658)) -+#define MCF_PSC_TFCNT0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C)) -+#define MCF_PSC_RFSR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664)) -+#define MCF_PSC_TFSR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684)) -+#define MCF_PSC_RFCR0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668)) -+#define MCF_PSC_TFCR0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688)) -+#define MCF_PSC_RFAR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00866E)) -+#define MCF_PSC_TFAR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00868E)) -+#define MCF_PSC_RFRP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672)) -+#define MCF_PSC_TFRP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692)) -+#define MCF_PSC_RFWP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676)) -+#define MCF_PSC_TFWP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696)) -+#define MCF_PSC_RLRFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A)) -+#define MCF_PSC_TLRFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A)) -+#define MCF_PSC_RLWFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E)) -+#define MCF_PSC_TLWFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E)) -+#define MCF_PSC_MR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008700)) -+#define MCF_PSC_SR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008704)) -+#define MCF_PSC_CSR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008704)) -+#define MCF_PSC_CR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008708)) -+#define MCF_PSC_RB1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) -+#define MCF_PSC_TB1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) -+#define MCF_PSC_TB_8BIT1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) -+#define MCF_PSC_TB_16BIT1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) -+#define MCF_PSC_TB_AC971 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) -+#define MCF_PSC_IPCR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710)) -+#define MCF_PSC_ACR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710)) -+#define MCF_PSC_ISR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714)) -+#define MCF_PSC_IMR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714)) -+#define MCF_PSC_CTUR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008718)) -+#define MCF_PSC_CTLR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00871C)) -+#define MCF_PSC_IP1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008734)) -+#define MCF_PSC_OPSET1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008738)) -+#define MCF_PSC_OPRESET1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00873C)) -+#define MCF_PSC_SICR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008740)) -+#define MCF_PSC_IRCR11 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008744)) -+#define MCF_PSC_IRCR21 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008748)) -+#define MCF_PSC_IRSDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00874C)) -+#define MCF_PSC_IRMDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008750)) -+#define MCF_PSC_IRFDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008754)) -+#define MCF_PSC_RFCNT1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008758)) -+#define MCF_PSC_TFCNT1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00875C)) -+#define MCF_PSC_RFSR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008764)) -+#define MCF_PSC_TFSR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008784)) -+#define MCF_PSC_RFCR1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008768)) -+#define MCF_PSC_TFCR1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008788)) -+#define MCF_PSC_RFAR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00876E)) -+#define MCF_PSC_TFAR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00878E)) -+#define MCF_PSC_RFRP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008772)) -+#define MCF_PSC_TFRP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008792)) -+#define MCF_PSC_RFWP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008776)) -+#define MCF_PSC_TFWP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008796)) -+#define MCF_PSC_RLRFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877A)) -+#define MCF_PSC_TLRFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879A)) -+#define MCF_PSC_RLWFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877E)) -+#define MCF_PSC_TLWFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879E)) -+#define MCF_PSC_MR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008800)) -+#define MCF_PSC_SR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008804)) -+#define MCF_PSC_CSR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008804)) -+#define MCF_PSC_CR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008808)) -+#define MCF_PSC_RB2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) -+#define MCF_PSC_TB2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) -+#define MCF_PSC_TB_8BIT2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) -+#define MCF_PSC_TB_16BIT2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) -+#define MCF_PSC_TB_AC972 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) -+#define MCF_PSC_IPCR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810)) -+#define MCF_PSC_ACR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810)) -+#define MCF_PSC_ISR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814)) -+#define MCF_PSC_IMR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814)) -+#define MCF_PSC_CTUR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008818)) -+#define MCF_PSC_CTLR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00881C)) -+#define MCF_PSC_IP2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008834)) -+#define MCF_PSC_OPSET2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008838)) -+#define MCF_PSC_OPRESET2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00883C)) -+#define MCF_PSC_SICR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008840)) -+#define MCF_PSC_IRCR12 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008844)) -+#define MCF_PSC_IRCR22 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008848)) -+#define MCF_PSC_IRSDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00884C)) -+#define MCF_PSC_IRMDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008850)) -+#define MCF_PSC_IRFDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008854)) -+#define MCF_PSC_RFCNT2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008858)) -+#define MCF_PSC_TFCNT2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00885C)) -+#define MCF_PSC_RFSR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008864)) -+#define MCF_PSC_TFSR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008884)) -+#define MCF_PSC_RFCR2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008868)) -+#define MCF_PSC_TFCR2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008888)) -+#define MCF_PSC_RFAR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00886E)) -+#define MCF_PSC_TFAR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00888E)) -+#define MCF_PSC_RFRP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008872)) -+#define MCF_PSC_TFRP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008892)) -+#define MCF_PSC_RFWP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008876)) -+#define MCF_PSC_TFWP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008896)) -+#define MCF_PSC_RLRFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887A)) -+#define MCF_PSC_TLRFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889A)) -+#define MCF_PSC_RLWFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887E)) -+#define MCF_PSC_TLWFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889E)) -+#define MCF_PSC_MR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008900)) -+#define MCF_PSC_SR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008904)) -+#define MCF_PSC_CSR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008904)) -+#define MCF_PSC_CR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008908)) -+#define MCF_PSC_RB3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) -+#define MCF_PSC_TB3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) -+#define MCF_PSC_TB_8BIT3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) -+#define MCF_PSC_TB_16BIT3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) -+#define MCF_PSC_TB_AC973 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) -+#define MCF_PSC_IPCR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910)) -+#define MCF_PSC_ACR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910)) -+#define MCF_PSC_ISR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914)) -+#define MCF_PSC_IMR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914)) -+#define MCF_PSC_CTUR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008918)) -+#define MCF_PSC_CTLR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00891C)) -+#define MCF_PSC_IP3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008934)) -+#define MCF_PSC_OPSET3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008938)) -+#define MCF_PSC_OPRESET3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00893C)) -+#define MCF_PSC_SICR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008940)) -+#define MCF_PSC_IRCR13 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008944)) -+#define MCF_PSC_IRCR23 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008948)) -+#define MCF_PSC_IRSDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00894C)) -+#define MCF_PSC_IRMDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008950)) -+#define MCF_PSC_IRFDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008954)) -+#define MCF_PSC_RFCNT3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008958)) -+#define MCF_PSC_TFCNT3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00895C)) -+#define MCF_PSC_RFSR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008964)) -+#define MCF_PSC_TFSR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008984)) -+#define MCF_PSC_RFCR3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008968)) -+#define MCF_PSC_TFCR3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008988)) -+#define MCF_PSC_RFAR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00896E)) -+#define MCF_PSC_TFAR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00898E)) -+#define MCF_PSC_RFRP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008972)) -+#define MCF_PSC_TFRP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008992)) -+#define MCF_PSC_RFWP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008976)) -+#define MCF_PSC_TFWP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008996)) -+#define MCF_PSC_RLRFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897A)) -+#define MCF_PSC_TLRFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899A)) -+#define MCF_PSC_RLWFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897E)) -+#define MCF_PSC_TLWFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899E)) -+#define MCF_PSC_MR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600+((x)*0x100))) -+#define MCF_PSC_SR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604+((x)*0x100))) -+#define MCF_PSC_CSR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604+((x)*0x100))) -+#define MCF_PSC_CR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608+((x)*0x100))) -+#define MCF_PSC_RB(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) -+#define MCF_PSC_TB(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) -+#define MCF_PSC_TB_8BIT(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) -+#define MCF_PSC_TB_16BIT(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) -+#define MCF_PSC_TB_AC97(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) -+#define MCF_PSC_IPCR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100))) -+#define MCF_PSC_ACR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100))) -+#define MCF_PSC_ISR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100))) -+#define MCF_PSC_IMR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100))) -+#define MCF_PSC_CTUR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618+((x)*0x100))) -+#define MCF_PSC_CTLR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C+((x)*0x100))) -+#define MCF_PSC_IP(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634+((x)*0x100))) -+#define MCF_PSC_OPSET(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638+((x)*0x100))) -+#define MCF_PSC_OPRESET(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C+((x)*0x100))) -+#define MCF_PSC_SICR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640+((x)*0x100))) -+#define MCF_PSC_IRCR1(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644+((x)*0x100))) -+#define MCF_PSC_IRCR2(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648+((x)*0x100))) -+#define MCF_PSC_IRSDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C+((x)*0x100))) -+#define MCF_PSC_IRMDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650+((x)*0x100))) -+#define MCF_PSC_IRFDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654+((x)*0x100))) -+#define MCF_PSC_RFCNT(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658+((x)*0x100))) -+#define MCF_PSC_TFCNT(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C+((x)*0x100))) -+#define MCF_PSC_RFSR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664+((x)*0x100))) -+#define MCF_PSC_TFSR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684+((x)*0x100))) -+#define MCF_PSC_RFCR(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668+((x)*0x100))) -+#define MCF_PSC_TFCR(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688+((x)*0x100))) -+#define MCF_PSC_RFAR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00866E)+((x)*0x100))) -+#define MCF_PSC_TFAR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00868E)+((x)*0x100))) -+#define MCF_PSC_RFRP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672+((x)*0x100))) -+#define MCF_PSC_TFRP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692+((x)*0x100))) -+#define MCF_PSC_RFWP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676+((x)*0x100))) -+#define MCF_PSC_TFWP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696+((x)*0x100))) -+#define MCF_PSC_RLRFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A+((x)*0x100))) -+#define MCF_PSC_TLRFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A+((x)*0x100))) -+#define MCF_PSC_RLWFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E+((x)*0x100))) -+#define MCF_PSC_TLWFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E+((x)*0x100))) -+ -+/* Bit definitions and macros for MCF_PSC_MR */ -+#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) -+#define MCF_PSC_MR_PT (0x04) -+#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) -+#define MCF_PSC_MR_ERR (0x20) -+#define MCF_PSC_MR_RXIRQ (0x40) -+#define MCF_PSC_MR_RXRTS (0x80) -+#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) -+#define MCF_PSC_MR_TXCTS (0x10) -+#define MCF_PSC_MR_TXRTS (0x20) -+#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) -+#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) -+#define MCF_PSC_MR_PM_MULTI_DATA (0x18) -+#define MCF_PSC_MR_PM_NONE (0x10) -+#define MCF_PSC_MR_PM_FORCE_HI (0x0C) -+#define MCF_PSC_MR_PM_FORCE_LO (0x08) -+#define MCF_PSC_MR_PM_ODD (0x04) -+#define MCF_PSC_MR_PM_EVEN (0x00) -+#define MCF_PSC_MR_BC_5 (0x00) -+#define MCF_PSC_MR_BC_6 (0x01) -+#define MCF_PSC_MR_BC_7 (0x02) -+#define MCF_PSC_MR_BC_8 (0x03) -+#define MCF_PSC_MR_CM_NORMAL (0x00) -+#define MCF_PSC_MR_CM_ECHO (0x40) -+#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) -+#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) -+#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) -+#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) -+#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) -+ -+/* Bit definitions and macros for MCF_PSC_SR */ -+#define MCF_PSC_SR_ERR (0x0040) -+#define MCF_PSC_SR_CDE_DEOF (0x0080) -+#define MCF_PSC_SR_RXRDY (0x0100) -+#define MCF_PSC_SR_FU (0x0200) -+#define MCF_PSC_SR_TXRDY (0x0400) -+#define MCF_PSC_SR_TXEMP_URERR (0x0800) -+#define MCF_PSC_SR_OE (0x1000) -+#define MCF_PSC_SR_PE_CRCERR (0x2000) -+#define MCF_PSC_SR_FE_PHYERR (0x4000) -+#define MCF_PSC_SR_RB_NEOF (0x8000) -+ -+/* Bit definitions and macros for MCF_PSC_CSR */ -+#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) -+#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) -+#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) -+#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) -+#define MCF_PSC_CSR_RCSEL_CTM (0xF0) -+#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) -+#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) -+#define MCF_PSC_CSR_TCSEL_CTM (0x0F) -+ -+/* Bit definitions and macros for MCF_PSC_CR */ -+#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) -+#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) -+#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) -+#define MCF_PSC_CR_NONE (0x00) -+#define MCF_PSC_CR_STOP_BREAK (0x70) -+#define MCF_PSC_CR_START_BREAK (0x60) -+#define MCF_PSC_CR_BKCHGINT (0x50) -+#define MCF_PSC_CR_RESET_ERROR (0x40) -+#define MCF_PSC_CR_RESET_TX (0x30) -+#define MCF_PSC_CR_RESET_RX (0x20) -+#define MCF_PSC_CR_RESET_MR (0x10) -+#define MCF_PSC_CR_TX_DISABLED (0x08) -+#define MCF_PSC_CR_TX_ENABLED (0x04) -+#define MCF_PSC_CR_RX_DISABLED (0x02) -+#define MCF_PSC_CR_RX_ENABLED (0x01) -+ -+/* Bit definitions and macros for MCF_PSC_TB_8BIT */ -+#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) -+#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) -+#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) -+#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) -+ -+/* Bit definitions and macros for MCF_PSC_TB_16BIT */ -+#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) -+#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) -+ -+/* Bit definitions and macros for MCF_PSC_TB_AC97 */ -+#define MCF_PSC_TB_AC97_SOF (0x00000800) -+#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) -+ -+/* Bit definitions and macros for MCF_PSC_IPCR */ -+#define MCF_PSC_IPCR_RESERVED (0x0C) -+#define MCF_PSC_IPCR_CTS (0x0D) -+#define MCF_PSC_IPCR_D_CTS (0x1C) -+#define MCF_PSC_IPCR_SYNC (0x8C) -+ -+/* Bit definitions and macros for MCF_PSC_ACR */ -+#define MCF_PSC_ACR_IEC0 (0x01) -+#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) -+#define MCF_PSC_ACR_BRG (0x80) -+ -+/* Bit definitions and macros for MCF_PSC_ISR */ -+#define MCF_PSC_ISR_ERR (0x0040) -+#define MCF_PSC_ISR_DEOF (0x0080) -+#define MCF_PSC_ISR_TXRDY (0x0100) -+#define MCF_PSC_ISR_RXRDY_FU (0x0200) -+#define MCF_PSC_ISR_DB (0x0400) -+#define MCF_PSC_ISR_IPC (0x8000) -+ -+/* Bit definitions and macros for MCF_PSC_IMR */ -+#define MCF_PSC_IMR_ERR (0x0040) -+#define MCF_PSC_IMR_DEOF (0x0080) -+#define MCF_PSC_IMR_TXRDY (0x0100) -+#define MCF_PSC_IMR_RXRDY_FU (0x0200) -+#define MCF_PSC_IMR_DB (0x0400) -+#define MCF_PSC_IMR_IPC (0x8000) -+ -+/* Bit definitions and macros for MCF_PSC_IP */ -+#define MCF_PSC_IP_CTS (0x01) -+#define MCF_PSC_IP_TGL (0x40) -+#define MCF_PSC_IP_LWPR_B (0x80) -+ -+/* Bit definitions and macros for MCF_PSC_OPSET */ -+#define MCF_PSC_OPSET_RTS (0x01) -+ -+/* Bit definitions and macros for MCF_PSC_OPRESET */ -+#define MCF_PSC_OPRESET_RTS (0x01) -+ -+/* Bit definitions and macros for MCF_PSC_SICR */ -+#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) -+#define MCF_PSC_SICR_SHDIR (0x10) -+#define MCF_PSC_SICR_DTS (0x20) -+#define MCF_PSC_SICR_AWR (0x40) -+#define MCF_PSC_SICR_ACRB (0x80) -+#define MCF_PSC_SICR_SIM_UART (0x00) -+#define MCF_PSC_SICR_SIM_MODEM8 (0x01) -+#define MCF_PSC_SICR_SIM_MODEM16 (0x02) -+#define MCF_PSC_SICR_SIM_AC97 (0x03) -+#define MCF_PSC_SICR_SIM_SIR (0x04) -+#define MCF_PSC_SICR_SIM_MIR (0x05) -+#define MCF_PSC_SICR_SIM_FIR (0x06) -+ -+/* Bit definitions and macros for MCF_PSC_IRCR1 */ -+#define MCF_PSC_IRCR1_SPUL (0x01) -+#define MCF_PSC_IRCR1_SIPEN (0x02) -+#define MCF_PSC_IRCR1_FD (0x04) -+ -+/* Bit definitions and macros for MCF_PSC_IRCR2 */ -+#define MCF_PSC_IRCR2_NXTEOF (0x01) -+#define MCF_PSC_IRCR2_ABORT (0x02) -+#define MCF_PSC_IRCR2_SIPREQ (0x04) -+ -+/* Bit definitions and macros for MCF_PSC_IRMDR */ -+#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) -+#define MCF_PSC_IRMDR_FREQ (0x80) -+ -+/* Bit definitions and macros for MCF_PSC_IRFDR */ -+#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_RFCNT */ -+#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_TFCNT */ -+#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_RFSR */ -+#define MCF_PSC_RFSR_EMT (0x0001) -+#define MCF_PSC_RFSR_ALARM (0x0002) -+#define MCF_PSC_RFSR_FU (0x0004) -+#define MCF_PSC_RFSR_FRMRY (0x0008) -+#define MCF_PSC_RFSR_OF (0x0010) -+#define MCF_PSC_RFSR_UF (0x0020) -+#define MCF_PSC_RFSR_RXW (0x0040) -+#define MCF_PSC_RFSR_FAE (0x0080) -+#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) -+#define MCF_PSC_RFSR_TAG (0x1000) -+#define MCF_PSC_RFSR_TXW (0x4000) -+#define MCF_PSC_RFSR_IP (0x8000) -+#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) -+#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) -+#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) -+#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) -+ -+/* Bit definitions and macros for MCF_PSC_TFSR */ -+#define MCF_PSC_TFSR_EMT (0x0001) -+#define MCF_PSC_TFSR_ALARM (0x0002) -+#define MCF_PSC_TFSR_FU (0x0004) -+#define MCF_PSC_TFSR_FRMRY (0x0008) -+#define MCF_PSC_TFSR_OF (0x0010) -+#define MCF_PSC_TFSR_UF (0x0020) -+#define MCF_PSC_TFSR_RXW (0x0040) -+#define MCF_PSC_TFSR_FAE (0x0080) -+#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) -+#define MCF_PSC_TFSR_TAG (0x1000) -+#define MCF_PSC_TFSR_TXW (0x4000) -+#define MCF_PSC_TFSR_IP (0x8000) -+#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) -+#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) -+#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) -+#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) -+ -+/* Bit definitions and macros for MCF_PSC_RFCR */ -+#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -+#define MCF_PSC_RFCR_TXW_MSK (0x00040000) -+#define MCF_PSC_RFCR_OF_MSK (0x00080000) -+#define MCF_PSC_RFCR_UF_MSK (0x00100000) -+#define MCF_PSC_RFCR_RXW_MSK (0x00200000) -+#define MCF_PSC_RFCR_FAE_MSK (0x00400000) -+#define MCF_PSC_RFCR_IP_MSK (0x00800000) -+#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) -+#define MCF_PSC_RFCR_FRMEN (0x08000000) -+#define MCF_PSC_RFCR_TIMER (0x10000000) -+#define MCF_PSC_RFCR_WRITETAG (0x20000000) -+#define MCF_PSC_RFCR_SHADOW (0x80000000) -+ -+/* Bit definitions and macros for MCF_PSC_TFCR */ -+#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -+#define MCF_PSC_TFCR_TXW_MSK (0x00040000) -+#define MCF_PSC_TFCR_OF_MSK (0x00080000) -+#define MCF_PSC_TFCR_UF_MSK (0x00100000) -+#define MCF_PSC_TFCR_RXW_MSK (0x00200000) -+#define MCF_PSC_TFCR_FAE_MSK (0x00400000) -+#define MCF_PSC_TFCR_IP_MSK (0x00800000) -+#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) -+#define MCF_PSC_TFCR_FRMEN (0x08000000) -+#define MCF_PSC_TFCR_TIMER (0x10000000) -+#define MCF_PSC_TFCR_WRITETAG (0x20000000) -+#define MCF_PSC_TFCR_SHADOW (0x80000000) -+ -+/* Bit definitions and macros for MCF_PSC_RFAR */ -+#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_TFAR */ -+#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_RFRP */ -+#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_TFRP */ -+#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_RFWP */ -+#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_TFWP */ -+#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_RLRFP */ -+#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_TLRFP */ -+#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_RLWFP */ -+#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) -+ -+/* Bit definitions and macros for MCF_PSC_TLWFP */ -+#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) -+ -+/********************************************************************/ -+ -+#endif /* __MCF548X_PSC_H__ */ ---- /dev/null -+++ b/include/asm-m68k/m5485sim.h -@@ -0,0 +1,219 @@ -+/* -+ * m5485sim.h -- ColdFire 547x/548x System Integration Unit support. -+ */ -+ -+#ifndef m5485sim_h -+#define m5485sim_h -+ -+ -+/* -+ * System Integration Unit Registers -+ */ -+#define MCF_SDRAMDS MCF_REG32(0x000004) /* SDRAM Drive Strength */ -+#define MCF_SBCR MCF_REG32(0x000010) /* System Breakpoint Control */ -+#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4))/* SDRAM Chip Select X */ -+#define MCF_SECSACR MCF_REG32(0x000038) /* Sequential Access Control */ -+#define MCF_RSR MCF_REG32(0x000044) /* Reset Status */ -+#define MCF_JTAGID MCF_REG32(0x000050) /* JTAG Device Identification */ -+ -+/* -+ * FlexBus Chip Selects Registers -+ */ -+#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC)) -+#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC)) -+#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC)) -+ -+/* -+ * Interrupt Controller Registers -+ */ -+#define MCF_IPRH MCF_REG32(0x000700) -+#define MCF_IPRL MCF_REG32(0x000704) -+#define MCF_IMRH MCF_REG32(0x000708) -+#define MCF_IMRL MCF_REG32(0x00070C) -+#define MCF_INTFRCH MCF_REG32(0x000710) -+#define MCF_INTFRCL MCF_REG32(0x000714) -+#define MCF_IRLR MCF_REG08(0x000718) -+#define MCF_IACKLPR MCF_REG08(0x000719) -+#define MCF_SWIACK MCF_REG08(0x0007E0) -+#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004)) -+#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001)) -+ -+/* -+ * Slice Timers Registers -+ */ -+#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010)) -+#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010)) -+#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010)) -+#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010)) -+ -+/* -+ * Interrupt sources -+ */ -+#define ISC_EPORT_Fn(x) (x) /* EPORT Interrupts */ -+#define ISC_USB_EPn(x) (15+(x)) /* USB Endopint */ -+#define ISC_USB_ISR (22) /* USB General source */ -+#define ISC_USB_AISR (22) /* USB core source */ -+#define ISC_DSPI_OVRFW (25) /* DSPI overflow */ -+#define ISC_DSPI_RFOF (26) -+#define ISC_DSPI_RFDF (27) -+#define ISC_DSPI_TFUF (28) -+#define ISC_DSPI_TCF (29) -+#define ISC_DSPI_TFFF (30) -+#define ISC_DSPI_EOQF (31) -+#define ISC_PSCn(x) (35-(x)) -+#define ISC_COMM_TIM (36) -+#define ISC_SEC (37) -+#define ISC_FEC1 (38) -+#define ISC_FEC0 (39) -+#define ISC_I2C (40) -+#define ISC_PCI_ARB (41) -+#define ISC_PCI_CB (42) -+#define ISC_PCI_XLB (43) -+#define ISC_DMA (48) -+#define ISC_CANn_ERR(x) (49+(6*(x))) -+#define ISC_CANn_BUSOFF(x) (50+(6*(x))) -+#define ISC_CANn_MBOR(x) (51+(6*(x))) -+#define ISC_CAN0_WAKEIN (52) -+#define ISC_SLTn(x) (54-(x)) -+#define ISC_GPTn(x) (62-(x)) -+ -+/* -+ * Interrupt level and priorities -+ */ -+#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3)) -+#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2)) -+#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1)) -+#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0)) -+#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7)) -+#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6)) -+#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5)) -+#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4)) -+#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3)) -+#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2)) -+#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1)) -+ -+#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x))) -+#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7)) -+#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6)) -+#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5)) -+#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4)) -+#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3)) -+#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2)) -+#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1)) -+#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0)) -+ -+#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7)) -+#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6)) -+#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5)) -+#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4)) -+#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3)) -+#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2)) -+#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1)) -+#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0)) -+ -+#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7)) -+#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3))) -+#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3)) -+#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2)) -+#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1)) -+#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0)) -+ -+ -+ -+ -+ -+/********************************************************************/ -+ -+/* -+ * System Integration Unit Bitfields -+ */ -+ -+/* SBCR */ -+#define MCF_SBCR_PIN2DSPI (0x08000000) -+#define MCF_SBCR_DMA2CPU (0x10000000) -+#define MCF_SBCR_CPU2DMA (0x20000000) -+#define MCF_SBCR_PIN2DMA (0x40000000) -+#define MCF_SBCR_PIN2CPU (0x80000000) -+ -+/* SECSACR */ -+#define MCF_SECSACR_SEQEN (0x00000001) -+ -+/* RSR */ -+#define MCF_RSR_RST (0x00000001) -+#define MCF_RSR_RSTWD (0x00000002) -+#define MCF_RSR_RSTJTG (0x00000008) -+ -+/* JTAGID */ -+#define MCF_JTAGID_REV (0xF0000000) -+#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF) -+#define MCF_JTAGID_MCF5485 (0x0800C01D) -+#define MCF_JTAGID_MCF5484 (0x0800D01D) -+#define MCF_JTAGID_MCF5483 (0x0800E01D) -+#define MCF_JTAGID_MCF5482 (0x0800F01D) -+#define MCF_JTAGID_MCF5481 (0x0801001D) -+#define MCF_JTAGID_MCF5480 (0x0801101D) -+#define MCF_JTAGID_MCF5475 (0x0801201D) -+#define MCF_JTAGID_MCF5474 (0x0801301D) -+#define MCF_JTAGID_MCF5473 (0x0801401D) -+#define MCF_JTAGID_MCF5472 (0x0801501D) -+#define MCF_JTAGID_MCF5471 (0x0801601D) -+#define MCF_JTAGID_MCF5470 (0x0801701D) -+ -+ -+/* -+ * Interrupt Controller Bitfields -+ */ -+#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1) -+#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0) -+#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4) -+#define MCF_ICR_IP(x) (((x)&0x07)<<0) -+#define MCF_ICR_IL(x) (((x)&0x07)<<3) -+ -+/* -+ * Slice Timers Bitfields -+ */ -+#define MCF_SCR_TEN (0x01000000) -+#define MCF_SCR_IEN (0x02000000) -+#define MCF_SCR_RUN (0x04000000) -+#define MCF_SSR_ST (0x01000000) -+#define MCF_SSR_BE (0x02000000) -+ -+ -+/* -+ * Some needed coldfire registers -+ */ -+#define MCF_PAR_PCIBG MCF_REG16(0x000A48) -+#define MCF_PAR_PCIBR MCF_REG16(0x000A4A) -+#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3)) -+#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44) -+#define MCF_EPPAR MCF_REG16(0x000F00) -+#define MCF_EPIER MCF_REG08(0x000F05) -+#define MCF_EPFR MCF_REG08(0x000F0C) -+ -+/* -+ * Some GPIO bitfields -+ */ -+#define MCF_PAR_SDA (0x0008) -+#define MCF_PAR_SCL (0x0004) -+#define MCF_PAR_PSC_TXD (0x04) -+#define MCF_PAR_PSC_RXD (0x08) -+#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) -+#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) -+#define MCF_PAR_PSC_CTS_GPIO (0x00) -+#define MCF_PAR_PSC_CTS_BCLK (0x80) -+#define MCF_PAR_PSC_CTS_CTS (0xC0) -+#define MCF_PAR_PSC_RTS_GPIO (0x00) -+#define MCF_PAR_PSC_RTS_FSYNC (0x20) -+#define MCF_PAR_PSC_RTS_RTS (0x30) -+#define MCF_PAR_PSC_CANRX (0x40) -+ -+ -+/* -+ * Some used coldfire values -+ */ -+#define MCF_EPIER_EPIE(x) (0x01 << (x)) -+#define MCF_EPPAR_EPPAx_FALLING (2) -+#define MCF_EPPAR_EPPA(n,x) (((x)&0x0003) << (2*n)) -+ -+ -+#endif /* m5485sim_h */ ---- a/include/asm-m68k/mcfsim.h -+++ b/include/asm-m68k/mcfsim.h -@@ -20,6 +20,11 @@ - #include <asm/mcf5445x_pci.h> - #include <asm/mcf5445x_pciarb.h> - #include <asm/mcf5445x_eport.h> -+#include <asm/mcf5445x_fbcs.h> -+#include <asm/mcf5445x_xbs.h> -+#include <asm/mcf5445x_dtim.h> -+#elif defined(CONFIG_M547X_8X) -+#include <asm/m5485sim.h> - #endif - - /* ---- a/include/asm-m68k/mcfuart.h -+++ b/include/asm-m68k/mcfuart.h -@@ -22,6 +22,15 @@ - #define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ - #define MCFINT_VECBASE 64 - #define MCFINT_UART0 26 -+ -+#elif defined(CONFIG_M547X_8X) -+ -+#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ -+#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ -+#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ -+#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ -+#define MCFINT_VECBASE 64 -+#define MCFINT_UART0 35 - #endif - - -@@ -97,6 +106,11 @@ - #define MCFUART_USR_RXFULL 0x02 /* Receiver full */ - #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ - -+#if defined(CONFIG_M547X_8X) -+#define MCFUART_USR_TXREADY_BN 0x0a -+#define MCFUART_USR_TXEMPTY_BN 0x0b -+#endif -+ - #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ - MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) - ---- a/include/asm-m68k/mmu_context.h -+++ b/include/asm-m68k/mmu_context.h -@@ -152,6 +152,7 @@ static inline void activate_mm(struct mm - - #else /* CONFIG_COLDFIRE */ - -+#include <asm/coldfire.h> - #include <asm/atomic.h> - #include <asm/bitops.h> - #include <asm/mmu.h> -@@ -227,6 +228,77 @@ static inline void activate_mm(struct mm - #define deactivate_mm(tsk, mm) do { } while (0) - - extern void mmu_context_init(void); -+#if defined(CONFIG_M547X_8X) -+#define prepare_arch_switch(next) load_ksp_mmu(next) -+ -+static inline void load_ksp_mmu(struct task_struct *task) -+{ -+ int flags; -+ struct mm_struct *mm; -+ int asid; -+ pgd_t *pgd; -+ pmd_t *pmd; -+ pte_t *pte; -+ unsigned long mmuar; -+ -+ local_irq_save(flags); -+ mmuar = task->thread.ksp; -+ -+ /* Search for a valid TLB entry, if one is found, don't remap */ -+ *MMUAR = mmuar; -+ *MMUOR = MMUOR_STLB | MMUOR_ADR; -+ if ((*MMUSR) & MMUSR_HIT) -+ goto end; -+ -+ if (mmuar >= PAGE_OFFSET) { -+ mm = &init_mm; -+ } else { -+ printk ("load_ksp_mmu: non-kernel mm found: 0x%08x\n", (unsigned int) task->mm); -+ mm = task->mm; -+ } -+ -+ if (!mm) -+ goto bug; -+ -+ pgd = pgd_offset(mm, mmuar); -+ if (pgd_none(*pgd)) -+ goto bug; -+ -+ pmd = pmd_offset(pgd, mmuar); -+ if (pmd_none(*pmd)) -+ goto bug; -+ -+ pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar) -+ : pte_offset_map(pmd, mmuar); -+ if (pte_none(*pte) || !pte_present(*pte)) -+ goto bug; -+ -+ set_pte(pte, pte_mkyoung(*pte)); -+ asid = mm->context & 0xff; -+ if (!pte_dirty(*pte) && mmuar<=PAGE_OFFSET) -+ set_pte(pte, pte_wrprotect(*pte)); -+ -+ *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT) -+ | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT) -+ | MMUTR_V; -+ -+ *MMUDR = (pte_val(*pte) & PAGE_MASK) -+ | ((pte->pte) & CF_PAGE_MMUDR_MASK) -+ | MMUDR_SZ8K | MMUDR_X; -+ -+ *MMUOR = MMUOR_ACC | MMUOR_UAA; -+ asm ("nop"); -+ -+ goto end; -+ -+bug: -+ printk ("ksp load failed: mm=0x%08x ksp=0x%08x\n", (unsigned int) mm, (unsigned int) mmuar); -+ -+end: -+ local_irq_restore(flags); -+} -+ -+#endif /* CONFIG_M547X_8X */ - - #endif /* CONFIG_COLDFIRE */ - #endif ---- a/include/asm-m68k/page_offset.h -+++ b/include/asm-m68k/page_offset.h -@@ -5,7 +5,12 @@ - #elif defined(CONFIG_SUN3) - #define PAGE_OFFSET_RAW 0x0E000000 - #else /* CONFIG_COLDFIRE */ -+#if defined(CONFIG_M54455) - #define PAGE_OFFSET_RAW 0xC0000000 - #define PHYS_OFFSET 0x40000000 -+#elif defined(CONFIG_M547X_8X) -+#define PAGE_OFFSET_RAW 0xC0000000 -+#define PHYS_OFFSET 0x00000000 -+#endif - #endif - |