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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-05-18 20:10:53 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-05-18 20:10:53 +0000
commit71f3abe21d082948e28c7310edf8a010dba12c13 (patch)
tree1eb806de4cc59e2f5d288d8d3ce0cfea82e374cb /target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch
parent2bb56acc0c06fea8bbcbeca7324ddf98682f057d (diff)
cns3xxx: add support for 3.3
Compile tested only. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31809 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch')
-rw-r--r--target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch11
1 files changed, 11 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch b/target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch
new file mode 100644
index 000000000..0c6c52503
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.3/054-cns3xxx_pcie_clock.patch
@@ -0,0 +1,11 @@
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -378,8 +378,6 @@ static int __init cns3xxx_pcie_init(void
+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+ iotable_init(cns3xxx_pcie[i].cfg_bases,
+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+ cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+ pci_common_init(&cns3xxx_pcie[i].hw_pci);