diff options
| author | jogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-03-28 20:42:25 +0000 |
|---|---|---|
| committer | jogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2012-03-28 20:42:25 +0000 |
| commit | 769a390d818dfd0957eb259cc7455a01b800c23e (patch) | |
| tree | 1ca409cf3ca8e84274f046e20df1cdda0ea20938 /target/linux/brcm63xx/patches-3.3/004-MIPS-BCM63XX-define-BCM6358-SPI-base-address.patch | |
| parent | 9bb8c69134019093dce8a8eca3b8a8aa1f040488 (diff) | |
bcm63xx: replace SPI driver with latest upstream version
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31130 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/patches-3.3/004-MIPS-BCM63XX-define-BCM6358-SPI-base-address.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.3/004-MIPS-BCM63XX-define-BCM6358-SPI-base-address.patch | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.3/004-MIPS-BCM63XX-define-BCM6358-SPI-base-address.patch b/target/linux/brcm63xx/patches-3.3/004-MIPS-BCM63XX-define-BCM6358-SPI-base-address.patch new file mode 100644 index 000000000..0c314da74 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.3/004-MIPS-BCM63XX-define-BCM6358-SPI-base-address.patch @@ -0,0 +1,21 @@ +From bfd78dda2ad5afb4434ebe99c05528614065bdb1 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli <florian@openwrt.org> +Date: Wed, 25 Jan 2012 17:39:56 +0100 +Subject: [PATCH 06/63] MIPS: BCM63XX: define BCM6358 SPI base address + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -289,7 +289,7 @@ enum bcm63xx_regs_set { + #define BCM_6358_UART0_BASE (0xfffe0100) + #define BCM_6358_UART1_BASE (0xfffe0120) + #define BCM_6358_GPIO_BASE (0xfffe0080) +-#define BCM_6358_SPI_BASE (0xdeadbeef) ++#define BCM_6358_SPI_BASE (0xfffe0800) + #define BCM_6358_SPI2_BASE (0xfffe0800) + #define BCM_6358_UDC0_BASE (0xfffe0800) + #define BCM_6358_OHCI0_BASE (0xfffe1400) |