summaryrefslogtreecommitdiffstats
path: root/target/linux/brcm63xx/files/include/asm-mips
diff options
context:
space:
mode:
authorflorian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-12-19 17:05:09 +0000
committerflorian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73>2008-12-19 17:05:09 +0000
commit693a86d5d09657d34b4a31742dda9ffcf6b41cda (patch)
treeab8904b9f3c3cbd6fef7317e53908106ccfbb3df /target/linux/brcm63xx/files/include/asm-mips
parente830a5a13e742c66916fdc44f52fa9b5036a434f (diff)
[brcm63xx] add experimental support for bcm6338
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13691 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm63xx/files/include/asm-mips')
-rw-r--r--target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h66
-rw-r--r--target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h30
2 files changed, 95 insertions, 1 deletions
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 4c8c3fd8b..560da0b29 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
* compile time if only one CPU support is enabled (idea stolen from
* arm mach-types)
*/
+#define BCM6338_CPU_ID 0x6338
#define BCM6348_CPU_ID 0x6348
#define BCM6358_CPU_ID 0x6358
@@ -17,6 +18,19 @@ u16 __bcm63xx_get_cpu_id(void);
u16 bcm63xx_get_cpu_rev(void);
unsigned int bcm63xx_get_cpu_freq(void);
+#ifdef CONFIG_BCM63XX_CPU_6338
+# ifdef bcm63xx_get_cpu_id
+# undef bcm63xx_get_cpu_id
+# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
+# define BCMCPU_RUNTIME_DETECT
+# else
+# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
+# endif
+# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+#else
+# define BCMCPU_IS_6338() (0)
+#endif
+
#ifdef CONFIG_BCM63XX_CPU_6348
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
@@ -88,6 +102,19 @@ enum bcm63xx_regs_set {
#define RSET_PCMCIA_SIZE 12
/*
+ * 6338 register sets base address
+ */
+
+#define BCM_6338_PERF_BASE (0xfffe0000)
+#define BCM_6338_TIMER_BASE (0xfffe0000)
+#define BCM_6338_WDT_BASE (0xfffe001c)
+#define BCM_6338_UART0_BASE (0xfffe0300)
+#define BCM_6338_GPIO_BASE (0xfffe0400)
+#define BCM_6338_SPI_BASE (0xfffe0c00)
+#define BCM_6338_SAR_BASE (0xfffe2000)
+#define BCM_6338_MEMC_BASE (0xfffe3100)
+
+/*
* 6348 register sets base address
*/
#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
@@ -147,6 +174,24 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
#ifdef BCMCPU_RUNTIME_DETECT
return bcm63xx_regs_base[set];
#else
+#ifdef CONFIG_BCM63XX_CPU_6338
+ switch (set) {
+ case RSET_PERF:
+ return BCM_6338_PERF_BASE;
+ case RSET_TIMER:
+ return BCM_6338_TIMER_BASE;
+ case RSET_WDT:
+ return BCM_6338_WDT_BASE;
+ case RSET_UART0:
+ return BCM_6338_UART0_BASE;
+ case RSET_GPIO:
+ return BCM_6338_GPIO_BASE;
+ case RSET_SPI:
+ return BCM_6338_SPI_BASE;
+ case RSET_MEMC:
+ return BCM_6338_MEMC_BASE;
+ }
+#endif
#ifdef CONFIG_BCM63XX_CPU_6348
switch (set) {
case RSET_DSL_LMEM:
@@ -267,6 +312,27 @@ enum bcm63xx_irq {
};
/*
+ * 6338 irqs
+ */
+#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IR (IRQ_INTERNAL_BASE + 1)
+#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
+#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
+#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
+#define BCM_6338_USBS_IRQ (IRQ_INTERNAL_BASE + 7)
+#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
+#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
+#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
+#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
+#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
+#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
+#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
+#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
+#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
+
+/*
* 6348 irqs
*/
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
index d628601ab..cdc44fc4c 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,15 @@
/* Clock Control register */
#define PERF_CKCTL_REG 0x4
+#define CKCTL_6338_ENET_EN (1 << 4)
+#define CKCTL_6338_USBS_EN (1 << 4)
+#define CKCTL_6338_SAR_EN (1 << 5)
+#define CKCTL_6338_SPI_EN (1 << 9)
+
+#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ENET_EN | \
+ CKCTL_6338_SAR_EN | \
+ CKCTL_6338_SPI_EN)
+
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
#define CKCTL_6348_MPI_EN (1 << 1)
#define CKCTL_6348_SDRAM_EN (1 << 2)
@@ -83,6 +92,25 @@
/* Soft Reset register */
#define PERF_SOFTRESET_REG 0x28
+#define SOFTRESET_6338_SPI_MASK (1 << 0)
+#define SOFTRESET_6338_ENET_MASK (1 << 2)
+#define SOFTRESET_6338_USBH_MASK (1 << 3)
+#define SOFTRESET_6338_USBS_MASK (1 << 4)
+#define SOFTRESET_6338_ADSL_MASK (1 << 5)
+#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
+#define SOFTRESET_6338_SAR_MASK (1 << 7)
+#define SOFTRESET_6338_ACLC_MASK (1 << 8)
+#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
+#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
+ SOFTRESET_6338_ENET_MASK | \
+ SOFTRESET_6338_USBH_MASK | \
+ SOFTRESET_6338_USBS_MASK | \
+ SOFTRESET_6338_ADSL_MASK | \
+ SOFTRESET_6338_DMAMEM_MASK | \
+ SOFTRESET_6338_SAR_MASK | \
+ SOFTRESET_6338_ACLC_MASK | \
+ SOFTRESET_6338_ADSLMIPSPLL_MASK)
+
#define SOFTRESET_6348_SPI_MASK (1 << 0)
#define SOFTRESET_6348_ENET_MASK (1 << 2)
#define SOFTRESET_6348_USBH_MASK (1 << 3)
@@ -763,7 +791,7 @@
#define SPI_INT_MASK 0x704
#define SPI_INTR_CMD_DONE 0x01
#define SPI_INTR_RX_OVERFLOW 0x02
-#define SPI_INTR_INTR_TX_UNDERFLOW 0x04
+#define SPI_INTR_TX_UNDERFLOW 0x04
#define SPI_INTR_TX_OVERFLOW 0x08
#define SPI_INTR_RX_UNDERFLOW 0x10
#define SPI_INTR_CLEAR_ALL 0x1f