diff options
author | hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-06-18 15:24:44 +0000 |
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committer | hauke <hauke@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-06-18 15:24:44 +0000 |
commit | 86a107e5443812428723192711f8def571f83aa9 (patch) | |
tree | db336d3a35705b7d66b95300b7131e97c4b93a5b /target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch | |
parent | e57d4b04d417bdc49fd28cd83c0a1a62ac2e3db4 (diff) |
brcm47xx: add support for kernel 3.0
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27217 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch')
-rw-r--r-- | target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch | 325 |
1 files changed, 325 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch new file mode 100644 index 000000000..bde1fb143 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch @@ -0,0 +1,325 @@ +--- a/drivers/net/tg3.c ++++ b/drivers/net/tg3.c +@@ -43,6 +43,7 @@ + #include <linux/prefetch.h> + #include <linux/dma-mapping.h> + #include <linux/firmware.h> ++#include <linux/ssb/ssb_driver_gige.h> + + #include <net/checksum.h> + #include <net/ip.h> +@@ -515,7 +516,8 @@ static void _tw32_flush(struct tg3 *tp, + static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) + { + tp->write32_mbox(tp, off, val); +- if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) ++ if (tg3_flag(tp, FLUSH_POSTED_WRITES) || ++ (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))) + tp->read32_mbox(tp, off); + } + +@@ -525,7 +527,7 @@ static void tg3_write32_tx_mbox(struct t + writel(val, mbox); + if (tg3_flag(tp, TXD_MBOX_HWBUG)) + writel(val, mbox); +- if (tg3_flag(tp, MBOX_WRITE_REORDER)) ++ if (tg3_flag(tp, MBOX_WRITE_REORDER) || tg3_flag(tp, FLUSH_POSTED_WRITES)) + readl(mbox); + } + +@@ -804,7 +806,7 @@ static void tg3_switch_clocks(struct tg3 + + #define PHY_BUSY_LOOPS 5000 + +-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ++static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val) + { + u32 frame_val; + unsigned int loops; +@@ -818,7 +820,7 @@ static int tg3_readphy(struct tg3 *tp, i + + *val = 0x0; + +- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & ++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) & + MI_COM_PHY_ADDR_MASK); + frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & + MI_COM_REG_ADDR_MASK); +@@ -853,7 +855,12 @@ static int tg3_readphy(struct tg3 *tp, i + return ret; + } + +-static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ++static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ++{ ++ return __tg3_readphy(tp, tp->phy_addr, reg, val); ++} ++ ++static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val) + { + u32 frame_val; + unsigned int loops; +@@ -869,7 +876,7 @@ static int tg3_writephy(struct tg3 *tp, + udelay(80); + } + +- frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & ++ frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) & + MI_COM_PHY_ADDR_MASK); + frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & + MI_COM_REG_ADDR_MASK); +@@ -902,6 +909,11 @@ static int tg3_writephy(struct tg3 *tp, + return ret; + } + ++static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ++{ ++ return __tg3_writephy(tp, tp->phy_addr, reg, val); ++} ++ + static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) + { + int err; +@@ -2532,6 +2544,9 @@ static int tg3_nvram_read(struct tg3 *tp + { + int ret; + ++ if (tg3_flag(tp, IS_SSB_CORE)) ++ return -ENODEV; ++ + if (!tg3_flag(tp, NVRAM)) + return tg3_nvram_read_using_eeprom(tp, offset, val); + +@@ -2855,8 +2870,10 @@ static int tg3_power_down_prepare(struct + tg3_frob_aux_power(tp); + + /* Workaround for unstable PLL clock */ +- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || +- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { ++ if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 && ++ /* !!! FIXME !!! */ ++ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || ++ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) { + u32 val = tr32(0x7d00); + + val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); +@@ -3377,6 +3394,14 @@ relink: + if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { + tg3_phy_copper_begin(tp); + ++ if (tg3_flag(tp, ROBOSWITCH)) { ++ current_link_up = 1; ++ current_speed = SPEED_1000; /* FIXME */ ++ current_duplex = DUPLEX_FULL; ++ tp->link_config.active_speed = current_speed; ++ tp->link_config.active_duplex = current_duplex; ++ } ++ + tg3_readphy(tp, MII_BMSR, &bmsr); + if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || + (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) +@@ -6962,6 +6987,11 @@ static int tg3_poll_fw(struct tg3 *tp) + int i; + u32 val; + ++ if (tg3_flag(tp, IS_SSB_CORE)) { ++ /* We don't use firmware. */ ++ return 0; ++ } ++ + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { + /* Wait up to 20ms for init done. */ + for (i = 0; i < 200; i++) { +@@ -7251,6 +7281,14 @@ static int tg3_chip_reset(struct tg3 *tp + tw32(0x5000, 0x400); + } + ++ if (tg3_flag(tp, IS_SSB_CORE)) { ++ /* BCM4785: In order to avoid repercussions from using potentially ++ * defective internal ROM, stop the Rx RISC CPU, which is not ++ * required. */ ++ tg3_stop_fw(tp); ++ tg3_halt_cpu(tp, RX_CPU_BASE); ++ } ++ + tw32(GRC_MODE, tp->grc_mode); + + if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { +@@ -7408,9 +7446,12 @@ static int tg3_halt_cpu(struct tg3 *tp, + return -ENODEV; + } + +- /* Clear firmware's nvram arbitration. */ +- if (tg3_flag(tp, NVRAM)) +- tw32(NVRAM_SWARB, SWARB_REQ_CLR0); ++ if (!tg3_flag(tp, IS_SSB_CORE)) { ++ /* Clear firmware's nvram arbitration. */ ++ if (tg3_flag(tp, NVRAM)) ++ tw32(NVRAM_SWARB, SWARB_REQ_CLR0); ++ } ++ + return 0; + } + +@@ -7472,6 +7513,11 @@ static int tg3_load_5701_a0_firmware_fix + const __be32 *fw_data; + int err, i; + ++ if (tg3_flag(tp, IS_SSB_CORE)) { ++ /* We don't use firmware. */ ++ return 0; ++ } ++ + fw_data = (void *)tp->fw->data; + + /* Firmware blob starts with version numbers, followed by +@@ -7528,6 +7574,11 @@ static int tg3_load_tso_firmware(struct + unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; + int err, i; + ++ if (tg3_flag(tp, IS_SSB_CORE)) { ++ /* We don't use firmware. */ ++ return 0; ++ } ++ + if (tg3_flag(tp, HW_TSO_1) || + tg3_flag(tp, HW_TSO_2) || + tg3_flag(tp, HW_TSO_3)) +@@ -8825,6 +8876,11 @@ static void tg3_timer(unsigned long __op + + spin_lock(&tp->lock); + ++ if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { ++ /* BCM4785: Flush posted writes from GbE to host memory. */ ++ tr32(HOSTCC_MODE); ++ } ++ + if (!tg3_flag(tp, TAGGED_STATUS)) { + /* All of this garbage is because when using non-tagged + * IRQ status the mailbox/status_block protocol the chip +@@ -10448,6 +10504,11 @@ static int tg3_test_nvram(struct tg3 *tp + if (tg3_flag(tp, NO_NVRAM)) + return 0; + ++ if (tg3_flag(tp, IS_SSB_CORE)) { ++ /* We don't have NVRAM. */ ++ return 0; ++ } ++ + if (tg3_nvram_read(tp, 0, &magic) != 0) + return -EIO; + +@@ -11442,7 +11503,7 @@ static int tg3_ioctl(struct net_device * + return -EAGAIN; + + spin_lock_bh(&tp->lock); +- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); ++ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval); + spin_unlock_bh(&tp->lock); + + data->val_out = mii_regval; +@@ -11458,7 +11519,7 @@ static int tg3_ioctl(struct net_device * + return -EAGAIN; + + spin_lock_bh(&tp->lock); +- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); ++ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); + spin_unlock_bh(&tp->lock); + + return err; +@@ -12188,6 +12249,13 @@ static void __devinit tg3_get_5720_nvram + /* Chips other than 5700/5701 use the NVRAM for fetching info. */ + static void __devinit tg3_nvram_init(struct tg3 *tp) + { ++ if (tg3_flag(tp, IS_SSB_CORE)) { ++ /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */ ++ tg3_flag_clear(tp, NVRAM); ++ tg3_flag_clear(tp, NVRAM_BUFFERED); ++ return; ++ } ++ + tw32_f(GRC_EEPROM_ADDR, + (EEPROM_ADDR_FSM_RESET | + (EEPROM_DEFAULT_CLOCK_PERIOD << +@@ -12454,6 +12522,9 @@ static int tg3_nvram_write_block(struct + { + int ret; + ++ if (tg3_flag(tp, IS_SSB_CORE)) ++ return -ENODEV; ++ + if (tg3_flag(tp, EEPROM_WRITE_PROT)) { + tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & + ~GRC_LCLCTRL_GPIO_OUTPUT1); +@@ -13863,6 +13934,11 @@ static int __devinit tg3_get_invariants( + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) + tg3_flag_set(tp, SRAM_USE_CONFIG); + ++ if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { ++ tp->write32_tx_mbox = tg3_write_flush_reg32; ++ tp->write32_rx_mbox = tg3_write_flush_reg32; ++ } ++ + /* Get eeprom hw config before calling tg3_set_power_state(). + * In particular, the TG3_FLAG_IS_NIC flag must be + * determined before calling tg3_set_power_state() so that +@@ -14274,6 +14350,8 @@ static int __devinit tg3_get_device_addr + } + + if (!is_valid_ether_addr(&dev->dev_addr[0])) { ++ if (tg3_flag(tp, IS_SSB_CORE)) ++ ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); + #ifdef CONFIG_SPARC + if (!tg3_get_default_macaddr_sparc(tp)) + return 0; +@@ -14772,6 +14850,7 @@ static char * __devinit tg3_phy_string(s + case TG3_PHY_ID_BCM5704: return "5704"; + case TG3_PHY_ID_BCM5705: return "5705"; + case TG3_PHY_ID_BCM5750: return "5750"; ++ case TG3_PHY_ID_BCM5750_2: return "5750-2"; + case TG3_PHY_ID_BCM5752: return "5752"; + case TG3_PHY_ID_BCM5714: return "5714"; + case TG3_PHY_ID_BCM5780: return "5780"; +@@ -14961,6 +15040,13 @@ static int __devinit tg3_init_one(struct + tp->msg_enable = tg3_debug; + else + tp->msg_enable = TG3_DEF_MSG_ENABLE; ++ if (pdev_is_ssb_gige_core(pdev)) { ++ tg3_flag_set(tp, IS_SSB_CORE); ++ if (ssb_gige_must_flush_posted_writes(pdev)) ++ tg3_flag_set(tp, FLUSH_POSTED_WRITES); ++ if (ssb_gige_have_roboswitch(pdev)) ++ tg3_flag_set(tp, ROBOSWITCH); ++ } + + /* The word/byte swap controls here control register access byte + * swapping. DMA data byte swapping is controlled in the GRC_MODE +--- a/drivers/net/tg3.h ++++ b/drivers/net/tg3.h +@@ -2901,6 +2901,9 @@ enum TG3_FLAGS { + TG3_FLAG_57765_PLUS, + TG3_FLAG_APE_HAS_NCSI, + TG3_FLAG_5717_PLUS, ++ TG3_FLAG_IS_SSB_CORE, ++ TG3_FLAG_FLUSH_POSTED_WRITES, ++ TG3_FLAG_ROBOSWITCH, + + /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ + TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ +@@ -3051,6 +3054,7 @@ struct tg3 { + #define TG3_PHY_ID_BCM5704 0x60008190 + #define TG3_PHY_ID_BCM5705 0x600081a0 + #define TG3_PHY_ID_BCM5750 0x60008180 ++#define TG3_PHY_ID_BCM5750_2 0xbc050cd0 + #define TG3_PHY_ID_BCM5752 0x60008100 + #define TG3_PHY_ID_BCM5714 0x60008340 + #define TG3_PHY_ID_BCM5780 0x60008350 +@@ -3088,7 +3092,7 @@ struct tg3 { + (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ + (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ + (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ +- (X) == TG3_PHY_ID_BCM8002) ++ (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2) + + u32 phy_flags; + #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 |