diff options
| author | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-02-16 09:23:15 +0000 |
|---|---|---|
| committer | nbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-02-16 09:23:15 +0000 |
| commit | 6869d66ad6e8d662dc124fc9103566cb1bd7454a (patch) | |
| tree | a876d1a91d12fc5c15d05d7ec65dbf21430bcacc /target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h | |
| parent | ee43602dd36fa25bf6e539f6fb89c0192fa9517d (diff) | |
major cleanup of the ar531x code, improved hardware detection and support for multiple ethernet interfaces
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6307 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h')
| -rw-r--r-- | target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h index ef2df8778..c3eeed18b 100644 --- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h +++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h @@ -121,11 +121,11 @@ */ #define AR5315_SREV (AR5315_DSLBASE + 0x0014) -#define REV_MAJ 0x00f0 -#define REV_MAJ_S 4 -#define REV_MIN 0x000f -#define REV_MIN_S 0 -#define REV_CHIP (REV_MAJ|REV_MIN) +#define AR5315_REV_MAJ 0x00f0 +#define AR5315_REV_MAJ_S 4 +#define AR5315_REV_MIN 0x000f +#define AR5315_REV_MIN_S 0 +#define AR5315_REV_CHIP (AR5315_REV_MAJ|AR5315_REV_MIN) /* * Interface Enable @@ -359,21 +359,21 @@ #define AR5315_PCICLK (AR5315_DSLBASE + 0x00a4) -#define PCICLK_INPUT_M 0x3 -#define PCICLK_INPUT_S 0 +#define AR5315_PCICLK_INPUT_M 0x3 +#define AR5315_PCICLK_INPUT_S 0 -#define PCICLK_PLLC_CLKM 0 -#define PCICLK_PLLC_CLKM1 1 -#define PCICLK_PLLC_CLKC 2 -#define PCICLK_REF_CLK 3 +#define AR5315_PCICLK_PLLC_CLKM 0 +#define AR5315_PCICLK_PLLC_CLKM1 1 +#define AR5315_PCICLK_PLLC_CLKC 2 +#define AR5315_PCICLK_REF_CLK 3 -#define PCICLK_DIV_M 0xc -#define PCICLK_DIV_S 2 +#define AR5315_PCICLK_DIV_M 0xc +#define AR5315_PCICLK_DIV_S 2 -#define PCICLK_IN_FREQ 0 -#define PCICLK_IN_FREQ_DIV_6 1 -#define PCICLK_IN_FREQ_DIV_8 2 -#define PCICLK_IN_FREQ_DIV_10 3 +#define AR5315_PCICLK_IN_FREQ 0 +#define AR5315_PCICLK_IN_FREQ_DIV_6 1 +#define AR5315_PCICLK_IN_FREQ_DIV_8 2 +#define AR5315_PCICLK_IN_FREQ_DIV_10 3 /* * Observation Control Register |