summaryrefslogtreecommitdiffstats
path: root/target/linux/ar71xx
diff options
context:
space:
mode:
authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2010-11-12 18:50:47 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2010-11-12 18:50:47 +0000
commit6be076283d2e559a33f5744b420c30d56f9930d6 (patch)
treef42f8520f59039ca4bf4177e1cef6325300d7de0 /target/linux/ar71xx
parentb6dbd839010e50246278038736b43b54a5da95a6 (diff)
ar71xx: fix trailing statements location
Signed-off-by: Arnaud Lacombe <lacombar@gmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23976 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c6
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c6
2 files changed, 8 insertions, 4 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c b/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
index 5d05562de..6c88985cc 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
@@ -157,10 +157,12 @@ EXPORT_SYMBOL_GPL(ar71xx_device_stopped);
void ar71xx_ddr_flush(u32 reg)
{
ar71xx_ddr_wr(reg, 1);
- while ((ar71xx_ddr_rr(reg) & 0x1));
+ while ((ar71xx_ddr_rr(reg) & 0x1))
+ ;
ar71xx_ddr_wr(reg, 1);
- while ((ar71xx_ddr_rr(reg) & 0x1));
+ while ((ar71xx_ddr_rr(reg) & 0x1))
+ ;
}
EXPORT_SYMBOL_GPL(ar71xx_ddr_flush);
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c b/target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c
index 4661d970b..76f69c562 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c
@@ -23,8 +23,10 @@
void prom_putchar(unsigned char ch)
{
- while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);
+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0)
+ ;
UART_WRITE(UART_TX, ch);
- while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);
+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0)
+ ;
}