diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-10-05 06:29:44 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2008-10-05 06:29:44 +0000 |
commit | 57e12bbb2422c82e434ba538e79c27f8579b369a (patch) | |
tree | c17739e99e21c1eb5f23ac66ec352a407dcba694 /target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch | |
parent | c2a8c2411892e04339828b499c6f63f5dee03ba7 (diff) |
[ar71xx] experimental support for 2.6.27
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12859 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch new file mode 100644 index 000000000..bdf0d0fb6 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch @@ -0,0 +1,65 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -13,6 +13,22 @@ + #include <asm/smtc_ipi.h> + #include <asm/time.h> + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -28,6 +44,7 @@ + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + #ifdef CONFIG_MIPS_MT_SMTC + evpe(vpflags); +@@ -187,7 +204,7 @@ + */ + if (c0_compare_int_pending()) { + write_c0_compare(read_c0_count()); +- irq_disable_hazard(); ++ compare_change_hazard(); + if (c0_compare_int_pending()) + return 0; + } +@@ -196,7 +213,7 @@ + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); +- irq_disable_hazard(); ++ compare_change_hazard(); + if ((int)(read_c0_count() - cnt) < 0) + break; + /* increase delta if the timer was already expired */ +@@ -205,11 +222,12 @@ + while ((int)(read_c0_count() - cnt) <= 0) + ; /* Wait for expiry */ + ++ compare_change_hazard(); + if (!c0_compare_int_pending()) + return 0; + + write_c0_compare(read_c0_count()); +- irq_disable_hazard(); ++ compare_change_hazard(); + if (c0_compare_int_pending()) + return 0; + |