ar71xx: use ar933x_uart.h in the AR933X serial driver

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27166 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 75 insertions, 339 deletions

diff --git a/target/linux/ar71xx/files/drivers/serial/ar933x_uart.c b/target/linux/ar71xx/files/drivers/serial/ar933x_uart.c
index ff0170fbb..66925c99b 100644
--- a/target/linux/ar71xx/files/drivers/serial/ar933x_uart.c
+++ b/target/linux/ar71xx/files/drivers/serial/ar933x_uart.c
@@ -38,6 +38,7 @@
 #include <linux/mutex.h>
 #include <linux/slab.h>
 
+#include <asm/mach-ar71xx/ar933x_uart.h>
 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
 
 #include <asm/io.h>
@@ -52,271 +53,6 @@
 #define AR933X_UART_FIFO_SIZE	16
 
 /*
- * Uart block
- */
-#define UARTDATA_UARTTXCSR_MSB			9
-#define UARTDATA_UARTTXCSR_LSB			9
-#define UARTDATA_UARTTXCSR_MASK			0x00000200
-#define UARTDATA_UARTTXCSR_GET(x)		(((x) & UARTDATA_UARTTXCSR_MASK) >> UARTDATA_UARTTXCSR_LSB)
-#define UARTDATA_UARTTXCSR_SET(x)		(((0 | (x)) << UARTDATA_UARTTXCSR_LSB) & UARTDATA_UARTTXCSR_MASK)
-#define UARTDATA_UARTTXCSR_RESET		0
-#define UARTDATA_UARTRXCSR_MSB			8
-#define UARTDATA_UARTRXCSR_LSB			8
-#define UARTDATA_UARTRXCSR_MASK			0x00000100
-#define UARTDATA_UARTRXCSR_GET(x)		(((x) & UARTDATA_UARTRXCSR_MASK) >> UARTDATA_UARTRXCSR_LSB)
-#define UARTDATA_UARTRXCSR_SET(x)		(((0 | (x)) << UARTDATA_UARTRXCSR_LSB) & UARTDATA_UARTRXCSR_MASK)
-#define UARTDATA_UARTRXCSR_RESET		0
-#define UARTDATA_UARTTXRXDATA_MSB		7
-#define UARTDATA_UARTTXRXDATA_LSB		0
-#define UARTDATA_UARTTXRXDATA_MASK		0x000000ff
-#define UARTDATA_UARTTXRXDATA_GET(x)		(((x) & UARTDATA_UARTTXRXDATA_MASK) >> UARTDATA_UARTTXRXDATA_LSB)
-#define UARTDATA_UARTTXRXDATA_SET(x)		(((0 | (x)) << UARTDATA_UARTTXRXDATA_LSB) & UARTDATA_UARTTXRXDATA_MASK)
-#define UARTDATA_UARTTXRXDATA_RESET		0
-#define UARTDATA_ADDRESS			0x0000
-#define UARTDATA_HW_MASK			0x000003ff
-#define UARTDATA_SW_MASK			0x000003ff
-#define UARTDATA_RSTMASK			0x000003ff
-#define UARTDATA_RESET				0x00000000
-
-// 0x0004 (UARTCS)
-#define UARTCS_UARTRXBUSY_MSB			15
-#define UARTCS_UARTRXBUSY_LSB			15
-#define UARTCS_UARTRXBUSY_MASK			0x00008000
-#define UARTCS_UARTRXBUSY_GET(x)		(((x) & UARTCS_UARTRXBUSY_MASK) >> UARTCS_UARTRXBUSY_LSB)
-#define UARTCS_UARTRXBUSY_SET(x)		(((0 | (x)) << UARTCS_UARTRXBUSY_LSB) & UARTCS_UARTRXBUSY_MASK)
-#define UARTCS_UARTRXBUSY_RESET			0
-#define UARTCS_UARTTXBUSY_MSB			14
-#define UARTCS_UARTTXBUSY_LSB			14
-#define UARTCS_UARTTXBUSY_MASK			0x00004000
-#define UARTCS_UARTTXBUSY_GET(x)		(((x) & UARTCS_UARTTXBUSY_MASK) >> UARTCS_UARTTXBUSY_LSB)
-#define UARTCS_UARTTXBUSY_SET(x)		(((0 | (x)) << UARTCS_UARTTXBUSY_LSB) & UARTCS_UARTTXBUSY_MASK)
-#define UARTCS_UARTTXBUSY_RESET			0
-#define UARTCS_UARTHOSTINTEN_MSB		13
-#define UARTCS_UARTHOSTINTEN_LSB		13
-#define UARTCS_UARTHOSTINTEN_MASK		0x00002000
-#define UARTCS_UARTHOSTINTEN_GET(x)		(((x) & UARTCS_UARTHOSTINTEN_MASK) >> UARTCS_UARTHOSTINTEN_LSB)
-#define UARTCS_UARTHOSTINTEN_SET(x)		(((0 | (x)) << UARTCS_UARTHOSTINTEN_LSB) & UARTCS_UARTHOSTINTEN_MASK)
-#define UARTCS_UARTHOSTINTEN_RESET		0
-#define UARTCS_UARTHOSTINT_MSB			12
-#define UARTCS_UARTHOSTINT_LSB			12
-#define UARTCS_UARTHOSTINT_MASK			0x00001000
-#define UARTCS_UARTHOSTINT_GET(x)		(((x) & UARTCS_UARTHOSTINT_MASK) >> UARTCS_UARTHOSTINT_LSB)
-#define UARTCS_UARTHOSTINT_SET(x)		(((0 | (x)) << UARTCS_UARTHOSTINT_LSB) & UARTCS_UARTHOSTINT_MASK)
-#define UARTCS_UARTHOSTINT_RESET		0
-#define UARTCS_UARTTXBREAK_MSB			11
-#define UARTCS_UARTTXBREAK_LSB			11
-#define UARTCS_UARTTXBREAK_MASK			0x00000800
-#define UARTCS_UARTTXBREAK_GET(x)		(((x) & UARTCS_UARTTXBREAK_MASK) >> UARTCS_UARTTXBREAK_LSB)
-#define UARTCS_UARTTXBREAK_SET(x)		(((0 | (x)) << UARTCS_UARTTXBREAK_LSB) & UARTCS_UARTTXBREAK_MASK)
-#define UARTCS_UARTTXBREAK_RESET		0
-#define UARTCS_UARTRXBREAK_MSB			10
-#define UARTCS_UARTRXBREAK_LSB			10
-#define UARTCS_UARTRXBREAK_MASK			0x00000400
-#define UARTCS_UARTRXBREAK_GET(x)		(((x) & UARTCS_UARTRXBREAK_MASK) >> UARTCS_UARTRXBREAK_LSB)
-#define UARTCS_UARTRXBREAK_SET(x)		(((0 | (x)) << UARTCS_UARTRXBREAK_LSB) & UARTCS_UARTRXBREAK_MASK)
-#define UARTCS_UARTRXBREAK_RESET		0
-#define UARTCS_UARTSERIATXREADY_MSB		9
-#define UARTCS_UARTSERIATXREADY_LSB		9
-#define UARTCS_UARTSERIATXREADY_MASK		0x00000200
-#define UARTCS_UARTSERIATXREADY_GET(x)		(((x) & UARTCS_UARTSERIATXREADY_MASK) >> UARTCS_UARTSERIATXREADY_LSB)
-#define UARTCS_UARTSERIATXREADY_SET(x)		(((0 | (x)) << UARTCS_UARTSERIATXREADY_LSB) & UARTCS_UARTSERIATXREADY_MASK)
-#define UARTCS_UARTSERIATXREADY_RESET		0
-#define UARTCS_UARTTXREADYORIDE_MSB		8
-#define UARTCS_UARTTXREADYORIDE_LSB		8
-#define UARTCS_UARTTXREADYORIDE_MASK		0x00000100
-#define UARTCS_UARTTXREADYORIDE_GET(x)		(((x) & UARTCS_UARTTXREADYORIDE_MASK) >> UARTCS_UARTTXREADYORIDE_LSB)
-#define UARTCS_UARTTXREADYORIDE_SET(x)		(((0 | (x)) << UARTCS_UARTTXREADYORIDE_LSB) & UARTCS_UARTTXREADYORIDE_MASK)
-#define UARTCS_UARTTXREADYORIDE_RESET		0
-#define UARTCS_UARTRXREADYORIDE_MSB		7
-#define UARTCS_UARTRXREADYORIDE_LSB		7
-#define UARTCS_UARTRXREADYORIDE_MASK		0x00000080
-#define UARTCS_UARTRXREADYORIDE_GET(x)		(((x) & UARTCS_UARTRXREADYORIDE_MASK) >> UARTCS_UARTRXREADYORIDE_LSB)
-#define UARTCS_UARTRXREADYORIDE_SET(x)		(((0 | (x)) << UARTCS_UARTRXREADYORIDE_LSB) & UARTCS_UARTRXREADYORIDE_MASK)
-#define UARTCS_UARTRXREADYORIDE_RESET		0
-#define UARTCS_UARTDMAEN_MSB			6
-#define UARTCS_UARTDMAEN_LSB			6
-#define UARTCS_UARTDMAEN_MASK			0x00000040
-#define UARTCS_UARTDMAEN_GET(x)			(((x) & UARTCS_UARTDMAEN_MASK) >> UARTCS_UARTDMAEN_LSB)
-#define UARTCS_UARTDMAEN_SET(x)			(((0 | (x)) << UARTCS_UARTDMAEN_LSB) & UARTCS_UARTDMAEN_MASK)
-#define UARTCS_UARTDMAEN_RESET			0
-#define UARTCS_UARTFLOWCONTROLMODE_MSB		5
-#define UARTCS_UARTFLOWCONTROLMODE_LSB		4
-#define UARTCS_UARTFLOWCONTROLMODE_MASK		0x00000030
-#define UARTCS_UARTFLOWCONTROLMODE_GET(x)	(((x) & UARTCS_UARTFLOWCONTROLMODE_MASK) >> UARTCS_UARTFLOWCONTROLMODE_LSB)
-#define UARTCS_UARTFLOWCONTROLMODE_SET(x)	(((0 | (x)) << UARTCS_UARTFLOWCONTROLMODE_LSB) & UARTCS_UARTFLOWCONTROLMODE_MASK)
-#define UARTCS_UARTFLOWCONTROLMODE_RESET	0
-#define UARTCS_UARTINTERFACEMODE_MSB		3
-#define UARTCS_UARTINTERFACEMODE_LSB		2
-#define UARTCS_UARTINTERFACEMODE_MASK		0x0000000c
-#define UARTCS_UARTINTERFACEMODE_GET(x)		(((x) & UARTCS_UARTINTERFACEMODE_MASK) >> UARTCS_UARTINTERFACEMODE_LSB)
-#define UARTCS_UARTINTERFACEMODE_SET(x)		(((0 | (x)) << UARTCS_UARTINTERFACEMODE_LSB) & UARTCS_UARTINTERFACEMODE_MASK)
-#define UARTCS_UARTINTERFACEMODE_RESET		0
-#define UARTCS_UARTPARITYMODE_MSB		1
-#define UARTCS_UARTPARITYMODE_LSB		0
-#define UARTCS_UARTPARITYMODE_MASK		0x00000003
-#define UARTCS_UARTPARITYMODE_GET(x)		(((x) & UARTCS_UARTPARITYMODE_MASK) >> UARTCS_UARTPARITYMODE_LSB)
-#define UARTCS_UARTPARITYMODE_SET(x)		(((0 | (x)) << UARTCS_UARTPARITYMODE_LSB) & UARTCS_UARTPARITYMODE_MASK)
-#define UARTCS_UARTPARITYMODE_RESET		0
-#define UARTCS_ADDRESS				0x0004
-#define UARTCS_HW_MASK				0x0000ffff
-#define UARTCS_SW_MASK				0x0000ffff
-#define UARTCS_RSTMASK				0x000029ff
-#define UARTCS_RESET				0x00000000
-
-// 0x0008 (UARTCLOCK)
-#define UARTCLOCK_UARTCLOCKSCALE_MSB		23
-#define UARTCLOCK_UARTCLOCKSCALE_LSB		16
-#define UARTCLOCK_UARTCLOCKSCALE_MASK		0x00ff0000
-#define UARTCLOCK_UARTCLOCKSCALE_GET(x)		(((x) & UARTCLOCK_UARTCLOCKSCALE_MASK) >> UARTCLOCK_UARTCLOCKSCALE_LSB)
-#define UARTCLOCK_UARTCLOCKSCALE_SET(x)		(((0 | (x)) << UARTCLOCK_UARTCLOCKSCALE_LSB) & UARTCLOCK_UARTCLOCKSCALE_MASK)
-#define UARTCLOCK_UARTCLOCKSCALE_RESET		0
-#define UARTCLOCK_UARTCLOCKSTEP_MSB		15
-#define UARTCLOCK_UARTCLOCKSTEP_LSB		0
-#define UARTCLOCK_UARTCLOCKSTEP_MASK		0x0000ffff
-#define UARTCLOCK_UARTCLOCKSTEP_GET(x)		(((x) & UARTCLOCK_UARTCLOCKSTEP_MASK) >> UARTCLOCK_UARTCLOCKSTEP_LSB)
-#define UARTCLOCK_UARTCLOCKSTEP_SET(x)		(((0 | (x)) << UARTCLOCK_UARTCLOCKSTEP_LSB) & UARTCLOCK_UARTCLOCKSTEP_MASK)
-#define UARTCLOCK_UARTCLOCKSTEP_RESET		0
-#define UARTCLOCK_ADDRESS			0x0008
-#define UARTCLOCK_HW_MASK			0x00ffffff
-#define UARTCLOCK_SW_MASK			0x00ffffff
-#define UARTCLOCK_RSTMASK			0x00ffffff
-#define UARTCLOCK_RESET				0x00000000
-
-// 0x000c (UARTINT)
-#define UARTINT_UARTTXEMPTYINT_MSB		9
-#define UARTINT_UARTTXEMPTYINT_LSB		9
-#define UARTINT_UARTTXEMPTYINT_MASK		0x00000200
-#define UARTINT_UARTTXEMPTYINT_GET(x)		(((x) & UARTINT_UARTTXEMPTYINT_MASK) >> UARTINT_UARTTXEMPTYINT_LSB)
-#define UARTINT_UARTTXEMPTYINT_SET(x)		(((0 | (x)) << UARTINT_UARTTXEMPTYINT_LSB) & UARTINT_UARTTXEMPTYINT_MASK)
-#define UARTINT_UARTTXEMPTYINT_RESET		0
-#define UARTINT_UARTRXFULLINT_MSB		8
-#define UARTINT_UARTRXFULLINT_LSB		8
-#define UARTINT_UARTRXFULLINT_MASK		0x00000100
-#define UARTINT_UARTRXFULLINT_GET(x)		(((x) & UARTINT_UARTRXFULLINT_MASK) >> UARTINT_UARTRXFULLINT_LSB)
-#define UARTINT_UARTRXFULLINT_SET(x)		(((0 | (x)) << UARTINT_UARTRXFULLINT_LSB) & UARTINT_UARTRXFULLINT_MASK)
-#define UARTINT_UARTRXFULLINT_RESET		0
-#define UARTINT_UARTRXBREAKOFFINT_MSB		7
-#define UARTINT_UARTRXBREAKOFFINT_LSB		7
-#define UARTINT_UARTRXBREAKOFFINT_MASK		0x00000080
-#define UARTINT_UARTRXBREAKOFFINT_GET(x)	(((x) & UARTINT_UARTRXBREAKOFFINT_MASK) >> UARTINT_UARTRXBREAKOFFINT_LSB)
-#define UARTINT_UARTRXBREAKOFFINT_SET(x)	(((0 | (x)) << UARTINT_UARTRXBREAKOFFINT_LSB) & UARTINT_UARTRXBREAKOFFINT_MASK)
-#define UARTINT_UARTRXBREAKOFFINT_RESET		0
-#define UARTINT_UARTRXBREAKONINT_MSB		6
-#define UARTINT_UARTRXBREAKONINT_LSB		6
-#define UARTINT_UARTRXBREAKONINT_MASK		0x00000040
-#define UARTINT_UARTRXBREAKONINT_GET(x)		(((x) & UARTINT_UARTRXBREAKONINT_MASK) >> UARTINT_UARTRXBREAKONINT_LSB)
-#define UARTINT_UARTRXBREAKONINT_SET(x)		(((0 | (x)) << UARTINT_UARTRXBREAKONINT_LSB) & UARTINT_UARTRXBREAKONINT_MASK)
-#define UARTINT_UARTRXBREAKONINT_RESET		0
-#define UARTINT_UARTRXPARITYERRINT_MSB		5
-#define UARTINT_UARTRXPARITYERRINT_LSB		5
-#define UARTINT_UARTRXPARITYERRINT_MASK		0x00000020
-#define UARTINT_UARTRXPARITYERRINT_GET(x)	(((x) & UARTINT_UARTRXPARITYERRINT_MASK) >> UARTINT_UARTRXPARITYERRINT_LSB)
-#define UARTINT_UARTRXPARITYERRINT_SET(x)	(((0 | (x)) << UARTINT_UARTRXPARITYERRINT_LSB) & UARTINT_UARTRXPARITYERRINT_MASK)
-#define UARTINT_UARTRXPARITYERRINT_RESET	0
-#define UARTINT_UARTTXOFLOWERRINT_MSB		4
-#define UARTINT_UARTTXOFLOWERRINT_LSB		4
-#define UARTINT_UARTTXOFLOWERRINT_MASK		0x00000010
-#define UARTINT_UARTTXOFLOWERRINT_GET(x)	(((x) & UARTINT_UARTTXOFLOWERRINT_MASK) >> UARTINT_UARTTXOFLOWERRINT_LSB)
-#define UARTINT_UARTTXOFLOWERRINT_SET(x)	(((0 | (x)) << UARTINT_UARTTXOFLOWERRINT_LSB) & UARTINT_UARTTXOFLOWERRINT_MASK)
-#define UARTINT_UARTTXOFLOWERRINT_RESET		0
-#define UARTINT_UARTRXOFLOWERRINT_MSB		3
-#define UARTINT_UARTRXOFLOWERRINT_LSB		3
-#define UARTINT_UARTRXOFLOWERRINT_MASK		0x00000008
-#define UARTINT_UARTRXOFLOWERRINT_GET(x)	(((x) & UARTINT_UARTRXOFLOWERRINT_MASK) >> UARTINT_UARTRXOFLOWERRINT_LSB)
-#define UARTINT_UARTRXOFLOWERRINT_SET(x)	(((0 | (x)) << UARTINT_UARTRXOFLOWERRINT_LSB) & UARTINT_UARTRXOFLOWERRINT_MASK)
-#define UARTINT_UARTRXOFLOWERRINT_RESET		0
-#define UARTINT_UARTRXFRAMINGERRINT_MSB		2
-#define UARTINT_UARTRXFRAMINGERRINT_LSB		2
-#define UARTINT_UARTRXFRAMINGERRINT_MASK	0x00000004
-#define UARTINT_UARTRXFRAMINGERRINT_GET(x)	(((x) & UARTINT_UARTRXFRAMINGERRINT_MASK) >> UARTINT_UARTRXFRAMINGERRINT_LSB)
-#define UARTINT_UARTRXFRAMINGERRINT_SET(x)	(((0 | (x)) << UARTINT_UARTRXFRAMINGERRINT_LSB) & UARTINT_UARTRXFRAMINGERRINT_MASK)
-#define UARTINT_UARTRXFRAMINGERRINT_RESET	0
-#define UARTINT_UARTTXREADYINT_MSB		1
-#define UARTINT_UARTTXREADYINT_LSB		1
-#define UARTINT_UARTTXREADYINT_MASK		0x00000002
-#define UARTINT_UARTTXREADYINT_GET(x)		(((x) & UARTINT_UARTTXREADYINT_MASK) >> UARTINT_UARTTXREADYINT_LSB)
-#define UARTINT_UARTTXREADYINT_SET(x)		(((0 | (x)) << UARTINT_UARTTXREADYINT_LSB) & UARTINT_UARTTXREADYINT_MASK)
-#define UARTINT_UARTTXREADYINT_RESET		0
-#define UARTINT_UARTRXVALIDINT_MSB		0
-#define UARTINT_UARTRXVALIDINT_LSB		0
-#define UARTINT_UARTRXVALIDINT_MASK		0x00000001
-#define UARTINT_UARTRXVALIDINT_GET(x)		(((x) & UARTINT_UARTRXVALIDINT_MASK) >> UARTINT_UARTRXVALIDINT_LSB)
-#define UARTINT_UARTRXVALIDINT_SET(x)		(((0 | (x)) << UARTINT_UARTRXVALIDINT_LSB) & UARTINT_UARTRXVALIDINT_MASK)
-#define UARTINT_UARTRXVALIDINT_RESET		0
-#define UARTINT_ADDRESS				0x000c
-#define UARTINT_HW_MASK				0x000003ff
-#define UARTINT_SW_MASK				0x000003ff
-#define UARTINT_RSTMASK				0x000003ff
-#define UARTINT_RESET				0x00000000
-
-// 0x0010 (UARTINTEN)
-#define UARTINTEN_UARTTXEMPTYINTEN_MSB		9
-#define UARTINTEN_UARTTXEMPTYINTEN_LSB		9
-#define UARTINTEN_UARTTXEMPTYINTEN_MASK		0x00000200
-#define UARTINTEN_UARTTXEMPTYINTEN_GET(x)	(((x) & UARTINTEN_UARTTXEMPTYINTEN_MASK) >> UARTINTEN_UARTTXEMPTYINTEN_LSB)
-#define UARTINTEN_UARTTXEMPTYINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTTXEMPTYINTEN_LSB) & UARTINTEN_UARTTXEMPTYINTEN_MASK)
-#define UARTINTEN_UARTTXEMPTYINTEN_RESET	0
-#define UARTINTEN_UARTRXFULLINTEN_MSB		8
-#define UARTINTEN_UARTRXFULLINTEN_LSB		8
-#define UARTINTEN_UARTRXFULLINTEN_MASK		0x00000100
-#define UARTINTEN_UARTRXFULLINTEN_GET(x)	(((x) & UARTINTEN_UARTRXFULLINTEN_MASK) >> UARTINTEN_UARTRXFULLINTEN_LSB)
-#define UARTINTEN_UARTRXFULLINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXFULLINTEN_LSB) & UARTINTEN_UARTRXFULLINTEN_MASK)
-#define UARTINTEN_UARTRXFULLINTEN_RESET		0
-#define UARTINTEN_UARTRXBREAKOFFINTEN_MSB	7
-#define UARTINTEN_UARTRXBREAKOFFINTEN_LSB	7
-#define UARTINTEN_UARTRXBREAKOFFINTEN_MASK	0x00000080
-#define UARTINTEN_UARTRXBREAKOFFINTEN_GET(x)	(((x) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK) >> UARTINTEN_UARTRXBREAKOFFINTEN_LSB)
-#define UARTINTEN_UARTRXBREAKOFFINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXBREAKOFFINTEN_LSB) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK)
-#define UARTINTEN_UARTRXBREAKOFFINTEN_RESET	0
-#define UARTINTEN_UARTRXBREAKONINTEN_MSB	6
-#define UARTINTEN_UARTRXBREAKONINTEN_LSB	6
-#define UARTINTEN_UARTRXBREAKONINTEN_MASK	0x00000040
-#define UARTINTEN_UARTRXBREAKONINTEN_GET(x)	(((x) & UARTINTEN_UARTRXBREAKONINTEN_MASK) >> UARTINTEN_UARTRXBREAKONINTEN_LSB)
-#define UARTINTEN_UARTRXBREAKONINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXBREAKONINTEN_LSB) & UARTINTEN_UARTRXBREAKONINTEN_MASK)
-#define UARTINTEN_UARTRXBREAKONINTEN_RESET	0
-#define UARTINTEN_UARTRXPARITYERRINTEN_MSB	5
-#define UARTINTEN_UARTRXPARITYERRINTEN_LSB	5
-#define UARTINTEN_UARTRXPARITYERRINTEN_MASK	0x00000020
-#define UARTINTEN_UARTRXPARITYERRINTEN_GET(x)	(((x) & UARTINTEN_UARTRXPARITYERRINTEN_MASK) >> UARTINTEN_UARTRXPARITYERRINTEN_LSB)
-#define UARTINTEN_UARTRXPARITYERRINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXPARITYERRINTEN_LSB) & UARTINTEN_UARTRXPARITYERRINTEN_MASK)
-#define UARTINTEN_UARTRXPARITYERRINTEN_RESET	0
-#define UARTINTEN_UARTTXOFLOWERRINTEN_MSB	4
-#define UARTINTEN_UARTTXOFLOWERRINTEN_LSB	4
-#define UARTINTEN_UARTTXOFLOWERRINTEN_MASK	0x00000010
-#define UARTINTEN_UARTTXOFLOWERRINTEN_GET(x)	(((x) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTTXOFLOWERRINTEN_LSB)
-#define UARTINTEN_UARTTXOFLOWERRINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTTXOFLOWERRINTEN_LSB) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK)
-#define UARTINTEN_UARTTXOFLOWERRINTEN_RESET	0
-#define UARTINTEN_UARTRXOFLOWERRINTEN_MSB	3
-#define UARTINTEN_UARTRXOFLOWERRINTEN_LSB	3
-#define UARTINTEN_UARTRXOFLOWERRINTEN_MASK	0x00000008
-#define UARTINTEN_UARTRXOFLOWERRINTEN_GET(x)	(((x) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTRXOFLOWERRINTEN_LSB)
-#define UARTINTEN_UARTRXOFLOWERRINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXOFLOWERRINTEN_LSB) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK)
-#define UARTINTEN_UARTRXOFLOWERRINTEN_RESET	0
-#define UARTINTEN_UARTRXFRAMINGERRINTEN_MSB	2
-#define UARTINTEN_UARTRXFRAMINGERRINTEN_LSB	2
-#define UARTINTEN_UARTRXFRAMINGERRINTEN_MASK	0x00000004
-#define UARTINTEN_UARTRXFRAMINGERRINTEN_GET(x)	(((x) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK) >> UARTINTEN_UARTRXFRAMINGERRINTEN_LSB)
-#define UARTINTEN_UARTRXFRAMINGERRINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXFRAMINGERRINTEN_LSB) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK)
-#define UARTINTEN_UARTRXFRAMINGERRINTEN_RESET	0
-#define UARTINTEN_UARTTXREADYINTEN_MSB		1
-#define UARTINTEN_UARTTXREADYINTEN_LSB		1
-#define UARTINTEN_UARTTXREADYINTEN_MASK		0x00000002
-#define UARTINTEN_UARTTXREADYINTEN_GET(x)	(((x) & UARTINTEN_UARTTXREADYINTEN_MASK) >> UARTINTEN_UARTTXREADYINTEN_LSB)
-#define UARTINTEN_UARTTXREADYINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTTXREADYINTEN_LSB) & UARTINTEN_UARTTXREADYINTEN_MASK)
-#define UARTINTEN_UARTTXREADYINTEN_RESET	0
-#define UARTINTEN_UARTRXVALIDINTEN_MSB		0
-#define UARTINTEN_UARTRXVALIDINTEN_LSB		0
-#define UARTINTEN_UARTRXVALIDINTEN_MASK		0x00000001
-#define UARTINTEN_UARTRXVALIDINTEN_GET(x)	(((x) & UARTINTEN_UARTRXVALIDINTEN_MASK) >> UARTINTEN_UARTRXVALIDINTEN_LSB)
-#define UARTINTEN_UARTRXVALIDINTEN_SET(x)	(((0 | (x)) << UARTINTEN_UARTRXVALIDINTEN_LSB) & UARTINTEN_UARTRXVALIDINTEN_MASK)
-#define UARTINTEN_UARTRXVALIDINTEN_RESET	0
-#define UARTINTEN_ADDRESS			0x0010
-#define UARTINTEN_HW_MASK			0x000003ff
-#define UARTINTEN_SW_MASK			0x000003ff
-#define UARTINTEN_RSTMASK			0x000003ff
-#define UARTINTEN_RESET				0x00000000
-
-/*
  * uncomment below to enable WAR for EV81847.
  */
 //#define AR933X_EV81847_WAR
@@ -406,8 +142,8 @@ static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
 
 static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
 {
-	ar933x_uart_rmw_set(up, UARTINTEN_ADDRESS,
-			    UARTINTEN_UARTTXEMPTYINTEN_SET(1));
+	ar933x_uart_rmw_set(up, AR933X_UART_INT_EN_REG,
+			    AR933X_UART_INT_TX_EMPTY);
 }
 
 static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
@@ -416,8 +152,8 @@ static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
 		up->ier &= ~UART_IER_THRI;
 
 		/* FIXME: why this uses RXVALIDINTEN? */
-		ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
-				      UARTINTEN_UARTRXVALIDINTEN_SET(1));
+		ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG,
+				      AR933X_UART_INT_RX_VALID);
 	}
 }
 
@@ -428,10 +164,10 @@ static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
 	unsigned int rdata;
 
 	spin_lock_irqsave(&up->port.lock, flags);
-	rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
+	rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
 	spin_unlock_irqrestore(&up->port.lock, flags);
 
-	return (rdata & UARTDATA_UARTTXCSR_MASK) ? 0 : TIOCSER_TEMT;
+	return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
 }
 
 static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
@@ -464,8 +200,8 @@ static void ar933x_uart_stop_rx(struct uart_port *port)
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 
-	ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
-			      UARTINTEN_UARTRXVALIDINTEN_SET(1));
+	ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG,
+			      AR933X_UART_INT_RX_VALID);
 }
 
 static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
@@ -481,13 +217,13 @@ static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
 	else
 		up->lcr &= ~UART_LCR_SBC;
 
-	rdata = ar933x_uart_read(up, UARTCS_ADDRESS);
+	rdata = ar933x_uart_read(up, AR933X_UART_CS_REG);
 	if (up->lcr & UART_LCR_SBC)
-		rdata |= UARTCS_UARTTXBREAK_SET(1);
+		rdata |= AR933X_UART_CS_TX_BREAK;
 	else
-		rdata &= ~UARTCS_UARTTXBREAK_SET(1);
+		rdata &= ~AR933X_UART_CS_TX_BREAK;
 
-	ar933x_uart_write(up, UARTCS_ADDRESS, rdata);
+	ar933x_uart_write(up, AR933X_UART_CS_REG, rdata);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
 }
@@ -613,8 +349,8 @@ static void ar933x_uart_set_termios(struct uart_port *port,
 	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 		up->ier |= UART_IER_MSI;
 
-	ar933x_uart_rmw_set(up, UARTCS_ADDRESS,
-			    UARTCS_UARTHOSTINTEN_SET(1));
+	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+			    AR933X_UART_CS_HOST_INT_EN);
 
 	/* Save LCR */
 	up->lcr = cval;
@@ -632,13 +368,13 @@ static void ar933x_uart_rx_chars(struct ar933x_uart_port *up, int *status)
 	char flag;
 
 	do {
-		ch = (unsigned char)UARTDATA_UARTTXRXDATA_GET(lsr);
+		ch = lsr & AR933X_UART_DATA_TX_RX_MASK;
 
 		flag = TTY_NORMAL;
 		up->port.icount.rx++;
 
-		lsr = UARTDATA_UARTRXCSR_SET(1);
-		ar933x_uart_write(up, UARTDATA_ADDRESS, lsr);
+		lsr = AR933X_UART_DATA_RX_CSR;
+		ar933x_uart_write(up, AR933X_UART_DATA_REG, lsr);
 
 		if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 				    UART_LSR_FE | UART_LSR_OE))) {
@@ -683,8 +419,8 @@ static void ar933x_uart_rx_chars(struct ar933x_uart_port *up, int *status)
 		uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 
 ignore_char:
-		lsr = ar933x_uart_read(up, UARTDATA_ADDRESS);
-	} while ((lsr & UARTDATA_UARTRXCSR_MASK) && (max_count-- > 0));
+		lsr = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+	} while ((lsr & AR933X_UART_DATA_RX_CSR) && (max_count-- > 0));
 
 	spin_unlock(&up->port.lock);
 	tty_flip_buffer_push(tty);
@@ -699,16 +435,16 @@ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
 	int count;
 	unsigned int rdata;
 
-	rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
-	if (UARTDATA_UARTTXCSR_GET(rdata) == 0) {
+	rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+	if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) {
 		ar933x_uart_start_tx_interrupt(up);
 		return;
 	}
 
 	if (up->port.x_char) {
-		rdata = UARTDATA_UARTTXRXDATA_SET((unsigned int)(up->port.x_char));
-		rdata |= UARTDATA_UARTTXCSR_SET(1);
-		ar933x_uart_write(up, UARTDATA_ADDRESS, rdata);
+		rdata = up->port.x_char & AR933X_UART_DATA_TX_RX_MASK;
+		rdata |= AR933X_UART_DATA_TX_CSR;
+		ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
 		up->port.icount.tx++;
 		up->port.x_char = 0;
 		ar933x_uart_start_tx_interrupt(up);
@@ -727,15 +463,15 @@ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
 
 	count = up->port.fifosize / 4;
 	do {
-		rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
-		if (UARTDATA_UARTTXCSR_GET(rdata) == 0) {
+		rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+		if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) {
 			ar933x_uart_start_tx_interrupt(up);
 			return;
 		}
 
-		rdata = UARTDATA_UARTTXRXDATA_SET((unsigned int)(xmit->buf[xmit->tail]));
-		rdata |= UARTDATA_UARTTXCSR_SET(1);
-		ar933x_uart_write(up, UARTDATA_ADDRESS, rdata);
+		rdata = xmit->buf[xmit->tail] & AR933X_UART_DATA_TX_RX_MASK;
+		rdata |= AR933X_UART_DATA_TX_CSR;
+		ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
 
 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 		up->port.icount.tx++;
@@ -743,8 +479,8 @@ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
 			break;
 	} while (--count > 0);
 
-	rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
-	if (UARTDATA_UARTTXCSR_GET(rdata) == 0) {
+	rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+	if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) {
 		ar933x_uart_start_tx_interrupt(up);
 		return;
 	}
@@ -778,26 +514,26 @@ static inline void ar933x_uart_clear_int(struct ar933x_uart_port *up)
 	//ar7240_reg_rmw_clear(AR7240_MISC_INT_MASK, BIT3);
 
 	/* 2. clear uartcs hostinten mask, bit13 */
-	ar933x_uart_rmw_clear(up, UARTCS_ADDRESS,
-			      UARTCS_UARTHOSTINTEN_SET(1));
+	ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
+			      AR933X_UART_CS_HOST_INT_EN);
 
 	/* 3. clear rx uartint */
-	ar933x_uart_write(up, UARTINT_ADDRESS, UARTINT_UARTRXVALIDINT_SET(1));
+	ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID);
 
 	/* 4. clear misc interrupt status  */
 	ar7240_reg_rmw_clear(AR7240_MISC_INT_STATUS, BIT3);
 
 	/* 5. clear rx uartinten*/
-	ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
-			      UARTINTEN_UARTRXVALIDINTEN_SET(1));
+	ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG,
+			      AR933X_UART_INT_RX_VALID);
 
 	/* 6. enable rx int*/
-	ar933x_uart_rmw_set(up, UARTINTEN_ADDRESS,
-			    UARTINTEN_UARTRXVALIDINTEN_SET(1));
+	ar933x_uart_rmw_set(up, AR933X_UART_INT_EN_REG,
+			    AR933X_UART_INT_RX_VALID);
 
 	/* 7. set uartcs hostinten mask */
-	ar933x_uart_rmw_set(up, UARTCS_ADDRESS,
-			    UARTCS_UARTHOSTINTEN_SET(1));
+	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+			    AR933X_UART_CS_HOST_INT_EN);
 
 	/* 8. set misc int mask */
 	//ar7240_reg_wr(AR7240_MISC_INT_MASK, BIT3);
@@ -810,23 +546,23 @@ static inline void ar933x_uart_handle_port(struct ar933x_uart_port *up)
 	unsigned int en_status;
 	unsigned long flags;
 
-	status = ar933x_uart_read(up, UARTDATA_ADDRESS);
-	int_status = ar933x_uart_read(up, UARTINT_ADDRESS);
-	en_status = ar933x_uart_read(up, UARTINTEN_ADDRESS);
+	status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+	int_status = ar933x_uart_read(up, AR933X_UART_INT_REG);
+	en_status = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
 
 	spin_lock_irqsave(&up->port.lock, flags);
 
-	if( (int_status & en_status) & UARTINT_UARTRXVALIDINT_MASK )
+	if( (int_status & en_status) & AR933X_UART_INT_RX_VALID )
 		ar933x_uart_rx_chars(up, &status);
 
-	if (((int_status & en_status) & UARTINT_UARTTXEMPTYINT_MASK)) {
+	if (((int_status & en_status) & AR933X_UART_INT_TX_EMPTY)) {
 		/* clear TX empty interrupts */
-		ar933x_uart_write(up, UARTINT_ADDRESS,
-				  UARTINT_UARTTXEMPTYINT_SET(1));
+		ar933x_uart_write(up, AR933X_UART_INT_REG,
+				  AR933X_UART_INT_TX_EMPTY);
 
 		/* disable TX empty interrupts */
-		ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
-				      UARTINTEN_UARTTXEMPTYINTEN_SET(1));
+		ar933x_uart_rmw_clear(up, AR933X_UART_INT_EN_REG,
+				      AR933X_UART_INT_TX_EMPTY);
 
 		if (!uart_circ_empty(&up->port.state->xmit))
 			ar933x_uart_tx_chars(up);
@@ -842,8 +578,8 @@ static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
 
 	up = (struct ar933x_uart_port *) dev_id;
 
-	iir = ar933x_uart_read(up, UARTCS_ADDRESS);
-	if ((iir & UARTCS_UARTHOSTINT_MASK) == 0)
+	iir = ar933x_uart_read(up, AR933X_UART_CS_REG);
+	if ((iir & AR933X_UART_CS_HOST_INT) == 0)
 		return IRQ_NONE;
 
 	DEBUG_INTR("ar933x_uart_interrupt(%d)...", irq);
@@ -874,8 +610,8 @@ static void ar933x_uart_timer(unsigned long data)
 			spin_unlock_irqrestore(&up->port.lock, flags);
 		}
 	} else {
-		iir = ar933x_uart_read(up, UARTCS_ADDRESS);
-		if (iir & UARTCS_UARTHOSTINT_MASK) {
+		iir = ar933x_uart_read(up, AR933X_UART_CS_REG);
+		if (iir & AR933X_UART_CS_HOST_INT) {
 			spin_lock(&up->port.lock);
 			ar933x_uart_handle_port(up);
 			spin_unlock(&up->port.lock);
@@ -901,8 +637,8 @@ static int ar933x_uart_startup(struct uart_port *port)
 	/*
 	 * Clear the interrupt registers.
 	 */
-	ar933x_uart_read(up, UARTCS_ADDRESS);
-	ar933x_uart_read(up, UARTINT_ADDRESS);
+	ar933x_uart_read(up, AR933X_UART_CS_REG);
+	ar933x_uart_read(up, AR933X_UART_INT_REG);
 
 	if (!is_real_interrupt(up->port.irq) || ar933x_ev81847_war()) {
 		setup_timer(&up->timer, ar933x_uart_timer, (unsigned long)port);
@@ -915,20 +651,20 @@ static int ar933x_uart_startup(struct uart_port *port)
 	/*
 	 * Enable host interrupts
 	 */
-	ar933x_uart_rmw_set(up, UARTCS_ADDRESS,
-			    UARTCS_UARTHOSTINTEN_SET(1));
+	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+			    AR933X_UART_CS_HOST_INT_EN);
 
 	/*
 	 * Enable RX interrupts
 	 */
 	up->ier = UART_IER_RLSI | UART_IER_RDI;
-	ar933x_uart_write(up, UARTINTEN_ADDRESS,
-			  UARTINTEN_UARTRXVALIDINTEN_SET(1));
+	ar933x_uart_write(up, AR933X_UART_INT_EN_REG,
+			  AR933X_UART_INT_RX_VALID);
 
 	/*
 	 * And clear the interrupt registers again for luck.
 	 */
-	ar933x_uart_read(up, UARTINT_ADDRESS);
+	ar933x_uart_read(up, AR933X_UART_INT_REG);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
 
@@ -944,7 +680,7 @@ static void ar933x_uart_shutdown(struct uart_port *port)
 	 * Disable all interrupts from this port
 	 */
 	up->ier = 0;
-	ar933x_uart_write(up, UARTINTEN_ADDRESS, 0);
+	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
 
 	spin_lock_irqsave(&up->port.lock, flags);
 	up->port.mctrl &= ~TIOCM_OUT2;
@@ -954,8 +690,8 @@ static void ar933x_uart_shutdown(struct uart_port *port)
 	/*
 	 * Disable break condition
 	 */
-	ar933x_uart_rmw_clear(up, UARTCS_ADDRESS,
-			      UARTCS_UARTTXBREAK_SET(1));
+	ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
+			      AR933X_UART_CS_TX_BREAK);
 
 	if (!is_real_interrupt(up->port.irq) ||
 	    ar933x_ev81847_war())
@@ -987,9 +723,9 @@ static void ar933x_uart_config_port(struct uart_port *port, int flags)
 	port->type = PORT_AR933X;
 
 	/* Clear mask, so no surprise interrupts. */
-	ar933x_uart_read(up, UARTCS_ADDRESS);
+	ar933x_uart_read(up, AR933X_UART_CS_REG);
 	/* Clear interrupts status register */
-	ar933x_uart_read(up, UARTINT_ADDRESS);
+	ar933x_uart_read(up, AR933X_UART_INT_REG);
 }
 
 static int ar933x_uart_verify_port(struct uart_port *port,
@@ -1028,11 +764,11 @@ static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
 
 	/* Wait up to 60ms for the character(s) to be sent. */
 	do {
-		status = ar933x_uart_read(up, UARTDATA_ADDRESS);
+		status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
 		if (--timeout == 0)
 			break;
 		udelay(1);
-	} while (UARTDATA_UARTTXCSR_GET(status) == 0);
+	} while ((status & AR933X_UART_DATA_TX_CSR) == 0);
 }
 
 static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
@@ -1042,9 +778,9 @@ static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
 
 	ar933x_uart_wait_xmitr(up);
 
-	rdata = UARTDATA_UARTTXRXDATA_SET(ch) |
-	        UARTDATA_UARTTXCSR_SET(1);
-	ar933x_uart_write(up, UARTDATA_ADDRESS, rdata);
+	rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
+	rdata |= AR933X_UART_DATA_TX_CSR;
+	ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
 }
 
 static void ar933x_uart_console_write(struct console *co, const char *s,
@@ -1067,8 +803,8 @@ static void ar933x_uart_console_write(struct console *co, const char *s,
 	/*
 	 * First save the IER then disable the interrupts
 	 */
-	ier = ar933x_uart_read(up, UARTINTEN_ADDRESS);
-	ar933x_uart_write(up, UARTINTEN_ADDRESS, 0);
+	ier = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
+	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
 
 	uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
 
@@ -1078,8 +814,8 @@ static void ar933x_uart_console_write(struct console *co, const char *s,
 	 */
 	ar933x_uart_wait_xmitr(up);
 
-	ar933x_uart_write(up, UARTINTEN_ADDRESS, ier);
-	ar933x_uart_write(up, UARTINT_ADDRESS, UARTINT_RSTMASK);
+	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, ier);
+	ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
 
 	if (locked)
 		spin_unlock(&up->port.lock);