surprise :p

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11894 3c298f89-4303-0410-b956-a3cf2f4a3e73

6 files changed, 1641 insertions, 0 deletions

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/Kconfig b/target/linux/ar71xx/files/drivers/net/ag71xx/Kconfig
new file mode 100644
index 000000000..8105744e8
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/Kconfig
@@ -0,0 +1,7 @@
+config AG71XX
+	tristate "Atheros AR71xx built-in ethernet mac support"
+	depends on ATHEROS_AR71XX
+	select PHYLIB
+	help
+	  If you wish to compile a kernel for AR71xx/91xx and enable
+	  ethernet support, then you should always answer Y to this.
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/Makefile b/target/linux/ar71xx/files/drivers/net/ag71xx/Makefile
new file mode 100644
index 000000000..452ee36cb
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the Atheros AR71xx built-in ethernet macs
+#
+
+obj-$(CONFIG_AG71XX)	+= ag71xx.o
+
+ag71xx-objs	:= ag71xx_main.o ag71xx_mii.o ag71xx_ethtool.o
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
new file mode 100644
index 000000000..e22a7e6d3
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -0,0 +1,281 @@
+/*
+ *  Atheros AR71xx built-in ethernet mac driver
+ *
+ *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Based on Atheros' AG7100 driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AG71XX_H
+#define __AG71XX_H
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/bitops.h>
+
+#include <asm/mach-ar71xx/ar71xx.h>
+#include <asm/mach-ar71xx/platform.h>
+
+#define ETH_FCS_LEN	4
+
+#define AG71XX_DRV_NAME		"ag71xx"
+#define AG71XX_DRV_VERSION	"0.3.9"
+
+#define AG71XX_NAPI_TX		1
+
+#define AG71XX_NAPI_WEIGHT	64
+
+#define AG71XX_INT_ERR	(AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
+#define AG71XX_INT_TX	(AG71XX_INT_TX_PS)
+#define AG71XX_INT_RX	(AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
+
+#ifdef AG71XX_NAPI_TX
+#define AG71XX_INT_POLL	(AG71XX_INT_RX | AG71XX_INT_TX)
+#define AG71XX_INT_INIT	(AG71XX_INT_ERR | AG71XX_INT_POLL)
+#else
+#define AG71XX_INT_POLL	(AG71XX_INT_RX)
+#define AG71XX_INT_INIT	(AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
+#endif
+
+#define AG71XX_TX_FIFO_LEN	2048
+#define AG71XX_TX_MTU_LEN	1536
+#define AG71XX_RX_PKT_RESERVE	64
+#define AG71XX_RX_PKT_SIZE	\
+	(AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
+
+#define AG71XX_TX_RING_SIZE	64
+#define AG71XX_TX_THRES_STOP	(AG71XX_TX_RING_SIZE - 4)
+#define AG71XX_TX_THRES_WAKEUP	\
+		(AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
+
+#define AG71XX_RX_RING_SIZE	128
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(fmt, args...)	printk(KERN_DEBUG fmt, ## args)
+#else
+#define DBG(fmt, args...)	do {} while (0)
+#endif
+
+#define ag71xx_assert(_cond)						\
+do {									\
+	if (_cond)							\
+		break;							\
+	printk("%s,%d: assertion failed\n", __FILE__, __LINE__);	\
+	BUG();								\
+} while (0)
+
+struct ag71xx_desc {
+	u32	data;
+	u32	ctrl;
+#define DESC_EMPTY	BIT(31)
+#define DESC_MORE	BIT(24)
+#define DESC_PKTLEN_M	0x1fff
+	u32	next;
+};
+
+struct ag71xx_buf {
+	struct sk_buff	*skb;
+};
+
+struct ag71xx_ring {
+	struct ag71xx_buf	*buf;
+	struct ag71xx_desc	*descs;
+	dma_addr_t		descs_dma;
+	unsigned int		curr;
+	unsigned int		dirty;
+	unsigned int		size;
+};
+
+struct ag71xx {
+	void __iomem		*mac_base;
+	void __iomem		*mii_ctrl;
+
+	spinlock_t		lock;
+	struct platform_device	*pdev;
+	struct net_device	*dev;
+	struct napi_struct	napi;
+
+	struct ag71xx_ring	rx_ring;
+	struct ag71xx_ring	tx_ring;
+
+	struct phy_device	*phy_dev;
+	struct mii_bus		mii_bus;
+
+	unsigned int		link;
+	unsigned int		speed;
+	int 			duplex;
+};
+
+extern struct ethtool_ops ag71xx_ethtool_ops;
+
+extern int ag71xx_mdio_init(struct ag71xx *ag, int id);
+extern void ag71xx_mdio_cleanup(struct ag71xx *ag);
+extern int ag71xx_mii_peek(struct ag71xx *ag);
+extern void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if);
+extern void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, unsigned int speed);
+extern void ag71xx_link_update(struct ag71xx *ag);
+
+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
+{
+	return ag->pdev->dev.platform_data;
+}
+
+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
+{
+	__raw_writel(value, ag->mac_base + reg);
+}
+
+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
+{
+	return __raw_readl(ag->mac_base + reg);
+}
+
+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
+{
+	void __iomem *r = ag->mac_base + reg;
+
+	__raw_writel(__raw_readl(r) | mask, r);
+}
+
+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
+{
+	void __iomem *r = ag->mac_base + reg;
+
+	__raw_writel(__raw_readl(r) & ~mask, r);
+}
+
+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
+{
+	return ((desc->ctrl & DESC_EMPTY) != 0);
+}
+
+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
+{
+	return (desc->ctrl & DESC_PKTLEN_M);
+}
+
+/* Register offsets */
+#define AG71XX_REG_MAC_CFG1	0x0000
+#define AG71XX_REG_MAC_CFG2	0x0004
+#define AG71XX_REG_MAC_IPG	0x0008
+#define AG71XX_REG_MAC_HDX	0x000c
+#define AG71XX_REG_MAC_MFL	0x0010
+#define AG71XX_REG_MII_CFG	0x0020
+#define AG71XX_REG_MII_CMD	0x0024
+#define AG71XX_REG_MII_ADDR	0x0028
+#define AG71XX_REG_MII_CTRL	0x002c
+#define AG71XX_REG_MII_STATUS	0x0030
+#define AG71XX_REG_MII_IND	0x0034
+#define AG71XX_REG_MAC_IFCTL	0x0038
+#define AG71XX_REG_MAC_ADDR1	0x0040
+#define AG71XX_REG_MAC_ADDR2	0x0044
+#define AG71XX_REG_FIFO_CFG0	0x0048
+#define AG71XX_REG_FIFO_CFG1	0x004c
+#define AG71XX_REG_FIFO_CFG2	0x0050
+#define AG71XX_REG_FIFO_CFG3	0x0054
+#define AG71XX_REG_FIFO_CFG4	0x0058
+#define AG71XX_REG_FIFO_CFG5	0x005c
+#define AG71XX_REG_FIFO_RAM0	0x0060
+#define AG71XX_REG_FIFO_RAM1	0x0064
+#define AG71XX_REG_FIFO_RAM2	0x0068
+#define AG71XX_REG_FIFO_RAM3	0x006c
+#define AG71XX_REG_FIFO_RAM4	0x0070
+#define AG71XX_REG_FIFO_RAM5	0x0074
+#define AG71XX_REG_FIFO_RAM6	0x0078
+#define AG71XX_REG_FIFO_RAM7	0x007c
+
+#define AG71XX_REG_TX_CTRL	0x0180
+#define AG71XX_REG_TX_DESC	0x0184
+#define AG71XX_REG_TX_STATUS	0x0188
+#define AG71XX_REG_RX_CTRL	0x018c
+#define AG71XX_REG_RX_DESC	0x0190
+#define AG71XX_REG_RX_STATUS	0x0194
+#define AG71XX_REG_INT_ENABLE	0x0198
+#define AG71XX_REG_INT_STATUS	0x019c
+
+#define MAC_CFG1_TXE		BIT(0)
+#define MAC_CFG1_STX		BIT(1)
+#define MAC_CFG1_RXE		BIT(2)
+#define MAC_CFG1_SRX		BIT(3)
+#define MAC_CFG1_LB		BIT(8)
+#define MAC_CFG1_SR		BIT(31)
+
+#define MAC_CFG2_FDX		BIT(0)
+#define MAC_CFG2_CRC_EN		BIT(1)
+#define MAC_CFG2_PAD_CRC_EN	BIT(2)
+#define MAC_CFG2_LEN_CHECK	BIT(4)
+#define MAC_CFG2_HUGE_FRAME_EN	BIT(5)
+#define MAC_CFG2_IF_1000	BIT(9)
+#define MAC_CFG2_IF_10_100	BIT(8)
+
+#define AG71XX_INT_TX_PS	BIT(0)
+#define AG71XX_INT_TX_UR	BIT(1)
+#define AG71XX_INT_TX_BE	BIT(3)
+#define AG71XX_INT_RX_PR	BIT(4)
+#define AG71XX_INT_RX_OF	BIT(6)
+#define AG71XX_INT_RX_BE	BIT(7)
+
+#define MAC_IFCTL_SPEED		BIT(16)
+
+#define MII_CFG_CLK_DIV_4	0
+#define MII_CFG_CLK_DIV_6	2
+#define MII_CFG_CLK_DIV_8	3
+#define MII_CFG_CLK_DIV_10	4
+#define MII_CFG_CLK_DIV_14	5
+#define MII_CFG_CLK_DIV_20	6
+#define MII_CFG_CLK_DIV_28	7
+
+#define MII_CMD_WRITE		0x0
+#define MII_CMD_READ		0x1
+#define MII_ADDR_S		8
+#define MII_IND_BUSY		BIT(0)
+#define MII_IND_INVALID		BIT(2)
+
+#define TX_CTRL_TXE		BIT(0)
+
+#define TX_STATUS_PS		BIT(0)
+#define TX_STATUS_UR		BIT(1)
+#define TX_STATUS_BE		BIT(3)
+
+#define RX_CTRL_RXE		BIT(0)
+
+#define RX_STATUS_PR		BIT(0)
+#define RX_STATUS_OF		BIT(1)
+#define RX_STATUS_BE		BIT(3)
+
+#define FIFO_CFG5_BYTE_PER_CLK	BIT(19)
+
+#define MII_CTRL_SPEED_S	4
+#define MII_CTRL_SPEED_M	3
+#define MII_CTRL_SPEED_10	0
+#define MII_CTRL_SPEED_100	1
+#define MII_CTRL_SPEED_1000	2
+
+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
+{
+	ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
+}
+
+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
+{
+	ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
+}
+
+#endif /* _AG71XX_H */
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ethtool.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ethtool.c
new file mode 100644
index 000000000..9aa7b3a23
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ethtool.c
@@ -0,0 +1,55 @@
+/*
+ *  Atheros AR71xx built-in ethernet mac driver
+ *
+ *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Based on Atheros' AG7100 driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+static int ag71xx_ethtool_get_settings(struct net_device *dev,
+				       struct ethtool_cmd *cmd)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+	struct phy_device *phydev = ag->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int ag71xx_ethtool_set_settings(struct net_device *dev,
+				       struct ethtool_cmd *cmd)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+	struct phy_device *phydev = ag->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static void ag71xx_ethtool_get_drvinfo(struct net_device *dev,
+				       struct ethtool_drvinfo *info)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+
+	strcpy(info->driver, ag->pdev->dev.driver->name);
+	strcpy(info->version, AG71XX_DRV_VERSION);
+	strcpy(info->bus_info, ag->pdev->dev.bus_id);
+}
+
+struct ethtool_ops ag71xx_ethtool_ops = {
+	.set_settings	= ag71xx_ethtool_set_settings,
+	.get_settings	= ag71xx_ethtool_get_settings,
+	.get_drvinfo	= ag71xx_ethtool_get_drvinfo,
+	.get_link	= ethtool_op_get_link,
+};
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
new file mode 100644
index 000000000..d4eebda05
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
@@ -0,0 +1,855 @@
+/*
+ *  Atheros AR71xx built-in ethernet mac driver
+ *
+ *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Based on Atheros' AG7100 driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+static void ag71xx_dump_regs(struct ag71xx *ag)
+{
+	DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
+		ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
+		ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
+		ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
+		ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
+	DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_MII_CFG),
+		ag71xx_rr(ag, AG71XX_REG_MII_CMD),
+		ag71xx_rr(ag, AG71XX_REG_MII_ADDR));
+	DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_MII_CTRL),
+		ag71xx_rr(ag, AG71XX_REG_MII_STATUS),
+		ag71xx_rr(ag, AG71XX_REG_MII_IND));
+	DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
+		ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
+		ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
+	DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
+	DBG("%s: fifo_cfg3=%08x, fifo_cfg3=%08x, fifo_cfg5=%08x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
+}
+
+static void ag71xx_ring_free(struct ag71xx_ring *ring)
+{
+	kfree(ring->buf);
+
+	if (ring->descs)
+		dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
+				  ring->descs, ring->descs_dma);
+}
+
+static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
+{
+	int err;
+
+	ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
+					 &ring->descs_dma,
+					 GFP_ATOMIC);
+	if (!ring->descs) {
+		err = -ENOMEM;
+		goto err;
+	}
+
+	ring->size = size;
+
+	ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
+	if (!ring->buf) {
+		err = -ENOMEM;
+		goto err;
+	}
+
+	return 0;
+
+err:
+	return err;
+}
+
+static void ag71xx_ring_tx_clean(struct ag71xx *ag)
+{
+	struct ag71xx_ring *ring = &ag->tx_ring;
+	struct net_device *dev = ag->dev;
+
+	while (ring->curr != ring->dirty) {
+		u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
+
+		if (!ag71xx_desc_empty(&ring->descs[i])) {
+			ring->descs[i].ctrl = 0;
+			dev->stats.tx_errors++;
+		}
+
+		if (ring->buf[i].skb)
+			dev_kfree_skb_any(ring->buf[i].skb);
+
+		ring->buf[i].skb = NULL;
+
+		ring->dirty++;
+	}
+
+	/* flush descriptors */
+	wmb();
+
+}
+
+static void ag71xx_ring_tx_init(struct ag71xx *ag)
+{
+	struct ag71xx_ring *ring = &ag->tx_ring;
+	int i;
+
+	for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
+		ring->descs[i].next = (u32) (ring->descs_dma +
+			sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
+
+		ring->descs[i].ctrl = DESC_EMPTY;
+		ring->buf[i].skb = NULL;
+	}
+
+	/* flush descriptors */
+	wmb();
+
+	ring->curr = 0;
+	ring->dirty = 0;
+}
+
+static void ag71xx_ring_rx_clean(struct ag71xx *ag)
+{
+	struct ag71xx_ring *ring = &ag->rx_ring;
+	int i;
+
+	if (!ring->buf)
+		return;
+
+	for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
+		if (ring->buf[i].skb)
+			kfree_skb(ring->buf[i].skb);
+
+}
+
+static int ag71xx_ring_rx_init(struct ag71xx *ag)
+{
+	struct ag71xx_ring *ring = &ag->rx_ring;
+	unsigned int i;
+	int ret;
+
+	ret = 0;
+	for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
+		ring->descs[i].next = (u32) (ring->descs_dma +
+			sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
+
+	for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
+		struct sk_buff *skb;
+
+		skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
+		if (!skb) {
+			ret = -ENOMEM;
+			break;
+		}
+
+		skb->dev = ag->dev;
+		skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
+
+		ring->buf[i].skb = skb;
+		ring->descs[i].data = virt_to_phys(skb->data);
+		ring->descs[i].ctrl = DESC_EMPTY;
+	}
+
+	/* flush descriptors */
+	wmb();
+
+	ring->curr = 0;
+	ring->dirty = 0;
+
+	return ret;
+}
+
+static int ag71xx_ring_rx_refill(struct ag71xx *ag)
+{
+	struct ag71xx_ring *ring = &ag->rx_ring;
+	unsigned int count;
+
+	count = 0;
+	for (; ring->curr - ring->dirty > 0; ring->dirty++) {
+		unsigned int i;
+
+		i = ring->dirty % AG71XX_RX_RING_SIZE;
+
+		if (ring->buf[i].skb == NULL) {
+			struct sk_buff *skb;
+
+			skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
+			if (skb == NULL) {
+				printk(KERN_ERR "%s: no memory for skb\n",
+					ag->dev->name);
+				break;
+			}
+
+			skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
+			skb->dev = ag->dev;
+			ring->buf[i].skb = skb;
+			ring->descs[i].data = virt_to_phys(skb->data);
+		}
+
+		ring->descs[i].ctrl = DESC_EMPTY;
+		count++;
+	}
+
+	/* flush descriptors */
+	wmb();
+
+	DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
+
+	return count;
+}
+
+static int ag71xx_rings_init(struct ag71xx *ag)
+{
+	int ret;
+
+	ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
+	if (ret)
+		return ret;
+
+	ag71xx_ring_tx_init(ag);
+
+	ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
+	if (ret)
+		return ret;
+
+	ret = ag71xx_ring_rx_init(ag);
+	return ret;
+}
+
+static void ag71xx_rings_cleanup(struct ag71xx *ag)
+{
+	ag71xx_ring_rx_clean(ag);
+	ag71xx_ring_free(&ag->rx_ring);
+
+	ag71xx_ring_tx_clean(ag);
+	ag71xx_ring_free(&ag->tx_ring);
+}
+
+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
+{
+	u32 t;
+
+	t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
+	  | (((u32) mac[2]) << 8) | ((u32) mac[2]);
+
+	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
+
+	t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
+	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
+}
+
+#define MAC_CFG1_INIT	(MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
+			| MAC_CFG1_STX)
+
+static void ag71xx_hw_init(struct ag71xx *ag)
+{
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+	ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
+	udelay(20);
+
+	ar71xx_device_stop(pdata->reset_bit);
+	mdelay(100);
+	ar71xx_device_start(pdata->reset_bit);
+	mdelay(100);
+
+	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
+
+	/* TODO: set max packet size */
+
+	ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
+		  MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
+
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00);
+
+	ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
+
+	ag71xx_wr(ag, AG71XX_REG_MII_CFG, MII_CFG_CLK_DIV_28);
+
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
+}
+
+static void ag71xx_hw_start(struct ag71xx *ag)
+{
+	/* start RX engine */
+	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+
+	/* enable interrupts */
+	ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
+}
+
+static void ag71xx_hw_stop(struct ag71xx *ag)
+{
+	/* stop RX and TX */
+	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+
+	/* disable all interrupts */
+	ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
+}
+
+static int ag71xx_open(struct net_device *dev)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+	int ret;
+
+	ret = ag71xx_rings_init(ag);
+	if (ret)
+		goto err;
+
+	napi_enable(&ag->napi);
+
+	netif_carrier_off(dev);
+	if (ag->phy_dev) {
+		phy_start(ag->phy_dev);
+	} else {
+		ag->duplex = DUPLEX_FULL;
+		ag->speed = SPEED_100;
+		ag->link = 1;
+		ag71xx_link_update(ag);
+	}
+
+	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
+	ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
+
+	ag71xx_hw_set_macaddr(ag, dev->dev_addr);
+
+	ag71xx_hw_start(ag);
+
+	netif_start_queue(dev);
+
+	return 0;
+
+err:
+	ag71xx_rings_cleanup(ag);
+	return ret;
+}
+
+static int ag71xx_stop(struct net_device *dev)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+	unsigned long flags;
+
+	spin_lock_irqsave(&ag->lock, flags);
+
+	netif_stop_queue(dev);
+
+	ag71xx_hw_stop(ag);
+
+	netif_carrier_off(dev);
+	if (ag->phy_dev) {
+		phy_stop(ag->phy_dev);
+	} else {
+		ag->duplex = -1;
+		ag->link = 0;
+		ag->speed = 0;
+		ag71xx_link_update(ag);
+	}
+
+	napi_disable(&ag->napi);
+
+	spin_unlock_irqrestore(&ag->lock, flags);
+
+	ag71xx_rings_cleanup(ag);
+
+	return 0;
+}
+
+static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+	struct ag71xx_ring *ring = &ag->tx_ring;
+	struct ag71xx_desc *desc;
+	unsigned long flags;
+	int i;
+
+	i = ring->curr % AG71XX_TX_RING_SIZE;
+	desc = &ring->descs[i];
+
+	spin_lock_irqsave(&ag->lock, flags);
+	ar71xx_ddr_flush(pdata->flush_reg);
+	spin_unlock_irqrestore(&ag->lock, flags);
+
+	if (!ag71xx_desc_empty(desc))
+		goto err_drop;
+
+	if (skb->len <= 0) {
+		DBG("%s: packet len is too small\n", ag->dev->name);
+		goto err_drop;
+	}
+
+	dma_cache_wback_inv((unsigned long)skb->data, skb->len);
+
+	ring->buf[i].skb = skb;
+
+	/* setup descriptor fields */
+	desc->data = virt_to_phys(skb->data);
+	desc->ctrl = (skb->len & DESC_PKTLEN_M);
+
+	/* flush descriptor */
+	wmb();
+
+	ring->curr++;
+	if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
+		DBG("%s: tx queue full\n", ag->dev->name);
+		netif_stop_queue(dev);
+	}
+
+	DBG("%s: packet injected into TX queue\n", ag->dev->name);
+
+	/* enable TX engine */
+	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
+
+	dev->trans_start = jiffies;
+
+	return 0;
+
+err_drop:
+	dev->stats.tx_dropped++;
+
+	dev_kfree_skb(skb);
+	return 0;
+}
+
+static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+	struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
+	struct ag71xx *ag = netdev_priv(dev);
+	int ret;
+
+	switch (cmd) {
+	case SIOCETHTOOL:
+		if (ag->phy_dev == NULL)
+			break;
+
+		spin_lock_irq(&ag->lock);
+		ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
+		spin_unlock_irq(&ag->lock);
+		return ret;
+
+	case SIOCSIFHWADDR:
+		if (copy_from_user
+			(dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
+			return -EFAULT;
+		return 0;
+
+	case SIOCGIFHWADDR:
+		if (copy_to_user
+			(ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
+			return -EFAULT;
+		return 0;
+
+	case SIOCGMIIPHY:
+	case SIOCGMIIREG:
+	case SIOCSMIIREG:
+		if (ag->phy_dev == NULL)
+			break;
+
+		return phy_mii_ioctl(ag->phy_dev, data, cmd);
+
+	default:
+		break;
+	}
+
+	return -EOPNOTSUPP;
+}
+
+static void ag71xx_tx_packets(struct ag71xx *ag)
+{
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+	struct ag71xx_ring *ring = &ag->tx_ring;
+	unsigned int sent;
+
+	DBG("%s: processing TX ring\n", ag->dev->name);
+
+#ifdef AG71XX_NAPI_TX
+	ar71xx_ddr_flush(pdata->flush_reg);
+#endif
+
+	sent = 0;
+	while (ring->dirty != ring->curr) {
+		unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
+		struct ag71xx_desc *desc = &ring->descs[i];
+		struct sk_buff *skb = ring->buf[i].skb;
+
+		if (!ag71xx_desc_empty(desc))
+			break;
+
+		ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
+
+		ag->dev->stats.tx_bytes += skb->len;
+		ag->dev->stats.tx_packets++;
+
+		dev_kfree_skb_any(skb);
+		ring->buf[i].skb = NULL;
+
+		ring->dirty++;
+		sent++;
+	}
+
+	DBG("%s: %d packets sent out\n", ag->dev->name, sent);
+
+	if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
+		netif_wake_queue(ag->dev);
+
+}
+
+static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
+{
+	struct net_device *dev = ag->dev;
+	struct ag71xx_ring *ring = &ag->rx_ring;
+#ifndef AG71XX_NAPI_TX
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+	unsigned long flags;
+#endif
+	int done = 0;
+
+#ifndef AG71XX_NAPI_TX
+	spin_lock_irqsave(&ag->lock, flags);
+	ar71xx_ddr_flush(pdata->flush_reg);
+	spin_unlock_irqrestore(&ag->lock, flags);
+#endif
+
+	DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
+			dev->name, limit, ring->curr, ring->dirty);
+
+	while (done < limit) {
+		unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
+		struct ag71xx_desc *desc = &ring->descs[i];
+		struct sk_buff *skb;
+		int pktlen;
+
+		if (ag71xx_desc_empty(desc))
+			break;
+
+		if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
+			ag71xx_assert(0);
+			break;
+		}
+
+		skb = ring->buf[i].skb;
+		pktlen = ag71xx_desc_pktlen(desc);
+		pktlen -= ETH_FCS_LEN;
+
+		/* TODO: move it into the refill function */
+		dma_cache_wback_inv((unsigned long)skb->data, pktlen);
+		skb_put(skb, pktlen);
+
+		skb->dev = dev;
+		skb->protocol = eth_type_trans(skb, dev);
+		skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+		netif_receive_skb(skb);
+
+		dev->last_rx = jiffies;
+		dev->stats.rx_packets++;
+		dev->stats.rx_bytes += pktlen;
+
+		ring->buf[i].skb = NULL;
+		done++;
+
+		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+
+		ring->curr++;
+		if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
+			ag71xx_ring_rx_refill(ag);
+	}
+
+	ag71xx_ring_rx_refill(ag);
+
+	DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
+		dev->name, ring->curr, ring->dirty, done);
+
+	return done;
+}
+
+static int ag71xx_poll(struct napi_struct *napi, int limit)
+{
+	struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
+#ifdef AG71XX_NAPI_TX
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+#endif
+	struct net_device *dev = ag->dev;
+	unsigned long flags;
+	u32 status;
+	int done;
+
+#ifdef AG71XX_NAPI_TX
+	ar71xx_ddr_flush(pdata->flush_reg);
+	ag71xx_tx_packets(ag);
+#endif
+
+	DBG("%s: processing RX ring\n", dev->name);
+	done = ag71xx_rx_packets(ag, limit);
+
+	/* TODO: add OOM handler */
+
+	status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
+	status &= AG71XX_INT_POLL;
+
+	if ((done < limit) && (!status)) {
+		DBG("%s: disable polling mode, done=%d, status=%x\n",
+			dev->name, done, status);
+
+		netif_rx_complete(dev, napi);
+
+		/* enable interrupts */
+		spin_lock_irqsave(&ag->lock, flags);
+		ag71xx_int_enable(ag, AG71XX_INT_POLL);
+		spin_unlock_irqrestore(&ag->lock, flags);
+		return 0;
+	}
+
+	if (status & AG71XX_INT_RX_OF) {
+		printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
+			dev->name);
+
+		/* ack interrupt */
+		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
+		/* restart RX */
+		ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+	}
+
+	DBG("%s: stay in polling mode, done=%d, status=%x\n",
+			dev->name, done, status);
+	return 1;
+}
+
+static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct ag71xx *ag = netdev_priv(dev);
+	u32 status;
+
+	status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
+	status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
+
+	if (unlikely(!status))
+		return IRQ_NONE;
+
+	if (unlikely(status & AG71XX_INT_ERR)) {
+		if (status & AG71XX_INT_TX_BE) {
+			ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
+			dev_err(&dev->dev, "TX BUS error\n");
+		}
+		if (status & AG71XX_INT_RX_BE) {
+			ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
+			dev_err(&dev->dev, "RX BUS error\n");
+		}
+	}
+
+#if 0
+	if (unlikely(status & AG71XX_INT_TX_UR)) {
+		ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
+		DBG("%s: TX underrun\n", dev->name);
+	}
+#endif
+
+#ifndef AG71XX_NAPI_TX
+	if (likely(status & AG71XX_INT_TX_PS))
+		ag71xx_tx_packets(ag);
+#endif
+
+	if (likely(status & AG71XX_INT_POLL)) {
+		ag71xx_int_disable(ag, AG71XX_INT_POLL);
+		DBG("%s: enable polling mode\n", dev->name);
+		netif_rx_schedule(dev, &ag->napi);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void ag71xx_set_multicast_list(struct net_device *dev)
+{
+	/* TODO */
+}
+
+static int __init ag71xx_probe(struct platform_device *pdev)
+{
+	static u8 default_mac[ETH_ALEN] = {0x00, 0xba, 0xdb, 0xad, 0xba, 0xd0};
+	struct net_device *dev;
+	struct resource *res;
+	struct ag71xx *ag;
+	int err;
+
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "no platform data specified\n");
+		err = -ENXIO;
+		goto err_out;
+	}
+
+	dev = alloc_etherdev(sizeof(*ag));
+	if (!dev) {
+		dev_err(&pdev->dev, "alloc_etherdev failed\n");
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	SET_NETDEV_DEV(dev, &pdev->dev);
+
+	ag = netdev_priv(dev);
+	ag->pdev = pdev;
+	ag->dev = dev;
+	spin_lock_init(&ag->lock);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
+	if (!res) {
+		dev_err(&pdev->dev, "no mac_base resource found\n");
+		err = -ENXIO;
+		goto err_out;
+	}
+
+	ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
+	if (!ag->mac_base) {
+		dev_err(&pdev->dev, "unable to ioremap mac_base\n");
+		err = -ENOMEM;
+		goto err_free_dev;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
+	if (!res) {
+		dev_err(&pdev->dev, "no mii_ctrl resource found\n");
+		err = -ENXIO;
+		goto err_unmap_base;
+	}
+
+	ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
+	if (!ag->mii_ctrl) {
+		dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
+		err = -ENOMEM;
+		goto err_unmap_base;
+	}
+
+	dev->irq = platform_get_irq(pdev, 0);
+	err = request_irq(dev->irq, ag71xx_interrupt,
+			  IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+			  dev->name, dev);
+	if (err) {
+		dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
+		goto err_unmap_mii_ctrl;
+	}
+
+	dev->base_addr = (unsigned long)ag->mac_base;
+	dev->open = ag71xx_open;
+	dev->stop = ag71xx_stop;
+	dev->hard_start_xmit = ag71xx_hard_start_xmit;
+	dev->set_multicast_list = ag71xx_set_multicast_list;
+	dev->do_ioctl = ag71xx_do_ioctl;
+	dev->ethtool_ops = &ag71xx_ethtool_ops;
+
+	netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
+
+	memcpy(dev->dev_addr, default_mac, ETH_ALEN);
+	dev->dev_addr[5] += pdev->id & 0xff;
+
+	err = register_netdev(dev);
+	if (err) {
+		dev_err(&pdev->dev, "unable to register net device\n");
+		goto err_free_irq;
+	}
+
+	printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
+	       dev->name, dev->base_addr, dev->irq);
+
+	ag71xx_dump_regs(ag);
+
+	ag71xx_hw_init(ag);
+
+	ag71xx_dump_regs(ag);
+
+	err = ag71xx_mdio_init(ag, pdev->id);
+	if (err)
+		goto err_unregister_netdev;
+
+	platform_set_drvdata(pdev, dev);
+
+	return 0;
+
+err_unregister_netdev:
+	unregister_netdev(dev);
+err_free_irq:
+	free_irq(dev->irq, dev);
+err_unmap_mii_ctrl:
+	iounmap(ag->mii_ctrl);
+err_unmap_base:
+	iounmap(ag->mac_base);
+err_free_dev:
+	kfree(dev);
+err_out:
+	platform_set_drvdata(pdev, NULL);
+	return err;
+}
+
+static int __exit ag71xx_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+
+	if (dev) {
+		struct ag71xx *ag = netdev_priv(dev);
+
+		if (ag->phy_dev)
+			phy_disconnect(ag->phy_dev);
+		ag71xx_mdio_cleanup(ag);
+		unregister_netdev(dev);
+		free_irq(dev->irq, dev);
+		iounmap(ag->mii_ctrl);
+		iounmap(ag->mac_base);
+		kfree(dev);
+		platform_set_drvdata(pdev, NULL);
+	}
+
+	return 0;
+}
+
+static struct platform_driver ag71xx_driver = {
+	.probe		= ag71xx_probe,
+	.remove		= __exit_p(ag71xx_remove),
+	.driver = {
+		.name	= AG71XX_DRV_NAME,
+	}
+};
+
+static int __init ag71xx_module_init(void)
+{
+	return platform_driver_register(&ag71xx_driver);
+}
+
+static void __exit ag71xx_module_exit(void)
+{
+	platform_driver_unregister(&ag71xx_driver);
+}
+
+module_init(ag71xx_module_init);
+module_exit(ag71xx_module_exit);
+
+MODULE_VERSION(AG71XX_DRV_VERSION);
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mii.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mii.c
new file mode 100644
index 000000000..65940d201
--- /dev/null
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_mii.c
@@ -0,0 +1,436 @@
+/*
+ *  Atheros AR71xx built-in ethernet mac driver
+ *
+ *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Based on Atheros' AG7100 driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+#define AG71XX_MII_RETRY	1000
+#define AG71XX_MII_DELAY	5
+
+static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
+{
+	__raw_writel(value, ag->mii_ctrl);
+}
+
+static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
+{
+	return __raw_readl(ag->mii_ctrl);
+}
+
+void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+	u32 t;
+
+	t = ag71xx_mii_ctrl_rr(ag);
+	t &= ~(0x3);
+	t |= (mii_if & 0x3);
+	ag71xx_mii_ctrl_wr(ag, t);
+}
+
+void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, unsigned int speed)
+{
+	u32 t;
+
+	t = ag71xx_mii_ctrl_rr(ag);
+	t &= ~(0x3 << 4);
+	t |= (speed & 0x3) << 4;
+	ag71xx_mii_ctrl_wr(ag, t);
+}
+
+static int ag71xx_mii_read(struct ag71xx *ag, int addr, int reg)
+{
+	int ret;
+	int i;
+
+	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
+			((addr & 0xff) << MII_ADDR_S) | (reg & 0xff));
+	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
+
+	i = AG71XX_MII_RETRY;
+	while (ag71xx_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
+		if (i-- == 0) {
+			printk(KERN_ERR "%s: mii_read timed out\n",
+				ag->dev->name);
+			ret = 0xffff;
+			goto out;
+		}
+		udelay(AG71XX_MII_DELAY);
+	}
+
+	ret = ag71xx_rr(ag, AG71XX_REG_MII_STATUS) & 0xffff;
+	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+
+	DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
+
+out:
+	return ret;
+}
+
+static void ag71xx_mii_write(struct ag71xx *ag, int addr, int reg, u16 val)
+{
+	int i;
+
+	DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
+
+	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
+			((addr & 0xff) << MII_ADDR_S) | (reg & 0xff));
+	ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
+
+	i = AG71XX_MII_RETRY;
+	while (ag71xx_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
+		if (i-- == 0) {
+			printk(KERN_ERR "%s: mii_write timed out\n",
+				ag->dev->name);
+			break;
+		}
+		udelay(AG71XX_MII_DELAY);
+	}
+}
+
+int ag71xx_mii_peek(struct ag71xx *ag)
+{
+	int cnt;
+	int i;
+
+	cnt = 0;
+	for (i = 0; i < PHY_MAX_ADDR; i++) {
+		u16 bmsr, id1, id2, bmcr, advert, lpa;
+
+		bmsr = ag71xx_mii_read(ag, i, MII_BMSR);
+		bmcr = ag71xx_mii_read(ag, i, MII_BMCR);
+		id1 = ag71xx_mii_read(ag, i, MII_PHYSID1);
+		id2 = ag71xx_mii_read(ag, i, MII_PHYSID2);
+		advert = ag71xx_mii_read(ag, i, MII_ADVERTISE);
+		lpa = ag71xx_mii_read(ag, i, MII_LPA);
+		DBG("%s: phy%02d bmsr=%04x, bmcr=%04x, "
+			"id=%04x.%04x, advertise=%04x, lpa=%04x\n",
+			ag->dev->name, i,
+			bmsr, bmcr, id1, id2, advert, lpa);
+
+		if ((bmsr | bmcr | id1 | id2 | advert | lpa) != 0)
+			cnt++;
+	}
+
+	return cnt;
+}
+
+#define PLL_SEC_CONFIG		0x18050004
+#define PLL_ETH0_INT_CLOCK	0x18050010
+#define PLL_ETH1_INT_CLOCK	0x18050014
+#define PLL_ETH_EXT_CLOCK	0x18050018
+
+#define ag7100_pll_shift(_ag)   (((_ag)->pdev->id) ? 19 : 17)
+#define ag7100_pll_offset(_ag)	(((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
+						   : PLL_ETH0_INT_CLOCK)
+
+static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
+{
+	void __iomem *pll_reg = ioremap_nocache(ag7100_pll_offset(ag), 4);
+	void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
+	u32 s;
+	u32 t;
+
+	s = ag7100_pll_shift(ag);
+
+	t = __raw_readl(pll_cfg);
+	t &= ~(3 << s);
+	t |=  (2 << s);
+	__raw_writel(t, pll_cfg);
+	udelay(100);
+
+	__raw_writel(pll_val, pll_reg);
+
+	t |= (3 << s);
+	__raw_writel(t, pll_cfg);
+	udelay(100);
+
+	t &= ~(3 << s);
+	__raw_writel(t, pll_cfg);
+	udelay(100);
+	DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
+			(unsigned int)pll_reg, __raw_readl(pll_reg));
+
+	iounmap(pll_cfg);
+	iounmap(pll_reg);
+}
+
+static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
+{
+	switch (ag->speed) {
+	case SPEED_1000:
+		return "1000";
+	case SPEED_100:
+		return "100";
+	case SPEED_10:
+		return "10";
+	}
+
+	return "?";
+}
+
+#if 1
+#define PLL_VAL_1000	0x00110000
+#define PLL_VAL_100	0x00001099
+#define PLL_VAL_10	0x00991099
+#else
+#define PLL_VAL_1000	0x01111000
+#define PLL_VAL_100	0x09991000
+#define PLL_VAL_10	0x09991999
+#endif
+
+void ag71xx_link_update(struct ag71xx *ag)
+{
+	u32 cfg2;
+	u32 ifctl;
+	u32 pll;
+	u32 fifo5;
+	u32 mii_speed;
+
+	if (!ag->link) {
+		netif_carrier_off(ag->dev);
+		printk(KERN_INFO "%s: link down\n", ag->dev->name);
+		return;
+	}
+
+	cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
+	cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
+	cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
+
+	ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
+	ifctl &= ~(MAC_IFCTL_SPEED);
+
+	fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
+	fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
+
+	switch (ag->speed) {
+	case SPEED_1000:
+		mii_speed =  MII_CTRL_SPEED_1000;
+		cfg2 |= MAC_CFG2_IF_1000;
+		pll = PLL_VAL_1000;
+		fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
+		break;
+	case SPEED_100:
+		mii_speed = MII_CTRL_SPEED_100;
+		cfg2 |= MAC_CFG2_IF_10_100;
+		ifctl |= MAC_IFCTL_SPEED;
+		pll = PLL_VAL_100;
+		break;
+	case SPEED_10:
+		mii_speed = MII_CTRL_SPEED_10;
+		cfg2 |= MAC_CFG2_IF_10_100;
+		pll = PLL_VAL_10;
+		break;
+	default:
+		BUG();
+		return;
+	}
+
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
+	ag71xx_set_pll(ag, pll);
+	ag71xx_mii_ctrl_set_speed(ag, mii_speed);
+
+	ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
+	ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
+
+	netif_carrier_on(ag->dev);
+	printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
+		ag->dev->name,
+		ag71xx_speed_str(ag),
+		(DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
+
+	DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
+		ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
+
+	DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n",
+		ag->dev->name,
+		ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
+		ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
+		ag71xx_mii_ctrl_rr(ag));
+}
+
+static void ag71xx_link_adjust(struct net_device *dev)
+{
+	struct ag71xx *ag = netdev_priv(dev);
+	struct phy_device *phydev = ag->phy_dev;
+	unsigned long flags;
+	int status_change = 0;
+
+	spin_lock_irqsave(&ag->lock, flags);
+
+	if (phydev->link) {
+		if (ag->duplex != phydev->duplex
+		    || ag->speed != phydev->speed) {
+			status_change = 1;
+		}
+	}
+
+	if (phydev->link != ag->link) {
+		if (phydev->link)
+			netif_schedule(dev);
+
+		status_change = 1;
+	}
+
+	ag->link = phydev->link;
+	ag->duplex = phydev->duplex;
+	ag->speed = phydev->speed;
+
+	if (status_change)
+		ag71xx_link_update(ag);
+
+	spin_unlock_irqrestore(&ag->lock, flags);
+}
+
+static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
+{
+	struct ag71xx *ag = bus->priv;
+
+	return ag71xx_mii_read(ag, addr, reg);
+}
+
+static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
+{
+	struct ag71xx *ag = bus->priv;
+
+	ag71xx_mii_write(ag, addr, reg, val);
+	return 0;
+}
+
+static int ag71xx_mdio_reset(struct mii_bus *bus)
+{
+	/* TODO */
+	return 0;
+}
+
+static int ag71xx_mdio_probe(struct ag71xx *ag)
+{
+	struct net_device *dev = ag->dev;
+	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+	struct phy_device *phydev = NULL;
+	int phy_count = 0;
+	int phy_addr;
+
+	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+		if (!(pdata->phy_mask & (1 << phy_addr)))
+			continue;
+
+		if (ag->mii_bus.phy_map[phy_addr] == NULL)
+			continue;
+
+		DBG("%s: PHY found at %s, uid=%08x\n",
+			dev->name,
+			ag->mii_bus.phy_map[phy_addr]->dev.bus_id,
+			ag->mii_bus.phy_map[phy_addr]->phy_id);
+
+		if (phydev == NULL)
+			phydev = ag->mii_bus.phy_map[phy_addr];
+
+		phy_count++;
+	}
+
+	switch (phy_count) {
+	case 0:
+		printk(KERN_ERR "%s: no PHY found\n", dev->name);
+		return -ENODEV;
+	case 1:
+		ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
+			&ag71xx_link_adjust, 0, pdata->phy_if_mode);
+
+		if (IS_ERR(ag->phy_dev)) {
+			printk(KERN_ERR "%s: could not connect to PHY at %s\n",
+				dev->name, phydev->dev.bus_id);
+			return PTR_ERR(ag->phy_dev);
+		}
+
+		/* mask with MAC supported features */
+		phydev->supported &= (SUPPORTED_10baseT_Half
+			| SUPPORTED_10baseT_Full
+			| SUPPORTED_100baseT_Half
+			| SUPPORTED_100baseT_Full
+			| SUPPORTED_Autoneg
+			| SUPPORTED_MII
+			| SUPPORTED_TP);
+
+		phydev->advertising = phydev->supported;
+
+		printk(KERN_DEBUG "%s: connected to PHY at %s "
+			"[uid=%08x, driver=%s]\n",
+			dev->name, phydev->dev.bus_id,
+			phydev->phy_id, phydev->drv->name);
+
+		ag->link = 0;
+		ag->speed = 0;
+		ag->duplex = -1;
+		break;
+	default:
+		ag->phy_dev = NULL;
+		printk(KERN_DEBUG "%s: connected to multiple PHYs (%d)\n",
+			dev->name, phy_count);
+		break;
+	}
+
+	return 0;
+}
+
+int ag71xx_mdio_init(struct ag71xx *ag, int id)
+{
+	int err;
+	int i;
+
+	ag->mii_bus.name = "ag71xx_mii";
+	ag->mii_bus.read = ag71xx_mdio_read;
+	ag->mii_bus.write = ag71xx_mdio_write;
+	ag->mii_bus.reset = ag71xx_mdio_reset;
+	ag->mii_bus.id = id;
+	ag->mii_bus.priv = ag;
+	ag->mii_bus.dev = &ag->dev->dev;
+
+	ag->mii_bus.irq = kmalloc(sizeof(*ag->mii_bus.irq) * PHY_MAX_ADDR,
+				  GFP_KERNEL);
+	if (!ag->mii_bus.irq) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		ag->mii_bus.irq[i] = PHY_POLL;
+
+	err = mdiobus_register(&ag->mii_bus);
+	if (err)
+		goto err_free_irqs;
+
+	err = ag71xx_mdio_probe(ag);
+	if (err)
+		goto err_unregister_bus;
+
+	return 0;
+
+err_unregister_bus:
+	mdiobus_unregister(&ag->mii_bus);
+err_free_irqs:
+	kfree(ag->mii_bus.irq);
+err_out:
+	return err;
+}
+
+void ag71xx_mdio_cleanup(struct ag71xx *ag)
+{
+	mdiobus_unregister(&ag->mii_bus);
+	kfree(ag->mii_bus.irq);
+}