diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-07-04 05:18:37 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2009-07-04 05:18:37 +0000 |
commit | c6263cfddc7619b031246699853200973f610ee7 (patch) | |
tree | 361b5b7cfbac6129401863d8a051f190f0a986a0 /target/linux/ar71xx/files/arch/mips/include/asm | |
parent | 868b2c94fae2a838cceee8122e31e3c7b0b2170c (diff) |
[ar71xx] fix AR7240 PCI IRQ support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16669 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include/asm')
-rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 0fc0d2066..7ce34b2cc 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -56,6 +56,13 @@ #define AR71XX_DMA_SIZE 0x10000 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) #define AR71XX_STEREO_SIZE 0x10000 + +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR724X_PCI_CRP_SIZE 0x100 + +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR91XX_WMAC_SIZE 0x30000 @@ -338,6 +345,34 @@ void ar71xx_ddr_flush(u32 reg); #define PCI_IDSEL_ADL_START 17 +#define AR7240_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN4_OFFS) +#define AR7240_PCI_CFG_SIZE 0x100 + +#define AR724X_PCI_REG_INT_STATUS 0x4c +#define AR724X_PCI_REG_INT_MASK 0x50 + +#define AR724X_PCI_INT_DEV0 BIT(14) + +static inline void ar724x_pci_wr(unsigned reg, u32 val) +{ + void __iomem *base; + + base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); + __raw_writel(val, base + reg); + iounmap(base); +} + +static inline u32 ar724x_pci_rr(unsigned reg) +{ + void __iomem *base; + u32 ret; + + base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); + ret = __raw_readl(base + reg); + iounmap(base); + return ret; +} + /* * RESET block */ |