diff options
author | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-04-07 20:52:45 +0000 |
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committer | juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-04-07 20:52:45 +0000 |
commit | a5bba4d8fbc31bd5d21bfb44400cbc2025d51e35 (patch) | |
tree | 48ea6b5e59ff76976cb7644399f411bad188ea68 /target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx | |
parent | ce4be8a009eb4f4f0c8800eecead35cae9e15335 (diff) |
ar71xx: add initial support for the AR934x SoCs
Signed-off-by: Jaiganesh Narayanan <jnarayanan@atheros.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26509 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx')
-rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 181 |
1 files changed, 179 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index ce9523d3f..0a3167862 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -1,10 +1,12 @@ /* * Atheros AR71xx SoC specific definitions * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -105,6 +107,7 @@ extern u32 ar71xx_ahb_freq; extern u32 ar71xx_cpu_freq; extern u32 ar71xx_ddr_freq; +extern u32 ar934x_ref_freq; enum ar71xx_soc_type { AR71XX_SOC_UNKNOWN, @@ -115,7 +118,10 @@ enum ar71xx_soc_type { AR71XX_SOC_AR7241, AR71XX_SOC_AR7242, AR71XX_SOC_AR9130, - AR71XX_SOC_AR9132 + AR71XX_SOC_AR9132, + AR71XX_SOC_AR9341, + AR71XX_SOC_AR9342, + AR71XX_SOC_AR9344, }; extern enum ar71xx_soc_type ar71xx_soc; @@ -167,6 +173,167 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR91XX_ETH0_PLL_SHIFT 20 #define AR91XX_ETH1_PLL_SHIFT 22 +#define AR934X_PLL_REG_CPU_CONFIG 0x00 +#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 + +#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21 +#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19 +#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000 + +#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \ + AR934X_CPU_PLL_CFG_OUTDIV_LSB) + +#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25 +#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23 +#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000 + +#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \ + AR934X_DDR_PLL_CFG_OUTDIV_LSB) + +#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \ + AR934X_DDR_PLL_CFG_OUTDIV_MASK) + +#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16 +#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12 +#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000 + +#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \ + AR934X_CPU_PLL_CFG_REFDIV_LSB) + +#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \ + (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \ + AR934X_CPU_PLL_CFG_REFDIV_MASK) + +#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2 + +#define AR934X_CPU_PLL_CFG_NINT_MSB 11 +#define AR934X_CPU_PLL_CFG_NINT_LSB 6 +#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0 + +#define AR934X_CPU_PLL_CFG_NINT_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \ + AR934X_CPU_PLL_CFG_NINT_LSB) + +#define AR934X_CPU_PLL_CFG_NINT_SET(x) \ + (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \ + AR934X_CPU_PLL_CFG_NINT_MASK) + +#define AR934X_CPU_PLL_CFG_NINT_RESET 20 + +#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5 +#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0 +#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f + +#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \ + AR934X_CPU_PLL_CFG_NFRAC_LSB) + +#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \ + (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \ + AR934X_CPU_PLL_CFG_NFRAC_MASK) + +#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20 +#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16 +#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000 + +#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \ + AR934X_DDR_PLL_CFG_REFDIV_LSB) + +#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \ + AR934X_DDR_PLL_CFG_REFDIV_MASK) + +#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2 + +#define AR934X_DDR_PLL_CFG_NINT_MSB 15 +#define AR934X_DDR_PLL_CFG_NINT_LSB 10 +#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00 + +#define AR934X_DDR_PLL_CFG_NINT_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \ + AR934X_DDR_PLL_CFG_NINT_LSB) + +#define AR934X_DDR_PLL_CFG_NINT_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \ + AR934X_DDR_PLL_CFG_NINT_MASK) + +#define AR934X_DDR_PLL_CFG_NINT_RESET 20 + +#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9 +#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0 +#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff + +#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \ + AR934X_DDR_PLL_CFG_NFRAC_LSB) + +#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \ + AR934X_DDR_PLL_CFG_NFRAC_MASK) + +#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512 + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19 +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15 +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000 + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0 + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14 +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10 +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00 + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0 + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9 +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5 +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0 + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0 + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24 +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24 +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1 + extern void __iomem *ar71xx_pll_base; static inline void ar71xx_pll_wr(unsigned reg, u32 val) @@ -385,6 +552,11 @@ void ar71xx_ddr_flush(u32 reg); #define AR724X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +/* 0 - 25MHz 1 - 40 MHz */ +#define AR934X_REF_CLK_40 (1 << 4) + #define WDOG_CTRL_LAST_RESET BIT(31) #define WDOG_CTRL_ACTION_MASK 3 #define WDOG_CTRL_ACTION_NONE 0 /* no action */ @@ -442,6 +614,9 @@ void ar71xx_ddr_flush(u32 reg); #define REV_ID_MAJOR_AR7240 0x00c0 #define REV_ID_MAJOR_AR7241 0x0100 #define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 @@ -458,6 +633,8 @@ void ar71xx_ddr_flush(u32 reg); #define AR724X_REV_ID_REVISION_MASK 0x3 +#define AR934X_REV_ID_REVISION_MASK 0xf + extern void __iomem *ar71xx_reset_base; static inline void ar71xx_reset_wr(unsigned reg, u32 val) |