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authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-04 12:49:54 +0000
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-12-04 12:49:54 +0000
commit863d4e55d391b9f2b7a43350a286138dd0dbdc00 (patch)
tree1465fd3bd890b4d1f0fa1869219e8c54fc5362a2 /target/linux/ar7/base-files.mk
parenta087e6c06e5b12d70c014d38851697c4f7daac40 (diff)
Fix VLYNQ device enable for DG834Gv1
This patch allows VLYNQ devices on the DG834Gv1 to be successfully enabled. Currently the "__vlynq_enable_device" function attempts to set the VLYNQ device clock divisor to values from 1 through 8 until a link is successfully established. On the DG834Gv1 (but not the DG834Gv2), setting the VLYNQ device clock divisor to 1 (full rate) results in all further VLYNQ operations failing (including software reset), so the device is never enabled. This patches changes the function to only attempt divisors 2 through 8, and hence the device is successfully enabled. Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com> --------- git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9656 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar7/base-files.mk')
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