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authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-07-23 22:10:11 +0000
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>2007-07-23 22:10:11 +0000
commite2133d3ce6588e979df1e3f46b6540b184e52084 (patch)
tree4d1d8efac3cb27f369b02bf8b3fc8352369e053f /target/linux/amazon-2.6/files/arch
parenta39d500fb40b2e3c5e6b7f31ce0cfe03f1778074 (diff)
initial merge of infineon code for amazon, pci is still broken a bit. a big thank you goes to infineon for providing info and reference code
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8137 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/amazon-2.6/files/arch')
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/Kconfig63
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/Makefile9
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.c1455
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.h69
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c238
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/pci.c293
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/prom.c61
-rw-r--r--target/linux/amazon-2.6/files/arch/mips/amazon/setup.c216
8 files changed, 2404 insertions, 0 deletions
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/Kconfig b/target/linux/amazon-2.6/files/arch/mips/amazon/Kconfig
new file mode 100644
index 000000000..179e35efd
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/Kconfig
@@ -0,0 +1,63 @@
+# copyright 2007 john crispin <blogic@openwrt.org>
+
+menu "Amazon built-in"
+
+config AMAZON_ASC_UART
+ bool "Amazon asc uart"
+ select SERIAL_CORE
+ select SERIAL_CORE_CONSOLE
+ default y
+
+config AMAZON_PCI
+ bool "Amazon PCI support"
+ default y
+ select HW_HAS_PCI
+ select PCI
+
+config AMAZON_NET_SW
+ bool "Amazon network"
+ default y
+
+config AMAZON_WDT
+ bool "Amazon watchdog timer"
+ default y
+
+config AMAZON_MTD
+ bool "Amazon MTD map"
+ default y
+
+choice
+ prompt "Flash Size"
+ depends on AMAZON_MTD
+
+config MTD_AMAZON_FLASH_SIZE_2
+ bool "2MB"
+
+config MTD_AMAZON_FLASH_SIZE_4
+ bool "4MB"
+
+config MTD_AMAZON_FLASH_SIZE_8
+ bool "8MB"
+
+config MTD_AMAZON_FLASH_SIZE_16
+ bool "16MB"
+
+endchoice
+
+choice
+ prompt "Bus Width"
+ depends on AMAZON_MTD
+
+config MTD_AMAZON_BUS_WIDTH_8
+ bool "8-bit"
+
+config MTD_AMAZON_BUS_WIDTH_16
+ bool "16-bit"
+
+config MTD_AMAZON_BUS_WIDTH_32
+ bool "32-bit"
+
+endchoice
+
+
+endmenu
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/Makefile b/target/linux/amazon-2.6/files/arch/mips/amazon/Makefile
new file mode 100644
index 000000000..9cdc100b8
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2007 openwrt.org
+# John Crispin <blogic@openwrt.org>
+#
+# Makefile for Infineon Amazon
+#
+obj-y := dma-core.o interrupt.o prom.o setup.o
+obj-$(CONFIG_PCI) += pci.o
+
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.c b/target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.c
new file mode 100644
index 000000000..242bc77af
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.c
@@ -0,0 +1,1455 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+//-----------------------------------------------------------------------
+/*
+ * Description:
+ * Driver for Infineon Amazon DMA
+ */
+//-----------------------------------------------------------------------
+/* Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com]
+ * Created: 7-April-2004
+ */
+//-----------------------------------------------------------------------
+/* History
+ * Last changed on: 4-May-2004
+ * Last changed by: <peng.liu@infineon.com>
+ * Reason: debug
+ */
+//-----------------------------------------------------------------------
+/* Last changed on: 03-Dec-2004
+ * Last changed by: peng.liu@infineon.com
+ * Reason: recover from TPE bug
+ */
+
+//000004:fchang 2005/6/2 Modified by Linpeng as described below
+//-----------------------------------------------------------------------
+/* Last changed on: 28-Jan-2004
+ * Last changed by: peng.liu@infineon.com
+ * Reason:
+ * - handle "out of memory" bug
+ */
+//000003:tc.chen 2005/06/16 fix memory leak when Tx buffer full (heaving traffic).
+//507261:tc.chen 2005/07/26 re-organize code address map to improve performance.
+
+#if defined(CONFIG_MODVERSIONS) && !defined(MODVERSIONS)
+#define MODVERSIONS
+#endif
+
+#if defined(MODVERSIONS) && !defined(__GENKSYMS__)
+#include <linux/modversions.h>
+#endif
+
+#ifndef EXPORT_SYMTAB
+#define EXPORT_SYMTAB /* need this one 'cause we export symbols */
+#endif
+
+#undef DMA_NO_POLLING
+
+/* no TX interrupt handling */
+#define NO_TX_INT
+/* need for DMA workaround */
+#undef AMAZON_DMA_TPE_AAL5_RECOVERY
+
+#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
+#define MAX_SYNC_FAILS 1000000 // 000004:fchang
+unsigned int dma_sync_fails = 0;
+unsigned int total_dma_tpe_reset = 0;
+int (*tpe_reset) (void);
+int (*tpe_start) (void);
+int (*tpe_inject) (void);
+#endif // AMAZON_DMA_TPE_AAL5_RECOVERY
+
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/proc_fs.h>
+#include <linux/stat.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/selection.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include <asm/amazon/amazon.h>
+#include <asm/amazon/irq.h>
+#include <asm/amazon/amazon_dma.h>
+#include "dma-core.h"
+
+#define AMAZON_DMA_EMSG(fmt, args...) printk( KERN_ERR "%s: " fmt,__FUNCTION__, ## args)
+
+static irqreturn_t dma_interrupt(int irq, void *dev_id);
+extern void mask_and_ack_amazon_irq(unsigned int irq_nr);
+
+/***************************************** global data *******************************************/
+u64 *g_desc_list;
+dev_list *g_current_dev = NULL;
+dev_list *g_head_dev = NULL;
+dev_list *g_tail_dev = NULL;
+channel_info g_log_chan[CHAN_TOTAL_NUM + 1];
+struct proc_dir_entry *g_amazon_dma_dir;
+static u8 rx_chan_list_len = 0;
+static u8 tx_chan_list_len = 0;
+static int rx_chan_list[RX_CHAN_NUM + 1];
+static int tx_chan_list[TX_CHAN_NUM + 1];
+static u32 comb_isr_mask[CHAN_TOTAL_NUM];
+
+static inline int is_rx_chan(int chan_no)
+/*judge if this is an rx channel*/
+{
+ int result = 0;
+ if (chan_no < RX_CHAN_NUM)
+ result = 1;
+ return result;
+}
+
+/* Ugly, Channel ON register is badly mapped to channel no. */
+static u8 ch_on_mapping[CHAN_TOTAL_NUM] =
+ { 0, 1, 2, 3, 6, 7, 10, 4, 5, 8, 9, 11 };
+
+/* Brief: check wether the chan_no is legal
+ * Parameter: chan_no: logical channel number
+ * Return: 0 if is not valid
+ * 1 if is valid
+ */
+static inline int is_valid_dma_ch(int chan_no)
+{
+ return ((chan_no >= 0) && (chan_no < CHAN_TOTAL_NUM));
+}
+
+/* Brief: check whether a channel is open through Channel ON register
+ * Parameter: chan_no: logical channel number
+ * Return: 1 channel is open
+ * 0 not yet
+ * EINVAL: invalid parameter
+ */
+static inline int is_channel_open(int chan_no)
+{
+ return (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &
+ (1 << ch_on_mapping[chan_no]));
+}
+
+/* Brief: add a list entry
+ * Description:
+ * always add to the tail and no redundancy allowed. (i.e. entries are unique)
+ * 0 : entry deleted
+ * <0 : not deleted (due to not unique)
+ */
+static inline int _add_list_entry(int *list, int size_of_list, int entry)
+{
+ int i;
+ for (i = 0; i < size_of_list; i++) {
+ if (list[i] == entry)
+ break;
+ if (list[i] < 0) {
+ list[i] = entry;
+ return 0;
+ }
+ }
+ return -1;
+}
+
+/* Brief: delete a list entry
+ * Description:
+ * find the entry and remove it. shift all entries behind it one step forward if necessary\
+ * Return:
+ * 0 : entry deleted
+ * <0 : not deleted (due to not found?)
+ */
+static inline int _delete_list_entry(int *list, int size_of_list,
+ int entry)
+{
+ int i, j;
+ for (i = 0; i < size_of_list; i++) {
+ if (list[i] == entry) {
+ for (j = i; j < size_of_list; j++) {
+ list[j] = list[j + 1];
+ if (list[j + 1] < 0) {
+ break;
+ }
+ }
+ return 0;
+ }
+ }
+ return -1;
+}
+
+/* Brief: enable a channel through Channel ON register
+ * Parameter: chan_no: logical channel number
+ * Description:
+ * Please don't open a channel without a valid descriptor (hardware pitfall)
+ */
+static inline void open_channel(int chan_no)
+{
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) |= (1 << ch_on_mapping[chan_no]);
+ if (is_rx_chan(chan_no)) {
+ if (_add_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) {
+ rx_chan_list_len++;
+ } else {
+ AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no);
+ }
+ } else {
+ if (_add_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) {
+ tx_chan_list_len++;
+ } else {
+ AMAZON_DMA_DMSG("cannot add chan %d to open list\n", chan_no);
+ }
+ }
+}
+
+/* Brief: disable a channel through Channel ON register
+ * Parameter: chan_no: logical channel number
+ */
+
+static inline void close_channel(int chan_no)
+{
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]);
+ if (is_rx_chan(chan_no)) {
+ if (_delete_list_entry(rx_chan_list, RX_CHAN_NUM, chan_no) == 0) {
+ rx_chan_list_len--;
+ } else {
+ AMAZON_DMA_DMSG("cannot remove chan %d from open list \n",
+ chan_no);
+ }
+ } else {
+ if (_delete_list_entry(tx_chan_list, TX_CHAN_NUM, chan_no) == 0) {
+ tx_chan_list_len--;
+ } else {
+ AMAZON_DMA_DMSG("cannot remove chan %d from open list \n",
+ chan_no);
+ }
+ }
+}
+
+/* Brief: clear RX interrupt
+ */
+inline void rx_chan_clear_isr(int chan_no)
+{
+#ifdef DMA_NO_POLLING
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) =
+ (AMAZON_DMA_REG32
+ (AMAZON_DMA_CH0_ISR +
+ chan_no *
+ AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP | DMA_ISR_CMDCPT
+ | DMA_ISR_DURR));
+#else
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) =
+ (AMAZON_DMA_REG32
+ (AMAZON_DMA_CH0_ISR +
+ chan_no *
+ AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP |
+ DMA_ISR_CMDCPT));
+#endif
+}
+
+
+/* Brief: hacking function, this will reset all descriptors back to DMA
+ */
+static void dma_reset_all_descriptors(int chan_no)
+{
+ volatile struct rx_desc *rx_desc_p = NULL;
+ int i;
+ rx_desc_p =
+ (struct rx_desc *) g_desc_list +
+ g_log_chan[chan_no].offset_from_base;
+ for (i = 0; i < g_log_chan[chan_no].desc_len; i++) {
+ rx_desc_p->status.word &=
+ (~(DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | DMA_DESC_CPT_SET));
+ rx_desc_p->status.word |=
+ (DMA_DESC_OWN_DMA | g_log_chan[chan_no].packet_size);
+ rx_desc_p++;
+ }
+}
+
+#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
+/* Brief: Reset DMA descriptors
+ */
+static void amazon_dma_reset_tpe_rx(int chan_no)
+{
+ struct tx_desc *tx_desc_p = NULL;
+ int j, i = 0;
+
+ // wait until all TX channels stop transmitting
+ for (j = 9; j <= 10; j++) {
+ tx_desc_p =
+ (struct tx_desc *) g_desc_list +
+ g_log_chan[j].offset_from_base;
+ for (i = 0; i < g_log_chan[j].desc_len; i++) {
+ while ((tx_desc_p->status.field.OWN != CPU_OWN)) {
+ AMAZON_DMA_DMSG("DMA TX in progress\n"); // 000004:fchang
+ udelay(100);
+ }
+ tx_desc_p++;
+ }
+ }
+
+ if (tpe_reset) {
+ total_dma_tpe_reset++;
+ AMAZON_DMA_DMSG
+ ("\n===============resetting TPE========================== \n");
+ if ((*tpe_reset) ()) {
+ panic("cannot reset TPE engien\n"); // 000004:fchang
+ }
+ } else {
+ panic("no tpe_reset function\n"); // 000004:fchang
+ return;
+ }
+ dma_reset_all_descriptors(chan_no);
+ rx_chan_clear_isr(chan_no);
+ mb();
+
+ // send EoP
+ if (tpe_inject) {
+ if ((*tpe_inject) ()) {
+ panic("cannot inject a cell\n"); // 000004:fchang
+ }
+ } else {
+ AMAZON_DMA_EMSG("no tpe_inject function\n");
+ return;
+ }
+ mb();
+ while (1) {
+ if (AMAZON_DMA_REG32
+ (AMAZON_DMA_CH0_ISR +
+ chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT)) {
+ rx_chan_clear_isr(chan_no);
+ mb();
+ dma_reset_all_descriptors(chan_no);
+ if (g_log_chan[chan_no].current_desc ==
+ (g_log_chan[chan_no].desc_len - 1)) {
+ g_log_chan[chan_no].current_desc = 0;
+ } else {
+ g_log_chan[chan_no].current_desc++;
+ }
+ break;
+ }
+ mdelay(1);
+ }
+ mb();
+#if 0
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &= ~(1 << ch_on_mapping[chan_no]);
+ while (AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) &
+ (1 << ch_on_mapping[chan_no])) {
+ printk("TPE channel still on\n");
+ mdelay(1);
+ }
+
+ // AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = (1<<chan_no);
+ mb();
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + chan_no * AMAZON_DMA_CH_STEP) =
+ 0x32;
+ mb();
+ rx_chan_clear_isr(chan_no);
+ dma_reset_all_descriptors(chan_no);
+ mb();
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_ON) |= (1 << ch_on_mapping[chan_no]);
+ // g_log_chan[chan_no].current_desc=0;
+ mb();
+ mdelay(1);
+#endif
+ if (tpe_start) {
+ (*tpe_start) ();
+ } else {
+ AMAZON_DMA_EMSG("cannot restart TPE engien\n");
+ }
+}
+#endif // AMAZON_DMA_TPE_AAL5_RECOVERY
+
+
+/* Brief: RX channel interrupt handler
+ * Parameter: RX channel no
+ * Description: the interrupt handler for each RX channel
+ * 1. check descriptor, clear ISR if no incoming packet
+ * 2. inform upper layer to receive packet (and update descriptors)
+ */
+inline void rx_chan_intr_handler(int chan_no)
+{
+ volatile struct rx_desc *rx_desc_p = NULL;
+
+ /* fetch the current descriptor */
+ rx_desc_p =
+ (struct rx_desc *) g_desc_list +
+ g_log_chan[chan_no].offset_from_base +
+ g_log_chan[chan_no].current_desc;
+
+ g_log_chan[chan_no].dma_dev->current_rx_chan =
+ chan_no - g_log_chan[chan_no].dma_dev->logic_rx_chan_base;
+
+ // workaround for DMA pitfall: complete bit set happends before the
+ // other two bits (own,eop) are ready
+ if ((rx_desc_p->status.field.EoP != 1)
+ || (rx_desc_p->status.field.OWN != CPU_OWN)
+ || (rx_desc_p->status.field.data_length ==
+ g_log_chan[chan_no].packet_size)) {
+#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
+ if (chan_no == 4 || chan_no == 5) {
+ dma_sync_fails++;
+ if (dma_sync_fails > MAX_SYNC_FAILS) {
+ // detect bug
+ rx_desc_p0 =
+ (struct rx_desc *) g_desc_list +
+ g_log_chan[chan_no].offset_from_base;
+ rx_desc_p1 =
+ (struct rx_desc *) g_desc_list +
+ g_log_chan[chan_no].offset_from_base + 1;
+ if ((rx_desc_p0->status.field.OWN == CPU_OWN
+ && rx_desc_p0->status.field.EoP != 1)
+ && (rx_desc_p1->status.field.OWN == CPU_OWN
+ && rx_desc_p1->status.field.EoP != 1)) {
+ amazon_dma_reset_tpe_rx(chan_no);
+ dma_sync_fails = 0;
+ return;
+ }
+ dma_sync_fails = 0;
+ AMAZON_DMA_DMSG("too many times ch:%d\n", chan_no); // 000004:fchang
+ return;
+ }
+ udelay(10); // 000004:fchang
+ }
+#endif // //AMAZON_DMA_TPE_AAL5_RECOVERY
+ return;
+ }
+
+ /* inform the upper layer to receive the packet */
+ g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev, RCV_INT);
+ /* check the next descriptor, if still contains the incoming packet,
+ then do not clear the interrupt status */
+ rx_desc_p =
+ (struct rx_desc *) g_desc_list +
+ g_log_chan[chan_no].offset_from_base +
+ g_log_chan[chan_no].current_desc;
+ if (!
+ ((rx_desc_p->status.field.OWN == CPU_OWN)
+ && (rx_desc_p->status.field.C == 1))) {
+ rx_chan_clear_isr(chan_no);
+ }
+}
+
+
+/* Brief: TX channel interrupt handler
+ * Parameter: TX channel no
+ * Description: the interrupt handler for each TX channel
+ * 1. check all the descripters,if any of them had transmitted a packet, then free buffer
+ * because we cannot garantee the which one has already transmitted out, we have to go through all the descriptors here
+ * 2. clear the interrupt status bit
+ */
+inline void tx_chan_intr_handler(int chan_no)
+{
+ struct tx_desc *tx_desc_p = NULL;
+ int i = 0;
+
+ tx_desc_p =
+ (struct tx_desc *) g_desc_list +
+ g_log_chan[chan_no].offset_from_base;
+
+ for (i = 0; i < g_log_chan[chan_no].desc_len; i++) {
+ if ((tx_desc_p->status.field.OWN == CPU_OWN)
+ && (tx_desc_p->status.field.C == 1)) {
+ /* if already transmitted, then free the buffer */
+ g_log_chan[chan_no].
+ buffer_free((u8 *) __va(tx_desc_p->Data_Pointer),
+ g_log_chan[chan_no].opt[i]);
+ tx_desc_p->status.field.C = 0;
+ /* inform the upper layer about the completion of the
+ transmitted packet, the upper layer may want to free the
+ packet */
+ g_log_chan[chan_no].intr_handler(g_log_chan[chan_no].dma_dev,
+ TRANSMIT_CPT_INT);
+ }
+ tx_desc_p++;
+ }
+
+ /* after all these operations, clear the interrupt status bit */
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR + chan_no * AMAZON_DMA_CH_STEP) =
+ (AMAZON_DMA_REG32
+ (AMAZON_DMA_CH0_ISR +
+ chan_no *
+ AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP |
+ DMA_ISR_CMDCPT));
+}
+
+/* Brief: DMA interrupt handler
+ */
+static irqreturn_t dma_interrupt(int irq, void *dev_id)
+{
+ int i = 0;
+ int chan_no;
+ u32 isr = 0;
+#ifdef NO_TX_INT // 000004:fchang
+ static int cnt = 0; // 000004:fchang
+#endif // 000004:fchang
+ while ((isr =
+ AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR)) & (COMB_ISR_RX_MASK |
+ COMB_ISR_TX_MASK)) {
+ if (isr & COMB_ISR_RX_MASK) {
+ // RX Channels: start WFQ algorithm
+ chan_no = CHAN_TOTAL_NUM;
+ for (i = 0; i < RX_CHAN_NUM; i++) {
+ if ((isr & (comb_isr_mask[i]))
+ && (g_log_chan[i].weight > 0)) {
+ if (g_log_chan[chan_no].weight < g_log_chan[i].weight) {
+ chan_no = i;
+ }
+ }
+ }
+ if (chan_no < CHAN_TOTAL_NUM) {
+ rx_chan_intr_handler(chan_no);
+ } else {
+ for (i = 0; i < RX_CHAN_NUM; i++) {
+ g_log_chan[i].weight = g_log_chan[i].default_weight;
+ }
+ }
+ }
+#ifdef NO_TX_INT
+ cnt++;
+ if (cnt == 10) {
+ cnt = 0;
+ for (i = 0; i < tx_chan_list_len; i++) {
+ if (AMAZON_DMA_REG32
+ (AMAZON_DMA_CH0_ISR +
+ tx_chan_list[i] *
+ AMAZON_DMA_CH_STEP) & (DMA_ISR_CPT | DMA_ISR_EOP)) {
+ tx_chan_intr_handler(tx_chan_list[i]);
+ }
+ }
+ }
+#else
+ if (isr & COMB_ISR_TX_MASK) {
+ // TX channels: RR
+ for (i = 0; i < tx_chan_list_len; i++) {
+ if (isr & (comb_isr_mask[tx_chan_list[i]])) {
+ tx_chan_intr_handler(tx_chan_list[i]);
+ }
+ }
+ }
+#endif
+ } // while
+ return IRQ_HANDLED;
+}
+
+
+/* Brief: read a packet from DMA RX channel
+ * Parameter:
+ * Return: packet length
+ * Description:
+ * This is called back in a context of DMA interrupt
+ * 1. prepare new descriptor
+ * 2. read data
+ * 3. update WFQ weight
+ */
+//507261:tc.chen int dma_device_read(struct dma_device_info* dma_dev, u8** dataptr, void** opt)
+int asmlinkage dma_device_read(struct dma_device_info *dma_dev,
+ u8 ** dataptr, void **opt)
+{
+ u8 *buf;
+ int len;
+ int chan_no = 0;
+ int byte_offset = 0;
+
+ struct rx_desc *rx_desc_p;
+ void *p = NULL;
+ int current_desc;
+
+ chan_no = dma_dev->logic_rx_chan_base + dma_dev->current_rx_chan;
+ current_desc = g_log_chan[chan_no].current_desc;
+ rx_desc_p =
+ (struct rx_desc *) (g_desc_list +
+ g_log_chan[chan_no].offset_from_base +
+ current_desc);
+ buf = (u8 *) __va(rx_desc_p->Data_Pointer); /* extract the virtual
+ address of the data
+ pointer */
+ len = rx_desc_p->status.field.data_length; /* extract the data length */
+#ifndef CONFIG_MIPS_UNCACHED
+ dma_cache_inv((unsigned long) buf, len);
+#endif // CONFIG_MIPS_UNCACHED
+ *(u32 *) dataptr = (u32) buf;
+ if (opt) {
+ *(int *) opt = (int) g_log_chan[chan_no].opt[current_desc]; /* read
+ out
+ the
+ opt
+ information */
+ }
+
+ buf =
+ (u8 *) g_log_chan[chan_no].buffer_alloc(g_log_chan[chan_no].
+ packet_size, &byte_offset,
+ &p);
+ // should check null!!!!
+ if (buf == NULL || p == NULL) {
+ *(u32 *) dataptr = 0;
+ *(int *) opt = 0;
+ len = 0;
+ } else {
+ g_log_chan[chan_no].opt[current_desc] = p;
+ /* reduce the weight for WFQ algorithm */
+ g_log_chan[chan_no].weight -= len;
+ rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
+ }
+ if (current_desc == g_log_chan[chan_no].desc_len - 1) {
+ current_desc = 0;
+ } else {
+ current_desc++;
+ }
+ g_log_chan[chan_no].current_desc = current_desc;
+
+ rx_desc_p->status.word = DMA_DESC_OWN_DMA
+ | (byte_offset << DMA_DESC_BYTEOFF_SHIFT)
+ | g_log_chan[chan_no].packet_size;
+ return len;
+}
+
+/* Brief: write a packet through DMA RX channel to peripheral
+ * Parameter:
+ * Return: packet length
+ * Description:
+ *
+ */
+u64 dma_tx_drop = 0;
+//507261:tc.chen int dma_device_write(struct dma_device_info* dma_dev, u8* dataptr, int len,void* opt)
+int asmlinkage dma_device_write(struct dma_device_info *dma_dev,
+ u8 * dataptr, int len, void *opt)
+{
+ int chan_no = 0;
+ struct tx_desc *tx_desc_p;
+
+ int byte_offset = 0;
+ int current_desc;
+ static int cnt = 0; // 000004:fchang
+
+ unsigned long flag;
+ local_irq_save(flag);
+
+ chan_no = dma_dev->logic_tx_chan_base + dma_dev->current_tx_chan;
+ current_desc = g_log_chan[chan_no].current_desc;
+ tx_desc_p =
+ (struct tx_desc *) (g_desc_list +
+ g_log_chan[chan_no].offset_from_base +
+ current_desc);
+ // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){
+ if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen
+ AMAZON_DMA_DMSG("no TX desc for CPU, drop packet\n");
+ dma_tx_drop++;
+ g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT);
+ local_irq_restore(flag);
+ return 0;
+ }
+ g_log_chan[chan_no].opt[current_desc] = opt;
+
+ /* byte offset----to adjust the starting address of the data buffer,
+ should be multiple of the burst length. */
+ byte_offset =
+ ((u32) CPHYSADDR((u32) dataptr)) % (g_log_chan[chan_no].burst_len *
+ 4);
+#ifndef CONFIG_MIPS_UNCACHED
+ dma_cache_wback((unsigned long) dataptr, len);
+ wmb();
+#endif // CONFIG_MIPS_UNCACHED
+
+ tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
+ wmb();
+ tx_desc_p->status.word = DMA_DESC_OWN_DMA
+ | DMA_DESC_SOP_SET
+ | DMA_DESC_EOP_SET | (byte_offset << DMA_DESC_BYTEOFF_SHIFT)
+ | len;
+ wmb();
+ if (is_channel_open(chan_no) == 0) {
+ // turn on if necessary
+ open_channel(chan_no);
+ }
+#ifdef DMA_NO_POLLING
+ if ((AMAZON_DMA_REG32
+ (AMAZON_DMA_CH0_ISR +
+ chan_no * AMAZON_DMA_CH_STEP) & (DMA_ISR_DURR | DMA_ISR_CPT)) ==
+ (DMA_ISR_DURR)) {
+ // clear DURR if (CPT is AND set and DURR is set)
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR +
+ chan_no * AMAZON_DMA_CH_STEP) = DMA_ISR_DURR;
+ }
+#endif
+
+ if (current_desc == (g_log_chan[chan_no].desc_len - 1)) {
+ current_desc = 0;
+ } else {
+ current_desc++;
+ }
+
+
+ g_log_chan[chan_no].current_desc = current_desc;
+ tx_desc_p =
+ (struct tx_desc *) (g_desc_list +
+ g_log_chan[chan_no].offset_from_base +
+ current_desc);
+ // 000003:tc.chen if(tx_desc_p->status.field.OWN==DMA_OWN){
+ if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C == 1) { // 000003:tc.chen
+ g_log_chan[chan_no].intr_handler(dma_dev, TX_BUF_FULL_INT);
+ }
+#ifdef NO_TX_INT
+//000004:fchang Start
+ cnt++;
+ if (cnt == 5) {
+ cnt = 0;
+ tx_chan_intr_handler(chan_no);
+ }
+//000004:fchang End
+#endif
+ local_irq_restore(flag); // 000004:fchang
+ return len;
+}
+
+
+
+int desc_list_proc_read(char *buf, char **start, off_t offset,
+ int count, int *eof, void *data)
+{
+ int i;
+ u32 *p = (u32 *) g_desc_list;
+ int len = 0;
+ len += sprintf(buf + len, "descriptor list:\n");
+ for (i = 0; i < 120; i++) {
+ len += sprintf(buf + len, "%d\n", i);
+ len += sprintf(buf + len, "%08x\n", *(p + i * 2 + 1));
+ len += sprintf(buf + len, "%08x\n", *(p + i * 2));
+
+ }
+
+ return len;
+
+}
+
+int channel_weight_proc_read(char *buf, char **start, off_t offset,
+ int count, int *eof, void *data)
+{
+
+ // int i=0;
+ int len = 0;
+ len += sprintf(buf + len, "Qos dma channel weight list\n");
+ len +=
+ sprintf(buf + len,
+ "channel_num default_weight current_weight device Tx/Rx\n");
+ len +=
+ sprintf(buf + len,
+ " 0 %08x %08x Switch Rx0\n",
+ g_log_chan[0].default_weight, g_log_chan[0].weight);
+ len +=
+ sprintf(buf + len,
+ " 1 %08x %08x Switch Rx1\n",
+ g_log_chan[1].default_weight, g_log_chan[1].weight);
+ len +=
+ sprintf(buf + len,
+ " 2 %08x %08x Switch Rx2\n",
+ g_log_chan[2].default_weight, g_log_chan[2].weight);
+ len +=
+ sprintf(buf + len,
+ " 3 %08x %08x Switch Rx3\n",
+ g_log_chan[3].default_weight, g_log_chan[3].weight);
+ len +=
+ sprintf(buf + len,
+ " 4 %08x %08x Switch Tx0\n",
+ g_log_chan[4].default_weight, g_log_chan[4].weight);
+ len +=
+ sprintf(buf + len,
+ " 5 %08x %08x Switch Tx1\n",
+ g_log_chan[5].default_weight, g_log_chan[5].weight);
+ /*
+ len+=sprintf(buf+len," 6 %08x %08x TPE
+ Rx0\n",g_log_chan[6].default_weight, g_log_chan[6].weight);
+ len+=sprintf(buf+len," 7 %08x %08x TPE
+ Rx0\n",g_log_chan[7].default_weight, g_log_chan[7].weight);
+ len+=sprintf(buf+len," 8 %08x %08x TPE
+ Tx0\n",g_log_chan[8].default_weight, g_log_chan[8].weight);
+ len+=sprintf(buf+len," 9 %08x %08x TPE
+ Rx0\n",g_log_chan[9].default_weight, g_log_chan[9].weight);
+ len+=sprintf(buf+len," 10 %08x %08x DPLUS
+ Rx0\n",g_log_chan[10].default_weight, g_log_chan[10].weight);
+ len+=sprintf(buf+len," 11 %08x %08x DPLUS
+ Rx0\n",g_log_chan[11].default_weight, g_log_chan[11].weight); */
+ return len;
+}
+
+int dma_register_proc_read(char *buf, char **start, off_t offset,
+ int count, int *eof, void *data)
+{
+ dev_list *temp_dev;
+ int len = 0;;
+
+ len += sprintf(buf + len, "amazon dma driver\n");
+ len += sprintf(buf + len, "version 1.0\n");
+ len += sprintf(buf + len, "devices registered:\n");
+ for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
+ len += sprintf(buf + len, "%s ", temp_dev->dev->device_name);
+ }
+ len += sprintf(buf + len, "\n");
+ len += sprintf(buf + len, "CH_ON=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_ON));
+ len += sprintf(buf + len, "CH_RST=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH_RST));
+ len += sprintf(buf + len, "CH0_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH0_ISR));
+ len += sprintf(buf + len, "CH1_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH1_ISR));
+ len += sprintf(buf + len, "CH2_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH2_ISR));
+ len += sprintf(buf + len, "CH3_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH3_ISR));
+ len += sprintf(buf + len, "CH4_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH4_ISR));
+ len += sprintf(buf + len, "CH5_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH5_ISR));
+ len += sprintf(buf + len, "CH6_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH6_ISR));
+ len += sprintf(buf + len, "CH7_ISR=%08x\n", AMAZON_DMA_REG32(AMAZON_DMA_CH7_ISR));
+ len += sprintf(buf + len, "CH8_ISR=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH8_ISR));
+ len +=
+ sprintf(buf + len, "CH9_ISR=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH9_ISR));
+ len +=
+ sprintf(buf + len, "CH10_ISR=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH10_ISR));
+ len +=
+ sprintf(buf + len, "CH11_ISR=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH11_ISR));
+ len +=
+ sprintf(buf + len, "LCH0_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK));
+ len +=
+ sprintf(buf + len, "LCH1_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH1_MSK));
+ len +=
+ sprintf(buf + len, "LCH2_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH2_MSK));
+ len +=
+ sprintf(buf + len, "LCH3_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH3_MSK));
+ len +=
+ sprintf(buf + len, "LCH4_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH4_MSK));
+ len +=
+ sprintf(buf + len, "LCH5_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH5_MSK));
+ len +=
+ sprintf(buf + len, "LCH6_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH6_MSK));
+ len +=
+ sprintf(buf + len, "LCH7_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH7_MSK));
+ len +=
+ sprintf(buf + len, "LCH8_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH8_MSK));
+ len +=
+ sprintf(buf + len, "LCH9_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH9_MSK));
+ len +=
+ sprintf(buf + len, "LCH10_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH10_MSK));
+ len +=
+ sprintf(buf + len, "LCH11_MSK=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH11_MSK));
+ len +=
+ sprintf(buf + len, "Desc_BA=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA));
+ len +=
+ sprintf(buf + len, "LCH0_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH1_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH2_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH3_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH4_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH5_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH6_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH7_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH8_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH9_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH10_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH11_DES_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_LEN));
+ len +=
+ sprintf(buf + len, "LCH1_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH2_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH2_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH3_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH3_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH4_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH4_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH5_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH5_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH6_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH6_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH7_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH7_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH8_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH8_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH9_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH9_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH10_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH10_DES_OFST));
+ len +=
+ sprintf(buf + len, "LCH11_DES_OFST=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH11_DES_OFST));
+ len +=
+ sprintf(buf + len, "AMAZON_DMA_SW_BL=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_SW_BL));
+ len +=
+ sprintf(buf + len, "AMAZON_DMA_TPE_BL=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_TPE_BL));
+ len +=
+ sprintf(buf + len, "DPlus2FPI_BL=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_DPlus2FPI_BL));
+ len +=
+ sprintf(buf + len, "GRX_BUF_LEN=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN));
+ len +=
+ sprintf(buf + len, "DMA_ECON_REG=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG));
+ len +=
+ sprintf(buf + len, "POLLING_REG=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG));
+ len +=
+ sprintf(buf + len, "CH_WGT=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_WGT));
+ len +=
+ sprintf(buf + len, "TX_WGT=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_TX_WGT));
+ len +=
+ sprintf(buf + len, "DPlus2FPI_CLASS=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_DPLus2FPI_CLASS));
+ len +=
+ sprintf(buf + len, "COMB_ISR=%08x\n",
+ AMAZON_DMA_REG32(AMAZON_DMA_COMB_ISR));
+#ifdef AMAZON_DMA_TPE_AAL5_RECOVERY
+ len += sprintf(buf + len, "TPE fails:%u\n", total_dma_tpe_reset); // 000004:fchang
+#endif
+ return len;
+}
+
+/* Brief: initialize DMA registers
+ * Description:
+ */
+static void dma_chip_init(void)
+{
+ int i;
+ for (i = 0; i < CHAN_TOTAL_NUM; i++) {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH1_DES_OFST +
+ i * AMAZON_DMA_CH_STEP) = DEFAULT_OFFSET;
+ }
+#ifdef DMA_NO_POLLING
+ AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = 0;
+#else
+ // enable poll mode and set polling counter
+ AMAZON_DMA_REG32(AMAZON_DMA_POLLING_REG) = DMA_POLLING_CNT | DMA_POLLING_ENABLE;
+#endif
+ // to enable DMA drop
+ AMAZON_DMA_REG32(AMAZON_DMA_GRX_BUF_LEN) = 0x10000;
+}
+
+int insert_dev_list(dev_list * dev)
+{
+ dev_list *temp_dev;
+ if (g_head_dev == NULL) {
+ g_head_dev = dev;
+ g_tail_dev = dev;
+ dev->prev = NULL;
+ dev->next = NULL;
+ } else {
+ for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
+ if (temp_dev->weight < dev->weight) {
+ if (temp_dev->prev)
+ temp_dev->prev->next = dev;
+
+ dev->prev = temp_dev->prev;
+ dev->next = temp_dev;
+ temp_dev->prev = dev;
+ if (temp_dev == g_head_dev)
+ g_head_dev = dev;
+ break;
+ }
+ }
+
+ if (!temp_dev) {
+ g_tail_dev->next = dev;
+ dev->prev = g_tail_dev;
+ dev->next = NULL;
+ g_tail_dev = dev;
+ }
+
+ }
+
+ return 1;
+}
+
+u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
+{
+ u8 *buffer = (u8 *) kmalloc(len * sizeof(u8), GFP_KERNEL);
+ *byte_offset = 0;
+ return buffer;
+
+}
+
+int common_buffer_free(u8 * dataptr, void *opt)
+{
+ if (dataptr)
+ kfree(dataptr);
+ return 0;
+}
+
+
+int register_dev(struct dma_device_info *dma_dev)
+{
+ int i, j, temp;
+ int burst_reg = 0;
+ u8 *buffer;
+ void *p = NULL;
+ int byte_offset = 0;
+
+ struct rx_desc *rx_desc_p;
+ struct tx_desc *tx_desc_p;
+ if (strcmp(dma_dev->device_name, "switch1") == 0) {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH1_RST_MASK; // resest
+ // channel
+ // 1st
+ AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian
+ // conversion
+ // for Switch
+ burst_reg = AMAZON_DMA_SW_BL;
+ dma_dev->logic_rx_chan_base = switch_rx_chan_base;
+ dma_dev->logic_tx_chan_base = switch_tx_chan_base;
+ }
+
+ else if (strcmp(dma_dev->device_name, "switch2") == 0) {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = SWITCH2_RST_MASK; // resest
+ // channel
+ // 1st
+ AMAZON_DMA_REG32(AMAZON_DMA_DMA_ECON_REG) |= 0x3; // endian
+ // conversion
+ // for Switch
+ burst_reg = AMAZON_DMA_SW_BL;
+ dma_dev->logic_rx_chan_base = switch2_rx_chan_base;
+ dma_dev->logic_tx_chan_base = switch2_tx_chan_base;
+
+ } else if (strcmp(dma_dev->device_name, "TPE") == 0) {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = TPE_RST_MASK; // resest
+ // channel 1st
+ //
+ burst_reg = AMAZON_DMA_TPE_BL;
+ dma_dev->logic_rx_chan_base = TPE_rx_chan_base;
+ dma_dev->logic_tx_chan_base = TPE_tx_chan_base;
+ }
+
+ else if (strcmp(dma_dev->device_name, "DPlus") == 0) {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH_RST) = DPlus2FPI_RST_MASK; // resest
+ // channel
+ // 1st
+ dma_dev->logic_rx_chan_base = DPLus2FPI_rx_chan_base;
+ dma_dev->logic_tx_chan_base = DPLus2FPI_tx_chan_base;
+
+ }
+
+ i = 0;
+ for (temp = dma_dev->tx_burst_len; temp > 2; temp /= 2) {
+ i += 1;
+ }
+
+
+ AMAZON_DMA_REG32(burst_reg) = i << 1;
+ i = 0;
+ for (temp = dma_dev->rx_burst_len; temp > 2; temp /= 2) {
+ i += 1;
+ }
+ AMAZON_DMA_REG32(burst_reg) += i;
+
+ for (i = 0; i < dma_dev->num_rx_chan; i++) {
+
+ temp = dma_dev->logic_rx_chan_base + i;
+ g_log_chan[temp].dma_dev = dma_dev;
+ g_log_chan[temp].weight = dma_dev->rx_chan[i].weight;
+ g_log_chan[temp].default_weight = dma_dev->rx_chan[i].weight;
+ g_log_chan[temp].current_desc = 0;
+ g_log_chan[temp].desc_ofst = DEFAULT_OFFSET;
+ g_log_chan[temp].desc_len = dma_dev->rx_chan[i].desc_num;
+ g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET;
+ g_log_chan[temp].packet_size = dma_dev->rx_chan[i].packet_size;
+
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->rx_chan[i].desc_num;
+ // enable interrupt mask
+ if (temp == 4 || temp == 5) {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x32;
+ } else {
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36;
+ }
+ strcpy(g_log_chan[temp].device_name, dma_dev->device_name);
+ g_log_chan[temp].burst_len = dma_dev->rx_burst_len;
+ g_log_chan[temp].control = dma_dev->rx_chan[i].control;
+
+
+ /* specify the buffer allocation and free method */
+ if (dma_dev->buffer_alloc)
+ g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc;
+ else
+ g_log_chan[temp].buffer_alloc = common_buffer_alloc;
+
+ if (dma_dev->buffer_free)
+ g_log_chan[temp].buffer_free = dma_dev->buffer_free;
+ else
+ g_log_chan[temp].buffer_free = common_buffer_free;
+
+ if (dma_dev->intr_handler)
+ g_log_chan[temp].intr_handler = dma_dev->intr_handler;
+ else
+ g_log_chan[temp].intr_handler = NULL;
+
+ for (j = 0; j < g_log_chan[temp].desc_len; j++) {
+ rx_desc_p = (struct rx_desc *) (g_desc_list + g_log_chan[temp].offset_from_base + j);
+ rx_desc_p->status.word = 0;
+ rx_desc_p->status.field.data_length = g_log_chan[temp].packet_size;
+ buffer = (u8 *) g_log_chan[temp].buffer_alloc(g_log_chan[temp].packet_size, &byte_offset, &p);
+ rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buffer);
+ rx_desc_p->status.field.byte_offset = byte_offset;
+ /* fix me, should check if the addresss comply with the burst
+ lenght requirment */
+ g_log_chan[temp].opt[j] = p;
+ rx_desc_p->status.field.OWN = DMA_OWN;
+
+ }
+ /* open or close the channel */
+ if (g_log_chan[temp].control)
+ open_channel(temp);
+ else
+ close_channel(temp);
+ }
+
+ for (i = 0; i < dma_dev->num_tx_chan; i++) {
+ temp = dma_dev->logic_tx_chan_base + i;
+ g_log_chan[temp].dma_dev = dma_dev;
+ g_log_chan[temp].weight = dma_dev->tx_chan[i].weight;
+ g_log_chan[temp].default_weight = dma_dev->tx_chan[i].weight;
+ g_log_chan[temp].current_desc = 0;
+ g_log_chan[temp].desc_ofst = DEFAULT_OFFSET;
+ g_log_chan[temp].desc_len = dma_dev->tx_chan[i].desc_num;
+ g_log_chan[temp].offset_from_base = temp * DEFAULT_OFFSET;
+ g_log_chan[temp].packet_size = dma_dev->tx_chan[i].packet_size;
+
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_DES_LEN + temp * AMAZON_DMA_CH_STEP) = dma_dev->tx_chan[i].desc_num;
+ // enable interrupt mask
+#ifdef NO_TX_INT
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x3e;
+#else
+ AMAZON_DMA_REG32(AMAZON_DMA_CH0_MSK + temp * AMAZON_DMA_CH_STEP) = 0x36;
+#endif
+
+ strcpy(g_log_chan[temp].device_name, dma_dev->device_name);
+ g_log_chan[temp].burst_len = dma_dev->tx_burst_len;
+ g_log_chan[temp].control = dma_dev->tx_chan[i].control;
+
+ if (dma_dev->buffer_alloc)
+ g_log_chan[temp].buffer_alloc = dma_dev->buffer_alloc;
+ else
+ g_log_chan[temp].buffer_alloc = common_buffer_alloc;
+
+ if (dma_dev->buffer_free)
+ g_log_chan[temp].buffer_free = dma_dev->buffer_free;
+ else
+ g_log_chan[temp].buffer_free = common_buffer_free;
+
+ if (dma_dev->intr_handler)
+ g_log_chan[temp].intr_handler = dma_dev->intr_handler;
+ else
+ g_log_chan[temp].intr_handler = NULL;
+
+ for (j = 0; j < g_log_chan[temp].desc_len; j++) {
+
+ tx_desc_p =
+ (struct tx_desc *) (g_desc_list +
+ g_log_chan[temp].offset_from_base + j);
+ tx_desc_p->status.word = 0;
+ tx_desc_p->status.field.data_length =
+ g_log_chan[temp].packet_size;
+ tx_desc_p->status.field.OWN = CPU_OWN;
+
+ }
+ /* workaround DMA pitfall, we never turn on channel if we don't
+ have proper descriptors */
+ if (!g_log_chan[temp].control) {
+ close_channel(temp);
+ }
+
+ }
+
+ return 0;
+}
+
+int dma_device_register(struct dma_device_info *dma_dev)
+{
+ dev_list *temp_dev;
+ temp_dev = (dev_list *) kmalloc(sizeof(dev_list), GFP_KERNEL);
+ temp_dev->dev = dma_dev;
+ temp_dev->weight = dma_dev->weight;
+ insert_dev_list(temp_dev);
+ /* check whether this is a known device */
+ if ((strcmp(dma_dev->device_name, "switch1") == 0)
+ || (strcmp(dma_dev->device_name, "TPE") == 0)
+ || (strcmp(dma_dev->device_name, "switch2") == 0)
+ || (strcmp(dma_dev->device_name, "DPlus") == 0)) {
+ register_dev(dma_dev);
+ }
+
+ return 0;
+}
+
+
+int unregister_dev(struct dma_device_info *dma_dev)
+{
+ int i, j, temp;
+ u8 *buffer;
+ struct rx_desc *rx_desc_p;
+
+ for (i = 0; i < dma_dev->num_rx_chan; i++) {
+ temp = dma_dev->logic_rx_chan_base + i;
+ close_channel(temp);
+ for (j = 0; j < g_log_chan[temp].desc_len; j++) {
+ rx_desc_p =
+ (struct rx_desc *) (g_desc_list +
+ g_log_chan[temp].offset_from_base + j);
+ buffer = (u8 *) __va(rx_desc_p->Data_Pointer);
+ g_log_chan[temp].buffer_free(buffer, g_log_chan[temp].opt[j]);
+ }
+ }
+ for (i = 0; i < dma_dev->num_tx_chan; i++) {
+ temp = dma_dev->logic_tx_chan_base + i;
+ close_channel(temp);
+ }
+ return 0;
+}
+
+int dma_device_unregister(struct dma_device_info *dev)
+{
+ dev_list *temp_dev;
+ for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
+ if (strcmp(dev->device_name, temp_dev->dev->device_name) == 0) {
+ if ((strcmp(dev->device_name, "switch1") == 0)
+ || (strcmp(dev->device_name, "TPE") == 0)
+ || (strcmp(dev->device_name, "switch2") == 0)
+ || (strcmp(dev->device_name, "DPlus") == 0))
+ unregister_dev(dev);
+ if (temp_dev == g_head_dev) {
+ g_head_dev = temp_dev->next;
+ kfree(temp_dev);
+ } else {
+ if (temp_dev == g_tail_dev)
+ g_tail_dev = temp_dev->prev;
+ if (temp_dev->prev)
+ temp_dev->prev->next = temp_dev->next;
+ if (temp_dev->next)
+ temp_dev->next->prev = temp_dev->prev;
+ kfree(temp_dev);
+ }
+ break;
+ }
+
+ }
+ return 0;
+}
+
+void dma_device_update_rx(struct dma_device_info *dma_dev)
+{
+ int i, temp;
+ for (i = 0; i < dma_dev->num_rx_chan; i++) {
+ temp = dma_dev->logic_rx_chan_base + i;
+ g_log_chan[temp].control = dma_dev->rx_chan[i].control;
+
+ if (g_log_chan[temp].control)
+ open_channel(temp);
+ else
+ close_channel(temp);
+ }
+
+}
+
+void dma_device_update_tx(struct dma_device_info *dma_dev)
+{
+ int i, temp;
+ for (i = 0; i < dma_dev->num_tx_chan; i++) {
+ temp = dma_dev->logic_tx_chan_base + i;
+ g_log_chan[temp].control = dma_dev->tx_chan[i].control;
+ if (g_log_chan[temp].control) {
+ /* we turn on channel when send out the very first packet */
+ // open_channel(temp);
+ } else
+ close_channel(temp);
+ }
+}
+
+int dma_device_update(struct dma_device_info *dma_dev)
+{
+ dma_device_update_rx(dma_dev);
+ dma_device_update_tx(dma_dev);
+ return 0;
+}
+
+static int dma_open(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static int dma_release(struct inode *inode, struct file *file)
+{
+ /* release the resources */
+ return 0;
+}
+
+static int dma_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ int value = 0;
+ int result = 0;
+ int chan_no = 0;
+
+ switch (cmd) {
+ case 0: /* get register value */
+ break;
+ case 1: /* return channel weight */
+ chan_no = *((int *) arg);
+ *((int *) arg + 1) = g_log_chan[chan_no].default_weight;
+ break;
+ case 2: /* set channel weight */
+ chan_no = *((int *) arg);
+ value = *((int *) arg + 1);
+ printk("new weight=%08x\n", value);
+ g_log_chan[chan_no].default_weight = value;
+ break;
+ default:
+ break;
+ }
+ return result;
+}
+
+
+static struct file_operations dma_fops = {
+ owner:THIS_MODULE,
+ open:dma_open,
+ release:dma_release,
+ ioctl:dma_ioctl,
+};
+
+static int dma_init(void)
+{
+ int result = 0;
+ int i;
+ printk("initialising dma core\n");
+ result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops);
+ if (result) {
+ AMAZON_DMA_EMSG("cannot register device dma-core!\n");
+ return result;
+ }
+ result = request_irq(AMAZON_DMA_INT, dma_interrupt, SA_INTERRUPT, "dma-core", (void *) &dma_interrupt);
+ if (result) {
+ AMAZON_DMA_EMSG("error, cannot get dma_irq!\n");
+ free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt);
+ return -EFAULT;
+ }
+
+ g_desc_list = (u64 *) KSEG1ADDR(__get_free_page(GFP_DMA));
+
+ if (g_desc_list == NULL) {
+ AMAZON_DMA_EMSG("no memory for desriptor\n");
+ return -ENOMEM;
+ }
+ memset(g_desc_list, 0, PAGE_SIZE);
+ AMAZON_DMA_REG32(AMAZON_DMA_Desc_BA) = (u32) CPHYSADDR((u32) g_desc_list);
+ g_amazon_dma_dir = proc_mkdir("amazon_dma", NULL);
+ create_proc_read_entry("dma_register", 0, g_amazon_dma_dir, dma_register_proc_read, NULL);
+ create_proc_read_entry("g_desc_list", 0, g_amazon_dma_dir, desc_list_proc_read, NULL);
+ create_proc_read_entry("channel_weight", 0, g_amazon_dma_dir, channel_weight_proc_read, NULL);
+
+ dma_chip_init();
+ for (i = 0; i < (RX_CHAN_NUM + 1); i++) {
+ rx_chan_list[i] = -1;
+ }
+ for (i = 0; i < (TX_CHAN_NUM + 1); i++) {
+ tx_chan_list[i] = -1;
+ }
+
+ for (i = 0; i < CHAN_TOTAL_NUM; i++) {
+ comb_isr_mask[i] = 0x80000000 >> (i);
+ }
+
+ g_log_chan[CHAN_TOTAL_NUM].weight = 0;
+ printk("initialising dma core ... done\n");
+
+ return 0;
+}
+
+arch_initcall(dma_init);
+
+
+void dma_cleanup(void)
+{
+ dev_list *temp_dev;
+
+ unregister_chrdev(DMA_MAJOR, "dma-core");
+ for (temp_dev = g_head_dev; temp_dev; temp_dev = temp_dev->next) {
+ kfree(temp_dev);
+ }
+ free_page(KSEG0ADDR((unsigned long) g_desc_list));
+ remove_proc_entry("channel_weight", g_amazon_dma_dir);
+ remove_proc_entry("dma_list", g_amazon_dma_dir);
+ remove_proc_entry("dma_register", g_amazon_dma_dir);
+ remove_proc_entry("amazon_dma", NULL);
+ /* release the resources */
+ free_irq(AMAZON_DMA_INT, (void *) &dma_interrupt);
+}
+
+EXPORT_SYMBOL(dma_device_register);
+EXPORT_SYMBOL(dma_device_unregister);
+EXPORT_SYMBOL(dma_device_read);
+EXPORT_SYMBOL(dma_device_write);
+EXPORT_SYMBOL(dma_device_update);
+EXPORT_SYMBOL(dma_device_update_rx);
+
+MODULE_LICENSE("GPL");
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.h b/target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.h
new file mode 100644
index 000000000..cb3d456c9
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/dma-core.h
@@ -0,0 +1,69 @@
+#ifndef DMA_CORE_H
+#define DMA_CORE_H
+
+#define AMAZON_DMA_REG32(reg_num) *((volatile u32*)(reg_num))
+#define AMAZON_DMA_CH_STEP 4
+
+#define COMB_ISR_RX_MASK 0xfe000000
+#define COMB_ISR_TX_MASK 0x01f00000
+
+
+#define DMA_OWN 1
+#define CPU_OWN 0
+#define DMA_MAJOR 250
+
+//Descriptors
+#define DMA_DESC_OWN_CPU 0x0
+#define DMA_DESC_OWN_DMA 0x80000000
+#define DMA_DESC_CPT_SET 0x40000000
+#define DMA_DESC_SOP_SET 0x20000000
+#define DMA_DESC_EOP_SET 0x10000000
+
+#define switch_rx_chan_base 0
+#define switch_tx_chan_base 7
+#define switch2_rx_chan_base 2
+#define switch2_tx_chan_base 8
+#define TPE_rx_chan_base 4
+#define TPE_tx_chan_base 9
+#define DPLus2FPI_rx_chan_base 6
+#define DPLus2FPI_tx_chan_base 11
+
+#define RX_CHAN_NUM 7
+#define TX_CHAN_NUM 5
+#define CHAN_TOTAL_NUM (RX_CHAN_NUM+TX_CHAN_NUM)
+#define DEFAULT_OFFSET 20
+#define DESCRIPTOR_SIZE 8
+
+typedef struct dev_list{
+ struct dma_device_info* dev;
+ int weight;
+ struct dev_list* prev;
+ struct dev_list* next;
+}dev_list;
+
+typedef struct channel_info{
+ char device_name[16];
+ int occupied;
+ enum attr_t attr;
+ int current_desc;
+ int weight;
+ int default_weight;
+ int desc_num;
+ int burst_len;
+ int desc_len;
+ int desc_ofst;
+ int packet_size;
+ int offset_from_base;
+ int control;
+ void* opt[DEFAULT_OFFSET];
+ u8* (*buffer_alloc)(int len,int* offset, void** opt);
+ int (*buffer_free)(u8* dataptr,void* opt);
+ int (*intr_handler)(struct dma_device_info* info,int status);
+
+ struct dma_device_info* dma_dev;
+}channel_info;
+
+
+
+#endif
+
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c b/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c
new file mode 100644
index 000000000..6702ecf3d
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/interrupt.c
@@ -0,0 +1,238 @@
+/*
+ * Gary Jennejohn (C) 2003 <gj@denx.de>
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Routines for generic manipulation of the interrupts found on the
+ * AMAZON boards.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+
+#include <asm/amazon/amazon.h>
+#include <asm/amazon/irq.h>
+#include <asm/bootinfo.h>
+#include <asm/irq_cpu.h>
+#include <asm/irq.h>
+#include <asm/time.h>
+
+static void amazon_disable_irq(unsigned int irq_nr)
+{
+ /* have to access the correct register here */
+ if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
+ /* access IM0 DMA channels */
+ *AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK));
+ else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
+ /* access IM0 except DMA*/
+ *AMAZON_ICU_IM0_IER &= (~AMAZON_ICU_IM0_IER_IR(irq_nr));
+ else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
+ /* access IM1 */
+ *AMAZON_ICU_IM1_IER &= (~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0));
+ else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
+ /* access IM2 */
+ *AMAZON_ICU_IM2_IER &= (~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0));
+ else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
+ /* access IM3 */
+ *AMAZON_ICU_IM3_IER &= (~AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0)));
+ else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
+ /* access IM4 */
+ *AMAZON_ICU_IM4_IER &= (~AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0)));
+}
+
+static void amazon_mask_and_ack_irq(unsigned int irq_nr)
+{
+ /* have to access the correct register here */
+ if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0) {
+ /* access IM0 DMA channels */
+ *AMAZON_ICU_IM0_IER &= (~(AMAZON_DMA_H_MASK)); /* mask */
+ *AMAZON_ICU_IM0_ISR = AMAZON_DMA_H_MASK; /* ack */
+ } else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12) {
+ /* access IM0 except DMA */
+ *AMAZON_ICU_IM0_IER &= ~AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0); /* mask */
+ *AMAZON_ICU_IM0_ISR = AMAZON_ICU_IM0_ISR_IR(irq_nr - INT_NUM_IM0_IRL0); /* ack */
+ } else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0) {
+ /* access IM1 */
+ *AMAZON_ICU_IM1_IER &= ~AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0); /* mask */
+ *AMAZON_ICU_IM1_ISR = AMAZON_ICU_IM1_ISR_IR(irq_nr - INT_NUM_IM1_IRL0); /* ack */
+ } else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0) {
+ /* access IM2 */
+ *AMAZON_ICU_IM2_IER &= ~AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0); /* mask */
+ *AMAZON_ICU_IM2_ISR = AMAZON_ICU_IM2_ISR_IR(irq_nr - INT_NUM_IM2_IRL0); /* ack */
+ } else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0) {
+ /* access IM3 */
+ *AMAZON_ICU_IM3_IER &= ~AMAZON_ICU_IM3_IER_IR(irq_nr - INT_NUM_IM3_IRL0); /* mask */
+ *AMAZON_ICU_IM3_ISR = AMAZON_ICU_IM3_ISR_IR(irq_nr - INT_NUM_IM3_IRL0); /* ack */
+ } else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0) {
+ *AMAZON_ICU_IM4_IER &= ~AMAZON_ICU_IM4_IER_IR(irq_nr - INT_NUM_IM4_IRL0); /* mask */
+ *AMAZON_ICU_IM4_ISR = AMAZON_ICU_IM4_ISR_IR(irq_nr - INT_NUM_IM4_IRL0); /* ack */
+ }
+}
+
+static void amazon_enable_irq(unsigned int irq_nr)
+{
+ /* have to access the correct register here */
+ if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
+ /* access IM0 DMA*/
+ *AMAZON_ICU_IM0_IER |= AMAZON_DMA_H_MASK;
+ else if (irq_nr <= INT_NUM_IM0_IRL31 && irq_nr >= INT_NUM_IM0_IRL12)
+ /* access IM0 except DMA*/
+ *AMAZON_ICU_IM0_IER |= AMAZON_ICU_IM0_IER_IR(irq_nr - INT_NUM_IM0_IRL0);
+ else if (irq_nr <= INT_NUM_IM1_IRL31 && irq_nr >= INT_NUM_IM1_IRL0)
+ /* access IM1 */
+ *AMAZON_ICU_IM1_IER |= AMAZON_ICU_IM1_IER_IR(irq_nr - INT_NUM_IM1_IRL0);
+ else if (irq_nr <= INT_NUM_IM2_IRL31 && irq_nr >= INT_NUM_IM2_IRL0)
+ /* access IM2 */
+ *AMAZON_ICU_IM2_IER |= AMAZON_ICU_IM2_IER_IR(irq_nr - INT_NUM_IM2_IRL0);
+ else if (irq_nr <= INT_NUM_IM3_IRL31 && irq_nr >= INT_NUM_IM3_IRL0)
+ /* access IM3 */
+ *AMAZON_ICU_IM3_IER |= AMAZON_ICU_IM3_IER_IR((irq_nr - INT_NUM_IM3_IRL0));
+ else if (irq_nr <= INT_NUM_IM4_IRL31 && irq_nr >= INT_NUM_IM4_IRL0)
+ /* access IM4 */
+ *AMAZON_ICU_IM4_IER |= AMAZON_ICU_IM4_IER_IR((irq_nr - INT_NUM_IM4_IRL0));
+}
+
+static unsigned int amazon_startup_irq(unsigned int irq)
+{
+ amazon_enable_irq(irq);
+ return 0;
+}
+
+static void amazon_end_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+ amazon_enable_irq(irq);
+ }
+}
+
+static struct hw_interrupt_type amazon_irq_type = {
+ "AMAZON",
+ .startup = amazon_startup_irq,
+ .enable = amazon_enable_irq,
+ .disable = amazon_disable_irq,
+ .unmask = amazon_enable_irq,
+ .ack = amazon_mask_and_ack_irq,
+ .mask = amazon_disable_irq,
+ .mask_ack = amazon_mask_and_ack_irq,
+ .end = amazon_end_irq
+};
+
+/* Cascaded interrupts from IM0 */
+static inline void amazon_hw0_irqdispatch(void)
+{
+ u32 irq;
+
+ irq = (*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM0_VEC_MASK;
+ if (irq <= 11 && irq >= 0) {
+ //DMA fixed to IM0_IRL0
+ irq = 0;
+ }
+ do_IRQ(irq + INT_NUM_IM0_IRL0);
+}
+
+/* Cascaded interrupts from IM1 */
+static inline void amazon_hw1_irqdispatch(void)
+{
+ u32 irq;
+
+ irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM1_VEC_MASK) >> 5;
+ do_IRQ(irq + INT_NUM_IM1_IRL0);
+}
+
+/* Cascaded interrupts from IM2 */
+static inline void amazon_hw2_irqdispatch(void)
+{
+ u32 irq;
+
+ irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM2_VEC_MASK) >> 10;
+ do_IRQ(irq + INT_NUM_IM2_IRL0);
+}
+
+/* Cascaded interrupts from IM3 */
+static inline void amazon_hw3_irqdispatch(void)
+{
+ u32 irq;
+
+ irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM3_VEC_MASK) >> 15;
+ do_IRQ(irq + INT_NUM_IM3_IRL0);
+}
+
+/* Cascaded interrupts from IM4 */
+static inline void amazon_hw4_irqdispatch(void)
+{
+ u32 irq;
+
+ irq = ((*AMAZON_ICU_IM_VEC) & AMAZON_ICU_IM4_VEC_MASK) >> 20;
+ do_IRQ(irq + INT_NUM_IM4_IRL0);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+ if (pending & CAUSEF_IP7){
+ do_IRQ(MIPS_CPU_TIMER_IRQ);
+ }
+ else if (pending & CAUSEF_IP2)
+ amazon_hw0_irqdispatch();
+ else if (pending & CAUSEF_IP3)
+ amazon_hw1_irqdispatch();
+ else if (pending & CAUSEF_IP4)
+ amazon_hw2_irqdispatch();
+ else if (pending & CAUSEF_IP5)
+ amazon_hw3_irqdispatch();
+ else if (pending & CAUSEF_IP6)
+ amazon_hw4_irqdispatch();
+ else
+ printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+}
+
+static struct irqaction cascade = {
+ .handler = no_action,
+ .flags = SA_INTERRUPT,
+ .name = "cascade",
+};
+
+
+/* Function for careful CP0 interrupt mask access */
+
+void __init arch_init_irq(void)
+{
+ int i;
+
+ /* mask all interrupt sources */
+ *AMAZON_ICU_IM0_IER = 0;
+ *AMAZON_ICU_IM1_IER = 0;
+ *AMAZON_ICU_IM2_IER = 0;
+ *AMAZON_ICU_IM3_IER = 0;
+ *AMAZON_ICU_IM4_IER = 0;
+
+ mips_cpu_irq_init();
+
+ /* set up irq cascade */
+ for (i = 2; i <= 6; i++) {
+ setup_irq(i, &cascade);
+ }
+
+ for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = 0;
+ irq_desc[i].depth = 1;
+ set_irq_chip(i, &amazon_irq_type);
+ }
+}
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/pci.c b/target/linux/amazon-2.6/files/arch/mips/amazon/pci.c
new file mode 100644
index 000000000..ab305a983
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/pci.c
@@ -0,0 +1,293 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+/* FIXME: convert nasty volatile register derefs to readl/writel calls */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/paccess.h>
+#include <asm/amazon/irq.h>
+#include <asm/amazon/amazon.h>
+
+#define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr))
+#ifndef AMAZON_PCI_MEM_BASE
+#define AMAZON_PCI_MEM_BASE 0xb2000000
+#endif
+#define AMAZON_PCI_MEM_SIZE 0x00400000
+#define AMAZON_PCI_IO_BASE 0xb2400000
+#define AMAZON_PCI_IO_SIZE 0x00002000
+
+#define AMAZON_PCI_CFG_BUSNUM_SHF 16
+#define AMAZON_PCI_CFG_DEVNUM_SHF 11
+#define AMAZON_PCI_CFG_FUNNUM_SHF 8
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+static inline u32 amazon_r32(u32 addr)
+{
+ u32 *ptr = (u32 *) addr;
+ return __raw_readl(ptr);
+}
+
+static inline void amazon_w32(u32 addr, u32 val)
+{
+ u32 *ptr = (u32 *) addr;
+ __raw_writel(val, ptr);
+}
+
+
+static struct resource pci_io_resource = {
+ .name = "io pci IO space",
+#if 0
+ .start = AMAZON_PCI_IO_BASE,
+ .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
+#endif
+ .start = 0,
+ .end = AMAZON_PCI_IO_SIZE - 1,
+ .flags = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+ .name = "ext pci memory space",
+ .start = AMAZON_PCI_MEM_BASE,
+ .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM
+};
+
+static inline u32 amazon_pci_swap(u32 val)
+{
+#ifdef CONFIG_AMAZON_PCI_HW_SWAP
+ return swab32(val);
+#else
+ return val;
+#endif
+}
+
+static int amazon_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
+{
+ unsigned long flags;
+ u32 pci_addr;
+ u32 val;
+ int ret;
+
+ /* Amazon support slot from 0 to 15 */
+ /* devfn 0 & 0x20 is itself */
+ if ((bus != 0) || (devfn == 0) || (devfn == 0x20))
+ return 1;
+
+ pci_addr=AMAZON_PCI_CFG_BASE |
+ bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
+ devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
+ (where & ~0x3);
+
+ local_irq_save(flags);
+ if (access_type == PCI_ACCESS_WRITE) {
+ val = amazon_pci_swap(*data);
+ ret = put_dbe(val, (u32 *)pci_addr);
+ } else {
+ ret = get_dbe(val, (u32 *)pci_addr);
+ *data = amazon_pci_swap(val);
+ }
+
+ amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
+ amazon_w32(STATUS_COMMAND_ADDR, amazon_r32(STATUS_COMMAND_ADDR));
+ amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+
+static int amazon_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
+{
+ u32 data = 0;
+ int ret = PCIBIOS_SUCCESSFUL;
+
+ if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) {
+ data = ~0;
+ ret = -1;
+ }
+
+ switch (size) {
+ case 1:
+ *((u8 *) val) = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ *((u16 *) val) = (data >> ((where & 3) << 3)) & 0xffff;
+ break;
+ case 4:
+ *val = data;
+ break;
+ default:
+ return -1;
+ }
+
+ return ret;
+}
+
+
+static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
+{
+ if (size != 4) {
+ u32 data;
+
+ if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ if (size == 1)
+ val = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
+ else if (size == 2)
+ val = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3));
+ else
+ return -1;
+ }
+
+ if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops amazon_pci_ops = {
+ amazon_pci_read,
+ amazon_pci_write
+};
+
+static struct pci_controller amazon_pci_controller = {
+ .pci_ops = &amazon_pci_ops,
+ .mem_resource = &pci_mem_resource,
+ .io_resource = &pci_io_resource
+};
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ switch (slot) {
+ case 13:
+ /* IDSEL = AD29 --> USB Host Controller */
+ return INT_NUM_IM2_IRL15;
+ case 14:
+ /* IDSEL = AD30 --> mini PCI connector */
+ return INT_NUM_IM2_IRL14;
+ default:
+ printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
+ return 0;
+ }
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ switch(dev->irq) {
+ case INT_NUM_IM2_IRL15:
+ /*
+ * IDSEL = AD29 --> USB Host Controller
+ * PCI_INTA/B/C--GPIO Port0.2--EXIN3
+ * IN/ALT0:1 ALT1:0
+ * PULL UP
+ */
+ (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb;
+ (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4;
+ (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb;
+ (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4;
+ (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4;
+ //External Interrupt Node
+ (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */
+ (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ break;
+ case INT_NUM_IM2_IRL14:
+ /*
+ * IDSEL = AD30 --> mini PCI connector
+ * PCI_INTA--GPIO Port0.1--EXIN2
+ * IN/ALT0:1 ALT1:0
+ * PULL UP
+ */
+ (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd;
+ (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2;
+ (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd;
+ (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2;
+ (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2;
+ //External Interrupt Node
+ (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600;
+ (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ break;
+ default:
+ return 1;
+ }
+ return 0;
+}
+
+int amazon_pci_init(void)
+{
+ u32 temp_buffer;
+
+#ifdef CONFIG_AMAZON_PCI_HW_SWAP
+ AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
+ wmb();
+#endif
+
+ AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
+ amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)));
+
+ AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
+
+ temp_buffer = AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR);
+ temp_buffer = temp_buffer | (1<< INTERNAL_ARB_ENABLE_BIT);
+ temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_REQ_MASK_2BITS);
+ temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_GNT_MASK_2BITS);
+
+ /* flash */
+ temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_REQ_MASK_2BITS);
+ temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_GNT_MASK_2BITS);
+
+ /* external master */
+ temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_REQ_MASK_2BITS);
+ temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_GNT_MASK_2BITS);
+
+ AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR) = temp_buffer;
+ wmb();
+
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0) = 0xb2000000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1) = 0xb2100000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2) = 0xb2200000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3) = 0xb2300000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4) = 0xb2400000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
+ AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
+
+ AMAZON_PCI_REG32(BAR11_MASK) = 0x0f000008;
+ AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
+ AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
+ amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)));
+ //use 8 dw burse length
+ AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
+
+ set_io_port_base(ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE));
+ register_pci_controller(&amazon_pci_controller);
+ return 0;
+}
+arch_initcall(amazon_pci_init);
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/prom.c b/target/linux/amazon-2.6/files/arch/mips/amazon/prom.c
new file mode 100644
index 000000000..d60c3faa2
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/prom.c
@@ -0,0 +1,61 @@
+/*
+ * copyright 2007 john crispin <blogic@openwrt.org>
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/ioport.h>
+#include <asm/bootinfo.h>
+#include <asm/amazon/amazon.h>
+#include <asm/amazon/irq.h>
+#include <asm/amazon/model.h>
+#include <asm/cpu.h>
+
+void prom_putchar(char c)
+{
+ /* Wait for FIFO to empty */
+ while (((*AMAZON_ASC_FSTAT) >> 8) != 0x00) ;
+ /* Crude cr/nl handling is better than none */
+ if(c == '\n')
+ *AMAZON_ASC_TBUF=('\r');
+ *AMAZON_ASC_TBUF=(c);
+}
+
+void prom_printf(const char * fmt, ...)
+{
+ va_list args;
+ int l;
+ char *p, *buf_end;
+ char buf[1024];
+
+ va_start(args, fmt);
+ l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
+ va_end(args);
+ buf_end = buf + l;
+
+ for (p = buf; p < buf_end; p++)
+ prom_putchar(*p);
+}
+
+
+void __init prom_init(void)
+{
+ mips_machgroup = MACH_GROUP_INFINEON;
+ mips_machtype = MACH_INFINEON_AMAZON;
+
+ strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
+
+ add_memory_region(0x00000000, 0x1000000, BOOT_MEM_RAM);
+}
+
+void prom_free_prom_memory(void)
+{
+}
+
+const char *get_system_type(void)
+{
+ return BOARD_SYSTEM_TYPE;
+}
diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c b/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c
new file mode 100644
index 000000000..4cd3b9b97
--- /dev/null
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2004 Peng Liu <peng.liu@infineon.com>
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/amazon/amazon.h>
+#include <asm/amazon/irq.h>
+#include <asm/amazon/model.h>
+
+extern void prom_printf(const char * fmt, ...);
+static void amazon_reboot_setup(void);
+
+/* the CPU clock rate - lifted from u-boot */
+unsigned int amazon_get_cpu_hz(void)
+{
+ /*-----------------------------------*/
+ /**CGU CPU Clock Reduction Register***/
+ /*-----------------------------------*/
+ switch((*AMAZON_CGU_CPUCRD) & 0x3){
+ case 0:
+ /*divider ration 1/1, 235 MHz clock */
+ return 235000000;
+ case 1:
+ /*divider ration 2/3, 235 MHz clock, clock not accurate, here */
+ return 150000000;
+ case 2:
+ /*divider ration 1/2, 235 MHz clock */
+ return 117500000;
+ default:
+ /*divider ration 1/4, 235 MHz clock */
+ return 58750000;
+ }
+}
+
+/* the FPI clock rate - lifted from u-boot */
+unsigned int amazon_get_fpi_hz(void)
+{
+ unsigned int clkCPU;
+ clkCPU = amazon_get_cpu_hz();
+
+ /*-------------------------------------*/
+ /***CGU Clock Divider Select Register***/
+ /*-------------------------------------*/
+ switch ((*AMAZON_CGU_DIV) & 0x3)
+ {
+ case 1:
+ return clkCPU >> 1;
+ case 2:
+ return clkCPU >> 2;
+ default:
+ return clkCPU;
+ /* '11' is reserved */
+ }
+}
+
+/* get the CPU version number - based on sysLib.c from VxWorks sources */
+/* this doesn't really belong here, but it's a convenient location */
+unsigned int amazon_get_cpu_ver(void)
+{
+ static unsigned int cpu_ver = 0;
+ if (cpu_ver == 0)
+ cpu_ver = *AMAZON_MCD_CHIPID & 0xFFFFF000;
+ return cpu_ver;
+}
+
+void amazon_time_init(void)
+{
+ mips_hpt_frequency = amazon_get_cpu_hz()/2;
+ printk("mips_hpt_frequency:%d\n",mips_hpt_frequency);
+}
+
+extern int hr_time_resolution;
+
+/* ISR GPTU Timer 6 for high resolution timer */
+static void amazon_timer6_interrupt(int irq, void *dev_id)
+{
+ timer_interrupt(AMAZON_TIMER6_INT, NULL);
+}
+
+static struct irqaction hrt_irqaction = {
+ .handler = amazon_timer6_interrupt,
+ .flags = SA_INTERRUPT,
+ .name = "hrt",
+};
+
+/*
+ * THe CPU counter for System timer, set to HZ
+ * GPTU Timer 6 for high resolution timer, set to hr_time_resolution
+ * Also misuse this routine to print out the CPU type and clock.
+ */
+void __init plat_timer_setup(struct irqaction *irq)
+{
+ /* cpu counter for timer interrupts */
+ setup_irq(MIPS_CPU_TIMER_IRQ, irq);
+
+#if 0
+ /* to generate the first CPU timer interrupt */
+ write_c0_compare(read_c0_count() + amazon_get_cpu_hz()/(2*HZ));
+#endif
+
+ /* enable the timer in the PMU */
+ *(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;
+ /* setup the GPTU for timer tick f_fpi == f_gptu*/
+ *(AMAZON_GPTU_CLC) = 0x100;
+
+ *(AMAZON_GPTU_CAPREL) = 0xffff;
+ *(AMAZON_GPTU_T6CON) = 0x80C0;
+ //setup_irq(AMAZON_TIMER6_INT,&hrt_irqaction);
+
+#if 0
+#ifdef CONFIG_HIGH_RES_TIMERS
+ /* GPTU timer 6 */
+ int retval;
+ if ( hr_time_resolution > 200000000 || hr_time_resolution < 40) {
+ prom_printf("hr_time_resolution is out of range, HIGH_RES_TIMER is diabled.\n");
+ return;
+ }
+
+ /* enable the timer in the PMU */
+ *(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;
+ /* setup the GPTU for timer tick f_fpi == f_gptu*/
+ *(AMAZON_GPTU_CLC) = 0x100;
+
+ *(AMAZON_GPTU_CAPREL) = 0xffff;
+ *(AMAZON_GPTU_T6CON) = 0x80C0;
+
+ retval = setup_irq(AMAZON_TIMER6_INT,&hrt_irqaction);
+ if (retval){
+ prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n",AMAZON_TIMER6_INT);
+ }
+#endif //CONFIG_HIGH_RES_TIMERS
+#endif
+}
+
+void __init plat_mem_setup(void)
+{
+ u32 chipid = 0;
+ u32 part_no = 0;
+
+ chipid = *(AMAZON_MCD_CHIPID);
+ part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
+
+ if(part_no == AMAZON_CHIPID_YANGTSE){
+ prom_printf("Yangtse Version\n");
+ } else if (part_no == AMAZON_CHIPID_STANDARD) {
+ prom_printf(SYSTEM_MODEL_NAME "\n");
+ } else {
+ prom_printf("unknown version %8x\n",part_no);
+ }
+
+ amazon_reboot_setup();
+ board_time_init = amazon_time_init;
+
+ //stop reset TPE and DFE
+ *(AMAZON_RST_REQ) = 0x0;
+ //clock
+ *(AMAZON_PMU_PWDCR) = 0x3fff;
+ //reenable trace capability
+ part_no = *(AMAZON_BCU_ECON);
+}
+
+static void amazon_machine_restart(char *command)
+{
+ local_irq_disable();
+ *AMAZON_RST_REQ = AMAZON_RST_ALL;
+ for (;;) ;
+}
+
+static void amazon_machine_halt(void)
+{
+ printk(KERN_NOTICE "System halted.\n");
+ local_irq_disable();
+ for (;;) ;
+}
+
+static void amazon_machine_power_off(void)
+{
+ printk(KERN_NOTICE "Please turn off the power now.\n");
+ local_irq_disable();
+ for (;;) ;
+}
+
+static void amazon_reboot_setup(void)
+{
+ _machine_restart = amazon_machine_restart;
+ _machine_halt = amazon_machine_halt;
+ pm_power_off = amazon_machine_power_off;
+}