diff options
| author | florian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-06-14 11:59:31 +0000 |
|---|---|---|
| committer | florian <florian@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2007-06-14 11:59:31 +0000 |
| commit | 5da973430ee902e017d204f59dbf1a983dc1a3e8 (patch) | |
| tree | e25963dcf01a84d5e6ec73f7cc32b073ff477f79 /target/linux/adm5120-2.6/files/include | |
| parent | eb12a445c6e6708f497b18efd8590e3ecd6f4bec (diff) | |
Fix memory detection and hcd compilation, thanks Gabor ! (closes #1813)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7631 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/adm5120-2.6/files/include')
| -rw-r--r-- | target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h | 2 | ||||
| -rw-r--r-- | target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h | 13 |
2 files changed, 15 insertions, 0 deletions
diff --git a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h index c78c46b3b..b4730dc0f 100644 --- a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h +++ b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_info.h @@ -50,6 +50,8 @@ extern unsigned int adm5120_package; #define ADM5120_PACKAGE_PQFP 0 #define ADM5120_PACKAGE_BGA 1 +extern unsigned long adm5120_memsize; + extern void adm5120_info_init(void); static inline int adm5120_package_pqfp(void) diff --git a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h index a0fc1e44e..f7664587d 100644 --- a/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h +++ b/target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h @@ -85,6 +85,19 @@ #define CODE_PK_BGA 0 /* BGA package */ #define CODE_PK_PQFP 1 /* PQFP package */ +/* MEMCTRL register bits */ +#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */ +#define MEMCTRL_SDRS_4M 0x01 +#define MEMCTRL_SDRS_8M 0x02 +#define MEMCTRL_SDRS_16M 0x03 +#define MEMCTRL_SDRS_64M 0x04 +#define MEMCTRL_SDRS_128M 0x05 +#define MEMCTRL_SDR1_ENABLE ONEBIT(5) /* enable SDRAM bank 1 */ +#define MEMCTRL_SR0S_MASK BITMASK(3) /* SRAM0 size */ +#define MEMCTRL_SR0S_SHIFT 8 +#define MEMCTRL_SR1S_MASK BITMAKS(3) /* SRAM1 size */ +#define MEMCTRL_SR1S_SHIFT 16 + /* GPIO_CONF0 register bits */ #define GPIO_CONF0_MASK BITMASK(8) #define GPIO_CONF0_IM_SHIFT 0 |