diff options
| author | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-02-24 07:41:10 +0000 |
|---|---|---|
| committer | blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2011-02-24 07:41:10 +0000 |
| commit | f40a767b0d5c43234a6e026c48e1c59fa1980963 (patch) | |
| tree | f4b2252c206039808ad9c54fbe62bb8419d4ec22 /package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h | |
| parent | ec4b08c1c100022f22b8f897d79d003e11c3c254 (diff) | |
[uboot-lantiq]
* adds stage1 lzma
* new boards
* fixes settings for PSC ram
* lost of cleanups
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25694 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h')
| -rw-r--r-- | package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h b/package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h deleted file mode 100644 index e1ab36d45..000000000 --- a/package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0xc0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x100 -#define MC_DC4_VALUE 0xd0f -#define MC_DC5_VALUE 0x204 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0xd47 -#define MC_DC22_VALUE 0xd0d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x2040 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -#define MC_DC46_VALUE 0x0 |