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authorluka <luka@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-07-14 23:54:20 +0000
committerluka <luka@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-07-14 23:54:20 +0000
commit2bc7082f7376cd910b240cae08cfcc103b321fc2 (patch)
treec8ae6d5cda92fb35eee6ea40f7f6f77ba87a7a51 /package/uboot-kirkwood/files/board
parentbeecfa6085aa6b523cbe9101e81112c472c44421 (diff)
[package] uboot-kirkwood: update to 2012.04.01
iConnect board tested by: Tim Fletcher <tim@night-shade.org.uk> Wojciech Dubowik <wojciech.dubowik@neratec.com> DockStar board tested by: Martin Mueller <mm@sig21.net> RaidSonic ICY BOX NAS6210 board tested by: Luka Perkov <uboot@lukaperkov.net> SheevaPlug was not tested but support for SheevaPlug is taken from upstream uboot and it is not reported to be broken there. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32717 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/uboot-kirkwood/files/board')
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/dockstar/Makefile51
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/dockstar/config.mk28
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.c155
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.h41
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/dockstar/kwbimage.cfg162
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/iconnect/config.mk28
-rw-r--r--package/uboot-kirkwood/files/board/Marvell/iconnect/kwbimage.cfg162
-rw-r--r--package/uboot-kirkwood/files/board/iomega/iconnect/Makefile (renamed from package/uboot-kirkwood/files/board/Marvell/iconnect/Makefile)16
-rw-r--r--package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c (renamed from package/uboot-kirkwood/files/board/Marvell/iconnect/iconnect.c)42
-rw-r--r--package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h (renamed from package/uboot-kirkwood/files/board/Marvell/iconnect/iconnect.h)12
-rw-r--r--package/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg165
11 files changed, 188 insertions, 674 deletions
diff --git a/package/uboot-kirkwood/files/board/Marvell/dockstar/Makefile b/package/uboot-kirkwood/files/board/Marvell/dockstar/Makefile
deleted file mode 100644
index da9d29ea1..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/dockstar/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := dockstar.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/package/uboot-kirkwood/files/board/Marvell/dockstar/config.mk b/package/uboot-kirkwood/files/board/Marvell/dockstar/config.mk
deleted file mode 100644
index 176641260..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/dockstar/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00800000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.c b/package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.c
deleted file mode 100644
index 13cd3474b..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/mpp.h>
-#include "dockstar.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
- DOCKSTAR_OE_VAL_HIGH,
- DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_UART0_RTS,
- MPP9_UART0_CTS,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_TSMP9,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config);
-
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.h b/package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.h
deleted file mode 100644
index 33f8b1947..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/dockstar/dockstar.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __DOCKSTAR_H
-#define __DOCKSTAR_H
-
-#define DOCKSTAR_OE_LOW (~(0))
-#define DOCKSTAR_OE_HIGH (~(0))
-#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
-#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __DOCKSTAR_H */
diff --git a/package/uboot-kirkwood/files/board/Marvell/dockstar/kwbimage.cfg b/package/uboot-kirkwood/files/board/Marvell/dockstar/kwbimage.cfg
deleted file mode 100644
index 3b9c53f57..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/dockstar/kwbimage.cfg
+++ /dev/null
@@ -1,162 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.kwimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/package/uboot-kirkwood/files/board/Marvell/iconnect/config.mk b/package/uboot-kirkwood/files/board/Marvell/iconnect/config.mk
deleted file mode 100644
index 2bd9f79fc..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/iconnect/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/package/uboot-kirkwood/files/board/Marvell/iconnect/kwbimage.cfg b/package/uboot-kirkwood/files/board/Marvell/iconnect/kwbimage.cfg
deleted file mode 100644
index 37042f5a4..000000000
--- a/package/uboot-kirkwood/files/board/Marvell/iconnect/kwbimage.cfg
+++ /dev/null
@@ -1,162 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.kwimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/package/uboot-kirkwood/files/board/Marvell/iconnect/Makefile b/package/uboot-kirkwood/files/board/iomega/iconnect/Makefile
index 0301f987c..f77fcfb99 100644
--- a/package/uboot-kirkwood/files/board/Marvell/iconnect/Makefile
+++ b/package/uboot-kirkwood/files/board/iomega/iconnect/Makefile
@@ -13,18 +13,16 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := iconnect.o
@@ -33,13 +31,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
diff --git a/package/uboot-kirkwood/files/board/Marvell/iconnect/iconnect.c b/package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c
index ee5d5875e..34ddadf8a 100644
--- a/package/uboot-kirkwood/files/board/Marvell/iconnect/iconnect.c
+++ b/package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c
@@ -1,7 +1,7 @@
/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -17,25 +17,24 @@
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <miiphy.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "iconnect.h"
DECLARE_GLOBAL_DATA_PTR;
-int board_init(void)
+int board_early_init_f(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
+ * the below configuration configures mainly initial LED status
*/
kw_config_gpio(ICONNECT_OE_VAL_LOW,
ICONNECT_OE_VAL_HIGH,
@@ -94,33 +93,21 @@ int board_init(void)
MPP48_GPIO,
MPP49_GPIO,
0
-};
+ };
kirkwood_mpp_conf(kwmpp_config);
-
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_ICONNECT;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
return 0;
}
-int dram_init(void)
+int board_init(void)
{
- int i;
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
- }
return 0;
}
#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
+/* Configure and initialize PHY */
void reset_phy(void)
{
u16 reg;
@@ -132,8 +119,7 @@ void reset_phy(void)
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
+ printf("Err..(%s) could not read PHY dev address\n", __func__);
return;
}
@@ -150,6 +136,6 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, devadr);
- printf("88E1116 Initialized on %s\n", name);
+ debug("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */
diff --git a/package/uboot-kirkwood/files/board/Marvell/iconnect/iconnect.h b/package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h
index 4774c0757..2fb3e5ed8 100644
--- a/package/uboot-kirkwood/files/board/Marvell/iconnect/iconnect.h
+++ b/package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h
@@ -1,7 +1,7 @@
/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -17,16 +17,14 @@
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ICONNECT_H
#define __ICONNECT_H
#define ICONNECT_OE_LOW (~(1 << 7))
-#define ICONNECT_OE_HIGH (~(1 << 10))
+#define ICONNECT_OE_HIGH (~(1 << 10))
#define ICONNECT_OE_VAL_LOW (0)
#define ICONNECT_OE_VAL_HIGH (1 << 10)
diff --git a/package/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg b/package/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg
new file mode 100644
index 000000000..dee546a52
--- /dev/null
+++ b/package/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg
@@ -0,0 +1,165 @@
+#
+# (C) Copyright 2009-2012
+# Wojciech Dubowik <wojciech.dubowik@neratec.com>
+# Luka Perkov <uboot@lukaperkov.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24: 0x1, enable exit self refresh mode on DDR access
+# bit25: 0x1, required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
+# bit4: 0x0, addr/cmd in smame cycle
+# bit5: 0x0, clk is driven during self refresh, we don't care for APX
+# bit6: 0x0, use recommended falling edge of clk for addr/cmd
+# bit14: 0x0, input buffer always powered up
+# bit18: 0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31: 0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11-8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width (x8)
+# bit3-2: 11, Cs0size (1Gb)
+# bit5-4: 00, Cs1width (x8)
+# bit7-6: 11, Cs1size (1Gb)
+# bit9-8: 00, Cs2width (nonexistent)
+# bit11-10: 00, Cs2size (nonexistent)
+# bit13-12: 00, Cs3width (nonexistent)
+# bit15-14: 00, Cs3size (nonexistent)
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0x0, required
+
+DATA 0xffd0141c 0x00000c52 # DDR Mode
+# bit2-0: 0x2, BurstLen=2 required
+# bit3: 0x0, BurstType=0 required
+# bit6-4: 0x4, CL=5
+# bit7: 0x0, TestMode=0 normal
+# bit8: 0x0, DLL reset=0 normal
+# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit12: 0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 0x0, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 0x0, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
+# bit2-0: 0x7, required
+# bit3: 0x1, MBUS Burst Chop disabled
+# bit6-4: 0x7, required
+# bit7: 0x0,
+# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0x0, no half clock cycle addition to dataout
+# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0x0, required
+
+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
+# bit0: 0x1, Window enabled
+# bit1: 0x0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff, required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
+DATA 0xffd01480 0x00000001 # DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0