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authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2010-11-11 22:39:12 +0000
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2010-11-11 22:39:12 +0000
commitb8702bf547fc3fc1d363e15202a24cd123ac4e7b (patch)
treee3494ed1cacb1e258cc117559a923684a740b3c5 /package/mac80211/patches
parentef689f44dbb1a9d77459d24cc66dfa05fe285e9c (diff)
mac80211: update to wireless-testing 2010-11-10 + some pending work
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23968 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/mac80211/patches')
-rw-r--r--package/mac80211/patches/008-led_default.patch8
-rw-r--r--package/mac80211/patches/012-remove_rfkill.patch33
-rw-r--r--package/mac80211/patches/030-backport_93c86_eeprom.patch6
-rw-r--r--package/mac80211/patches/100-disable_pcmcia_compat.patch8
-rw-r--r--package/mac80211/patches/110-disable_usb_compat.patch4
-rw-r--r--package/mac80211/patches/300-ath9k_gpio_settings.patch (renamed from package/mac80211/patches/310-ath9k_gpio_settings.patch)8
-rw-r--r--package/mac80211/patches/300-nl80211_dump_crash_fix.patch13
-rw-r--r--package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch8
-rw-r--r--package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch2
-rw-r--r--package/mac80211/patches/409-ath9k_platform_settings.patch8
-rw-r--r--package/mac80211/patches/500-ath9k_eeprom_debugfs.patch6
-rw-r--r--package/mac80211/patches/510-ath9k_aggr_delim_fix.patch13
-rw-r--r--package/mac80211/patches/510-pending_work.patch3644
-rw-r--r--package/mac80211/patches/520-ath9k_ar9003_regulatory_power.patch18
-rw-r--r--package/mac80211/patches/521-ath9k_hw_tx_power.patch327
-rw-r--r--package/mac80211/patches/522-ath9k_tx_power_init.patch115
-rw-r--r--package/mac80211/patches/530-ath9k_locking_fix.patch363
-rw-r--r--package/mac80211/patches/540-ath9k_fix_survey_crash.patch12
-rw-r--r--package/mac80211/patches/550-ath9k_xretry_fix.patch25
-rw-r--r--package/mac80211/patches/560-ath9k_aggr_sampling_fix.patch22
-rw-r--r--package/mac80211/patches/561-minstrel_sample_retransmit.patch13
-rw-r--r--package/mac80211/patches/562-minstrel_sample_performance.patch52
-rw-r--r--package/mac80211/patches/570-ath9k_reset_aggr_fix.patch42
-rw-r--r--package/mac80211/patches/571-ath9k_ar9300_aggr_flush.patch34
-rw-r--r--package/mac80211/patches/572-ath9k_xmit_queue_cleanup.patch714
-rw-r--r--package/mac80211/patches/580-cfg80211_ibss_mcast_rate.patch58
-rw-r--r--package/mac80211/patches/581-mac80211_ibss_mcast_rate.patch106
-rw-r--r--package/mac80211/patches/590-ath9k_fix_cycle_counter_ps.patch33
-rw-r--r--package/mac80211/patches/591-ath9k_swba_intr_fix.patch20
-rw-r--r--package/mac80211/patches/601-rt2x00-fix-hang-on-ifdown.patch2
-rw-r--r--package/mac80211/patches/700-mwl8k-missing-pci-id-for-WNR854T.patch2
-rw-r--r--package/mac80211/patches/800-b43-gpio-mask-module-option.patch2
-rw-r--r--package/mac80211/patches/900-bash-location.patch128
33 files changed, 3676 insertions, 2173 deletions
diff --git a/package/mac80211/patches/008-led_default.patch b/package/mac80211/patches/008-led_default.patch
index 5a2105bbd..be4f8e855 100644
--- a/package/mac80211/patches/008-led_default.patch
+++ b/package/mac80211/patches/008-led_default.patch
@@ -81,7 +81,7 @@
void ath_deinit_leds(struct ath_softc *sc)
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
-@@ -860,6 +860,7 @@ static void ath9k_led_brightness_work(st
+@@ -822,6 +822,7 @@ static void ath9k_led_brightness_work(st
}
}
@@ -89,7 +89,7 @@
static void ath9k_led_brightness(struct led_classdev *led_cdev,
enum led_brightness brightness)
{
-@@ -871,6 +872,7 @@ static void ath9k_led_brightness(struct
+@@ -833,6 +834,7 @@ static void ath9k_led_brightness(struct
ieee80211_queue_delayed_work(priv->hw,
&led->brightness_work, 0);
}
@@ -97,7 +97,7 @@
static void ath9k_led_stop_brightness(struct ath9k_htc_priv *priv)
{
-@@ -883,6 +885,7 @@ static void ath9k_led_stop_brightness(st
+@@ -845,6 +847,7 @@ static void ath9k_led_stop_brightness(st
static int ath9k_register_led(struct ath9k_htc_priv *priv, struct ath_led *led,
char *trigger)
{
@@ -105,7 +105,7 @@
int ret;
led->priv = priv;
-@@ -900,14 +903,19 @@ static int ath9k_register_led(struct ath
+@@ -862,14 +865,19 @@ static int ath9k_register_led(struct ath
INIT_DELAYED_WORK(&led->brightness_work, ath9k_led_brightness_work);
return ret;
diff --git a/package/mac80211/patches/012-remove_rfkill.patch b/package/mac80211/patches/012-remove_rfkill.patch
deleted file mode 100644
index ae80b6ef9..000000000
--- a/package/mac80211/patches/012-remove_rfkill.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/net/wireless/ath/ath5k/base.h
-+++ b/drivers/net/wireless/ath/ath5k/base.h
-@@ -46,7 +46,7 @@
- #include <linux/wireless.h>
- #include <linux/if_ether.h>
- #include <linux/leds.h>
--#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31))
-+#if 0
- #include <linux/rfkill.h>
- #else
- #include <linux/rfkill_backport.h>
---- a/net/wireless/core.h
-+++ b/net/wireless/core.h
-@@ -11,7 +11,7 @@
- #include <linux/kref.h>
- #include <linux/rbtree.h>
- #include <linux/debugfs.h>
--#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31))
-+#if 0
- #include <linux/rfkill.h>
- #else
- #include <linux/rfkill_backport.h>
---- a/include/linux/rfkill_backport.h
-+++ b/include/linux/rfkill_backport.h
-@@ -149,7 +149,7 @@ struct rfkill_ops {
- int (*set_block)(void *data, bool blocked);
- };
-
--#if defined(CONFIG_RFKILL_BACKPORT) || defined(CONFIG_RFKILL_BACKPORT_MODULE)
-+#if 0
- /**
- * rfkill_alloc - allocate rfkill structure
- * @name: name of the struct -- the string is not copied internally
diff --git a/package/mac80211/patches/030-backport_93c86_eeprom.patch b/package/mac80211/patches/030-backport_93c86_eeprom.patch
index ac568f7f2..be91eafb8 100644
--- a/package/mac80211/patches/030-backport_93c86_eeprom.patch
+++ b/package/mac80211/patches/030-backport_93c86_eeprom.patch
@@ -1,8 +1,8 @@
--- a/include/linux/compat-2.6.36.h
+++ b/include/linux/compat-2.6.36.h
-@@ -56,6 +56,8 @@ static inline int pcmcia_write_config_by
- return pcmcia_access_configuration_register(p_dev, &reg);
- }
+@@ -90,6 +90,8 @@ struct pm_qos_request_list {
+
+ #endif
+#define PCI_EEPROM_WIDTH_93C86 8
+
diff --git a/package/mac80211/patches/100-disable_pcmcia_compat.patch b/package/mac80211/patches/100-disable_pcmcia_compat.patch
index affdc3864..a88d1f590 100644
--- a/package/mac80211/patches/100-disable_pcmcia_compat.patch
+++ b/package/mac80211/patches/100-disable_pcmcia_compat.patch
@@ -1,6 +1,6 @@
--- a/compat/compat-2.6.28.c
+++ b/compat/compat-2.6.28.c
-@@ -89,7 +89,7 @@ EXPORT_SYMBOL_GPL(usb_poison_urb);
+@@ -86,7 +86,7 @@ EXPORT_SYMBOL_GPL(usb_poison_urb);
#endif
#endif /* CONFIG_USB */
@@ -11,8 +11,8 @@
struct pcmcia_cfg_mem {
--- a/compat/compat-2.6.33.c
+++ b/compat/compat-2.6.33.c
-@@ -14,7 +14,7 @@
-
+@@ -11,7 +11,7 @@
+ #include <linux/compat.h>
#include <linux/autoconf.h>
-#if defined(CONFIG_PCCARD) || defined(CONFIG_PCCARD_MODULE)
@@ -20,7 +20,7 @@
/**
* pccard_loop_tuple() - loop over tuples in the CIS
-@@ -76,7 +76,7 @@ next_entry:
+@@ -73,7 +73,7 @@ next_entry:
EXPORT_SYMBOL(pccard_loop_tuple);
/* Source: drivers/pcmcia/cistpl.c */
diff --git a/package/mac80211/patches/110-disable_usb_compat.patch b/package/mac80211/patches/110-disable_usb_compat.patch
index 5c9147c77..a07e978bd 100644
--- a/package/mac80211/patches/110-disable_usb_compat.patch
+++ b/package/mac80211/patches/110-disable_usb_compat.patch
@@ -1,6 +1,6 @@
--- a/compat/compat-2.6.28.c
+++ b/compat/compat-2.6.28.c
-@@ -168,7 +168,7 @@ EXPORT_SYMBOL(pcmcia_loop_config);
+@@ -165,7 +165,7 @@ EXPORT_SYMBOL(pcmcia_loop_config);
#endif /* CONFIG_PCMCIA */
@@ -11,7 +11,7 @@
{
--- a/compat/compat-2.6.29.c
+++ b/compat/compat-2.6.29.c
-@@ -52,7 +52,7 @@ void netdev_attach_ops(struct net_device
+@@ -49,7 +49,7 @@ void netdev_attach_ops(struct net_device
EXPORT_SYMBOL(netdev_attach_ops);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23))
diff --git a/package/mac80211/patches/310-ath9k_gpio_settings.patch b/package/mac80211/patches/300-ath9k_gpio_settings.patch
index f3c8db3f6..2bee61011 100644
--- a/package/mac80211/patches/310-ath9k_gpio_settings.patch
+++ b/package/mac80211/patches/300-ath9k_gpio_settings.patch
@@ -1,6 +1,6 @@
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -920,6 +920,12 @@ int ath9k_init_debug(struct ath_hw *ah)
+@@ -932,6 +932,12 @@ int ath9k_init_debug(struct ath_hw *ah)
sc->debug.debugfs_phy, &ah->config.cwm_ignore_extcca))
goto err;
@@ -15,7 +15,7 @@
err:
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -743,6 +743,8 @@ struct ath_hw {
+@@ -751,6 +751,8 @@ struct ath_hw {
int initPDADC;
int PDADCdelta;
u8 led_pin;
@@ -26,7 +26,7 @@
struct ar5416IniArray iniCommon;
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1178,6 +1178,20 @@ static bool ath9k_hw_channel_change(stru
+@@ -1182,6 +1182,20 @@ static bool ath9k_hw_channel_change(stru
return true;
}
@@ -47,7 +47,7 @@
bool ath9k_hw_check_alive(struct ath_hw *ah)
{
int count = 50;
-@@ -1464,6 +1478,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1468,6 +1482,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
if (AR_SREV_9300_20_OR_LATER(ah))
ar9003_hw_bb_watchdog_config(ah);
diff --git a/package/mac80211/patches/300-nl80211_dump_crash_fix.patch b/package/mac80211/patches/300-nl80211_dump_crash_fix.patch
deleted file mode 100644
index 3c6385f89..000000000
--- a/package/mac80211/patches/300-nl80211_dump_crash_fix.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/net/wireless/nl80211.c
-+++ b/net/wireless/nl80211.c
-@@ -224,8 +224,8 @@ static int nl80211_prepare_netdev_dump(s
- }
-
- *rdev = cfg80211_get_dev_from_ifindex(sock_net(skb->sk), ifidx);
-- if (IS_ERR(dev)) {
-- err = PTR_ERR(dev);
-+ if (IS_ERR(*rdev)) {
-+ err = PTR_ERR(*rdev);
- goto out_rtnl;
- }
-
diff --git a/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch b/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch
index 615bce561..87ea00a2a 100644
--- a/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch
+++ b/package/mac80211/patches/406-ath9k-set-AH_USE_EEPROM-only-if-no-platform-data-present.patch
@@ -1,16 +1,16 @@
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -15,6 +15,7 @@
- */
+@@ -16,6 +16,7 @@
#include <linux/nl80211.h>
+ #include <linux/pm_qos_params.h>
+#include <linux/ath9k_platform.h>
#include "ath9k.h"
#include "btcoex.h"
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -559,6 +559,7 @@ static int ath9k_init_softc(u16 devid, s
+@@ -522,6 +522,7 @@ static int ath9k_init_softc(u16 devid, s
{
struct ath_hw *ah = NULL;
struct ath_common *common;
@@ -18,7 +18,7 @@
int ret = 0, i;
int csz = 0;
-@@ -570,6 +571,10 @@ static int ath9k_init_softc(u16 devid, s
+@@ -533,6 +534,10 @@ static int ath9k_init_softc(u16 devid, s
ah->hw_version.subsysid = subsysid;
sc->sc_ah = ah;
diff --git a/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch b/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch
index d12a53244..0b0197aa9 100644
--- a/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch
+++ b/package/mac80211/patches/408-ath9k_tweak_rx_intr_mitigation.patch
@@ -1,6 +1,6 @@
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1434,7 +1434,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1438,7 +1438,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
if (ah->config.rx_intr_mitigation) {
REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
diff --git a/package/mac80211/patches/409-ath9k_platform_settings.patch b/package/mac80211/patches/409-ath9k_platform_settings.patch
index 3355d955a..ef3035cb2 100644
--- a/package/mac80211/patches/409-ath9k_platform_settings.patch
+++ b/package/mac80211/patches/409-ath9k_platform_settings.patch
@@ -1,14 +1,14 @@
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -16,6 +16,7 @@
-
+@@ -17,6 +17,7 @@
#include <linux/slab.h>
+ #include <linux/pm_qos_params.h>
+#include "linux/ath9k_platform.h"
#include "ath9k.h"
static char *dev_info = "ath9k";
-@@ -572,8 +573,14 @@ static int ath9k_init_softc(u16 devid, s
+@@ -535,8 +536,14 @@ static int ath9k_init_softc(u16 devid, s
sc->sc_ah = ah;
pdata = (struct ath9k_platform_data *) sc->dev->platform_data;
@@ -26,7 +26,7 @@
common->ops = &ath9k_common_ops;
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -742,7 +742,7 @@ struct ath_hw {
+@@ -750,7 +750,7 @@ struct ath_hw {
u32 originalGain[22];
int initPDADC;
int PDADCdelta;
diff --git a/package/mac80211/patches/500-ath9k_eeprom_debugfs.patch b/package/mac80211/patches/500-ath9k_eeprom_debugfs.patch
index 26c045cd9..eaf51310e 100644
--- a/package/mac80211/patches/500-ath9k_eeprom_debugfs.patch
+++ b/package/mac80211/patches/500-ath9k_eeprom_debugfs.patch
@@ -1,7 +1,7 @@
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -861,6 +861,53 @@ static const struct file_operations fops
- .owner = THIS_MODULE
+@@ -873,6 +873,53 @@ static const struct file_operations fops
+ .llseek = default_llseek,
};
+static ssize_t read_file_eeprom(struct file *file, char __user *user_buf,
@@ -54,7 +54,7 @@
int ath9k_init_debug(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
-@@ -926,6 +973,10 @@ int ath9k_init_debug(struct ath_hw *ah)
+@@ -938,6 +985,10 @@ int ath9k_init_debug(struct ath_hw *ah)
debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
sc->debug.debugfs_phy, &sc->sc_ah->gpio_val);
diff --git a/package/mac80211/patches/510-ath9k_aggr_delim_fix.patch b/package/mac80211/patches/510-ath9k_aggr_delim_fix.patch
deleted file mode 100644
index a34ff9264..000000000
--- a/package/mac80211/patches/510-ath9k_aggr_delim_fix.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ath9k.h
-+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
-@@ -177,8 +177,8 @@ void ath_descdma_cleanup(struct ath_soft
-
- /* returns delimiter padding required given the packet length */
- #define ATH_AGGR_GET_NDELIM(_len) \
-- (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
-- (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
-+ (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
-+ DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
-
- #define BAW_WITHIN(_start, _bawsz, _seqno) \
- ((((_seqno) - (_start)) & 4095) < (_bawsz))
diff --git a/package/mac80211/patches/510-pending_work.patch b/package/mac80211/patches/510-pending_work.patch
new file mode 100644
index 000000000..c4c589cf5
--- /dev/null
+++ b/package/mac80211/patches/510-pending_work.patch
@@ -0,0 +1,3644 @@
+--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+@@ -1579,6 +1579,37 @@ static void ar5008_hw_set_nf_limits(stru
+ ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
+ }
+
++static void ar5008_hw_set_radar_params(struct ath_hw *ah,
++ struct ath_hw_radar_conf *conf)
++{
++ u32 radar_0 = 0, radar_1 = 0;
++
++ if (!conf) {
++ REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
++ return;
++ }
++
++ radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
++ radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
++ radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
++ radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
++ radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
++ radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
++
++ radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
++ radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
++ radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
++ radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
++ radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
++
++ REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
++ REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
++ if (conf->ext_channel)
++ REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
++ else
++ REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
++}
++
+ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
+ {
+ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+@@ -1609,6 +1640,7 @@ void ar5008_hw_attach_phy_ops(struct ath
+ priv_ops->restore_chainmask = ar5008_restore_chainmask;
+ priv_ops->set_diversity = ar5008_set_diversity;
+ priv_ops->do_getnf = ar5008_hw_do_getnf;
++ priv_ops->set_radar_params = ar5008_hw_set_radar_params;
+
+ if (modparam_force_new_ani) {
+ priv_ops->ani_control = ar5008_hw_ani_control_new;
+--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+@@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct at
+ struct ath9k_channel *chan)
+ {
+ struct ath_common *common = ath9k_hw_common(ah);
++ int val;
+
+- /*
+- * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
+- * running AGC/TxIQ cals
+- */
+- ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
++ val = REG_READ(ah, AR_ENT_OTP);
++ ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
++
++ if (val & AR_ENT_OTP_CHAIN2_DISABLE)
++ ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
++ else
++ /*
++ * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
++ * mode before running AGC/TxIQ cals
++ */
++ ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
+
+ /* Do Tx IQ Calibration */
+ ar9003_hw_tx_iq_cal(ah);
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -22,12 +22,14 @@
+ #define COMP_CKSUM_LEN 2
+
+ #define AR_CH0_TOP (0x00016288)
+-#define AR_CH0_TOP_XPABIASLVL (0x3)
++#define AR_CH0_TOP_XPABIASLVL (0x300)
+ #define AR_CH0_TOP_XPABIASLVL_S (8)
+
+ #define AR_CH0_THERM (0x00016290)
+-#define AR_CH0_THERM_SPARE (0x3f)
+-#define AR_CH0_THERM_SPARE_S (0)
++#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
++#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
++#define AR_CH0_THERM_XPASHORT2GND 0x4
++#define AR_CH0_THERM_XPASHORT2GND_S 2
+
+ #define AR_SWITCH_TABLE_COM_ALL (0xffff)
+ #define AR_SWITCH_TABLE_COM_ALL_S (0)
+@@ -55,15 +57,2327 @@
+ #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
+ #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
+
++static int ar9003_hw_power_interpolate(int32_t x,
++ int32_t *px, int32_t *py, u_int16_t np);
+ static const struct ar9300_eeprom ar9300_default = {
+ .eepromVersion = 2,
+- .templateVersion = 2,
+- .macAddr = {1, 2, 3, 4, 5, 6},
+- .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
++ .templateVersion = 2,
++ .macAddr = {1, 2, 3, 4, 5, 6},
++ .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
++ .baseEepHeader = {
++ .regDmn = { LE16(0), LE16(0x1f) },
++ .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
++ .opCapFlags = {
++ .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
++ .eepMisc = 0,
++ },
++ .rfSilent = 0,
++ .blueToothOptions = 0,
++ .deviceCap = 0,
++ .deviceType = 5, /* takes lower byte in eeprom location */
++ .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
++ .params_for_tuning_caps = {0, 0},
++ .featureEnable = 0x0c,
++ /*
++ * bit0 - enable tx temp comp - disabled
++ * bit1 - enable tx volt comp - disabled
++ * bit2 - enable fastClock - enabled
++ * bit3 - enable doubling - enabled
++ * bit4 - enable internal regulator - disabled
++ * bit5 - enable pa predistortion - disabled
++ */
++ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
++ .eepromWriteEnableGpio = 3,
++ .wlanDisableGpio = 0,
++ .wlanLedGpio = 8,
++ .rxBandSelectGpio = 0xff,
++ .txrxgain = 0,
++ .swreg = 0,
++ },
++ .modalHeader2G = {
++ /* ar9300_modal_eep_header 2g */
++ /* 4 idle,t1,t2,b(4 bits per setting) */
++ .antCtrlCommon = LE32(0x110),
++ /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
++ .antCtrlCommon2 = LE32(0x22222),
++
++ /*
++ * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
++ * rx1, rx12, b (2 bits each)
++ */
++ .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
++
++ /*
++ * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
++ * for ar9280 (0xa20c/b20c 5:0)
++ */
++ .xatten1DB = {0, 0, 0},
++
++ /*
++ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
++ * for ar9280 (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0, 0, 0},
++ .tempSlope = 36,
++ .voltSlope = 0,
++
++ /*
++ * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
++ * channels in usual fbin coding format
++ */
++ .spurChans = {0, 0, 0, 0, 0},
++
++ /*
++ * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
++ * if the register is per chain
++ */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {1, 1, 1},/* 3 chain */
++ .db_stage2 = {1, 1, 1}, /* 3 chain */
++ .db_stage3 = {0, 0, 0},
++ .db_stage4 = {0, 0, 0},
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2c,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
++ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext1 = {
++ .ant_div_control = 0,
++ .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
++ },
++ .calFreqPier2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1),
++ },
++ /* ar9300_cal_data_per_freq_op_loop 2g */
++ .calPierData2G = {
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ },
++ .calTarget_freqbin_Cck = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2484, 1),
++ },
++ .calTarget_freqbin_2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT20 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT40 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTargetPowerCck = {
++ /* 1L-5L,5S,11L,11S */
++ { {36, 36, 36, 36} },
++ { {36, 36, 36, 36} },
++ },
++ .calTargetPower2G = {
++ /* 6-24,36,48,54 */
++ { {32, 32, 28, 24} },
++ { {32, 32, 28, 24} },
++ { {32, 32, 28, 24} },
++ },
++ .calTargetPower2GHT20 = {
++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ },
++ .calTargetPower2GHT40 = {
++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ },
++ .ctlIndex_2G = {
++ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
++ 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
++ },
++ .ctl_freqbin_2G = {
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2457, 1),
++ FREQ2FBIN(2462, 1)
++ },
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++ {
++ FREQ2FBIN(2422, 1),
++ FREQ2FBIN(2427, 1),
++ FREQ2FBIN(2447, 1),
++ FREQ2FBIN(2452, 1)
++ },
++
++ {
++ /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
++ },
++
++ {
++ /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
++ /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
++ /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
++ /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
++ },
++
++ {
++ /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ },
++
++ {
++ /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
++ /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
++ /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
++ /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
++ }
++ },
++ .ctlPowerData_2G = {
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++
++ { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ },
++ .modalHeader5G = {
++ /* 4 idle,t1,t2,b (4 bits per setting) */
++ .antCtrlCommon = LE32(0x110),
++ /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
++ .antCtrlCommon2 = LE32(0x22222),
++ /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
++ .antCtrlChain = {
++ LE16(0x000), LE16(0x000), LE16(0x000),
++ },
++ /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
++ .xatten1DB = {0, 0, 0},
++
++ /*
++ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
++ * for merlin (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0, 0, 0},
++ .tempSlope = 68,
++ .voltSlope = 0,
++ /* spurChans spur channels in usual fbin coding format */
++ .spurChans = {0, 0, 0, 0, 0},
++ /* noiseFloorThreshCh Check if the register is per chain */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {3, 3, 3}, /* 3 chain */
++ .db_stage2 = {3, 3, 3}, /* 3 chain */
++ .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
++ .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2d,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0c80c080),
++ .papdRateMaskHt40 = LE32(0x0080c080),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext2 = {
++ .tempSlopeLow = 0,
++ .tempSlopeHigh = 0,
++ .xatten1DBLow = {0, 0, 0},
++ .xatten1MarginLow = {0, 0, 0},
++ .xatten1DBHigh = {0, 0, 0},
++ .xatten1MarginHigh = {0, 0, 0}
++ },
++ .calFreqPier5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calPierData5G = {
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++
++ },
++ .calTarget_freqbin_5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT20 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT40 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTargetPower5G = {
++ /* 6-24,36,48,54 */
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ { {20, 20, 20, 10} },
++ },
++ .calTargetPower5GHT20 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ },
++ .calTargetPower5GHT40 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ },
++ .ctlIndex_5G = {
++ 0x10, 0x16, 0x18, 0x40, 0x46,
++ 0x48, 0x30, 0x36, 0x38
++ },
++ .ctl_freqbin_5G = {
++ {
++ /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
++ /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
++ /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++ {
++ /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
++ /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
++ /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
++ /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
++ /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
++ /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
++ },
++
++ {
++ /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
++ /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
++ /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[3].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[3].ctlEdges[7].bChannel */ 0xFF,
++ },
++
++ {
++ /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[4].ctlEdges[4].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[5].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[7].bChannel */ 0xFF,
++ },
++
++ {
++ /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
++ /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
++ /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[5].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[5].ctlEdges[7].bChannel */ 0xFF
++ },
++
++ {
++ /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
++ /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
++ /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
++ /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
++ },
++
++ {
++ /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
++ /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
++ /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
++ /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
++ /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
++ /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
++ }
++ },
++ .ctlPowerData_5G = {
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 1}, {60, 0},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ {60, 0}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 0}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ }
++ },
++ }
++};
++
++static const struct ar9300_eeprom ar9300_x113 = {
++ .eepromVersion = 2,
++ .templateVersion = 6,
++ .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
++ .custData = {"x113-023-f0000"},
++ .baseEepHeader = {
++ .regDmn = { LE16(0), LE16(0x1f) },
++ .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
++ .opCapFlags = {
++ .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
++ .eepMisc = 0,
++ },
++ .rfSilent = 0,
++ .blueToothOptions = 0,
++ .deviceCap = 0,
++ .deviceType = 5, /* takes lower byte in eeprom location */
++ .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
++ .params_for_tuning_caps = {0, 0},
++ .featureEnable = 0x0d,
++ /*
++ * bit0 - enable tx temp comp - disabled
++ * bit1 - enable tx volt comp - disabled
++ * bit2 - enable fastClock - enabled
++ * bit3 - enable doubling - enabled
++ * bit4 - enable internal regulator - disabled
++ * bit5 - enable pa predistortion - disabled
++ */
++ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
++ .eepromWriteEnableGpio = 6,
++ .wlanDisableGpio = 0,
++ .wlanLedGpio = 8,
++ .rxBandSelectGpio = 0xff,
++ .txrxgain = 0x21,
++ .swreg = 0,
++ },
++ .modalHeader2G = {
++ /* ar9300_modal_eep_header 2g */
++ /* 4 idle,t1,t2,b(4 bits per setting) */
++ .antCtrlCommon = LE32(0x110),
++ /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
++ .antCtrlCommon2 = LE32(0x44444),
++
++ /*
++ * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
++ * rx1, rx12, b (2 bits each)
++ */
++ .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
++
++ /*
++ * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
++ * for ar9280 (0xa20c/b20c 5:0)
++ */
++ .xatten1DB = {0, 0, 0},
++
++ /*
++ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
++ * for ar9280 (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0, 0, 0},
++ .tempSlope = 25,
++ .voltSlope = 0,
++
++ /*
++ * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
++ * channels in usual fbin coding format
++ */
++ .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
++
++ /*
++ * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
++ * if the register is per chain
++ */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {1, 1, 1},/* 3 chain */
++ .db_stage2 = {1, 1, 1}, /* 3 chain */
++ .db_stage3 = {0, 0, 0},
++ .db_stage4 = {0, 0, 0},
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2c,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0c80c080),
++ .papdRateMaskHt40 = LE32(0x0080c080),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext1 = {
++ .ant_div_control = 0,
++ .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
++ },
++ .calFreqPier2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1),
++ },
++ /* ar9300_cal_data_per_freq_op_loop 2g */
++ .calPierData2G = {
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ },
++ .calTarget_freqbin_Cck = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2472, 1),
++ },
++ .calTarget_freqbin_2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT20 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT40 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTargetPowerCck = {
++ /* 1L-5L,5S,11L,11S */
++ { {34, 34, 34, 34} },
++ { {34, 34, 34, 34} },
++ },
++ .calTargetPower2G = {
++ /* 6-24,36,48,54 */
++ { {34, 34, 32, 32} },
++ { {34, 34, 32, 32} },
++ { {34, 34, 32, 32} },
++ },
++ .calTargetPower2GHT20 = {
++ { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
++ { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
++ { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
++ },
++ .calTargetPower2GHT40 = {
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
++ },
++ .ctlIndex_2G = {
++ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
++ 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
++ },
++ .ctl_freqbin_2G = {
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2457, 1),
++ FREQ2FBIN(2462, 1)
++ },
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++ {
++ FREQ2FBIN(2422, 1),
++ FREQ2FBIN(2427, 1),
++ FREQ2FBIN(2447, 1),
++ FREQ2FBIN(2452, 1)
++ },
++
++ {
++ /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
++ },
++
++ {
++ /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
++ /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
++ /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
++ /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
++ },
++
++ {
++ /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ },
++
++ {
++ /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
++ /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
++ /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
++ /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
++ }
++ },
++ .ctlPowerData_2G = {
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++
++ { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ },
++ .modalHeader5G = {
++ /* 4 idle,t1,t2,b (4 bits per setting) */
++ .antCtrlCommon = LE32(0x220),
++ /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
++ .antCtrlCommon2 = LE32(0x11111),
++ /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
++ .antCtrlChain = {
++ LE16(0x150), LE16(0x150), LE16(0x150),
++ },
++ /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
++ .xatten1DB = {0, 0, 0},
++
++ /*
++ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
++ * for merlin (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0, 0, 0},
++ .tempSlope = 68,
++ .voltSlope = 0,
++ /* spurChans spur channels in usual fbin coding format */
++ .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
++ /* noiseFloorThreshCh Check if the register is per chain */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {3, 3, 3}, /* 3 chain */
++ .db_stage2 = {3, 3, 3}, /* 3 chain */
++ .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
++ .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2d,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
++ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext2 = {
++ .tempSlopeLow = 72,
++ .tempSlopeHigh = 105,
++ .xatten1DBLow = {0, 0, 0},
++ .xatten1MarginLow = {0, 0, 0},
++ .xatten1DBHigh = {0, 0, 0},
++ .xatten1MarginHigh = {0, 0, 0}
++ },
++ .calFreqPier5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5785, 0)
++ },
++ .calPierData5G = {
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++
++ },
++ .calTarget_freqbin_5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5785, 0)
++ },
++ .calTarget_freqbin_5GHT20 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT40 = {
++ FREQ2FBIN(5190, 0),
++ FREQ2FBIN(5230, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5410, 0),
++ FREQ2FBIN(5510, 0),
++ FREQ2FBIN(5670, 0),
++ FREQ2FBIN(5755, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTargetPower5G = {
++ /* 6-24,36,48,54 */
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ { {42, 40, 40, 34} },
++ },
++ .calTargetPower5GHT20 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
++ { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
++ { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
++ { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
++ { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
++ { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
++ { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
++ { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
++ },
++ .calTargetPower5GHT40 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
++ { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
++ { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
++ { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
++ { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
++ { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
++ { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
++ { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
++ },
++ .ctlIndex_5G = {
++ 0x10, 0x16, 0x18, 0x40, 0x46,
++ 0x48, 0x30, 0x36, 0x38
++ },
++ .ctl_freqbin_5G = {
++ {
++ /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
++ /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
++ /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++ {
++ /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
++ /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
++ /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
++ /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
++ /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
++ /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
++ },
++
++ {
++ /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
++ /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
++ /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[3].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[3].ctlEdges[7].bChannel */ 0xFF,
++ },
++
++ {
++ /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[4].ctlEdges[4].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[5].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[7].bChannel */ 0xFF,
++ },
++
++ {
++ /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
++ /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
++ /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[5].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[5].ctlEdges[7].bChannel */ 0xFF
++ },
++
++ {
++ /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
++ /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
++ /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
++ /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
++ },
++
++ {
++ /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
++ /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
++ /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
++ /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
++ /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
++ /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
++ }
++ },
++ .ctlPowerData_5G = {
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 1}, {60, 0},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ {60, 0}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 0}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ }
++ },
++ }
++};
++
++
++static const struct ar9300_eeprom ar9300_h112 = {
++ .eepromVersion = 2,
++ .templateVersion = 3,
++ .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
++ .custData = {"h112-241-f0000"},
++ .baseEepHeader = {
++ .regDmn = { LE16(0), LE16(0x1f) },
++ .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
++ .opCapFlags = {
++ .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
++ .eepMisc = 0,
++ },
++ .rfSilent = 0,
++ .blueToothOptions = 0,
++ .deviceCap = 0,
++ .deviceType = 5, /* takes lower byte in eeprom location */
++ .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
++ .params_for_tuning_caps = {0, 0},
++ .featureEnable = 0x0d,
++ /*
++ * bit0 - enable tx temp comp - disabled
++ * bit1 - enable tx volt comp - disabled
++ * bit2 - enable fastClock - enabled
++ * bit3 - enable doubling - enabled
++ * bit4 - enable internal regulator - disabled
++ * bit5 - enable pa predistortion - disabled
++ */
++ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
++ .eepromWriteEnableGpio = 6,
++ .wlanDisableGpio = 0,
++ .wlanLedGpio = 8,
++ .rxBandSelectGpio = 0xff,
++ .txrxgain = 0x10,
++ .swreg = 0,
++ },
++ .modalHeader2G = {
++ /* ar9300_modal_eep_header 2g */
++ /* 4 idle,t1,t2,b(4 bits per setting) */
++ .antCtrlCommon = LE32(0x110),
++ /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
++ .antCtrlCommon2 = LE32(0x44444),
++
++ /*
++ * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
++ * rx1, rx12, b (2 bits each)
++ */
++ .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
++
++ /*
++ * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
++ * for ar9280 (0xa20c/b20c 5:0)
++ */
++ .xatten1DB = {0, 0, 0},
++
++ /*
++ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
++ * for ar9280 (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0, 0, 0},
++ .tempSlope = 25,
++ .voltSlope = 0,
++
++ /*
++ * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
++ * channels in usual fbin coding format
++ */
++ .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
++
++ /*
++ * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
++ * if the register is per chain
++ */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {1, 1, 1},/* 3 chain */
++ .db_stage2 = {1, 1, 1}, /* 3 chain */
++ .db_stage3 = {0, 0, 0},
++ .db_stage4 = {0, 0, 0},
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2c,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x80c080),
++ .papdRateMaskHt40 = LE32(0x80c080),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext1 = {
++ .ant_div_control = 0,
++ .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
++ },
++ .calFreqPier2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1),
++ },
++ /* ar9300_cal_data_per_freq_op_loop 2g */
++ .calPierData2G = {
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ },
++ .calTarget_freqbin_Cck = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2484, 1),
++ },
++ .calTarget_freqbin_2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT20 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT40 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTargetPowerCck = {
++ /* 1L-5L,5S,11L,11S */
++ { {34, 34, 34, 34} },
++ { {34, 34, 34, 34} },
++ },
++ .calTargetPower2G = {
++ /* 6-24,36,48,54 */
++ { {34, 34, 32, 32} },
++ { {34, 34, 32, 32} },
++ { {34, 34, 32, 32} },
++ },
++ .calTargetPower2GHT20 = {
++ { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
++ { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
++ { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
++ },
++ .calTargetPower2GHT40 = {
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
++ },
++ .ctlIndex_2G = {
++ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
++ 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
++ },
++ .ctl_freqbin_2G = {
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2457, 1),
++ FREQ2FBIN(2462, 1)
++ },
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++ {
++ FREQ2FBIN(2422, 1),
++ FREQ2FBIN(2427, 1),
++ FREQ2FBIN(2447, 1),
++ FREQ2FBIN(2452, 1)
++ },
++
++ {
++ /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
++ },
++
++ {
++ /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
++ /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
++ /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
++ /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
++ },
++
++ {
++ /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ },
++
++ {
++ /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
++ /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
++ /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
++ /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
++ /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
++ /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
++ }
++ },
++ .ctlPowerData_2G = {
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++
++ { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ },
++ .modalHeader5G = {
++ /* 4 idle,t1,t2,b (4 bits per setting) */
++ .antCtrlCommon = LE32(0x220),
++ /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
++ .antCtrlCommon2 = LE32(0x44444),
++ /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
++ .antCtrlChain = {
++ LE16(0x150), LE16(0x150), LE16(0x150),
++ },
++ /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
++ .xatten1DB = {0, 0, 0},
++
++ /*
++ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
++ * for merlin (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0, 0, 0},
++ .tempSlope = 45,
++ .voltSlope = 0,
++ /* spurChans spur channels in usual fbin coding format */
++ .spurChans = {0, 0, 0, 0, 0},
++ /* noiseFloorThreshCh Check if the register is per chain */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {3, 3, 3}, /* 3 chain */
++ .db_stage2 = {3, 3, 3}, /* 3 chain */
++ .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
++ .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2d,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
++ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext2 = {
++ .tempSlopeLow = 40,
++ .tempSlopeHigh = 50,
++ .xatten1DBLow = {0, 0, 0},
++ .xatten1MarginLow = {0, 0, 0},
++ .xatten1DBHigh = {0, 0, 0},
++ .xatten1MarginHigh = {0, 0, 0}
++ },
++ .calFreqPier5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calPierData5G = {
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++
++ },
++ .calTarget_freqbin_5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT20 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT40 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5240, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5745, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTargetPower5G = {
++ /* 6-24,36,48,54 */
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ },
++ .calTargetPower5GHT20 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
++ { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
++ { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
++ { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
++ { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
++ { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
++ { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
++ { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
++ },
++ .calTargetPower5GHT40 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
++ { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
++ { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
++ { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
++ { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
++ { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
++ { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
++ { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
++ },
++ .ctlIndex_5G = {
++ 0x10, 0x16, 0x18, 0x40, 0x46,
++ 0x48, 0x30, 0x36, 0x38
++ },
++ .ctl_freqbin_5G = {
++ {
++ /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
++ /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
++ /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++ {
++ /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
++ /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
++ /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
++ /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
++ /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
++ /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
++ },
++
++ {
++ /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
++ /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
++ /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[3].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[3].ctlEdges[7].bChannel */ 0xFF,
++ },
++
++ {
++ /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[4].ctlEdges[4].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[5].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[4].ctlEdges[7].bChannel */ 0xFF,
++ },
++
++ {
++ /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
++ /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
++ /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[5].ctlEdges[6].bChannel */ 0xFF,
++ /* Data[5].ctlEdges[7].bChannel */ 0xFF
++ },
++
++ {
++ /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
++ /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
++ /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
++ /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
++ },
++
++ {
++ /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
++ /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
++ /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
++ /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
++ /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
++ /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
++ /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
++ /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
++ /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
++ /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
++ /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
++ /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
++ /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
++ /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
++ /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
++ }
++ },
++ .ctlPowerData_5G = {
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 1}, {60, 0},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ {60, 0}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 0}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ }
++ },
++ }
++};
++
++
++static const struct ar9300_eeprom ar9300_x112 = {
++ .eepromVersion = 2,
++ .templateVersion = 5,
++ .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
++ .custData = {"x112-041-f0000"},
++ .baseEepHeader = {
++ .regDmn = { LE16(0), LE16(0x1f) },
++ .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
++ .opCapFlags = {
++ .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
++ .eepMisc = 0,
++ },
++ .rfSilent = 0,
++ .blueToothOptions = 0,
++ .deviceCap = 0,
++ .deviceType = 5, /* takes lower byte in eeprom location */
++ .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
++ .params_for_tuning_caps = {0, 0},
++ .featureEnable = 0x0d,
++ /*
++ * bit0 - enable tx temp comp - disabled
++ * bit1 - enable tx volt comp - disabled
++ * bit2 - enable fastclock - enabled
++ * bit3 - enable doubling - enabled
++ * bit4 - enable internal regulator - disabled
++ * bit5 - enable pa predistortion - disabled
++ */
++ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
++ .eepromWriteEnableGpio = 6,
++ .wlanDisableGpio = 0,
++ .wlanLedGpio = 8,
++ .rxBandSelectGpio = 0xff,
++ .txrxgain = 0x0,
++ .swreg = 0,
++ },
++ .modalHeader2G = {
++ /* ar9300_modal_eep_header 2g */
++ /* 4 idle,t1,t2,b(4 bits per setting) */
++ .antCtrlCommon = LE32(0x110),
++ /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
++ .antCtrlCommon2 = LE32(0x22222),
++
++ /*
++ * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
++ * rx1, rx12, b (2 bits each)
++ */
++ .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
++
++ /*
++ * xatten1DB[AR9300_max_chains]; 3 xatten1_db
++ * for ar9280 (0xa20c/b20c 5:0)
++ */
++ .xatten1DB = {0x1b, 0x1b, 0x1b},
++
++ /*
++ * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
++ * for ar9280 (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0x15, 0x15, 0x15},
++ .tempSlope = 50,
++ .voltSlope = 0,
++
++ /*
++ * spurChans[OSPrey_eeprom_modal_sPURS]; spur
++ * channels in usual fbin coding format
++ */
++ .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
++
++ /*
++ * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
++ * if the register is per chain
++ */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {1, 1, 1},/* 3 chain */
++ .db_stage2 = {1, 1, 1}, /* 3 chain */
++ .db_stage3 = {0, 0, 0},
++ .db_stage4 = {0, 0, 0},
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2c,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0c80c080),
++ .papdRateMaskHt40 = LE32(0x0080c080),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext1 = {
++ .ant_div_control = 0,
++ .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
++ },
++ .calFreqPier2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1),
++ },
++ /* ar9300_cal_data_per_freq_op_loop 2g */
++ .calPierData2G = {
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
++ },
++ .calTarget_freqbin_Cck = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2472, 1),
++ },
++ .calTarget_freqbin_2G = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT20 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTarget_freqbin_2GHT40 = {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2437, 1),
++ FREQ2FBIN(2472, 1)
++ },
++ .calTargetPowerCck = {
++ /* 1L-5L,5S,11L,11s */
++ { {38, 38, 38, 38} },
++ { {38, 38, 38, 38} },
++ },
++ .calTargetPower2G = {
++ /* 6-24,36,48,54 */
++ { {38, 38, 36, 34} },
++ { {38, 38, 36, 34} },
++ { {38, 38, 34, 32} },
++ },
++ .calTargetPower2GHT20 = {
++ { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
++ { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
++ { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
++ },
++ .calTargetPower2GHT40 = {
++ { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
++ { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
++ { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
++ },
++ .ctlIndex_2G = {
++ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
++ 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
++ },
++ .ctl_freqbin_2G = {
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2457, 1),
++ FREQ2FBIN(2462, 1)
++ },
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++
++ {
++ FREQ2FBIN(2412, 1),
++ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2462, 1),
++ 0xFF,
++ },
++ {
++ FREQ2FBIN(2422, 1),
++ FREQ2FBIN(2427, 1),
++ FREQ2FBIN(2447, 1),
++ FREQ2FBIN(2452, 1)
++ },
++
++ {
++ /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
++ /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
++ /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
++ /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
++ },
++
++ {
++ /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
++ /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
++ /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
++ /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
++ FREQ2FBIN(2472, 1),
++ 0,
++ },
++
++ {
++ /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
++ /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
++ /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
++ /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
++ },
++
++ {
++ /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
++ /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
++ /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
++ },
++
++ {
++ /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
++ /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
++ /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
++ /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
++ /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
++ 0
++ },
++
++ {
++ /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
++ /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
++ /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
++ /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
++ }
++ },
++ .ctlPowerData_2G = {
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++
++ { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++
++ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ },
++ .modalHeader5G = {
++ /* 4 idle,t1,t2,b (4 bits per setting) */
++ .antCtrlCommon = LE32(0x110),
++ /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
++ .antCtrlCommon2 = LE32(0x22222),
++ /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
++ .antCtrlChain = {
++ LE16(0x0), LE16(0x0), LE16(0x0),
++ },
++ /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
++ .xatten1DB = {0x13, 0x19, 0x17},
++
++ /*
++ * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
++ * for merlin (0xa20c/b20c 16:12
++ */
++ .xatten1Margin = {0x19, 0x19, 0x19},
++ .tempSlope = 70,
++ .voltSlope = 15,
++ /* spurChans spur channels in usual fbin coding format */
++ .spurChans = {0, 0, 0, 0, 0},
++ /* noiseFloorThreshch check if the register is per chain */
++ .noiseFloorThreshCh = {-1, 0, 0},
++ .ob = {3, 3, 3}, /* 3 chain */
++ .db_stage2 = {3, 3, 3}, /* 3 chain */
++ .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
++ .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
++ .xpaBiasLvl = 0,
++ .txFrameToDataStart = 0x0e,
++ .txFrameToPaOn = 0x0e,
++ .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
++ .antennaGain = 0,
++ .switchSettling = 0x2d,
++ .adcDesiredSize = -30,
++ .txEndToXpaOff = 0,
++ .txEndToRxOn = 0x2,
++ .txFrameToXpaOn = 0xe,
++ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
++ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .futureModal = {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ },
++ },
++ .base_ext2 = {
++ .tempSlopeLow = 72,
++ .tempSlopeHigh = 105,
++ .xatten1DBLow = {0x10, 0x14, 0x10},
++ .xatten1MarginLow = {0x19, 0x19 , 0x19},
++ .xatten1DBHigh = {0x1d, 0x20, 0x24},
++ .xatten1MarginHigh = {0x10, 0x10, 0x10}
++ },
++ .calFreqPier5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5785, 0)
++ },
++ .calPierData5G = {
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++ {
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ {0, 0, 0, 0, 0},
++ },
++
++ },
++ .calTarget_freqbin_5G = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT20 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTarget_freqbin_5GHT40 = {
++ FREQ2FBIN(5180, 0),
++ FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
++ FREQ2FBIN(5500, 0),
++ FREQ2FBIN(5600, 0),
++ FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5825, 0)
++ },
++ .calTargetPower5G = {
++ /* 6-24,36,48,54 */
++ { {32, 32, 28, 26} },
++ { {32, 32, 28, 26} },
++ { {32, 32, 28, 26} },
++ { {32, 32, 26, 24} },
++ { {32, 32, 26, 24} },
++ { {32, 32, 24, 22} },
++ { {30, 30, 24, 22} },
++ { {30, 30, 24, 22} },
++ },
++ .calTargetPower5GHT20 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
++ { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
++ { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
++ { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
++ { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
++ { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
++ { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
++ { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
++ },
++ .calTargetPower5GHT40 = {
++ /*
++ * 0_8_16,1-3_9-11_17-19,
++ * 4,5,6,7,12,13,14,15,20,21,22,23
++ */
++ { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
++ { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
++ { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
++ { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
++ { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
++ { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
++ { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
++ { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
++ },
++ .ctlIndex_5G = {
++ 0x10, 0x16, 0x18, 0x40, 0x46,
++ 0x48, 0x30, 0x36, 0x38
++ },
++ .ctl_freqbin_5G = {
++ {
++ /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
++ /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
++ /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
++ /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
++ /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
++ /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
++ /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
++ /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
++ },
++ {
++ /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
++ /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
++ /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
++ /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
++ /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
++ /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
++ /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
++ /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
++ /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
++ /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
++ /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
++ /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
++ /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
++ /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
++ /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
++ },
++
++ {
++ /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
++ /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
++ /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
++ /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
++ /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
++ /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
++ /* Data[3].ctledges[6].bchannel */ 0xFF,
++ /* Data[3].ctledges[7].bchannel */ 0xFF,
++ },
++
++ {
++ /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
++ /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
++ /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
++ /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
++ /* Data[4].ctledges[4].bchannel */ 0xFF,
++ /* Data[4].ctledges[5].bchannel */ 0xFF,
++ /* Data[4].ctledges[6].bchannel */ 0xFF,
++ /* Data[4].ctledges[7].bchannel */ 0xFF,
++ },
++
++ {
++ /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
++ /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
++ /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
++ /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
++ /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
++ /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
++ /* Data[5].ctledges[6].bchannel */ 0xFF,
++ /* Data[5].ctledges[7].bchannel */ 0xFF
++ },
++
++ {
++ /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
++ /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
++ /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
++ /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
++ /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
++ /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
++ /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
++ /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
++ },
++
++ {
++ /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
++ /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
++ /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
++ /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
++ /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
++ /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
++ /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
++ /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
++ },
++
++ {
++ /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
++ /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
++ /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
++ /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
++ /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
++ /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
++ /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
++ /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
++ }
++ },
++ .ctlPowerData_5G = {
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 0}, {60, 1}, {60, 1}, {60, 0},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ {60, 0}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 0}, {60, 0}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 1},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ {60, 1}, {60, 1}, {60, 1}, {60, 0},
++ }
++ },
++ {
++ {
++ {60, 1}, {60, 0}, {60, 1}, {60, 1},
++ {60, 1}, {60, 1}, {60, 0}, {60, 1},
++ }
++ },
++ }
++};
++
++static const struct ar9300_eeprom ar9300_h116 = {
++ .eepromVersion = 2,
++ .templateVersion = 4,
++ .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
++ .custData = {"h116-041-f0000"},
+ .baseEepHeader = {
+ .regDmn = { LE16(0), LE16(0x1f) },
+- .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
++ .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
+ .opCapFlags = {
+ .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
+ .eepMisc = 0,
+@@ -74,7 +2388,7 @@ static const struct ar9300_eeprom ar9300
+ .deviceType = 5, /* takes lower byte in eeprom location */
+ .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+ .params_for_tuning_caps = {0, 0},
+- .featureEnable = 0x0c,
++ .featureEnable = 0x0d,
+ /*
+ * bit0 - enable tx temp comp - disabled
+ * bit1 - enable tx volt comp - disabled
+@@ -84,11 +2398,11 @@ static const struct ar9300_eeprom ar9300
+ * bit5 - enable pa predistortion - disabled
+ */
+ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+- .eepromWriteEnableGpio = 3,
++ .eepromWriteEnableGpio = 6,
+ .wlanDisableGpio = 0,
+ .wlanLedGpio = 8,
+ .rxBandSelectGpio = 0xff,
+- .txrxgain = 0,
++ .txrxgain = 0x10,
+ .swreg = 0,
+ },
+ .modalHeader2G = {
+@@ -96,33 +2410,33 @@ static const struct ar9300_eeprom ar9300
+ /* 4 idle,t1,t2,b(4 bits per setting) */
+ .antCtrlCommon = LE32(0x110),
+ /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+- .antCtrlCommon2 = LE32(0x22222),
++ .antCtrlCommon2 = LE32(0x44444),
+
+ /*
+ * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+ * rx1, rx12, b (2 bits each)
+ */
+- .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
++ .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+ /*
+ * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
+ * for ar9280 (0xa20c/b20c 5:0)
+ */
+- .xatten1DB = {0, 0, 0},
++ .xatten1DB = {0x1f, 0x1f, 0x1f},
+
+ /*
+ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+ * for ar9280 (0xa20c/b20c 16:12
+ */
+- .xatten1Margin = {0, 0, 0},
+- .tempSlope = 36,
++ .xatten1Margin = {0x12, 0x12, 0x12},
++ .tempSlope = 25,
+ .voltSlope = 0,
+
+ /*
+ * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+ * channels in usual fbin coding format
+ */
+- .spurChans = {0, 0, 0, 0, 0},
++ .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+ /*
+ * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+@@ -144,13 +2458,16 @@ static const struct ar9300_eeprom ar9300
+ .txEndToRxOn = 0x2,
+ .txFrameToXpaOn = 0xe,
+ .thresh62 = 28,
+- .papdRateMaskHt20 = LE32(0x80c080),
+- .papdRateMaskHt40 = LE32(0x80c080),
++ .papdRateMaskHt20 = LE32(0x0c80C080),
++ .papdRateMaskHt40 = LE32(0x0080C080),
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
++ .base_ext1 = {
++ .ant_div_control = 0,
++ .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
++ },
+ .calFreqPier2G = {
+ FREQ2FBIN(2412, 1),
+ FREQ2FBIN(2437, 1),
+@@ -164,7 +2481,7 @@ static const struct ar9300_eeprom ar9300
+ },
+ .calTarget_freqbin_Cck = {
+ FREQ2FBIN(2412, 1),
+- FREQ2FBIN(2484, 1),
++ FREQ2FBIN(2472, 1),
+ },
+ .calTarget_freqbin_2G = {
+ FREQ2FBIN(2412, 1),
+@@ -183,24 +2500,24 @@ static const struct ar9300_eeprom ar9300
+ },
+ .calTargetPowerCck = {
+ /* 1L-5L,5S,11L,11S */
+- { {36, 36, 36, 36} },
+- { {36, 36, 36, 36} },
++ { {34, 34, 34, 34} },
++ { {34, 34, 34, 34} },
+ },
+ .calTargetPower2G = {
+ /* 6-24,36,48,54 */
+- { {32, 32, 28, 24} },
+- { {32, 32, 28, 24} },
+- { {32, 32, 28, 24} },
++ { {34, 34, 32, 32} },
++ { {34, 34, 32, 32} },
++ { {34, 34, 32, 32} },
+ },
+ .calTargetPower2GHT20 = {
+- { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
+- { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
+- { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
++ { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
++ { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+ },
+ .calTargetPower2GHT40 = {
+- { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
+- { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
+- { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
++ { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+ },
+ .ctlIndex_2G = {
+ 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+@@ -285,8 +2602,7 @@ static const struct ar9300_eeprom ar9300
+ /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+ /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+ /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+- /* Data[11].ctlEdges[3].bChannel */
+- FREQ2FBIN(2462, 1),
++ /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+ }
+ },
+ .ctlPowerData_2G = {
+@@ -304,25 +2620,26 @@ static const struct ar9300_eeprom ar9300
+
+ { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++ { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
+ },
+ .modalHeader5G = {
+ /* 4 idle,t1,t2,b (4 bits per setting) */
+- .antCtrlCommon = LE32(0x110),
++ .antCtrlCommon = LE32(0x220),
+ /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+- .antCtrlCommon2 = LE32(0x22222),
++ .antCtrlCommon2 = LE32(0x44444),
+ /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+ .antCtrlChain = {
+- LE16(0x000), LE16(0x000), LE16(0x000),
++ LE16(0x150), LE16(0x150), LE16(0x150),
+ },
+ /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+- .xatten1DB = {0, 0, 0},
++ .xatten1DB = {0x19, 0x19, 0x19},
+
+ /*
+ * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+ * for merlin (0xa20c/b20c 16:12
+ */
+- .xatten1Margin = {0, 0, 0},
+- .tempSlope = 68,
++ .xatten1Margin = {0x14, 0x14, 0x14},
++ .tempSlope = 70,
+ .voltSlope = 0,
+ /* spurChans spur channels in usual fbin coding format */
+ .spurChans = {0, 0, 0, 0, 0},
+@@ -343,13 +2660,20 @@ static const struct ar9300_eeprom ar9300
+ .txEndToRxOn = 0x2,
+ .txFrameToXpaOn = 0xe,
+ .thresh62 = 28,
+- .papdRateMaskHt20 = LE32(0xf0e0e0),
+- .papdRateMaskHt40 = LE32(0xf0e0e0),
++ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
++ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
++ .base_ext2 = {
++ .tempSlopeLow = 35,
++ .tempSlopeHigh = 50,
++ .xatten1DBLow = {0, 0, 0},
++ .xatten1MarginLow = {0, 0, 0},
++ .xatten1DBHigh = {0, 0, 0},
++ .xatten1MarginHigh = {0, 0, 0}
++ },
+ .calFreqPier5G = {
+ FREQ2FBIN(5180, 0),
+ FREQ2FBIN(5220, 0),
+@@ -357,8 +2681,8 @@ static const struct ar9300_eeprom ar9300
+ FREQ2FBIN(5400, 0),
+ FREQ2FBIN(5500, 0),
+ FREQ2FBIN(5600, 0),
+- FREQ2FBIN(5725, 0),
+- FREQ2FBIN(5825, 0)
++ FREQ2FBIN(5700, 0),
++ FREQ2FBIN(5785, 0)
+ },
+ .calPierData5G = {
+ {
+@@ -395,72 +2719,72 @@ static const struct ar9300_eeprom ar9300
+ },
+ .calTarget_freqbin_5G = {
+ FREQ2FBIN(5180, 0),
+- FREQ2FBIN(5220, 0),
++ FREQ2FBIN(5240, 0),
+ FREQ2FBIN(5320, 0),
+ FREQ2FBIN(5400, 0),
+ FREQ2FBIN(5500, 0),
+ FREQ2FBIN(5600, 0),
+- FREQ2FBIN(5725, 0),
++ FREQ2FBIN(5700, 0),
+ FREQ2FBIN(5825, 0)
+ },
+ .calTarget_freqbin_5GHT20 = {
+ FREQ2FBIN(5180, 0),
+ FREQ2FBIN(5240, 0),
+ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
+ FREQ2FBIN(5500, 0),
+ FREQ2FBIN(5700, 0),
+ FREQ2FBIN(5745, 0),
+- FREQ2FBIN(5725, 0),
+ FREQ2FBIN(5825, 0)
+ },
+ .calTarget_freqbin_5GHT40 = {
+ FREQ2FBIN(5180, 0),
+ FREQ2FBIN(5240, 0),
+ FREQ2FBIN(5320, 0),
++ FREQ2FBIN(5400, 0),
+ FREQ2FBIN(5500, 0),
+ FREQ2FBIN(5700, 0),
+ FREQ2FBIN(5745, 0),
+- FREQ2FBIN(5725, 0),
+ FREQ2FBIN(5825, 0)
+ },
+ .calTargetPower5G = {
+ /* 6-24,36,48,54 */
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
+- { {20, 20, 20, 10} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
++ { {30, 30, 28, 24} },
+ },
+ .calTargetPower5GHT20 = {
+ /*
+ * 0_8_16,1-3_9-11_17-19,
+ * 4,5,6,7,12,13,14,15,20,21,22,23
+ */
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
++ { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
++ { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
++ { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
++ { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
++ { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
++ { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
++ { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+ },
+ .calTargetPower5GHT40 = {
+ /*
+ * 0_8_16,1-3_9-11_17-19,
+ * 4,5,6,7,12,13,14,15,20,21,22,23
+ */
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
+- { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
++ { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
++ { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
++ { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
++ { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
++ { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
++ { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
++ { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
++ { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+ },
+ .ctlIndex_5G = {
+ 0x10, 0x16, 0x18, 0x40, 0x46,
+@@ -623,6 +2947,28 @@ static const struct ar9300_eeprom ar9300
+ }
+ };
+
++
++static const struct ar9300_eeprom *ar9300_eep_templates[] = {
++ &ar9300_default,
++ &ar9300_x112,
++ &ar9300_h116,
++ &ar9300_h112,
++ &ar9300_x113,
++};
++
++static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
++{
++#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
++ int it;
++
++ for (it = 0; it < N_LOOP; it++)
++ if (ar9300_eep_templates[it]->templateVersion == id)
++ return ar9300_eep_templates[it];
++ return NULL;
++#undef N_LOOP
++}
++
++
+ static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
+ {
+ if (fbin == AR9300_BCHAN_UNUSED)
+@@ -636,6 +2982,16 @@ static int ath9k_hw_ar9300_check_eeprom(
+ return 0;
+ }
+
++static int interpolate(int x, int xa, int xb, int ya, int yb)
++{
++ int bf, factor, plus;
++
++ bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
++ factor = bf / 2;
++ plus = bf % 2;
++ return ya + factor + plus;
++}
++
+ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
+ enum eeprom_param param)
+ {
+@@ -824,6 +3180,7 @@ static int ar9300_compress_decision(stru
+ {
+ struct ath_common *common = ath9k_hw_common(ah);
+ u8 *dptr;
++ const struct ar9300_eeprom *eep = NULL;
+
+ switch (code) {
+ case _CompressNone:
+@@ -841,13 +3198,14 @@ static int ar9300_compress_decision(stru
+ if (reference == 0) {
+ dptr = mptr;
+ } else {
+- if (reference != 2) {
++ eep = ar9003_eeprom_struct_find_by_id(reference);
++ if (eep == NULL) {
+ ath_print(common, ATH_DBG_EEPROM,
+ "cant find reference eeprom"
+ "struct %d\n", reference);
+ return -1;
+ }
+- memcpy(mptr, &ar9300_default, mdata_size);
++ memcpy(mptr, eep, mdata_size);
+ }
+ ath_print(common, ATH_DBG_EEPROM,
+ "restore eeprom %d: block, reference %d,"
+@@ -992,9 +3350,9 @@ static s32 ar9003_hw_xpa_bias_level_get(
+ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
+ {
+ int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
+- REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
+- REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
+- ((bias >> 2) & 0x3));
++ REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
++ REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
++ REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
+ }
+
+ static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
+@@ -1097,6 +3455,82 @@ static void ar9003_hw_drive_strength_app
+ REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
+ }
+
++static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
++ struct ath9k_channel *chan)
++{
++ int f[3], t[3];
++ u16 value;
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++
++ if (chain >= 0 && chain < 3) {
++ if (IS_CHAN_2GHZ(chan))
++ return eep->modalHeader2G.xatten1DB[chain];
++ else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
++ t[0] = eep->base_ext2.xatten1DBLow[chain];
++ f[0] = 5180;
++ t[1] = eep->modalHeader5G.xatten1DB[chain];
++ f[1] = 5500;
++ t[2] = eep->base_ext2.xatten1DBHigh[chain];
++ f[2] = 5785;
++ value = ar9003_hw_power_interpolate((s32) chan->channel,
++ f, t, 3);
++ return value;
++ } else
++ return eep->modalHeader5G.xatten1DB[chain];
++ }
++
++ return 0;
++}
++
++
++static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
++ struct ath9k_channel *chan)
++{
++ int f[3], t[3];
++ u16 value;
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++
++ if (chain >= 0 && chain < 3) {
++ if (IS_CHAN_2GHZ(chan))
++ return eep->modalHeader2G.xatten1Margin[chain];
++ else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
++ t[0] = eep->base_ext2.xatten1MarginLow[chain];
++ f[0] = 5180;
++ t[1] = eep->modalHeader5G.xatten1Margin[chain];
++ f[1] = 5500;
++ t[2] = eep->base_ext2.xatten1MarginHigh[chain];
++ f[2] = 5785;
++ value = ar9003_hw_power_interpolate((s32) chan->channel,
++ f, t, 3);
++ return value;
++ } else
++ return eep->modalHeader5G.xatten1Margin[chain];
++ }
++
++ return 0;
++}
++
++static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
++{
++ int i;
++ u16 value;
++ unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
++ AR_PHY_EXT_ATTEN_CTL_1,
++ AR_PHY_EXT_ATTEN_CTL_2,
++ };
++
++ /* Test value. if 0 then attenuation is unused. Don't load anything. */
++ for (i = 0; i < 3; i++) {
++ value = ar9003_hw_atten_chain_get(ah, i, chan);
++ REG_RMW_FIELD(ah, ext_atten_reg[i],
++ AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
++
++ value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
++ REG_RMW_FIELD(ah, ext_atten_reg[i],
++ AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
++ }
++}
++
+ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
+ {
+ int internal_regulator =
+@@ -1128,6 +3562,7 @@ static void ath9k_hw_ar9300_set_board_va
+ ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
+ ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
+ ar9003_hw_drive_strength_apply(ah);
++ ar9003_hw_atten_apply(ah, chan);
+ ar9003_hw_internal_regulator_apply(ah);
+ }
+
+@@ -1189,7 +3624,7 @@ static int ar9003_hw_power_interpolate(i
+ if (hx == lx)
+ y = ly;
+ else /* interpolate */
+- y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
++ y = interpolate(x, lx, hx, ly, hy);
+ } else /* only low is good, use it */
+ y = ly;
+ } else if (hhave) /* only high is good, use it */
+@@ -1637,6 +4072,7 @@ static int ar9003_hw_power_control_overr
+ {
+ int tempSlope = 0;
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ int f[3], t[3];
+
+ REG_RMW(ah, AR_PHY_TPC_11_B0,
+ (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+@@ -1665,7 +4101,16 @@ static int ar9003_hw_power_control_overr
+ */
+ if (frequency < 4000)
+ tempSlope = eep->modalHeader2G.tempSlope;
+- else
++ else if (eep->base_ext2.tempSlopeLow != 0) {
++ t[0] = eep->base_ext2.tempSlopeLow;
++ f[0] = 5180;
++ t[1] = eep->modalHeader5G.tempSlope;
++ f[1] = 5500;
++ t[2] = eep->base_ext2.tempSlopeHigh;
++ f[2] = 5785;
++ tempSlope = ar9003_hw_power_interpolate((s32) frequency,
++ f, t, 3);
++ } else
+ tempSlope = eep->modalHeader5G.tempSlope;
+
+ REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
+@@ -1769,25 +4214,23 @@ static int ar9003_hw_calibration_apply(s
+ /* so is the high frequency, interpolate */
+ if (hfrequency[ichain] - frequency < 1000) {
+
+- correction[ichain] = lcorrection[ichain] +
+- (((frequency - lfrequency[ichain]) *
+- (hcorrection[ichain] -
+- lcorrection[ichain])) /
+- (hfrequency[ichain] - lfrequency[ichain]));
+-
+- temperature[ichain] = ltemperature[ichain] +
+- (((frequency - lfrequency[ichain]) *
+- (htemperature[ichain] -
+- ltemperature[ichain])) /
+- (hfrequency[ichain] - lfrequency[ichain]));
+-
+- voltage[ichain] =
+- lvoltage[ichain] +
+- (((frequency -
+- lfrequency[ichain]) * (hvoltage[ichain] -
+- lvoltage[ichain]))
+- / (hfrequency[ichain] -
+- lfrequency[ichain]));
++ correction[ichain] = interpolate(frequency,
++ lfrequency[ichain],
++ hfrequency[ichain],
++ lcorrection[ichain],
++ hcorrection[ichain]);
++
++ temperature[ichain] = interpolate(frequency,
++ lfrequency[ichain],
++ hfrequency[ichain],
++ ltemperature[ichain],
++ htemperature[ichain]);
++
++ voltage[ichain] = interpolate(frequency,
++ lfrequency[ichain],
++ hfrequency[ichain],
++ lvoltage[ichain],
++ hvoltage[ichain]);
+ }
+ /* only low is good, use it */
+ else {
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+@@ -236,7 +236,7 @@ struct ar9300_modal_eep_header {
+ u8 thresh62;
+ __le32 papdRateMaskHt20;
+ __le32 papdRateMaskHt40;
+- u8 futureModal[24];
++ u8 futureModal[10];
+ } __packed;
+
+ struct ar9300_cal_data_per_freq_op_loop {
+@@ -274,6 +274,20 @@ struct cal_ctl_data_5g {
+ struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+ } __packed;
+
++struct ar9300_BaseExtension_1 {
++ u8 ant_div_control;
++ u8 future[13];
++} __packed;
++
++struct ar9300_BaseExtension_2 {
++ int8_t tempSlopeLow;
++ int8_t tempSlopeHigh;
++ u8 xatten1DBLow[AR9300_MAX_CHAINS];
++ u8 xatten1MarginLow[AR9300_MAX_CHAINS];
++ u8 xatten1DBHigh[AR9300_MAX_CHAINS];
++ u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
++} __packed;
++
+ struct ar9300_eeprom {
+ u8 eepromVersion;
+ u8 templateVersion;
+@@ -283,6 +297,7 @@ struct ar9300_eeprom {
+ struct ar9300_base_eep_hdr baseEepHeader;
+
+ struct ar9300_modal_eep_header modalHeader2G;
++ struct ar9300_BaseExtension_1 base_ext1;
+ u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
+ struct ar9300_cal_data_per_freq_op_loop
+ calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
+@@ -302,6 +317,7 @@ struct ar9300_eeprom {
+ u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
+ struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
+ struct ar9300_modal_eep_header modalHeader5G;
++ struct ar9300_BaseExtension_2 base_ext2;
+ u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
+ struct ar9300_cal_data_per_freq_op_loop
+ calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
+--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+@@ -410,12 +410,36 @@ static void ar9003_hw_set11n_ratescenari
+ static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
+ u32 aggrLen)
+ {
++#define FIRST_DESC_NDELIMS 60
+ struct ar9003_txc *ads = (struct ar9003_txc *) ds;
+
+ ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
+
+- ads->ctl17 &= ~AR_AggrLen;
+- ads->ctl17 |= SM(aggrLen, AR_AggrLen);
++ if (ah->ent_mode & AR_ENT_OTP_MPSD) {
++ u32 ctl17, ndelim;
++ /*
++ * Add delimiter when using RTS/CTS with aggregation
++ * and non enterprise AR9003 card
++ */
++ ctl17 = ads->ctl17;
++ ndelim = MS(ctl17, AR_PadDelim);
++
++ if (ndelim < FIRST_DESC_NDELIMS) {
++ aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
++ ndelim = FIRST_DESC_NDELIMS;
++ }
++
++ ctl17 &= ~AR_AggrLen;
++ ctl17 |= SM(aggrLen, AR_AggrLen);
++
++ ctl17 &= ~AR_PadDelim;
++ ctl17 |= SM(ndelim, AR_PadDelim);
++
++ ads->ctl17 = ctl17;
++ } else {
++ ads->ctl17 &= ~AR_AggrLen;
++ ads->ctl17 |= SM(aggrLen, AR_AggrLen);
++ }
+ }
+
+ static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -1113,6 +1113,37 @@ static void ar9003_hw_ani_cache_ini_regs
+ aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
+ }
+
++static void ar9003_hw_set_radar_params(struct ath_hw *ah,
++ struct ath_hw_radar_conf *conf)
++{
++ u32 radar_0 = 0, radar_1 = 0;
++
++ if (!conf) {
++ REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
++ return;
++ }
++
++ radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
++ radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
++ radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
++ radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
++ radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
++ radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
++
++ radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
++ radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
++ radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
++ radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
++ radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
++
++ REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
++ REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
++ if (conf->ext_channel)
++ REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
++ else
++ REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
++}
++
+ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
+ {
+ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+@@ -1141,6 +1172,7 @@ void ar9003_hw_attach_phy_ops(struct ath
+ priv_ops->ani_control = ar9003_hw_ani_control;
+ priv_ops->do_getnf = ar9003_hw_do_getnf;
+ priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
++ priv_ops->set_radar_params = ar9003_hw_set_radar_params;
+
+ ar9003_hw_set_nf_limits(ah);
+ memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -177,8 +177,8 @@ void ath_descdma_cleanup(struct ath_soft
+
+ /* returns delimiter padding required given the packet length */
+ #define ATH_AGGR_GET_NDELIM(_len) \
+- (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
+- (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
++ (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
++ DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
+
+ #define BAW_WITHIN(_start, _bawsz, _seqno) \
+ ((((_seqno) - (_start)) & 4095) < (_bawsz))
+@@ -229,6 +229,7 @@ struct ath_buf_state {
+ unsigned long bfs_paprd_timestamp;
+ u32 bfs_keyix;
+ enum ath9k_key_type bfs_keytype;
++ enum ath9k_internal_frame_type bfs_ftype;
+ };
+
+ struct ath_buf {
+@@ -712,7 +713,7 @@ void ath9k_ps_restore(struct ath_softc *
+ void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
+ int ath9k_wiphy_add(struct ath_softc *sc);
+ int ath9k_wiphy_del(struct ath_wiphy *aphy);
+-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
++void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
+ int ath9k_wiphy_pause(struct ath_wiphy *aphy);
+ int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
+ int ath9k_wiphy_select(struct ath_wiphy *aphy);
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -1991,6 +1991,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw
+ if (AR_SREV_9300_20_OR_LATER(ah))
+ pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
+
++ if (AR_SREV_9300_20_OR_LATER(ah))
++ ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
++
+ if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
+ pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
+
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -485,6 +485,40 @@ struct ath_hw_antcomb_conf {
+ };
+
+ /**
++ * struct ath_hw_radar_conf - radar detection initialization parameters
++ *
++ * @pulse_inband: threshold for checking the ratio of in-band power
++ * to total power for short radar pulses (half dB steps)
++ * @pulse_inband_step: threshold for checking an in-band power to total
++ * power ratio increase for short radar pulses (half dB steps)
++ * @pulse_height: threshold for detecting the beginning of a short
++ * radar pulse (dB step)
++ * @pulse_rssi: threshold for detecting if a short radar pulse is
++ * gone (dB step)
++ * @pulse_maxlen: maximum pulse length (0.8 us steps)
++ *
++ * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
++ * @radar_inband: threshold for checking the ratio of in-band power
++ * to total power for long radar pulses (half dB steps)
++ * @fir_power: threshold for detecting the end of a long radar pulse (dB)
++ *
++ * @ext_channel: enable extension channel radar detection
++ */
++struct ath_hw_radar_conf {
++ unsigned int pulse_inband;
++ unsigned int pulse_inband_step;
++ unsigned int pulse_height;
++ unsigned int pulse_rssi;
++ unsigned int pulse_maxlen;
++
++ unsigned int radar_rssi;
++ unsigned int radar_inband;
++ int fir_power;
++
++ bool ext_channel;
++};
++
++/**
+ * struct ath_hw_private_ops - callbacks used internally by hardware code
+ *
+ * This structure contains private callbacks designed to only be used internally
+@@ -549,6 +583,8 @@ struct ath_hw_private_ops {
+ bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
+ int param);
+ void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
++ void (*set_radar_params)(struct ath_hw *ah,
++ struct ath_hw_radar_conf *conf);
+
+ /* ANI */
+ void (*ani_cache_ini_regs)(struct ath_hw *ah);
+@@ -806,6 +842,9 @@ struct ath_hw {
+ * this register when in sleep states.
+ */
+ u32 WARegVal;
++
++ /* Enterprise mode cap */
++ u32 ent_mode;
+ };
+
+ static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
+--- a/drivers/net/wireless/ath/ath9k/rc.c
++++ b/drivers/net/wireless/ath/ath9k/rc.c
+@@ -1354,23 +1354,7 @@ static void ath_tx_status(void *priv, st
+ tx_info->status.ampdu_len = 1;
+ }
+
+- /*
+- * If an underrun error is seen assume it as an excessive retry only
+- * if max frame trigger level has been reached (2 KB for singel stream,
+- * and 4 KB for dual stream). Adjust the long retry as if the frame was
+- * tried hw->max_rate_tries times to affect how ratectrl updates PER for
+- * the failed rate. In case of congestion on the bus penalizing these
+- * type of underruns should help hardware actually transmit new frames
+- * successfully by eventually preferring slower rates. This itself
+- * should also alleviate congestion on the bus.
+- */
+- if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
+- (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
+- tx_status = 1;
+- is_underrun = 1;
+- }
+-
+- if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
++ if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
+ tx_status = 1;
+
+ ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
+@@ -1596,8 +1580,6 @@ static void *ath_rate_alloc_sta(void *pr
+ return NULL;
+ }
+
+- rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
+-
+ return rate_priv;
+ }
+
+--- a/drivers/net/wireless/ath/ath9k/rc.h
++++ b/drivers/net/wireless/ath/ath9k/rc.h
+@@ -215,7 +215,6 @@ struct ath_rate_priv {
+ u32 per_down_time;
+ u32 probe_interval;
+ u32 prev_data_rix;
+- u32 tx_triglevel_max;
+ struct ath_rateset neg_rates;
+ struct ath_rateset neg_ht_rates;
+ struct ath_rate_softc *asc;
+@@ -225,11 +224,6 @@ struct ath_rate_priv {
+ struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
+ };
+
+-#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
+-#define ATH_TX_INFO_FRAME_TYPE_PAUSE (1 << 1)
+-#define ATH_TX_INFO_XRETRY (1 << 3)
+-#define ATH_TX_INFO_UNDERRUN (1 << 4)
+-
+ enum ath9k_internal_frame_type {
+ ATH9K_IFT_NOT_INTERNAL,
+ ATH9K_IFT_PAUSE,
+--- a/drivers/net/wireless/ath/ath9k/reg.h
++++ b/drivers/net/wireless/ath/ath9k/reg.h
+@@ -1066,6 +1066,9 @@ enum {
+ #define AR_INTR_PRIO_ASYNC_MASK 0x40c8
+ #define AR_INTR_PRIO_SYNC_MASK 0x40cc
+ #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
++#define AR_ENT_OTP 0x40d8
++#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
++#define AR_ENT_OTP_MPSD 0x00800000
+
+ #define AR_RTC_9300_PLL_DIV 0x000003ff
+ #define AR_RTC_9300_PLL_DIV_S 0
+--- a/drivers/net/wireless/ath/ath9k/virtual.c
++++ b/drivers/net/wireless/ath/ath9k/virtual.c
+@@ -305,13 +305,12 @@ void ath9k_wiphy_chan_work(struct work_s
+ * ath9k version of ieee80211_tx_status() for TX frames that are generated
+ * internally in the driver.
+ */
+-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
++void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype)
+ {
+ struct ath_wiphy *aphy = hw->priv;
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+
+- if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
+- aphy->state == ATH_WIPHY_PAUSING) {
++ if (ftype == ATH9K_IFT_PAUSE && aphy->state == ATH_WIPHY_PAUSING) {
+ if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
+ printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
+ "frame\n", wiphy_name(hw->wiphy));
+--- a/drivers/net/wireless/ath/ath9k/xmit.c
++++ b/drivers/net/wireless/ath/ath9k/xmit.c
+@@ -48,9 +48,9 @@ static u16 bits_per_symbol[][2] = {
+
+ #define IS_HT_RATE(_rate) ((_rate) & 0x80)
+
+-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
+- struct ath_atx_tid *tid,
+- struct list_head *bf_head);
++static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
++ struct ath_atx_tid *tid,
++ struct list_head *bf_head);
+ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
+ struct ath_txq *txq, struct list_head *bf_q,
+ struct ath_tx_status *ts, int txok, int sendbar);
+@@ -160,7 +160,7 @@ static void ath_tx_flush_tid(struct ath_
+ ath_tx_update_baw(sc, tid, bf->bf_seqno);
+ ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
+ } else {
+- ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
++ ath_tx_send_normal(sc, txq, tid, &bf_head);
+ }
+ }
+
+@@ -1322,9 +1322,9 @@ static void ath_tx_send_ampdu(struct ath
+ ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
+ }
+
+-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
+- struct ath_atx_tid *tid,
+- struct list_head *bf_head)
++static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
++ struct ath_atx_tid *tid,
++ struct list_head *bf_head)
+ {
+ struct ath_buf *bf;
+
+@@ -1332,7 +1332,8 @@ static void ath_tx_send_ht_normal(struct
+ bf->bf_state.bf_type &= ~BUF_AMPDU;
+
+ /* update starting sequence number for subsequent ADDBA request */
+- INCR(tid->seq_start, IEEE80211_SEQ_MAX);
++ if (tid)
++ INCR(tid->seq_start, IEEE80211_SEQ_MAX);
+
+ bf->bf_nframes = 1;
+ bf->bf_lastbf = bf;
+@@ -1341,20 +1342,6 @@ static void ath_tx_send_ht_normal(struct
+ TX_STAT_INC(txq->axq_qnum, queued);
+ }
+
+-static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+- struct list_head *bf_head)
+-{
+- struct ath_buf *bf;
+-
+- bf = list_first_entry(bf_head, struct ath_buf, list);
+-
+- bf->bf_lastbf = bf;
+- bf->bf_nframes = 1;
+- ath_buf_set_rate(sc, bf);
+- ath_tx_txqaddbuf(sc, txq, bf_head);
+- TX_STAT_INC(txq->axq_qnum, queued);
+-}
+-
+ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
+ {
+ struct ieee80211_hdr *hdr;
+@@ -1411,7 +1398,7 @@ static void assign_aggr_tid_seqno(struct
+ INCR(tid->seq_next, IEEE80211_SEQ_MAX);
+ }
+
+-static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
++static int setup_tx_flags(struct sk_buff *skb)
+ {
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ int flags = 0;
+@@ -1422,7 +1409,7 @@ static int setup_tx_flags(struct sk_buff
+ if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
+ flags |= ATH9K_TXDESC_NOACK;
+
+- if (use_ldpc)
++ if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
+ flags |= ATH9K_TXDESC_LDPC;
+
+ return flags;
+@@ -1567,30 +1554,25 @@ static void ath_buf_set_rate(struct ath_
+ ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
+ }
+
+-static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
+- struct sk_buff *skb,
+- struct ath_tx_control *txctl)
++static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
++ struct sk_buff *skb)
+ {
+ struct ath_wiphy *aphy = hw->priv;
+ struct ath_softc *sc = aphy->sc;
++ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
++ struct ath_buf *bf;
+ int hdrlen;
+ __le16 fc;
+ int padpos, padsize;
+- bool use_ldpc = false;
+
+- tx_info->pad[0] = 0;
+- switch (txctl->frame_type) {
+- case ATH9K_IFT_NOT_INTERNAL:
+- break;
+- case ATH9K_IFT_PAUSE:
+- tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
+- /* fall through */
+- case ATH9K_IFT_UNPAUSE:
+- tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
+- break;
++ bf = ath_tx_get_buffer(sc);
++ if (!bf) {
++ ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
++ return NULL;
+ }
++
+ hdrlen = ieee80211_get_hdrlen_from_skb(skb);
+ fc = hdr->frame_control;
+
+@@ -1605,16 +1587,13 @@ static int ath_tx_setup_buffer(struct ie
+ bf->bf_frmlen -= padsize;
+ }
+
+- if (!txctl->paprd && conf_is_ht(&hw->conf)) {
++ if (ieee80211_is_data_qos(fc) && conf_is_ht(&hw->conf)) {
+ bf->bf_state.bf_type |= BUF_HT;
+- if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
+- use_ldpc = true;
++ if (sc->sc_flags & SC_OP_TXAGGR)
++ assign_aggr_tid_seqno(skb, bf);
+ }
+
+- bf->bf_state.bfs_paprd = txctl->paprd;
+- if (txctl->paprd)
+- bf->bf_state.bfs_paprd_timestamp = jiffies;
+- bf->bf_flags = setup_tx_flags(skb, use_ldpc);
++ bf->bf_flags = setup_tx_flags(skb);
+
+ bf->bf_keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
+ if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
+@@ -1624,10 +1603,6 @@ static int ath_tx_setup_buffer(struct ie
+ bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
+ }
+
+- if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
+- (sc->sc_flags & SC_OP_TXAGGR))
+- assign_aggr_tid_seqno(skb, bf);
+-
+ bf->bf_mpdu = skb;
+
+ bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+@@ -1637,12 +1612,13 @@ static int ath_tx_setup_buffer(struct ie
+ bf->bf_buf_addr = 0;
+ ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
+ "dma_mapping_error() on TX\n");
+- return -ENOMEM;
++ ath_tx_return_buffer(sc, bf);
++ return NULL;
+ }
+
+ bf->bf_tx_aborted = false;
+
+- return 0;
++ return bf;
+ }
+
+ /* FIXME: tx power */
+@@ -1690,11 +1666,6 @@ static void ath_tx_start_dma(struct ath_
+ an = (struct ath_node *)tx_info->control.sta->drv_priv;
+ tid = ATH_AN_2_TID(an, bf->bf_tidno);
+
+- if (!ieee80211_is_data_qos(fc)) {
+- ath_tx_send_normal(sc, txctl->txq, &bf_head);
+- goto tx_done;
+- }
+-
+ WARN_ON(tid->ac->txq != txctl->txq);
+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+ /*
+@@ -1707,14 +1678,18 @@ static void ath_tx_start_dma(struct ath_
+ * Send this frame as regular when ADDBA
+ * exchange is neither complete nor pending.
+ */
+- ath_tx_send_ht_normal(sc, txctl->txq,
+- tid, &bf_head);
++ ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
+ }
+ } else {
+- ath_tx_send_normal(sc, txctl->txq, &bf_head);
++ bf->bf_state.bfs_ftype = txctl->frame_type;
++ bf->bf_state.bfs_paprd = txctl->paprd;
++
++ if (txctl->paprd)
++ bf->bf_state.bfs_paprd_timestamp = jiffies;
++
++ ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head);
+ }
+
+-tx_done:
+ spin_unlock_bh(&txctl->txq->axq_lock);
+ }
+
+@@ -1724,39 +1699,15 @@ int ath_tx_start(struct ieee80211_hw *hw
+ {
+ struct ath_wiphy *aphy = hw->priv;
+ struct ath_softc *sc = aphy->sc;
+- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_txq *txq = txctl->txq;
+ struct ath_buf *bf;
+- int q, r;
++ int q;
+
+- bf = ath_tx_get_buffer(sc);
+- if (!bf) {
+- ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
+- return -1;
+- }
++ bf = ath_tx_setup_buffer(hw, skb);
++ if (unlikely(!bf))
++ return -ENOMEM;
+
+ q = skb_get_queue_mapping(skb);
+- r = ath_tx_setup_buffer(hw, bf, skb, txctl);
+- if (unlikely(r)) {
+- ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
+-
+- /* upon ath_tx_processq() this TX queue will be resumed, we
+- * guarantee this will happen by knowing beforehand that
+- * we will at least have to run TX completionon one buffer
+- * on the queue */
+- spin_lock_bh(&txq->axq_lock);
+- if (txq == sc->tx.txq_map[q] && !txq->stopped &&
+- txq->axq_depth > 1) {
+- ath_mac80211_stop_queue(sc, q);
+- txq->stopped = 1;
+- }
+- spin_unlock_bh(&txq->axq_lock);
+-
+- ath_tx_return_buffer(sc, bf);
+-
+- return r;
+- }
+-
+ spin_lock_bh(&txq->axq_lock);
+ if (txq == sc->tx.txq_map[q] &&
+ ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
+@@ -1828,7 +1779,7 @@ exit:
+ /*****************/
+
+ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
+- struct ath_wiphy *aphy, int tx_flags,
++ struct ath_wiphy *aphy, int tx_flags, int ftype,
+ struct ath_txq *txq)
+ {
+ struct ieee80211_hw *hw = sc->hw;
+@@ -1872,8 +1823,8 @@ static void ath_tx_complete(struct ath_s
+ PS_WAIT_FOR_TX_ACK));
+ }
+
+- if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
+- ath9k_tx_status(hw, skb);
++ if (unlikely(ftype))
++ ath9k_tx_status(hw, skb, ftype);
+ else {
+ q = skb_get_queue_mapping(skb);
+ if (txq == sc->tx.txq_map[q]) {
+@@ -1917,7 +1868,8 @@ static void ath_tx_complete_buf(struct a
+ complete(&sc->paprd_complete);
+ } else {
+ ath_debug_stat_tx(sc, bf, ts);
+- ath_tx_complete(sc, skb, bf->aphy, tx_flags, txq);
++ ath_tx_complete(sc, skb, bf->aphy, tx_flags,
++ bf->bf_state.bfs_ftype, txq);
+ }
+ /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
+ * accidentally reference it later.
+@@ -1968,6 +1920,8 @@ static void ath_tx_rc_status(struct ath_
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_hw *hw = bf->aphy->hw;
++ struct ath_softc *sc = bf->aphy->sc;
++ struct ath_hw *ah = sc->sc_ah;
+ u8 i, tx_rateindex;
+
+ if (txok)
+@@ -1989,14 +1943,24 @@ static void ath_tx_rc_status(struct ath_
+
+ if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
+ (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
+- if (ieee80211_is_data(hdr->frame_control)) {
+- if (ts->ts_flags &
+- (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
+- tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
+- if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
+- (ts->ts_status & ATH9K_TXERR_FIFO))
+- tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
+- }
++ /*
++ * If an underrun error is seen assume it as an excessive
++ * retry only if max frame trigger level has been reached
++ * (2 KB for single stream, and 4 KB for dual stream).
++ * Adjust the long retry as if the frame was tried
++ * hw->max_rate_tries times to affect how rate control updates
++ * PER for the failed rate.
++ * In case of congestion on the bus penalizing this type of
++ * underruns should help hardware actually transmit new frames
++ * successfully by eventually preferring slower rates.
++ * This itself should also alleviate congestion on the bus.
++ */
++ if (ieee80211_is_data(hdr->frame_control) &&
++ (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
++ ATH9K_TX_DELIM_UNDERRUN)) &&
++ ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
++ tx_info->status.rates[tx_rateindex].count =
++ hw->max_rate_tries;
+ }
+
+ for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
diff --git a/package/mac80211/patches/520-ath9k_ar9003_regulatory_power.patch b/package/mac80211/patches/520-ath9k_ar9003_regulatory_power.patch
deleted file mode 100644
index 6d0ecef86..000000000
--- a/package/mac80211/patches/520-ath9k_ar9003_regulatory_power.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -2133,6 +2133,7 @@ static void ath9k_hw_ar9300_set_txpower(
- u8 twiceMaxRegulatoryPower,
- u8 powerLimit)
- {
-+ struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
- struct ath_common *common = ath9k_hw_common(ah);
- u8 targetPowerValT2[ar9300RateSize];
- unsigned int i = 0;
-@@ -2180,6 +2181,7 @@ static void ath9k_hw_ar9300_set_txpower(
- i = ALL_TARGET_HT20_0_8_16; /* ht20 */
-
- ah->txpower_limit = targetPowerValT2[i];
-+ regulatory->max_power_level = ratesArray[i];
-
- ar9003_hw_calibration_apply(ah, chan->channel);
- }
diff --git a/package/mac80211/patches/521-ath9k_hw_tx_power.patch b/package/mac80211/patches/521-ath9k_hw_tx_power.patch
deleted file mode 100644
index 118345088..000000000
--- a/package/mac80211/patches/521-ath9k_hw_tx_power.patch
+++ /dev/null
@@ -1,327 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/eeprom.h
-+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
-@@ -680,7 +680,8 @@ struct eeprom_ops {
- void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
- void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
- u16 cfgCtl, u8 twiceAntennaReduction,
-- u8 twiceMaxRegulatoryPower, u8 powerLimit);
-+ u8 twiceMaxRegulatoryPower, u8 powerLimit,
-+ bool test);
- u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
- };
-
---- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
-+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
-@@ -726,7 +726,7 @@ static void ath9k_hw_4k_set_txpower(stru
- u16 cfgCtl,
- u8 twiceAntennaReduction,
- u8 twiceMaxRegulatoryPower,
-- u8 powerLimit)
-+ u8 powerLimit, bool test)
- {
- struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
- struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
-@@ -751,15 +751,20 @@ static void ath9k_hw_4k_set_txpower(stru
-
- ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
-
-+ regulatory->max_power_level = 0;
- for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
- ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
- if (ratesArray[i] > AR5416_MAX_RATE_POWER)
- ratesArray[i] = AR5416_MAX_RATE_POWER;
-+
-+ if (ratesArray[i] > regulatory->max_power_level)
-+ regulatory->max_power_level = ratesArray[i];
- }
-
-+ if (test)
-+ return;
-
- /* Update regulatory */
--
- i = rate6mb;
- if (IS_CHAN_HT40(chan))
- i = rateHt40_0;
---- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
-+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
-@@ -853,7 +853,7 @@ static void ath9k_hw_ar9287_set_txpower(
- struct ath9k_channel *chan, u16 cfgCtl,
- u8 twiceAntennaReduction,
- u8 twiceMaxRegulatoryPower,
-- u8 powerLimit)
-+ u8 powerLimit, bool test)
- {
- struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
- struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
-@@ -877,12 +877,26 @@ static void ath9k_hw_ar9287_set_txpower(
-
- ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
-
-+ regulatory->max_power_level = 0;
- for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
- ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
- if (ratesArray[i] > AR9287_MAX_RATE_POWER)
- ratesArray[i] = AR9287_MAX_RATE_POWER;
-+
-+ if (ratesArray[i] > regulatory->max_power_level)
-+ regulatory->max_power_level = ratesArray[i];
- }
-
-+ if (test)
-+ return;
-+
-+ if (IS_CHAN_2GHZ(chan))
-+ i = rate1l;
-+ else
-+ i = rate6mb;
-+
-+ regulatory->max_power_level = ratesArray[i];
-+
- if (AR_SREV_9280_20_OR_LATER(ah)) {
- for (i = 0; i < Ar5416RateSize; i++)
- ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
-@@ -971,17 +985,6 @@ static void ath9k_hw_ar9287_set_txpower(
- | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
- | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
- }
--
-- if (IS_CHAN_2GHZ(chan))
-- i = rate1l;
-- else
-- i = rate6mb;
--
-- if (AR_SREV_9280_20_OR_LATER(ah))
-- regulatory->max_power_level =
-- ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
-- else
-- regulatory->max_power_level = ratesArray[i];
- }
-
- static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
---- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
-+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
-@@ -1258,7 +1258,7 @@ static void ath9k_hw_def_set_txpower(str
- u16 cfgCtl,
- u8 twiceAntennaReduction,
- u8 twiceMaxRegulatoryPower,
-- u8 powerLimit)
-+ u8 powerLimit, bool test)
- {
- #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
- struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
-@@ -1285,12 +1285,44 @@ static void ath9k_hw_def_set_txpower(str
-
- ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
-
-+ regulatory->max_power_level = 0;
- for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
- ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
- if (ratesArray[i] > AR5416_MAX_RATE_POWER)
- ratesArray[i] = AR5416_MAX_RATE_POWER;
-+ if (ratesArray[i] > regulatory->max_power_level)
-+ regulatory->max_power_level = ratesArray[i];
- }
-
-+ if (!test) {
-+ i = rate6mb;
-+
-+ if (IS_CHAN_HT40(chan))
-+ i = rateHt40_0;
-+ else if (IS_CHAN_HT20(chan))
-+ i = rateHt20_0;
-+
-+ regulatory->max_power_level = ratesArray[i];
-+ }
-+
-+ switch(ar5416_get_ntxchains(ah->txchainmask)) {
-+ case 1:
-+ break;
-+ case 2:
-+ regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
-+ break;
-+ case 3:
-+ regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
-+ break;
-+ default:
-+ ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
-+ "Invalid chainmask configuration\n");
-+ break;
-+ }
-+
-+ if (test)
-+ return;
-+
- if (AR_SREV_9280_20_OR_LATER(ah)) {
- for (i = 0; i < Ar5416RateSize; i++) {
- int8_t pwr_table_offset;
-@@ -1387,34 +1419,6 @@ static void ath9k_hw_def_set_txpower(str
- REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
- ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
- | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
--
-- i = rate6mb;
--
-- if (IS_CHAN_HT40(chan))
-- i = rateHt40_0;
-- else if (IS_CHAN_HT20(chan))
-- i = rateHt20_0;
--
-- if (AR_SREV_9280_20_OR_LATER(ah))
-- regulatory->max_power_level =
-- ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
-- else
-- regulatory->max_power_level = ratesArray[i];
--
-- switch(ar5416_get_ntxchains(ah->txchainmask)) {
-- case 1:
-- break;
-- case 2:
-- regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
-- break;
-- case 3:
-- regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
-- break;
-- default:
-- ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
-- "Invalid chainmask configuration\n");
-- break;
-- }
- }
-
- static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -2131,7 +2131,7 @@ static void ath9k_hw_ar9300_set_txpower(
- struct ath9k_channel *chan, u16 cfgCtl,
- u8 twiceAntennaReduction,
- u8 twiceMaxRegulatoryPower,
-- u8 powerLimit)
-+ u8 powerLimit, bool test)
- {
- struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
- struct ath_common *common = ath9k_hw_common(ah);
-@@ -2145,7 +2145,16 @@ static void ath9k_hw_ar9300_set_txpower(
- twiceMaxRegulatoryPower,
- powerLimit);
-
-- while (i < ar9300RateSize) {
-+ regulatory->max_power_level = 0;
-+ for (i = 0; i < ar9300RateSize; i++) {
-+ if (targetPowerValT2[i] > regulatory->max_power_level)
-+ regulatory->max_power_level = targetPowerValT2[i];
-+ }
-+
-+ if (test)
-+ return;
-+
-+ for (i = 0; i < ar9300RateSize; i++) {
- ath_print(common, ATH_DBG_EEPROM,
- "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
- i++;
-@@ -2160,9 +2169,6 @@ static void ath9k_hw_ar9300_set_txpower(
- i++;
- }
-
-- /* Write target power array to registers */
-- ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
--
- /*
- * This is the TX power we send back to driver core,
- * and it can use to pass to userspace to display our
-@@ -2181,8 +2187,10 @@ static void ath9k_hw_ar9300_set_txpower(
- i = ALL_TARGET_HT20_0_8_16; /* ht20 */
-
- ah->txpower_limit = targetPowerValT2[i];
-- regulatory->max_power_level = ratesArray[i];
-+ regulatory->max_power_level = targetPowerValT2[i];
-
-+ /* Write target power array to registers */
-+ ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
- ar9003_hw_calibration_apply(ah, chan->channel);
- }
-
---- a/drivers/net/wireless/ath/ath9k/hw.c
-+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1178,7 +1178,7 @@ static bool ath9k_hw_channel_change(stru
- channel->max_antenna_gain * 2,
- channel->max_power * 2,
- min((u32) MAX_RATE_POWER,
-- (u32) regulatory->power_limit));
-+ (u32) regulatory->power_limit), false);
-
- ath9k_hw_rfbus_done(ah);
-
-@@ -2193,7 +2193,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
- }
- EXPORT_SYMBOL(ath9k_hw_disable);
-
--void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
-+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
- {
- struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
- struct ath9k_channel *chan = ah->curchan;
-@@ -2206,7 +2206,7 @@ void ath9k_hw_set_txpowerlimit(struct at
- channel->max_antenna_gain * 2,
- channel->max_power * 2,
- min((u32) MAX_RATE_POWER,
-- (u32) regulatory->power_limit));
-+ (u32) regulatory->power_limit), test);
- }
- EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
-
---- a/drivers/net/wireless/ath/ath9k/hw.h
-+++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -862,7 +862,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *
- void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
- bool ath9k_hw_phy_disable(struct ath_hw *ah);
- bool ath9k_hw_disable(struct ath_hw *ah);
--void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
-+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
- void ath9k_hw_setopmode(struct ath_hw *ah);
- void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
- void ath9k_hw_setbssidmask(struct ath_hw *ah);
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -24,7 +24,7 @@ static void ath_update_txpow(struct ath_
- struct ath_hw *ah = sc->sc_ah;
-
- if (sc->curtxpow != sc->config.txpowlimit) {
-- ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
-+ ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
- /* read back in case value is clamped */
- sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
- }
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-@@ -614,7 +614,7 @@ static int ar9003_hw_process_ini(struct
- channel->max_antenna_gain * 2,
- channel->max_power * 2,
- min((u32) MAX_RATE_POWER,
-- (u32) regulatory->power_limit));
-+ (u32) regulatory->power_limit), false);
-
- return 0;
- }
---- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
-@@ -875,7 +875,7 @@ static int ar5008_hw_process_ini(struct
- channel->max_antenna_gain * 2,
- channel->max_power * 2,
- min((u32) MAX_RATE_POWER,
-- (u32) regulatory->power_limit));
-+ (u32) regulatory->power_limit), false);
-
- /* Write analog registers */
- if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
---- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
-+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
-@@ -29,7 +29,7 @@ static void ath_update_txpow(struct ath9
- struct ath_hw *ah = priv->ah;
-
- if (priv->curtxpow != priv->txpowlimit) {
-- ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit);
-+ ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit, false);
- /* read back in case value is clamped */
- priv->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
- }
diff --git a/package/mac80211/patches/522-ath9k_tx_power_init.patch b/package/mac80211/patches/522-ath9k_tx_power_init.patch
deleted file mode 100644
index de25219f3..000000000
--- a/package/mac80211/patches/522-ath9k_tx_power_init.patch
+++ /dev/null
@@ -1,115 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/init.c
-+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -654,6 +654,37 @@ err_hw:
- return ret;
- }
-
-+static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
-+{
-+ struct ieee80211_supported_band *sband;
-+ struct ieee80211_channel *chan;
-+ struct ath_hw *ah = sc->sc_ah;
-+ struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
-+ int i;
-+
-+ sband = &sc->sbands[band];
-+ for (i = 0; i < sband->n_channels; i++) {
-+ chan = &sband->channels[i];
-+ ah->curchan = &ah->channels[chan->hw_value];
-+ ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
-+ ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
-+ chan->max_power = reg->max_power_level / 2;
-+ }
-+}
-+
-+static void ath9k_init_txpower_limits(struct ath_softc *sc)
-+{
-+ struct ath_hw *ah = sc->sc_ah;
-+ struct ath9k_channel *curchan = ah->curchan;
-+
-+ if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
-+ ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
-+ if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
-+ ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
-+
-+ ah->curchan = curchan;
-+}
-+
- void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
- {
- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-@@ -748,6 +779,8 @@ int ath9k_init_device(u16 devid, struct
- if (error != 0)
- goto error_rx;
-
-+ ath9k_init_txpower_limits(sc);
-+
- /* Register with mac80211 */
- error = ieee80211_register_hw(hw);
- if (error)
---- a/drivers/net/wireless/ath/ath9k/common.c
-+++ b/drivers/net/wireless/ath/ath9k/common.c
-@@ -107,12 +107,10 @@ static u32 ath9k_get_extchanmode(struct
- /*
- * Update internal channel flags.
- */
--void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-- struct ath9k_channel *ichan)
-+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
-+ struct ieee80211_channel *chan,
-+ enum nl80211_channel_type channel_type)
- {
-- struct ieee80211_channel *chan = hw->conf.channel;
-- struct ieee80211_conf *conf = &hw->conf;
--
- ichan->channel = chan->center_freq;
- ichan->chan = chan;
-
-@@ -124,9 +122,8 @@ void ath9k_cmn_update_ichannel(struct ie
- ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
- }
-
-- if (conf_is_ht(conf))
-- ichan->chanmode = ath9k_get_extchanmode(chan,
-- conf->channel_type);
-+ if (channel_type != NL80211_CHAN_NO_HT)
-+ ichan->chanmode = ath9k_get_extchanmode(chan, channel_type);
- }
- EXPORT_SYMBOL(ath9k_cmn_update_ichannel);
-
-@@ -142,7 +139,7 @@ struct ath9k_channel *ath9k_cmn_get_curc
-
- chan_idx = curchan->hw_value;
- channel = &ah->channels[chan_idx];
-- ath9k_cmn_update_ichannel(hw, channel);
-+ ath9k_cmn_update_ichannel(channel, curchan, hw->conf.channel_type);
-
- return channel;
- }
---- a/drivers/net/wireless/ath/ath9k/common.h
-+++ b/drivers/net/wireless/ath/ath9k/common.h
-@@ -62,8 +62,9 @@ enum ath_stomp_type {
-
- int ath9k_cmn_padpos(__le16 frame_control);
- int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb);
--void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-- struct ath9k_channel *ichan);
-+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
-+ struct ieee80211_channel *chan,
-+ enum nl80211_channel_type channel_type);
- struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
- struct ath_hw *ah);
- int ath9k_cmn_count_streams(unsigned int chainmask, int max);
---- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
-+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
-@@ -1405,7 +1405,9 @@ static int ath9k_htc_config(struct ieee8
- ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
- curchan->center_freq);
-
-- ath9k_cmn_update_ichannel(hw, &priv->ah->channels[pos]);
-+ ath9k_cmn_update_ichannel(&priv->ah->channels[pos],
-+ hw->conf.channel,
-+ hw->conf.channel_type);
-
- if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
- ath_print(common, ATH_DBG_FATAL,
diff --git a/package/mac80211/patches/530-ath9k_locking_fix.patch b/package/mac80211/patches/530-ath9k_locking_fix.patch
deleted file mode 100644
index 354b72030..000000000
--- a/package/mac80211/patches/530-ath9k_locking_fix.patch
+++ /dev/null
@@ -1,363 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ath9k.h
-+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
-@@ -309,7 +309,6 @@ struct ath_rx {
- u8 rxotherant;
- u32 *rxlink;
- unsigned int rxfilter;
-- spinlock_t rxflushlock;
- spinlock_t rxbuflock;
- struct list_head rxbuf;
- struct ath_descdma rxdma;
-@@ -599,9 +598,9 @@ struct ath_softc {
- struct ath_hw *sc_ah;
- void __iomem *mem;
- int irq;
-- spinlock_t sc_resetlock;
- spinlock_t sc_serial_rw;
- spinlock_t sc_pm_lock;
-+ spinlock_t sc_pcu_lock;
- struct mutex mutex;
- struct work_struct paprd_work;
- struct work_struct hw_check_work;
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -228,6 +228,8 @@ int ath_set_channel(struct ath_softc *sc
-
- ath9k_ps_wakeup(sc);
-
-+ spin_lock_bh(&sc->sc_pcu_lock);
-+
- /*
- * This is only performed if the channel settings have
- * actually changed.
-@@ -239,6 +241,7 @@ int ath_set_channel(struct ath_softc *sc
- */
- ath9k_hw_disable_interrupts(ah);
- ath_drain_all_txq(sc, false);
-+
- stopped = ath_stoprecv(sc);
-
- /* XXX: do not flush receive queue here. We don't want
-@@ -257,18 +260,14 @@ int ath_set_channel(struct ath_softc *sc
- channel->center_freq, conf_is_ht40(conf),
- fastcc);
-
-- spin_lock_bh(&sc->sc_resetlock);
--
- r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
- if (r) {
- ath_print(common, ATH_DBG_FATAL,
- "Unable to reset channel (%u MHz), "
- "reset status %d\n",
- channel->center_freq, r);
-- spin_unlock_bh(&sc->sc_resetlock);
- goto ps_restore;
- }
-- spin_unlock_bh(&sc->sc_resetlock);
-
- if (ath_startrecv(sc) != 0) {
- ath_print(common, ATH_DBG_FATAL,
-@@ -287,6 +286,8 @@ int ath_set_channel(struct ath_softc *sc
- }
-
- ps_restore:
-+ spin_unlock_bh(&sc->sc_pcu_lock);
-+
- ath9k_ps_restore(sc);
- return r;
- }
-@@ -600,6 +601,8 @@ void ath9k_tasklet(unsigned long data)
- return;
- }
-
-+ spin_lock_bh(&sc->sc_pcu_lock);
-+
- if (!ath9k_hw_check_alive(ah))
- ieee80211_queue_work(sc->hw, &sc->hw_check_work);
-
-@@ -610,15 +613,12 @@ void ath9k_tasklet(unsigned long data)
- rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
-
- if (status & rxmask) {
-- spin_lock_bh(&sc->rx.rxflushlock);
--
- /* Check for high priority Rx first */
- if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
- (status & ATH9K_INT_RXHP))
- ath_rx_tasklet(sc, 0, true);
-
- ath_rx_tasklet(sc, 0, false);
-- spin_unlock_bh(&sc->rx.rxflushlock);
- }
-
- if (status & ATH9K_INT_TX) {
-@@ -644,6 +644,8 @@ void ath9k_tasklet(unsigned long data)
-
- /* re-enable hardware interrupt */
- ath9k_hw_enable_interrupts(ah);
-+
-+ spin_unlock_bh(&sc->sc_pcu_lock);
- ath9k_ps_restore(sc);
- }
-
-@@ -871,12 +873,13 @@ void ath_radio_enable(struct ath_softc *
- int r;
-
- ath9k_ps_wakeup(sc);
-+ spin_lock_bh(&sc->sc_pcu_lock);
-+
- ath9k_hw_configpcipowersave(ah, 0, 0);
-
- if (!ah->curchan)
- ah->curchan = ath_get_curchannel(sc, sc->hw);
-
-- spin_lock_bh(&sc->sc_resetlock);
- r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
- if (r) {
- ath_print(common, ATH_DBG_FATAL,
-@@ -884,15 +887,14 @@ void ath_radio_enable(struct ath_softc *
- "reset status %d\n",
- channel->center_freq, r);
- }
-- spin_unlock_bh(&sc->sc_resetlock);
-
- ath_update_txpow(sc);
- if (ath_startrecv(sc) != 0) {
- ath_print(common, ATH_DBG_FATAL,
- "Unable to restart recv logic\n");
-+ spin_unlock_bh(&sc->sc_pcu_lock);
- return;
- }
--
- if (sc->sc_flags & SC_OP_BEACONS)
- ath_beacon_config(sc, NULL); /* restart beacons */
-
-@@ -905,6 +907,8 @@ void ath_radio_enable(struct ath_softc *
- ath9k_hw_set_gpio(ah, ah->led_pin, 0);
-
- ieee80211_wake_queues(hw);
-+ spin_unlock_bh(&sc->sc_pcu_lock);
-+
- ath9k_ps_restore(sc);
- }
-
-@@ -915,6 +919,8 @@ void ath_radio_disable(struct ath_softc
- int r;
-
- ath9k_ps_wakeup(sc);
-+ spin_lock_bh(&sc->sc_pcu_lock);
-+
- ieee80211_stop_queues(hw);
-
- /*
-@@ -930,13 +936,13 @@ void ath_radio_disable(struct ath_softc
- ath9k_hw_disable_interrupts(ah);
-
- ath_drain_all_txq(sc, false); /* clear pending tx frames */
-+
- ath_stoprecv(sc); /* turn off frame recv */
- ath_flushrecv(sc); /* flush recv queue */
-
- if (!ah->curchan)
- ah->curchan = ath_get_curchannel(sc, hw);
-
-- spin_lock_bh(&sc->sc_resetlock);
- r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
- if (r) {
- ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-@@ -944,11 +950,14 @@ void ath_radio_disable(struct ath_softc
- "reset status %d\n",
- channel->center_freq, r);
- }
-- spin_unlock_bh(&sc->sc_resetlock);
-
- ath9k_hw_phy_disable(ah);
-+
- ath9k_hw_configpcipowersave(ah, 1, 1);
-+
-+ spin_unlock_bh(&sc->sc_pcu_lock);
- ath9k_ps_restore(sc);
-+
- ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
- }
-
-@@ -962,19 +971,20 @@ int ath_reset(struct ath_softc *sc, bool
- /* Stop ANI */
- del_timer_sync(&common->ani.timer);
-
-+ spin_lock_bh(&sc->sc_pcu_lock);
-+
- ieee80211_stop_queues(hw);
-
- ath9k_hw_disable_interrupts(ah);
- ath_drain_all_txq(sc, retry_tx);
-+
- ath_stoprecv(sc);
- ath_flushrecv(sc);
-
-- spin_lock_bh(&sc->sc_resetlock);
- r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
- if (r)
- ath_print(common, ATH_DBG_FATAL,
- "Unable to reset hardware; reset status %d\n", r);
-- spin_unlock_bh(&sc->sc_resetlock);
-
- if (ath_startrecv(sc) != 0)
- ath_print(common, ATH_DBG_FATAL,
-@@ -1004,6 +1014,7 @@ int ath_reset(struct ath_softc *sc, bool
- }
-
- ieee80211_wake_queues(hw);
-+ spin_unlock_bh(&sc->sc_pcu_lock);
-
- /* Start ANI */
- ath_start_ani(common);
-@@ -1142,17 +1153,16 @@ static int ath9k_start(struct ieee80211_
- * be followed by initialization of the appropriate bits
- * and then setup of the interrupt mask.
- */
-- spin_lock_bh(&sc->sc_resetlock);
-+ spin_lock_bh(&sc->sc_pcu_lock);
- r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
- if (r) {
- ath_print(common, ATH_DBG_FATAL,
- "Unable to reset hardware; reset status %d "
- "(freq %u MHz)\n", r,
- curchan->center_freq);
-- spin_unlock_bh(&sc->sc_resetlock);
-+ spin_unlock_bh(&sc->sc_pcu_lock);
- goto mutex_unlock;
- }
-- spin_unlock_bh(&sc->sc_resetlock);
-
- /*
- * This is needed only to setup initial state
-@@ -1171,8 +1181,10 @@ static int ath9k_start(struct ieee80211_
- ath_print(common, ATH_DBG_FATAL,
- "Unable to start recv logic\n");
- r = -EIO;
-+ spin_unlock_bh(&sc->sc_pcu_lock);
- goto mutex_unlock;
- }
-+ spin_unlock_bh(&sc->sc_pcu_lock);
-
- /* Setup our intr mask. */
- ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
-@@ -1367,6 +1379,8 @@ static void ath9k_stop(struct ieee80211_
- ath9k_btcoex_timer_pause(sc);
- }
-
-+ spin_lock_bh(&sc->sc_pcu_lock);
-+
- /* make sure h/w will not generate any interrupt
- * before setting the invalid flag. */
- ath9k_hw_disable_interrupts(ah);
-@@ -1381,6 +1395,9 @@ static void ath9k_stop(struct ieee80211_
- /* disable HAL and put h/w to sleep */
- ath9k_hw_disable(ah);
- ath9k_hw_configpcipowersave(ah, 1, 1);
-+
-+ spin_unlock_bh(&sc->sc_pcu_lock);
-+
- ath9k_ps_restore(sc);
-
- /* Finally, put the chip in FULL SLEEP mode */
---- a/drivers/net/wireless/ath/ath9k/recv.c
-+++ b/drivers/net/wireless/ath/ath9k/recv.c
-@@ -297,19 +297,17 @@ static void ath_edma_start_recv(struct a
- ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
- sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
-
-- spin_unlock_bh(&sc->rx.rxbuflock);
--
- ath_opmode_init(sc);
-
- ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
-+
-+ spin_unlock_bh(&sc->rx.rxbuflock);
- }
-
- static void ath_edma_stop_recv(struct ath_softc *sc)
- {
-- spin_lock_bh(&sc->rx.rxbuflock);
- ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
- ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
-- spin_unlock_bh(&sc->rx.rxbuflock);
- }
-
- int ath_rx_init(struct ath_softc *sc, int nbufs)
-@@ -319,7 +317,7 @@ int ath_rx_init(struct ath_softc *sc, in
- struct ath_buf *bf;
- int error = 0;
-
-- spin_lock_init(&sc->rx.rxflushlock);
-+ spin_lock_init(&sc->sc_pcu_lock);
- sc->sc_flags &= ~SC_OP_RXFLUSH;
- spin_lock_init(&sc->rx.rxbuflock);
-
-@@ -506,9 +504,9 @@ int ath_startrecv(struct ath_softc *sc)
- ath9k_hw_rxena(ah);
-
- start_recv:
-- spin_unlock_bh(&sc->rx.rxbuflock);
- ath_opmode_init(sc);
- ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
-+ spin_unlock_bh(&sc->rx.rxbuflock);
-
- return 0;
- }
-@@ -518,6 +516,7 @@ bool ath_stoprecv(struct ath_softc *sc)
- struct ath_hw *ah = sc->sc_ah;
- bool stopped;
-
-+ spin_lock_bh(&sc->rx.rxbuflock);
- ath9k_hw_stoppcurecv(ah);
- ath9k_hw_setrxfilter(ah, 0);
- stopped = ath9k_hw_stopdmarecv(ah);
-@@ -526,19 +525,18 @@ bool ath_stoprecv(struct ath_softc *sc)
- ath_edma_stop_recv(sc);
- else
- sc->rx.rxlink = NULL;
-+ spin_unlock_bh(&sc->rx.rxbuflock);
-
- return stopped;
- }
-
- void ath_flushrecv(struct ath_softc *sc)
- {
-- spin_lock_bh(&sc->rx.rxflushlock);
- sc->sc_flags |= SC_OP_RXFLUSH;
- if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
- ath_rx_tasklet(sc, 1, true);
- ath_rx_tasklet(sc, 1, false);
- sc->sc_flags &= ~SC_OP_RXFLUSH;
-- spin_unlock_bh(&sc->rx.rxflushlock);
- }
-
- static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
---- a/drivers/net/wireless/ath/ath9k/init.c
-+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -592,7 +592,6 @@ static int ath9k_init_softc(u16 devid, s
- spin_lock_init(&common->cc_lock);
-
- spin_lock_init(&sc->wiphy_lock);
-- spin_lock_init(&sc->sc_resetlock);
- spin_lock_init(&sc->sc_serial_rw);
- spin_lock_init(&sc->sc_pm_lock);
- mutex_init(&sc->mutex);
---- a/drivers/net/wireless/ath/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -1142,13 +1142,11 @@ void ath_drain_all_txq(struct ath_softc
- ath_print(common, ATH_DBG_FATAL,
- "Failed to stop TX DMA. Resetting hardware!\n");
-
-- spin_lock_bh(&sc->sc_resetlock);
- r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
- if (r)
- ath_print(common, ATH_DBG_FATAL,
- "Unable to reset hardware; reset status %d\n",
- r);
-- spin_unlock_bh(&sc->sc_resetlock);
- }
-
- for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
diff --git a/package/mac80211/patches/540-ath9k_fix_survey_crash.patch b/package/mac80211/patches/540-ath9k_fix_survey_crash.patch
deleted file mode 100644
index b627f8f4a..000000000
--- a/package/mac80211/patches/540-ath9k_fix_survey_crash.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -183,6 +183,9 @@ static void ath_update_survey_stats(stru
- struct ath_cycle_counters *cc = &common->cc_survey;
- unsigned int div = common->clockrate * 1000;
-
-+ if (!ah->curchan)
-+ return;
-+
- if (ah->power_mode == ATH9K_PM_AWAKE)
- ath_hw_cycle_counters_update(common);
-
diff --git a/package/mac80211/patches/550-ath9k_xretry_fix.patch b/package/mac80211/patches/550-ath9k_xretry_fix.patch
deleted file mode 100644
index 122be5b2a..000000000
--- a/package/mac80211/patches/550-ath9k_xretry_fix.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
-@@ -237,13 +237,15 @@ static int ar9002_hw_proc_txdesc(struct
- status = ACCESS_ONCE(ads->ds_txstatus1);
- if (status & AR_FrmXmitOK)
- ts->ts_status |= ATH9K_TX_ACKED;
-- if (status & AR_ExcessiveRetries)
-- ts->ts_status |= ATH9K_TXERR_XRETRY;
-- if (status & AR_Filtered)
-- ts->ts_status |= ATH9K_TXERR_FILT;
-- if (status & AR_FIFOUnderrun) {
-- ts->ts_status |= ATH9K_TXERR_FIFO;
-- ath9k_hw_updatetxtriglevel(ah, true);
-+ else {
-+ if (status & AR_ExcessiveRetries)
-+ ts->ts_status |= ATH9K_TXERR_XRETRY;
-+ if (status & AR_Filtered)
-+ ts->ts_status |= ATH9K_TXERR_FILT;
-+ if (status & AR_FIFOUnderrun) {
-+ ts->ts_status |= ATH9K_TXERR_FIFO;
-+ ath9k_hw_updatetxtriglevel(ah, true);
-+ }
- }
- if (status & AR_TxTimerExpired)
- ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
diff --git a/package/mac80211/patches/560-ath9k_aggr_sampling_fix.patch b/package/mac80211/patches/560-ath9k_aggr_sampling_fix.patch
deleted file mode 100644
index 66a341901..000000000
--- a/package/mac80211/patches/560-ath9k_aggr_sampling_fix.patch
+++ /dev/null
@@ -1,22 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -673,6 +673,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
- u16 aggr_limit = 0, al = 0, bpad = 0,
- al_delta, h_baw = tid->baw_size / 2;
- enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
-+ struct ieee80211_tx_info *tx_info;
-
- bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
-
-@@ -699,6 +700,11 @@ static enum ATH_AGGR_STATUS ath_tx_form_
- break;
- }
-
-+ tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
-+ if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
-+ !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
-+ break;
-+
- /* do not exceed subframe limit */
- if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
- status = ATH_AGGR_LIMITED;
diff --git a/package/mac80211/patches/561-minstrel_sample_retransmit.patch b/package/mac80211/patches/561-minstrel_sample_retransmit.patch
deleted file mode 100644
index 2ae03d878..000000000
--- a/package/mac80211/patches/561-minstrel_sample_retransmit.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/net/mac80211/rc80211_minstrel_ht.c
-+++ b/net/mac80211/rc80211_minstrel_ht.c
-@@ -506,7 +506,9 @@ minstrel_ht_set_rate(struct minstrel_pri
- if (!mr->retry_updated)
- minstrel_calc_retransmit(mp, mi, index);
-
-- if (mr->probability < MINSTREL_FRAC(20, 100))
-+ if (sample)
-+ rate->count = 1;
-+ else if (mr->probability < MINSTREL_FRAC(20, 100))
- rate->count = 2;
- else if (rtscts)
- rate->count = mr->retry_count_rtscts;
diff --git a/package/mac80211/patches/562-minstrel_sample_performance.patch b/package/mac80211/patches/562-minstrel_sample_performance.patch
deleted file mode 100644
index 424a74160..000000000
--- a/package/mac80211/patches/562-minstrel_sample_performance.patch
+++ /dev/null
@@ -1,52 +0,0 @@
---- a/net/mac80211/rc80211_minstrel_ht.c
-+++ b/net/mac80211/rc80211_minstrel_ht.c
-@@ -407,8 +407,8 @@ minstrel_ht_tx_status(void *priv, struct
- mi->ampdu_len += info->status.ampdu_len;
-
- if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
-- mi->sample_wait = 4 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
-- mi->sample_tries = 3;
-+ mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
-+ mi->sample_tries = 2;
- mi->sample_count--;
- }
-
-@@ -564,7 +564,7 @@ minstrel_get_sample_rate(struct minstrel
- */
- if (minstrel_get_duration(sample_idx) >
- minstrel_get_duration(mi->max_tp_rate)) {
-- if (mr->sample_skipped < 10)
-+ if (mr->sample_skipped < 20)
- goto next;
-
- if (mi->sample_slow++ > 2)
-@@ -588,6 +588,7 @@ minstrel_ht_get_rate(void *priv, struct
- struct minstrel_ht_sta *mi = &msp->ht;
- struct minstrel_priv *mp = priv;
- int sample_idx;
-+ bool sample = false;
-
- if (rate_control_send_low(sta, priv_sta, txrc))
- return;
-@@ -598,10 +599,11 @@ minstrel_ht_get_rate(void *priv, struct
- info->flags |= mi->tx_flags;
- sample_idx = minstrel_get_sample_rate(mp, mi);
- if (sample_idx >= 0) {
-+ sample = true;
- minstrel_ht_set_rate(mp, mi, &ar[0], sample_idx,
- txrc, true, false);
- minstrel_ht_set_rate(mp, mi, &ar[1], mi->max_tp_rate,
-- txrc, false, true);
-+ txrc, false, false);
- info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
- } else {
- minstrel_ht_set_rate(mp, mi, &ar[0], mi->max_tp_rate,
-@@ -609,7 +611,7 @@ minstrel_ht_get_rate(void *priv, struct
- minstrel_ht_set_rate(mp, mi, &ar[1], mi->max_tp_rate2,
- txrc, false, true);
- }
-- minstrel_ht_set_rate(mp, mi, &ar[2], mi->max_prob_rate, txrc, false, true);
-+ minstrel_ht_set_rate(mp, mi, &ar[2], mi->max_prob_rate, txrc, false, !sample);
-
- ar[3].count = 0;
- ar[3].idx = -1;
diff --git a/package/mac80211/patches/570-ath9k_reset_aggr_fix.patch b/package/mac80211/patches/570-ath9k_reset_aggr_fix.patch
deleted file mode 100644
index 81866d6e8..000000000
--- a/package/mac80211/patches/570-ath9k_reset_aggr_fix.patch
+++ /dev/null
@@ -1,42 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -581,7 +581,7 @@ void ath_hw_check(struct work_struct *wo
-
- msleep(1);
- }
-- ath_reset(sc, false);
-+ ath_reset(sc, true);
-
- out:
- ath9k_ps_restore(sc);
-@@ -599,7 +599,7 @@ void ath9k_tasklet(unsigned long data)
- ath9k_ps_wakeup(sc);
-
- if (status & ATH9K_INT_FATAL) {
-- ath_reset(sc, false);
-+ ath_reset(sc, true);
- ath9k_ps_restore(sc);
- return;
- }
---- a/drivers/net/wireless/ath/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -2161,7 +2161,7 @@ static void ath_tx_complete_poll_work(st
- ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
- "tx hung, resetting the chip\n");
- ath9k_ps_wakeup(sc);
-- ath_reset(sc, false);
-+ ath_reset(sc, true);
- ath9k_ps_restore(sc);
- }
-
---- a/drivers/net/wireless/ath/ath9k/beacon.c
-+++ b/drivers/net/wireless/ath/ath9k/beacon.c
-@@ -370,7 +370,7 @@ void ath_beacon_tasklet(unsigned long da
- ath_print(common, ATH_DBG_BSTUCK,
- "beacon is officially stuck\n");
- sc->sc_flags |= SC_OP_TSF_RESET;
-- ath_reset(sc, false);
-+ ath_reset(sc, true);
- }
-
- return;
diff --git a/package/mac80211/patches/571-ath9k_ar9300_aggr_flush.patch b/package/mac80211/patches/571-ath9k_ar9300_aggr_flush.patch
deleted file mode 100644
index 3d4cfe88a..000000000
--- a/package/mac80211/patches/571-ath9k_ar9300_aggr_flush.patch
+++ /dev/null
@@ -1,34 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -1089,15 +1089,6 @@ void ath_draintxq(struct ath_softc *sc,
- txq->axq_tx_inprogress = false;
- spin_unlock_bh(&txq->axq_lock);
-
-- /* flush any pending frames if aggregation is enabled */
-- if (sc->sc_flags & SC_OP_TXAGGR) {
-- if (!retry_tx) {
-- spin_lock_bh(&txq->axq_lock);
-- ath_txq_drain_pending_buffers(sc, txq);
-- spin_unlock_bh(&txq->axq_lock);
-- }
-- }
--
- if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
- spin_lock_bh(&txq->axq_lock);
- while (!list_empty(&txq->txq_fifo_pending)) {
-@@ -1118,6 +1109,15 @@ void ath_draintxq(struct ath_softc *sc,
- }
- spin_unlock_bh(&txq->axq_lock);
- }
-+
-+ /* flush any pending frames if aggregation is enabled */
-+ if (sc->sc_flags & SC_OP_TXAGGR) {
-+ if (!retry_tx) {
-+ spin_lock_bh(&txq->axq_lock);
-+ ath_txq_drain_pending_buffers(sc, txq);
-+ spin_unlock_bh(&txq->axq_lock);
-+ }
-+ }
- }
-
- void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
diff --git a/package/mac80211/patches/572-ath9k_xmit_queue_cleanup.patch b/package/mac80211/patches/572-ath9k_xmit_queue_cleanup.patch
deleted file mode 100644
index 3e99c080a..000000000
--- a/package/mac80211/patches/572-ath9k_xmit_queue_cleanup.patch
+++ /dev/null
@@ -1,714 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/ath9k.h
-+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
-@@ -195,7 +195,6 @@ enum ATH_AGGR_STATUS {
-
- #define ATH_TXFIFO_DEPTH 8
- struct ath_txq {
-- int axq_class;
- u32 axq_qnum;
- u32 *axq_link;
- struct list_head axq_q;
-@@ -208,11 +207,12 @@ struct ath_txq {
- struct list_head txq_fifo_pending;
- u8 txq_headidx;
- u8 txq_tailidx;
-+ int pending_frames;
- };
-
- struct ath_atx_ac {
-+ struct ath_txq *txq;
- int sched;
-- int qnum;
- struct list_head list;
- struct list_head tid_q;
- };
-@@ -290,12 +290,11 @@ struct ath_tx_control {
- struct ath_tx {
- u16 seq_no;
- u32 txqsetup;
-- int hwq_map[WME_NUM_AC];
- spinlock_t txbuflock;
- struct list_head txbuf;
- struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
- struct ath_descdma txdma;
-- int pending_frames[WME_NUM_AC];
-+ struct ath_txq *txq_map[WME_NUM_AC];
- };
-
- struct ath_rx_edma {
-@@ -325,7 +324,6 @@ void ath_rx_cleanup(struct ath_softc *sc
- int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
- struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
- void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
--int ath_tx_setup(struct ath_softc *sc, int haltype);
- void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
- void ath_draintxq(struct ath_softc *sc,
- struct ath_txq *txq, bool retry_tx);
-@@ -665,7 +663,6 @@ struct ath_wiphy {
-
- void ath9k_tasklet(unsigned long data);
- int ath_reset(struct ath_softc *sc, bool retry_tx);
--int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
- int ath_cabq_update(struct ath_softc *);
-
- static inline void ath_read_cachesize(struct ath_common *common, int *csz)
---- a/drivers/net/wireless/ath/ath9k/beacon.c
-+++ b/drivers/net/wireless/ath/ath9k/beacon.c
-@@ -28,7 +28,7 @@ int ath_beaconq_config(struct ath_softc
- struct ath_hw *ah = sc->sc_ah;
- struct ath_common *common = ath9k_hw_common(ah);
- struct ath9k_tx_queue_info qi, qi_be;
-- int qnum;
-+ struct ath_txq *txq;
-
- ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
- if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
-@@ -38,8 +38,8 @@ int ath_beaconq_config(struct ath_softc
- qi.tqi_cwmax = 0;
- } else {
- /* Adhoc mode; important thing is to use 2x cwmin. */
-- qnum = sc->tx.hwq_map[WME_AC_BE];
-- ath9k_hw_get_txq_props(ah, qnum, &qi_be);
-+ txq = sc->tx.txq_map[WME_AC_BE];
-+ ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi_be);
- qi.tqi_aifs = qi_be.tqi_aifs;
- qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
- qi.tqi_cwmax = qi_be.tqi_cwmax;
---- a/drivers/net/wireless/ath/ath9k/common.h
-+++ b/drivers/net/wireless/ath/ath9k/common.h
-@@ -31,10 +31,11 @@
- #define WME_MAX_BA WME_BA_BMP_SIZE
- #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
-
--#define WME_AC_BE 0
--#define WME_AC_BK 1
--#define WME_AC_VI 2
--#define WME_AC_VO 3
-+/* These must match mac80211 skb queue mapping numbers */
-+#define WME_AC_VO 0
-+#define WME_AC_VI 1
-+#define WME_AC_BE 2
-+#define WME_AC_BK 3
- #define WME_NUM_AC 4
-
- #define ATH_RSSI_DUMMY_MARKER 0x127
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -331,7 +331,7 @@ void ath_paprd_calibrate(struct work_str
- struct ath_tx_control txctl;
- struct ath9k_hw_cal_data *caldata = ah->caldata;
- struct ath_common *common = ath9k_hw_common(ah);
-- int qnum, ftype;
-+ int ftype;
- int chain_ok = 0;
- int chain;
- int len = 1800;
-@@ -358,8 +358,7 @@ void ath_paprd_calibrate(struct work_str
- memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
-
- memset(&txctl, 0, sizeof(txctl));
-- qnum = sc->tx.hwq_map[WME_AC_BE];
-- txctl.txq = &sc->tx.txq[qnum];
-+ txctl.txq = sc->tx.txq_map[WME_AC_BE];
-
- ath9k_ps_wakeup(sc);
- ar9003_paprd_init_table(ah);
-@@ -1025,56 +1024,6 @@ int ath_reset(struct ath_softc *sc, bool
- return r;
- }
-
--static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
--{
-- int qnum;
--
-- switch (queue) {
-- case 0:
-- qnum = sc->tx.hwq_map[WME_AC_VO];
-- break;
-- case 1:
-- qnum = sc->tx.hwq_map[WME_AC_VI];
-- break;
-- case 2:
-- qnum = sc->tx.hwq_map[WME_AC_BE];
-- break;
-- case 3:
-- qnum = sc->tx.hwq_map[WME_AC_BK];
-- break;
-- default:
-- qnum = sc->tx.hwq_map[WME_AC_BE];
-- break;
-- }
--
-- return qnum;
--}
--
--int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
--{
-- int qnum;
--
-- switch (queue) {
-- case WME_AC_VO:
-- qnum = 0;
-- break;
-- case WME_AC_VI:
-- qnum = 1;
-- break;
-- case WME_AC_BE:
-- qnum = 2;
-- break;
-- case WME_AC_BK:
-- qnum = 3;
-- break;
-- default:
-- qnum = -1;
-- break;
-- }
--
-- return qnum;
--}
--
- /* XXX: Remove me once we don't depend on ath9k_channel for all
- * this redundant data */
- void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
-@@ -1244,7 +1193,6 @@ static int ath9k_tx(struct ieee80211_hw
- struct ath_tx_control txctl;
- int padpos, padsize;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
-- int qnum;
-
- if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
- ath_print(common, ATH_DBG_XMIT,
-@@ -1317,8 +1265,7 @@ static int ath9k_tx(struct ieee80211_hw
- memmove(skb->data, skb->data + padsize, padpos);
- }
-
-- qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
-- txctl.txq = &sc->tx.txq[qnum];
-+ txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
-
- ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
-
-@@ -1802,12 +1749,15 @@ static int ath9k_conf_tx(struct ieee8021
- struct ath_wiphy *aphy = hw->priv;
- struct ath_softc *sc = aphy->sc;
- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-+ struct ath_txq *txq;
- struct ath9k_tx_queue_info qi;
-- int ret = 0, qnum;
-+ int ret = 0;
-
- if (queue >= WME_NUM_AC)
- return 0;
-
-+ txq = sc->tx.txq_map[queue];
-+
- mutex_lock(&sc->mutex);
-
- memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
-@@ -1816,20 +1766,19 @@ static int ath9k_conf_tx(struct ieee8021
- qi.tqi_cwmin = params->cw_min;
- qi.tqi_cwmax = params->cw_max;
- qi.tqi_burstTime = params->txop;
-- qnum = ath_get_hal_qnum(queue, sc);
-
- ath_print(common, ATH_DBG_CONFIG,
- "Configure tx [queue/halq] [%d/%d], "
- "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-- queue, qnum, params->aifs, params->cw_min,
-+ queue, txq->axq_qnum, params->aifs, params->cw_min,
- params->cw_max, params->txop);
-
-- ret = ath_txq_update(sc, qnum, &qi);
-+ ret = ath_txq_update(sc, txq->axq_qnum, &qi);
- if (ret)
- ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
-
- if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
-- if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
-+ if (queue == WME_AC_BE && !ret)
- ath_beaconq_config(sc);
-
- mutex_unlock(&sc->mutex);
---- a/drivers/net/wireless/ath/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath/ath9k/xmit.c
-@@ -124,7 +124,7 @@ static void ath_tx_queue_tid(struct ath_
-
- static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
- {
-- struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
-+ struct ath_txq *txq = tid->ac->txq;
-
- WARN_ON(!tid->paused);
-
-@@ -142,7 +142,7 @@ unlock:
-
- static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
- {
-- struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
-+ struct ath_txq *txq = tid->ac->txq;
- struct ath_buf *bf;
- struct list_head bf_head;
- struct ath_tx_status ts;
-@@ -817,7 +817,7 @@ void ath_tx_aggr_stop(struct ath_softc *
- {
- struct ath_node *an = (struct ath_node *)sta->drv_priv;
- struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
-- struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
-+ struct ath_txq *txq = txtid->ac->txq;
-
- if (txtid->state & AGGR_CLEANUP)
- return;
-@@ -888,10 +888,16 @@ struct ath_txq *ath_txq_setup(struct ath
- struct ath_hw *ah = sc->sc_ah;
- struct ath_common *common = ath9k_hw_common(ah);
- struct ath9k_tx_queue_info qi;
-+ static const int subtype_txq_to_hwq[] = {
-+ [WME_AC_BE] = ATH_TXQ_AC_BE,
-+ [WME_AC_BK] = ATH_TXQ_AC_BK,
-+ [WME_AC_VI] = ATH_TXQ_AC_VI,
-+ [WME_AC_VO] = ATH_TXQ_AC_VO,
-+ };
- int qnum, i;
-
- memset(&qi, 0, sizeof(qi));
-- qi.tqi_subtype = subtype;
-+ qi.tqi_subtype = subtype_txq_to_hwq[subtype];
- qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
- qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
- qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
-@@ -940,7 +946,6 @@ struct ath_txq *ath_txq_setup(struct ath
- if (!ATH_TXQ_SETUP(sc, qnum)) {
- struct ath_txq *txq = &sc->tx.txq[qnum];
-
-- txq->axq_class = subtype;
- txq->axq_qnum = qnum;
- txq->axq_link = NULL;
- INIT_LIST_HEAD(&txq->axq_q);
-@@ -1210,24 +1215,6 @@ void ath_txq_schedule(struct ath_softc *
- }
- }
-
--int ath_tx_setup(struct ath_softc *sc, int haltype)
--{
-- struct ath_txq *txq;
--
-- if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
-- ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-- "HAL AC %u out of range, max %zu!\n",
-- haltype, ARRAY_SIZE(sc->tx.hwq_map));
-- return 0;
-- }
-- txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
-- if (txq != NULL) {
-- sc->tx.hwq_map[haltype] = txq->axq_qnum;
-- return 1;
-- } else
-- return 0;
--}
--
- /***********/
- /* TX, DMA */
- /***********/
-@@ -1708,6 +1695,7 @@ static void ath_tx_start_dma(struct ath_
- goto tx_done;
- }
-
-+ WARN_ON(tid->ac->txq != txctl->txq);
- if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
- /*
- * Try aggregation if it's a unicast data frame
-@@ -1747,6 +1735,7 @@ int ath_tx_start(struct ieee80211_hw *hw
- return -1;
- }
-
-+ q = skb_get_queue_mapping(skb);
- r = ath_tx_setup_buffer(hw, bf, skb, txctl);
- if (unlikely(r)) {
- ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
-@@ -1756,8 +1745,9 @@ int ath_tx_start(struct ieee80211_hw *hw
- * we will at least have to run TX completionon one buffer
- * on the queue */
- spin_lock_bh(&txq->axq_lock);
-- if (!txq->stopped && txq->axq_depth > 1) {
-- ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-+ if (txq == sc->tx.txq_map[q] && !txq->stopped &&
-+ txq->axq_depth > 1) {
-+ ath_mac80211_stop_queue(sc, q);
- txq->stopped = 1;
- }
- spin_unlock_bh(&txq->axq_lock);
-@@ -1767,13 +1757,10 @@ int ath_tx_start(struct ieee80211_hw *hw
- return r;
- }
-
-- q = skb_get_queue_mapping(skb);
-- if (q >= 4)
-- q = 0;
--
- spin_lock_bh(&txq->axq_lock);
-- if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
-- ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-+ if (txq == sc->tx.txq_map[q] &&
-+ ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
-+ ath_mac80211_stop_queue(sc, q);
- txq->stopped = 1;
- }
- spin_unlock_bh(&txq->axq_lock);
-@@ -1841,7 +1828,8 @@ exit:
- /*****************/
-
- static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
-- struct ath_wiphy *aphy, int tx_flags)
-+ struct ath_wiphy *aphy, int tx_flags,
-+ struct ath_txq *txq)
- {
- struct ieee80211_hw *hw = sc->hw;
- struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-@@ -1888,11 +1876,12 @@ static void ath_tx_complete(struct ath_s
- ath9k_tx_status(hw, skb);
- else {
- q = skb_get_queue_mapping(skb);
-- if (q >= 4)
-- q = 0;
--
-- if (--sc->tx.pending_frames[q] < 0)
-- sc->tx.pending_frames[q] = 0;
-+ if (txq == sc->tx.txq_map[q]) {
-+ spin_lock_bh(&txq->axq_lock);
-+ if (WARN_ON(--txq->pending_frames < 0))
-+ txq->pending_frames = 0;
-+ spin_unlock_bh(&txq->axq_lock);
-+ }
-
- ieee80211_tx_status(hw, skb);
- }
-@@ -1927,8 +1916,8 @@ static void ath_tx_complete_buf(struct a
- else
- complete(&sc->paprd_complete);
- } else {
-- ath_debug_stat_tx(sc, txq, bf, ts);
-- ath_tx_complete(sc, skb, bf->aphy, tx_flags);
-+ ath_debug_stat_tx(sc, bf, ts);
-+ ath_tx_complete(sc, skb, bf->aphy, tx_flags, txq);
- }
- /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
- * accidentally reference it later.
-@@ -2018,16 +2007,13 @@ static void ath_tx_rc_status(struct ath_
- tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
- }
-
--static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
-+static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum)
- {
-- int qnum;
--
-- qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
-- if (qnum == -1)
-- return;
-+ struct ath_txq *txq;
-
-+ txq = sc->tx.txq_map[qnum];
- spin_lock_bh(&txq->axq_lock);
-- if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
-+ if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
- if (ath_mac80211_start_queue(sc, qnum))
- txq->stopped = 0;
- }
-@@ -2044,6 +2030,7 @@ static void ath_tx_processq(struct ath_s
- struct ath_tx_status ts;
- int txok;
- int status;
-+ int qnum;
-
- ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
- txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
-@@ -2119,12 +2106,15 @@ static void ath_tx_processq(struct ath_s
- ath_tx_rc_status(bf, &ts, txok ? 0 : 1, txok, true);
- }
-
-+ qnum = skb_get_queue_mapping(bf->bf_mpdu);
-+
- if (bf_isampdu(bf))
- ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
- else
- ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
-
-- ath_wake_mac80211_queue(sc, txq);
-+ if (txq == sc->tx.txq_map[qnum])
-+ ath_wake_mac80211_queue(sc, qnum);
-
- spin_lock_bh(&txq->axq_lock);
- if (sc->sc_flags & SC_OP_TXAGGR)
-@@ -2194,6 +2184,7 @@ void ath_tx_edma_tasklet(struct ath_soft
- struct list_head bf_head;
- int status;
- int txok;
-+ int qnum;
-
- for (;;) {
- status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
-@@ -2237,13 +2228,16 @@ void ath_tx_edma_tasklet(struct ath_soft
- ath_tx_rc_status(bf, &txs, txok ? 0 : 1, txok, true);
- }
-
-+ qnum = skb_get_queue_mapping(bf->bf_mpdu);
-+
- if (bf_isampdu(bf))
- ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
- else
- ath_tx_complete_buf(sc, bf, txq, &bf_head,
- &txs, txok, 0);
-
-- ath_wake_mac80211_queue(sc, txq);
-+ if (txq == sc->tx.txq_map[qnum])
-+ ath_wake_mac80211_queue(sc, qnum);
-
- spin_lock_bh(&txq->axq_lock);
- if (!list_empty(&txq->txq_fifo_pending)) {
-@@ -2375,7 +2369,7 @@ void ath_tx_node_init(struct ath_softc *
- for (acno = 0, ac = &an->ac[acno];
- acno < WME_NUM_AC; acno++, ac++) {
- ac->sched = false;
-- ac->qnum = sc->tx.hwq_map[acno];
-+ ac->txq = sc->tx.txq_map[acno];
- INIT_LIST_HEAD(&ac->tid_q);
- }
- }
-@@ -2385,17 +2379,13 @@ void ath_tx_node_cleanup(struct ath_soft
- struct ath_atx_ac *ac;
- struct ath_atx_tid *tid;
- struct ath_txq *txq;
-- int i, tidno;
-+ int tidno;
-
- for (tidno = 0, tid = &an->tid[tidno];
- tidno < WME_NUM_TID; tidno++, tid++) {
-- i = tid->ac->qnum;
--
-- if (!ATH_TXQ_SETUP(sc, i))
-- continue;
-
-- txq = &sc->tx.txq[i];
- ac = tid->ac;
-+ txq = ac->txq;
-
- spin_lock_bh(&txq->axq_lock);
-
---- a/drivers/net/wireless/ath/ath9k/hw.h
-+++ b/drivers/net/wireless/ath/ath9k/hw.h
-@@ -157,6 +157,13 @@
- #define PAPRD_GAIN_TABLE_ENTRIES 32
- #define PAPRD_TABLE_SZ 24
-
-+enum ath_hw_txq_subtype {
-+ ATH_TXQ_AC_BE = 0,
-+ ATH_TXQ_AC_BK = 1,
-+ ATH_TXQ_AC_VI = 2,
-+ ATH_TXQ_AC_VO = 3,
-+};
-+
- enum ath_ini_subsys {
- ATH_INI_PRE = 0,
- ATH_INI_CORE,
---- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
-+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
-@@ -20,8 +20,15 @@
- /* TX */
- /******/
-
-+static const int subtype_txq_to_hwq[] = {
-+ [WME_AC_BE] = ATH_TXQ_AC_BE,
-+ [WME_AC_BK] = ATH_TXQ_AC_BK,
-+ [WME_AC_VI] = ATH_TXQ_AC_VI,
-+ [WME_AC_VO] = ATH_TXQ_AC_VO,
-+};
-+
- #define ATH9K_HTC_INIT_TXQ(subtype) do { \
-- qi.tqi_subtype = subtype; \
-+ qi.tqi_subtype = subtype_txq_to_hwq[subtype]; \
- qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; \
- qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; \
- qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; \
---- a/drivers/net/wireless/ath/ath9k/init.c
-+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -396,7 +396,8 @@ static void ath9k_init_crypto(struct ath
-
- static int ath9k_init_btcoex(struct ath_softc *sc)
- {
-- int r, qnum;
-+ struct ath_txq *txq;
-+ int r;
-
- switch (sc->sc_ah->btcoex_hw.scheme) {
- case ATH_BTCOEX_CFG_NONE:
-@@ -409,8 +410,8 @@ static int ath9k_init_btcoex(struct ath_
- r = ath_init_btcoex_timer(sc);
- if (r)
- return -1;
-- qnum = sc->tx.hwq_map[WME_AC_BE];
-- ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
-+ txq = sc->tx.txq_map[WME_AC_BE];
-+ ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
- sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
- break;
- default:
-@@ -423,59 +424,18 @@ static int ath9k_init_btcoex(struct ath_
-
- static int ath9k_init_queues(struct ath_softc *sc)
- {
-- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
- int i = 0;
-
-- for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
-- sc->tx.hwq_map[i] = -1;
--
- sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
-- if (sc->beacon.beaconq == -1) {
-- ath_print(common, ATH_DBG_FATAL,
-- "Unable to setup a beacon xmit queue\n");
-- goto err;
-- }
--
- sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
-- if (sc->beacon.cabq == NULL) {
-- ath_print(common, ATH_DBG_FATAL,
-- "Unable to setup CAB xmit queue\n");
-- goto err;
-- }
-
- sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
- ath_cabq_update(sc);
-
-- if (!ath_tx_setup(sc, WME_AC_BK)) {
-- ath_print(common, ATH_DBG_FATAL,
-- "Unable to setup xmit queue for BK traffic\n");
-- goto err;
-- }
--
-- if (!ath_tx_setup(sc, WME_AC_BE)) {
-- ath_print(common, ATH_DBG_FATAL,
-- "Unable to setup xmit queue for BE traffic\n");
-- goto err;
-- }
-- if (!ath_tx_setup(sc, WME_AC_VI)) {
-- ath_print(common, ATH_DBG_FATAL,
-- "Unable to setup xmit queue for VI traffic\n");
-- goto err;
-- }
-- if (!ath_tx_setup(sc, WME_AC_VO)) {
-- ath_print(common, ATH_DBG_FATAL,
-- "Unable to setup xmit queue for VO traffic\n");
-- goto err;
-- }
-+ for (i = 0; i < WME_NUM_AC; i++)
-+ sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
-
- return 0;
--
--err:
-- for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
-- if (ATH_TXQ_SETUP(sc, i))
-- ath_tx_cleanupq(sc, &sc->tx.txq[i]);
--
-- return -EIO;
- }
-
- static int ath9k_init_channels_rates(struct ath_softc *sc)
---- a/drivers/net/wireless/ath/ath9k/virtual.c
-+++ b/drivers/net/wireless/ath/ath9k/virtual.c
-@@ -187,7 +187,7 @@ static int ath9k_send_nullfunc(struct at
- info->control.rates[1].idx = -1;
-
- memset(&txctl, 0, sizeof(struct ath_tx_control));
-- txctl.txq = &sc->tx.txq[sc->tx.hwq_map[WME_AC_VO]];
-+ txctl.txq = sc->tx.txq_map[WME_AC_VO];
- txctl.frame_type = ps ? ATH9K_IFT_PAUSE : ATH9K_IFT_UNPAUSE;
-
- if (ath_tx_start(aphy->hw, skb, &txctl) != 0)
---- a/drivers/net/wireless/ath/ath9k/debug.c
-+++ b/drivers/net/wireless/ath/ath9k/debug.c
-@@ -579,10 +579,10 @@ static const struct file_operations fops
- do { \
- len += snprintf(buf + len, size - len, \
- "%s%13u%11u%10u%10u\n", str, \
-- sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BE]].elem, \
-- sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BK]].elem, \
-- sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VI]].elem, \
-- sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VO]].elem); \
-+ sc->debug.stats.txstats[WME_AC_BE].elem, \
-+ sc->debug.stats.txstats[WME_AC_BK].elem, \
-+ sc->debug.stats.txstats[WME_AC_VI].elem, \
-+ sc->debug.stats.txstats[WME_AC_VO].elem); \
- } while(0)
-
- static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
-@@ -624,33 +624,35 @@ static ssize_t read_file_xmit(struct fil
- return retval;
- }
-
--void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-- struct ath_buf *bf, struct ath_tx_status *ts)
-+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
-+ struct ath_tx_status *ts)
- {
-- TX_STAT_INC(txq->axq_qnum, tx_pkts_all);
-- sc->debug.stats.txstats[txq->axq_qnum].tx_bytes_all += bf->bf_mpdu->len;
-+ int qnum = skb_get_queue_mapping(bf->bf_mpdu);
-+
-+ TX_STAT_INC(qnum, tx_pkts_all);
-+ sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len;
-
- if (bf_isampdu(bf)) {
- if (bf_isxretried(bf))
-- TX_STAT_INC(txq->axq_qnum, a_xretries);
-+ TX_STAT_INC(qnum, a_xretries);
- else
-- TX_STAT_INC(txq->axq_qnum, a_completed);
-+ TX_STAT_INC(qnum, a_completed);
- } else {
-- TX_STAT_INC(txq->axq_qnum, completed);
-+ TX_STAT_INC(qnum, completed);
- }
-
- if (ts->ts_status & ATH9K_TXERR_FIFO)
-- TX_STAT_INC(txq->axq_qnum, fifo_underrun);
-+ TX_STAT_INC(qnum, fifo_underrun);
- if (ts->ts_status & ATH9K_TXERR_XTXOP)
-- TX_STAT_INC(txq->axq_qnum, xtxop);
-+ TX_STAT_INC(qnum, xtxop);
- if (ts->ts_status & ATH9K_TXERR_TIMER_EXPIRED)
-- TX_STAT_INC(txq->axq_qnum, timer_exp);
-+ TX_STAT_INC(qnum, timer_exp);
- if (ts->ts_flags & ATH9K_TX_DESC_CFG_ERR)
-- TX_STAT_INC(txq->axq_qnum, desc_cfg_err);
-+ TX_STAT_INC(qnum, desc_cfg_err);
- if (ts->ts_flags & ATH9K_TX_DATA_UNDERRUN)
-- TX_STAT_INC(txq->axq_qnum, data_underrun);
-+ TX_STAT_INC(qnum, data_underrun);
- if (ts->ts_flags & ATH9K_TX_DELIM_UNDERRUN)
-- TX_STAT_INC(txq->axq_qnum, delim_underrun);
-+ TX_STAT_INC(qnum, delim_underrun);
- }
-
- static const struct file_operations fops_xmit = {
---- a/drivers/net/wireless/ath/ath9k/debug.h
-+++ b/drivers/net/wireless/ath/ath9k/debug.h
-@@ -169,8 +169,8 @@ void ath9k_exit_debug(struct ath_hw *ah)
- int ath9k_debug_create_root(void);
- void ath9k_debug_remove_root(void);
- void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
--void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-- struct ath_buf *bf, struct ath_tx_status *ts);
-+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
-+ struct ath_tx_status *ts);
- void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
-
- #else
-@@ -199,7 +199,6 @@ static inline void ath_debug_stat_interr
- }
-
- static inline void ath_debug_stat_tx(struct ath_softc *sc,
-- struct ath_txq *txq,
- struct ath_buf *bf,
- struct ath_tx_status *ts)
- {
diff --git a/package/mac80211/patches/580-cfg80211_ibss_mcast_rate.patch b/package/mac80211/patches/580-cfg80211_ibss_mcast_rate.patch
deleted file mode 100644
index 7ec4ce49d..000000000
--- a/package/mac80211/patches/580-cfg80211_ibss_mcast_rate.patch
+++ /dev/null
@@ -1,58 +0,0 @@
---- a/include/linux/nl80211.h
-+++ b/include/linux/nl80211.h
-@@ -804,6 +804,8 @@ enum nl80211_commands {
- * @NL80211_ATTR_SUPPORT_IBSS_RSN: The device supports IBSS RSN, which mostly
- * means support for per-station GTKs.
- *
-+ * @NL80211_ATTR_MCAST_RATE: Multicast tx rate (in 100 kbps) for IBSS
-+ *
- * @NL80211_ATTR_MAX: highest attribute number currently defined
- * @__NL80211_ATTR_AFTER_LAST: internal use
- */
-@@ -973,6 +975,8 @@ enum nl80211_attrs {
-
- NL80211_ATTR_SUPPORT_IBSS_RSN,
-
-+ NL80211_ATTR_MCAST_RATE,
-+
- /* add attributes here, update the policy in nl80211.c */
-
- __NL80211_ATTR_AFTER_LAST,
---- a/include/net/cfg80211.h
-+++ b/include/net/cfg80211.h
-@@ -924,6 +924,7 @@ struct cfg80211_disassoc_request {
- * @privacy: this is a protected network, keys will be configured
- * after joining
- * @basic_rates: bitmap of basic rates to use when creating the IBSS
-+ * @mcast_rate: multicast tx rate (in 100 kbps)
- */
- struct cfg80211_ibss_params {
- u8 *ssid;
-@@ -935,6 +936,7 @@ struct cfg80211_ibss_params {
- u32 basic_rates;
- bool channel_fixed;
- bool privacy;
-+ int mcast_rate;
- };
-
- /**
---- a/net/wireless/nl80211.c
-+++ b/net/wireless/nl80211.c
-@@ -167,6 +167,7 @@ static const struct nla_policy nl80211_p
- [NL80211_ATTR_WIPHY_TX_POWER_SETTING] = { .type = NLA_U32 },
- [NL80211_ATTR_WIPHY_TX_POWER_LEVEL] = { .type = NLA_U32 },
- [NL80211_ATTR_FRAME_TYPE] = { .type = NLA_U16 },
-+ [NL80211_ATTR_MCAST_RATE] = { .type = NLA_U32 },
- };
-
- /* policy for the key attributes */
-@@ -3652,6 +3653,9 @@ static int nl80211_join_ibss(struct sk_b
- return -EINVAL;
- }
- }
-+ if (info->attrs[NL80211_ATTR_MCAST_RATE])
-+ ibss.mcast_rate =
-+ nla_get_u32(info->attrs[NL80211_ATTR_MCAST_RATE]);
-
- if (ibss.privacy && info->attrs[NL80211_ATTR_KEYS]) {
- connkeys = nl80211_parse_connkeys(rdev,
diff --git a/package/mac80211/patches/581-mac80211_ibss_mcast_rate.patch b/package/mac80211/patches/581-mac80211_ibss_mcast_rate.patch
deleted file mode 100644
index 07ba6f096..000000000
--- a/package/mac80211/patches/581-mac80211_ibss_mcast_rate.patch
+++ /dev/null
@@ -1,106 +0,0 @@
---- a/net/mac80211/ibss.c
-+++ b/net/mac80211/ibss.c
-@@ -914,6 +914,7 @@ int ieee80211_ibss_join(struct ieee80211
-
- sdata->u.ibss.privacy = params->privacy;
- sdata->u.ibss.basic_rates = params->basic_rates;
-+ sdata->vif.bss_conf.mcast_rate = params->mcast_rate;
-
- sdata->vif.bss_conf.beacon_int = params->beacon_interval;
-
---- a/include/net/mac80211.h
-+++ b/include/net/mac80211.h
-@@ -244,6 +244,7 @@ struct ieee80211_bss_conf {
- u16 assoc_capability;
- u64 timestamp;
- u32 basic_rates;
-+ u32 mcast_rate;
- u16 ht_operation_mode;
- s32 cqm_rssi_thold;
- u32 cqm_rssi_hyst;
-@@ -2644,7 +2645,7 @@ enum rate_control_changed {
- * @rate_idx_mask: user-requested rate mask (not MCS for now)
- * @skb: the skb that will be transmitted, the control information in it needs
- * to be filled in
-- * @ap: whether this frame is sent out in AP mode
-+ * @bss: whether this frame is sent out in AP or IBSS mode
- */
- struct ieee80211_tx_rate_control {
- struct ieee80211_hw *hw;
-@@ -2655,7 +2656,7 @@ struct ieee80211_tx_rate_control {
- bool rts, short_preamble;
- u8 max_rate_idx;
- u32 rate_idx_mask;
-- bool ap;
-+ bool bss;
- };
-
- struct rate_control_ops {
---- a/net/mac80211/rate.c
-+++ b/net/mac80211/rate.c
-@@ -210,10 +210,20 @@ static bool rc_no_data_or_no_ack(struct
- return ((info->flags & IEEE80211_TX_CTL_NO_ACK) || !ieee80211_is_data(fc));
- }
-
--static void rc_send_low_broadcast(s8 *idx, u32 basic_rates, u8 max_rate_idx)
-+static void rc_send_low_broadcast(s8 *idx, u32 basic_rates, u32 mcast_rate,
-+ struct ieee80211_supported_band *sband)
- {
- u8 i;
-
-+ if (mcast_rate) {
-+ for (i = 0; i < sband->n_bitrates; i++) {
-+ if (sband->bitrates[i].bitrate == mcast_rate) {
-+ *idx = i;
-+ return;
-+ }
-+ }
-+ }
-+
- if (basic_rates == 0)
- return; /* assume basic rates unknown and accept rate */
- if (*idx < 0)
-@@ -221,7 +231,7 @@ static void rc_send_low_broadcast(s8 *id
- if (basic_rates & (1 << *idx))
- return; /* selected rate is a basic rate */
-
-- for (i = *idx + 1; i <= max_rate_idx; i++) {
-+ for (i = *idx + 1; i <= sband->n_bitrates; i++) {
- if (basic_rates & (1 << i)) {
- *idx = i;
- return;
-@@ -242,10 +252,11 @@ bool rate_control_send_low(struct ieee80
- info->control.rates[0].count =
- (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
- 1 : txrc->hw->max_rate_tries;
-- if (!sta && txrc->ap)
-+ if (!sta && txrc->bss)
- rc_send_low_broadcast(&info->control.rates[0].idx,
- txrc->bss_conf->basic_rates,
-- txrc->sband->n_bitrates);
-+ txrc->bss_conf->mcast_rate,
-+ txrc->sband);
- return true;
- }
- return false;
---- a/net/mac80211/tx.c
-+++ b/net/mac80211/tx.c
-@@ -622,7 +622,8 @@ ieee80211_tx_h_rate_ctrl(struct ieee8021
- txrc.max_rate_idx = -1;
- else
- txrc.max_rate_idx = fls(txrc.rate_idx_mask) - 1;
-- txrc.ap = tx->sdata->vif.type == NL80211_IFTYPE_AP;
-+ txrc.bss = (tx->sdata->vif.type == NL80211_IFTYPE_AP ||
-+ tx->sdata->vif.type == NL80211_IFTYPE_ADHOC);
-
- /* set up RTS protection if desired */
- if (len > tx->local->hw.wiphy->rts_threshold) {
-@@ -2312,7 +2313,7 @@ struct sk_buff *ieee80211_beacon_get_tim
- txrc.max_rate_idx = -1;
- else
- txrc.max_rate_idx = fls(txrc.rate_idx_mask) - 1;
-- txrc.ap = true;
-+ txrc.bss = true;
- rate_control_get_rate(sdata, NULL, &txrc);
-
- info->control.vif = vif;
diff --git a/package/mac80211/patches/590-ath9k_fix_cycle_counter_ps.patch b/package/mac80211/patches/590-ath9k_fix_cycle_counter_ps.patch
deleted file mode 100644
index 4ee5f7359..000000000
--- a/package/mac80211/patches/590-ath9k_fix_cycle_counter_ps.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/main.c
-+++ b/drivers/net/wireless/ath/ath9k/main.c
-@@ -94,11 +94,13 @@ void ath9k_ps_wakeup(struct ath_softc *s
- {
- struct ath_common *common = ath9k_hw_common(sc->sc_ah);
- unsigned long flags;
-+ enum ath9k_power_mode power_mode;
-
- spin_lock_irqsave(&sc->sc_pm_lock, flags);
- if (++sc->ps_usecount != 1)
- goto unlock;
-
-+ power_mode = sc->sc_ah->power_mode;
- ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
-
- /*
-@@ -106,10 +108,12 @@ void ath9k_ps_wakeup(struct ath_softc *s
- * useful data. Better clear them now so that they don't mess up
- * survey data results.
- */
-- spin_lock(&common->cc_lock);
-- ath_hw_cycle_counters_update(common);
-- memset(&common->cc_survey, 0, sizeof(common->cc_survey));
-- spin_unlock(&common->cc_lock);
-+ if (power_mode != ATH9K_PM_AWAKE) {
-+ spin_lock(&common->cc_lock);
-+ ath_hw_cycle_counters_update(common);
-+ memset(&common->cc_survey, 0, sizeof(common->cc_survey));
-+ spin_unlock(&common->cc_lock);
-+ }
-
- unlock:
- spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
diff --git a/package/mac80211/patches/591-ath9k_swba_intr_fix.patch b/package/mac80211/patches/591-ath9k_swba_intr_fix.patch
deleted file mode 100644
index 5bea9f90a..000000000
--- a/package/mac80211/patches/591-ath9k_swba_intr_fix.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/net/wireless/ath/ath9k/beacon.c
-+++ b/drivers/net/wireless/ath/ath9k/beacon.c
-@@ -506,7 +506,7 @@ static void ath_beacon_config_ap(struct
- ath9k_hw_disable_interrupts(ah);
- ath9k_beacon_init(sc, nexttbtt, intval);
- sc->beacon.bmisscnt = 0;
-- ath9k_hw_enable_interrupts(ah);
-+ ath9k_hw_set_interrupts(ah, ah->imask);
-
- /* Clear the reset TSF flag, so that subsequent beacon updation
- will not reset the HW TSF. */
-@@ -689,7 +689,7 @@ static void ath_beacon_config_adhoc(stru
- ath9k_hw_disable_interrupts(ah);
- ath9k_beacon_init(sc, nexttbtt, intval);
- sc->beacon.bmisscnt = 0;
-- ath9k_hw_enable_interrupts(ah);
-+ ath9k_hw_set_interrupts(ah, ah->imask);
- }
-
- void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
diff --git a/package/mac80211/patches/601-rt2x00-fix-hang-on-ifdown.patch b/package/mac80211/patches/601-rt2x00-fix-hang-on-ifdown.patch
index 3bee27105..75e9c9fae 100644
--- a/package/mac80211/patches/601-rt2x00-fix-hang-on-ifdown.patch
+++ b/package/mac80211/patches/601-rt2x00-fix-hang-on-ifdown.patch
@@ -16,7 +16,7 @@ Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
-@@ -593,6 +593,10 @@ static void rt2800pci_kill_tx_queue(stru
+@@ -590,6 +590,10 @@ static void rt2800pci_kill_tx_queue(stru
return;
}
diff --git a/package/mac80211/patches/700-mwl8k-missing-pci-id-for-WNR854T.patch b/package/mac80211/patches/700-mwl8k-missing-pci-id-for-WNR854T.patch
index c0e918e8f..6e7504804 100644
--- a/package/mac80211/patches/700-mwl8k-missing-pci-id-for-WNR854T.patch
+++ b/package/mac80211/patches/700-mwl8k-missing-pci-id-for-WNR854T.patch
@@ -1,6 +1,6 @@
--- a/drivers/net/wireless/mwl8k.c
+++ b/drivers/net/wireless/mwl8k.c
-@@ -3897,6 +3897,7 @@ MODULE_FIRMWARE("mwl8k/helper_8366.fw");
+@@ -3902,6 +3902,7 @@ MODULE_FIRMWARE("mwl8k/helper_8366.fw");
MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
diff --git a/package/mac80211/patches/800-b43-gpio-mask-module-option.patch b/package/mac80211/patches/800-b43-gpio-mask-module-option.patch
index bef3b58c3..e9fe5d2a3 100644
--- a/package/mac80211/patches/800-b43-gpio-mask-module-option.patch
+++ b/package/mac80211/patches/800-b43-gpio-mask-module-option.patch
@@ -1,6 +1,6 @@
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
-@@ -705,6 +705,7 @@ struct b43_wldev {
+@@ -718,6 +718,7 @@ struct b43_wldev {
bool qos_enabled; /* TRUE, if QoS is used. */
bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */
bool use_pio; /* TRUE if next init should use PIO */
diff --git a/package/mac80211/patches/900-bash-location.patch b/package/mac80211/patches/900-bash-location.patch
index 42b7d56f2..e8cab3337 100644
--- a/package/mac80211/patches/900-bash-location.patch
+++ b/package/mac80211/patches/900-bash-location.patch
@@ -21,54 +21,6 @@
#
# Copyright 2007, 2008, 2010 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
#
---- a/scripts/athenable
-+++ b/scripts/athenable
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- #
- # Copyright 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
- #
---- a/scripts/athload
-+++ b/scripts/athload
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- # Copyright 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
- #
- # Loads ath5k or madwifi
---- a/scripts/b43enable
-+++ b/scripts/b43enable
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- #
- # Copyright 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
- #
---- a/scripts/b43load
-+++ b/scripts/b43load
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- # Copyright 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
- #
- # Loads new broadcom drivers (b43 and b43legacy) or the old ones (bcm43xx)
---- a/scripts/btload.sh
-+++ b/scripts/btload.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- MODULES="bluetooth btusb l2cap sco hidp rfcomm bnep"
- for i in $MODULES; do
- echo Loading $i...
---- a/scripts/btunload.sh
-+++ b/scripts/btunload.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- MODULES="hidp rfcomm bnep l2cap sco btusb bluetooth"
- echo Stoping bluetooth service..
- /etc/init.d/bluetooth stop
--- a/scripts/check_config.sh
+++ b/scripts/check_config.sh
@@ -1,4 +1,4 @@
@@ -77,22 +29,6 @@
# This script checks the compat-wireless configuration file and if changes were made
# regenerates the compat_autoconf header.
---- a/scripts/check_depmod
-+++ b/scripts/check_depmod
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- # Copyright 2009 Luis R. Rodriguez <mcgrof@gmail.com>
- #
- # Ensures your distribution likes to prefer updates/ over the kernel/
---- a/scripts/compress_modules
-+++ b/scripts/compress_modules
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- # To be used by distributions using compressed modules
-
- COMPRESSION_FOUND="n"
--- a/scripts/driver-select
+++ b/scripts/driver-select
@@ -1,4 +1,4 @@
@@ -117,73 +53,9 @@
# Copyright 2009 Luis R. Rodriguez <mcgrof@gmail.com>
#
# You can use this to make stable compat-wireless releases
---- a/scripts/iwl-enable
-+++ b/scripts/iwl-enable
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- #
- # Copyright 2007 Luis R. Rodriguez <lrodriguez@atheros.com>
- #
---- a/scripts/iwl-load
-+++ b/scripts/iwl-load
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- # Copyright 2008 Luis R. Rodriguez <lrodriguez@atheros.com>
- #
- # Loads new Intel iwl (iwlagn) or the old ones (iwl4965)
---- a/scripts/load.sh
-+++ b/scripts/load.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- MODULES="ipw2100 ipw2200 libertas_cs usb8xxx"
- MODULES="$MODULES p54pci p54usb"
- MODULES="$MODULES adm8211 zd1211rw"
---- a/scripts/modlib.sh
-+++ b/scripts/modlib.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- #
- # Copyright 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
- #
--- a/scripts/skip-colors
+++ b/scripts/skip-colors
@@ -1,2 +1,2 @@
-#!/bin/bash
+#!/usr/bin/env bash
perl -pe 's|(\e)\[(\d+)(;*)(\d*)(\w)||g'
---- a/scripts/unload.sh
-+++ b/scripts/unload.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
-
- # The old stack drivers and the mac80211 rc80211_simple modules
- # which is no longer on recent kernels (its internal)
---- a/scripts/update-initramfs
-+++ b/scripts/update-initramfs
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- # Copyright 2009 Luis R. Rodriguez <mcgrof@gmail.com>
- #
- # Since we provide ssb, the Ethernet module b44 some people may
---- a/scripts/wlload.sh
-+++ b/scripts/wlload.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
- MODULES="ipw2100 ipw2200 libertas_cs usb8xxx"
- MODULES="$MODULES p54pci p54usb"
- MODULES="$MODULES adm8211 zd1211rw"
---- a/scripts/wlunload.sh
-+++ b/scripts/wlunload.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/usr/bin/env bash
-
- # The old stack drivers and the mac80211 rc80211_simple modules
- # which is no longer on recent kernels (its internal)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 11:08:25 +0000