diff options
| author | mirko <mirko@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-01-07 14:10:01 +0000 |
|---|---|---|
| committer | mirko <mirko@3c298f89-4303-0410-b956-a3cf2f4a3e73> | 2013-01-07 14:10:01 +0000 |
| commit | a2763ca68d07fd90264a1f859b9c8d5da663a8be (patch) | |
| tree | e6bbb4cc46961482fff071b74e8666cefe5e5206 /package/boot/uboot-xburst/files/include/configs/avt2.h | |
| parent | 41c32f9c525b5b5a4b44bd7a685eb4e46015a9c4 (diff) | |
This patch updates uboot-xburst from 2009.11 to 2012.10-rc2 - Ingenic SoC support went upstream
Summary:
* remove all files/* (since merged to upstream)
* patches on nand-spl, mmc and lcd driver
Thanks a lot to Xiangfu Liu!
Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35034 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/boot/uboot-xburst/files/include/configs/avt2.h')
| -rw-r--r-- | package/boot/uboot-xburst/files/include/configs/avt2.h | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/package/boot/uboot-xburst/files/include/configs/avt2.h b/package/boot/uboot-xburst/files/include/configs/avt2.h deleted file mode 100644 index cbf34d720..000000000 --- a/package/boot/uboot-xburst/files/include/configs/avt2.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __CONFIG_AVT2_H -#define __CONFIG_AVT2_H - -#include <configs/nanonote.h> - -#define CONFIG_AVT2 1 - -#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait avt2=1" -#define CONFIG_BOOTARGSFROMSD "mem=64M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait avt2=1" -#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" - -/* SDRAM paramters */ -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ -#define SDRAM_ROW 13 /* Row address: 11 to 13 */ -#define SDRAM_COL 10 /* Column address: 8 to 12 */ -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ - -/* SDRAM Timings, unit: ns */ -#define SDRAM_TRAS 45 /* RAS# Active Time */ -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ -#define SDRAM_TPC 20 /* RAS# Precharge Time */ -#define SDRAM_TRWL 7 /* Write Latency Time */ -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ - -#endif /* __CONFIG_AVT_H */ |