update ath9k to latest git version

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12079 3c298f89-4303-0410-b956-a3cf2f4a3e73

16 files changed, 2715 insertions, 2850 deletions

diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h b/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
index c3294c02f..a4387f9c4 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
@@ -52,54 +52,54 @@
 #endif
 
 struct ath_tx_status {
-	u_int32_t ts_tstamp;
-	u_int16_t ts_seqnum;
-	u_int8_t ts_status;
-	u_int8_t ts_ratecode;
-	u_int8_t ts_rateindex;
+	u32 ts_tstamp;
+	u16 ts_seqnum;
+	u8 ts_status;
+	u8 ts_ratecode;
+	u8 ts_rateindex;
 	int8_t ts_rssi;
-	u_int8_t ts_shortretry;
-	u_int8_t ts_longretry;
-	u_int8_t ts_virtcol;
-	u_int8_t ts_antenna;
-	u_int8_t ts_flags;
+	u8 ts_shortretry;
+	u8 ts_longretry;
+	u8 ts_virtcol;
+	u8 ts_antenna;
+	u8 ts_flags;
 	int8_t ts_rssi_ctl0;
 	int8_t ts_rssi_ctl1;
 	int8_t ts_rssi_ctl2;
 	int8_t ts_rssi_ext0;
 	int8_t ts_rssi_ext1;
 	int8_t ts_rssi_ext2;
-	u_int8_t pad[3];
-	u_int32_t ba_low;
-	u_int32_t ba_high;
-	u_int32_t evm0;
-	u_int32_t evm1;
-	u_int32_t evm2;
+	u8 pad[3];
+	u32 ba_low;
+	u32 ba_high;
+	u32 evm0;
+	u32 evm1;
+	u32 evm2;
 };
 
 struct ath_rx_status {
-	u_int32_t rs_tstamp;
-	u_int16_t rs_datalen;
-	u_int8_t rs_status;
-	u_int8_t rs_phyerr;
+	u32 rs_tstamp;
+	u16 rs_datalen;
+	u8 rs_status;
+	u8 rs_phyerr;
 	int8_t rs_rssi;
-	u_int8_t rs_keyix;
-	u_int8_t rs_rate;
-	u_int8_t rs_antenna;
-	u_int8_t rs_more;
+	u8 rs_keyix;
+	u8 rs_rate;
+	u8 rs_antenna;
+	u8 rs_more;
 	int8_t rs_rssi_ctl0;
 	int8_t rs_rssi_ctl1;
 	int8_t rs_rssi_ctl2;
 	int8_t rs_rssi_ext0;
 	int8_t rs_rssi_ext1;
 	int8_t rs_rssi_ext2;
-	u_int8_t rs_isaggr;
-	u_int8_t rs_moreaggr;
-	u_int8_t rs_num_delims;
-	u_int8_t rs_flags;
-	u_int32_t evm0;
-	u_int32_t evm1;
-	u_int32_t evm2;
+	u8 rs_isaggr;
+	u8 rs_moreaggr;
+	u8 rs_num_delims;
+	u8 rs_flags;
+	u32 evm0;
+	u32 evm1;
+	u32 evm2;
 };
 
 #define ATH9K_RXERR_CRC           0x01
@@ -116,15 +116,15 @@ struct ath_rx_status {
 #define ATH9K_RX_DELIM_CRC_POST   0x20
 #define ATH9K_RX_DECRYPT_BUSY     0x40
 
-#define	HAL_RXKEYIX_INVALID	((u_int8_t)-1)
-#define	HAL_TXKEYIX_INVALID	((u_int)-1)
+#define ATH9K_RXKEYIX_INVALID	((u8)-1)
+#define ATH9K_TXKEYIX_INVALID	((u32)-1)
 
 struct ath_desc {
-	u_int32_t ds_link;
-	u_int32_t ds_data;
-	u_int32_t ds_ctl0;
-	u_int32_t ds_ctl1;
-	u_int32_t ds_hw[20];
+	u32 ds_link;
+	u32 ds_data;
+	u32 ds_ctl0;
+	u32 ds_ctl1;
+	u32 ds_hw[20];
 	union {
 		struct ath_tx_status tx;
 		struct ath_rx_status rx;
@@ -137,18 +137,18 @@ struct ath_desc {
 #define	ds_rxstat	ds_us.rx
 #define ds_stat		ds_us.stats
 
-#define	HAL_TXDESC_CLRDMASK	0x0001
-#define	HAL_TXDESC_NOACK	0x0002
-#define	HAL_TXDESC_RTSENA	0x0004
-#define	HAL_TXDESC_CTSENA	0x0008
-#define	HAL_TXDESC_INTREQ	0x0010
-#define	HAL_TXDESC_VEOL		0x0020
-#define HAL_TXDESC_EXT_ONLY     0x0040
-#define HAL_TXDESC_EXT_AND_CTL  0x0080
-#define HAL_TXDESC_VMF          0x0100
-#define HAL_TXDESC_FRAG_IS_ON   0x0200
+#define ATH9K_TXDESC_CLRDMASK		0x0001
+#define ATH9K_TXDESC_NOACK		0x0002
+#define ATH9K_TXDESC_RTSENA		0x0004
+#define ATH9K_TXDESC_CTSENA		0x0008
+#define ATH9K_TXDESC_INTREQ		0x0010
+#define ATH9K_TXDESC_VEOL		0x0020
+#define ATH9K_TXDESC_EXT_ONLY		0x0040
+#define ATH9K_TXDESC_EXT_AND_CTL	0x0080
+#define ATH9K_TXDESC_VMF		0x0100
+#define ATH9K_TXDESC_FRAG_IS_ON 	0x0200
 
-#define	HAL_RXDESC_INTREQ	0x0020
+#define ATH9K_RXDESC_INTREQ		0x0020
 
 enum hal_capability_type {
 	HAL_CAP_CIPHER = 0,
@@ -168,7 +168,7 @@ enum hal_capability_type {
 };
 
 struct hal_capabilities {
-	u_int halChanSpreadSupport:1,
+	u32 halChanSpreadSupport:1,
 		halChapTuningSupport:1,
 		halMicAesCcmSupport:1,
 		halMicCkipSupport:1,
@@ -192,20 +192,20 @@ struct hal_capabilities {
 		halAutoSleepSupport:1,
 		hal4kbSplitTransSupport:1,
 		halWowMatchPatternExact:1;
-	u_int32_t halWirelessModes;
-	u_int16_t halTotalQueues;
-	u_int16_t halKeyCacheSize;
-	u_int16_t halLow5GhzChan, halHigh5GhzChan;
-	u_int16_t halLow2GhzChan, halHigh2GhzChan;
-	u_int16_t halNumMRRetries;
-	u_int16_t halRtsAggrLimit;
-	u_int8_t halTxChainMask;
-	u_int8_t halRxChainMask;
-	u_int16_t halTxTrigLevelMax;
-	u_int16_t halRegCap;
-	u_int8_t halNumGpioPins;
-	u_int8_t halNumAntCfg2GHz;
-	u_int8_t halNumAntCfg5GHz;
+	u32 halWirelessModes;
+	u16 halTotalQueues;
+	u16 halKeyCacheSize;
+	u16 halLow5GhzChan, halHigh5GhzChan;
+	u16 halLow2GhzChan, halHigh2GhzChan;
+	u16 halNumMRRetries;
+	u16 halRtsAggrLimit;
+	u8 halTxChainMask;
+	u8 halRxChainMask;
+	u16 halTxTrigLevelMax;
+	u16 halRegCap;
+	u8 halNumGpioPins;
+	u8 halNumAntCfg2GHz;
+	u8 halNumAntCfg5GHz;
 };
 
 struct hal_ops_config {
@@ -214,28 +214,28 @@ struct hal_ops_config {
 	int ath_hal_additional_swba_backoff;
 	int ath_hal_6mb_ack;
 	int ath_hal_cwmIgnoreExtCCA;
-	u_int8_t ath_hal_pciePowerSaveEnable;
-	u_int8_t ath_hal_pcieL1SKPEnable;
-	u_int8_t ath_hal_pcieClockReq;
-	u_int32_t ath_hal_pcieWaen;
+	u8 ath_hal_pciePowerSaveEnable;
+	u8 ath_hal_pcieL1SKPEnable;
+	u8 ath_hal_pcieClockReq;
+	u32 ath_hal_pcieWaen;
 	int ath_hal_pciePowerReset;
-	u_int8_t ath_hal_pcieRestore;
-	u_int8_t ath_hal_analogShiftReg;
-	u_int8_t ath_hal_htEnable;
-	u_int32_t ath_hal_ofdmTrigLow;
-	u_int32_t ath_hal_ofdmTrigHigh;
-	u_int32_t ath_hal_cckTrigHigh;
-	u_int32_t ath_hal_cckTrigLow;
-	u_int32_t ath_hal_enableANI;
-	u_int8_t ath_hal_noiseImmunityLvl;
-	u_int32_t ath_hal_ofdmWeakSigDet;
-	u_int32_t ath_hal_cckWeakSigThr;
-	u_int8_t ath_hal_spurImmunityLvl;
-	u_int8_t ath_hal_firStepLvl;
+	u8 ath_hal_pcieRestore;
+	u8 ath_hal_analogShiftReg;
+	u8 ath_hal_htEnable;
+	u32 ath_hal_ofdmTrigLow;
+	u32 ath_hal_ofdmTrigHigh;
+	u32 ath_hal_cckTrigHigh;
+	u32 ath_hal_cckTrigLow;
+	u32 ath_hal_enableANI;
+	u8 ath_hal_noiseImmunityLvl;
+	u32 ath_hal_ofdmWeakSigDet;
+	u32 ath_hal_cckWeakSigThr;
+	u8 ath_hal_spurImmunityLvl;
+	u8 ath_hal_firStepLvl;
 	int8_t ath_hal_rssiThrHigh;
 	int8_t ath_hal_rssiThrLow;
-	u_int16_t ath_hal_diversityControl;
-	u_int16_t ath_hal_antennaSwitchSwap;
+	u16 ath_hal_diversityControl;
+	u16 ath_hal_antennaSwitchSwap;
 	int ath_hal_serializeRegMode;
 	int ath_hal_intrMitigation;
 #define SPUR_DISABLE        	0
@@ -250,29 +250,29 @@ struct hal_ops_config {
 #define AR_SPUR_FEEQ_BOUND_HT40 19
 #define AR_SPUR_FEEQ_BOUND_HT20 10
 	int ath_hal_spurMode;
-	u_int16_t ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
+	u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
 };
 
-enum hal_tx_queue {
-	HAL_TX_QUEUE_INACTIVE = 0,
-	HAL_TX_QUEUE_DATA,
-	HAL_TX_QUEUE_BEACON,
-	HAL_TX_QUEUE_CAB,
-	HAL_TX_QUEUE_UAPSD,
-	HAL_TX_QUEUE_PSPOLL
+enum ath9k_tx_queue {
+	ATH9K_TX_QUEUE_INACTIVE = 0,
+	ATH9K_TX_QUEUE_DATA,
+	ATH9K_TX_QUEUE_BEACON,
+	ATH9K_TX_QUEUE_CAB,
+	ATH9K_TX_QUEUE_UAPSD,
+	ATH9K_TX_QUEUE_PSPOLL
 };
 
-#define	HAL_NUM_TX_QUEUES 10
+#define	ATH9K_NUM_TX_QUEUES 10
 
-enum hal_tx_queue_subtype {
-	HAL_WME_AC_BK = 0,
-	HAL_WME_AC_BE,
-	HAL_WME_AC_VI,
-	HAL_WME_AC_VO,
-	HAL_WME_UPSD
+enum ath9k_tx_queue_subtype {
+	ATH9K_WME_AC_BK = 0,
+	ATH9K_WME_AC_BE,
+	ATH9K_WME_AC_VI,
+	ATH9K_WME_AC_VO,
+	ATH9K_WME_UPSD
 };
 
-enum hal_tx_queue_flags {
+enum ath9k_tx_queue_flags {
 	TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
 	TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
 	TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
@@ -284,150 +284,141 @@ enum hal_tx_queue_flags {
 	TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
 };
 
-struct hal_txq_info {
-	u_int32_t tqi_ver;
-	enum hal_tx_queue_subtype tqi_subtype;
-	enum hal_tx_queue_flags tqi_qflags;
-	u_int32_t tqi_priority;
-	u_int32_t tqi_aifs;
-	u_int32_t tqi_cwmin;
-	u_int32_t tqi_cwmax;
-	u_int16_t tqi_shretry;
-	u_int16_t tqi_lgretry;
-	u_int32_t tqi_cbrPeriod;
-	u_int32_t tqi_cbrOverflowLimit;
-	u_int32_t tqi_burstTime;
-	u_int32_t tqi_readyTime;
-	u_int32_t tqi_compBuf;
+struct ath9k_txq_info {
+	u32 tqi_ver;
+	enum ath9k_tx_queue_subtype tqi_subtype;
+	enum ath9k_tx_queue_flags tqi_qflags;
+	u32 tqi_priority;
+	u32 tqi_aifs;
+	u32 tqi_cwmin;
+	u32 tqi_cwmax;
+	u16 tqi_shretry;
+	u16 tqi_lgretry;
+	u32 tqi_cbrPeriod;
+	u32 tqi_cbrOverflowLimit;
+	u32 tqi_burstTime;
+	u32 tqi_readyTime;
+	u32 tqi_compBuf;
 };
 
-#define HAL_TQI_NONVAL 0xffff
+#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
 
-#define	HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
+#define ATH9K_DECOMP_MASK_SIZE     128
+#define ATH9K_READY_TIME_LO_BOUND  50
+#define ATH9K_READY_TIME_HI_BOUND  96
 
-#define HAL_COMP_BUF_MAX_SIZE    9216
-#define HAL_COMP_BUF_ALIGN_SIZE  512
-#define HAL_DECOMP_MASK_SIZE     128
-
-#define HAL_READY_TIME_LO_BOUND  50
-#define HAL_READY_TIME_HI_BOUND  96
-
-enum hal_pkt_type {
-	HAL_PKT_TYPE_NORMAL = 0,
-	HAL_PKT_TYPE_ATIM,
-	HAL_PKT_TYPE_PSPOLL,
-	HAL_PKT_TYPE_BEACON,
-	HAL_PKT_TYPE_PROBE_RESP,
-	HAL_PKT_TYPE_CHIRP,
-	HAL_PKT_TYPE_GRP_POLL,
+enum ath9k_pkt_type {
+	ATH9K_PKT_TYPE_NORMAL = 0,
+	ATH9K_PKT_TYPE_ATIM,
+	ATH9K_PKT_TYPE_PSPOLL,
+	ATH9K_PKT_TYPE_BEACON,
+	ATH9K_PKT_TYPE_PROBE_RESP,
+	ATH9K_PKT_TYPE_CHIRP,
+	ATH9K_PKT_TYPE_GRP_POLL,
 };
 
-struct hal_tx_queue_info {
-	u_int32_t tqi_ver;
-	enum hal_tx_queue tqi_type;
-	enum hal_tx_queue_subtype tqi_subtype;
-	enum hal_tx_queue_flags tqi_qflags;
-	u_int32_t tqi_priority;
-	u_int32_t tqi_aifs;
-	u_int32_t tqi_cwmin;
-	u_int32_t tqi_cwmax;
-	u_int16_t tqi_shretry;
-	u_int16_t tqi_lgretry;
-	u_int32_t tqi_cbrPeriod;
-	u_int32_t tqi_cbrOverflowLimit;
-	u_int32_t tqi_burstTime;
-	u_int32_t tqi_readyTime;
-	u_int32_t tqi_physCompBuf;
-	u_int32_t tqi_intFlags;
+struct ath9k_tx_queue_info {
+	u32 tqi_ver;
+	enum ath9k_tx_queue tqi_type;
+	enum ath9k_tx_queue_subtype tqi_subtype;
+	enum ath9k_tx_queue_flags tqi_qflags;
+	u32 tqi_priority;
+	u32 tqi_aifs;
+	u32 tqi_cwmin;
+	u32 tqi_cwmax;
+	u16 tqi_shretry;
+	u16 tqi_lgretry;
+	u32 tqi_cbrPeriod;
+	u32 tqi_cbrOverflowLimit;
+	u32 tqi_burstTime;
+	u32 tqi_readyTime;
+	u32 tqi_physCompBuf;
+	u32 tqi_intFlags;
 };
 
-enum hal_rx_filter {
-	HAL_RX_FILTER_UCAST = 0x00000001,
-	HAL_RX_FILTER_MCAST = 0x00000002,
-	HAL_RX_FILTER_BCAST = 0x00000004,
-	HAL_RX_FILTER_CONTROL = 0x00000008,
-	HAL_RX_FILTER_BEACON = 0x00000010,
-	HAL_RX_FILTER_PROM = 0x00000020,
-	HAL_RX_FILTER_PROBEREQ = 0x00000080,
-	HAL_RX_FILTER_PSPOLL = 0x00004000,
-	HAL_RX_FILTER_PHYERR = 0x00000100,
-	HAL_RX_FILTER_PHYRADAR = 0x00002000,
+enum ath9k_rx_filter {
+	ATH9K_RX_FILTER_UCAST = 0x00000001,
+	ATH9K_RX_FILTER_MCAST = 0x00000002,
+	ATH9K_RX_FILTER_BCAST = 0x00000004,
+	ATH9K_RX_FILTER_CONTROL = 0x00000008,
+	ATH9K_RX_FILTER_BEACON = 0x00000010,
+	ATH9K_RX_FILTER_PROM = 0x00000020,
+	ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
+	ATH9K_RX_FILTER_PSPOLL = 0x00004000,
+	ATH9K_RX_FILTER_PHYERR = 0x00000100,
+	ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
 };
 
-enum hal_int {
-	HAL_INT_RX = 0x00000001,
-	HAL_INT_RXDESC = 0x00000002,
-	HAL_INT_RXNOFRM = 0x00000008,
-	HAL_INT_RXEOL = 0x00000010,
-	HAL_INT_RXORN = 0x00000020,
-	HAL_INT_TX = 0x00000040,
-	HAL_INT_TXDESC = 0x00000080,
-	HAL_INT_TIM_TIMER = 0x00000100,
-	HAL_INT_TXURN = 0x00000800,
-	HAL_INT_MIB = 0x00001000,
-	HAL_INT_RXPHY = 0x00004000,
-	HAL_INT_RXKCM = 0x00008000,
-	HAL_INT_SWBA = 0x00010000,
-	HAL_INT_BMISS = 0x00040000,
-	HAL_INT_BNR = 0x00100000,
-	HAL_INT_TIM = 0x00200000,
-	HAL_INT_DTIM = 0x00400000,
-	HAL_INT_DTIMSYNC = 0x00800000,
-	HAL_INT_GPIO = 0x01000000,
-	HAL_INT_CABEND = 0x02000000,
-	HAL_INT_CST = 0x10000000,
-	HAL_INT_GTT = 0x20000000,
-	HAL_INT_FATAL = 0x40000000,
-	HAL_INT_GLOBAL = 0x80000000,
-	HAL_INT_BMISC = HAL_INT_TIM
-	    | HAL_INT_DTIM | HAL_INT_DTIMSYNC | HAL_INT_CABEND,
-	HAL_INT_COMMON = HAL_INT_RXNOFRM
-	    | HAL_INT_RXDESC
-	    | HAL_INT_RXEOL
-	    | HAL_INT_RXORN
-	    | HAL_INT_TXURN
-	    | HAL_INT_TXDESC
-	    | HAL_INT_MIB
-	    | HAL_INT_RXPHY
-	    | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO,
-	HAL_INT_NOCARD = 0xffffffff
+enum ath9k_int {
+	ATH9K_INT_RX = 0x00000001,
+	ATH9K_INT_RXDESC = 0x00000002,
+	ATH9K_INT_RXNOFRM = 0x00000008,
+	ATH9K_INT_RXEOL = 0x00000010,
+	ATH9K_INT_RXORN = 0x00000020,
+	ATH9K_INT_TX = 0x00000040,
+	ATH9K_INT_TXDESC = 0x00000080,
+	ATH9K_INT_TIM_TIMER = 0x00000100,
+	ATH9K_INT_TXURN = 0x00000800,
+	ATH9K_INT_MIB = 0x00001000,
+	ATH9K_INT_RXPHY = 0x00004000,
+	ATH9K_INT_RXKCM = 0x00008000,
+	ATH9K_INT_SWBA = 0x00010000,
+	ATH9K_INT_BMISS = 0x00040000,
+	ATH9K_INT_BNR = 0x00100000,
+	ATH9K_INT_TIM = 0x00200000,
+	ATH9K_INT_DTIM = 0x00400000,
+	ATH9K_INT_DTIMSYNC = 0x00800000,
+	ATH9K_INT_GPIO = 0x01000000,
+	ATH9K_INT_CABEND = 0x02000000,
+	ATH9K_INT_CST = 0x10000000,
+	ATH9K_INT_GTT = 0x20000000,
+	ATH9K_INT_FATAL = 0x40000000,
+	ATH9K_INT_GLOBAL = 0x80000000,
+	ATH9K_INT_BMISC = ATH9K_INT_TIM |
+		ATH9K_INT_DTIM |
+		ATH9K_INT_DTIMSYNC |
+		ATH9K_INT_CABEND,
+	ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
+		ATH9K_INT_RXDESC |
+		ATH9K_INT_RXEOL |
+		ATH9K_INT_RXORN |
+		ATH9K_INT_TXURN |
+		ATH9K_INT_TXDESC |
+		ATH9K_INT_MIB |
+		ATH9K_INT_RXPHY |
+		ATH9K_INT_RXKCM |
+		ATH9K_INT_SWBA |
+		ATH9K_INT_BMISS |
+		ATH9K_INT_GPIO,
+	ATH9K_INT_NOCARD = 0xffffffff
 };
 
-struct hal_rate_table {
+struct ath9k_rate_table {
 	int rateCount;
-	u_int8_t rateCodeToIndex[256];
+	u8 rateCodeToIndex[256];
 	struct {
-		u_int8_t valid;
-		u_int8_t phy;
-		u_int32_t rateKbps;
-		u_int8_t rateCode;
-		u_int8_t shortPreamble;
-		u_int8_t dot11Rate;
-		u_int8_t controlRate;
-		u_int16_t lpAckDuration;
-		u_int16_t spAckDuration;
+		u8 valid;
+		u8 phy;
+		u32 rateKbps;
+		u8 rateCode;
+		u8 shortPreamble;
+		u8 dot11Rate;
+		u8 controlRate;
+		u16 lpAckDuration;
+		u16 spAckDuration;
 	} info[32];
 };
 
-#define HAL_RATESERIES_RTS_CTS  0x0001
-#define HAL_RATESERIES_2040     0x0002
-#define HAL_RATESERIES_HALFGI   0x0004
-
-struct hal_11n_rate_series {
-	u_int Tries;
-	u_int Rate;
-	u_int PktDuration;
-	u_int ChSel;
-	u_int RateFlags;
-};
+#define ATH9K_RATESERIES_RTS_CTS  0x0001
+#define ATH9K_RATESERIES_2040     0x0002
+#define ATH9K_RATESERIES_HALFGI   0x0004
 
-struct hal_channel {
-	u_int16_t channel;
-	u_int32_t channelFlags;
-	u_int8_t privFlags;
-	int8_t maxRegTxPower;
-	int8_t maxTxPower;
-	int8_t minTxPower;
+struct ath9k_11n_rate_series {
+	u32 Tries;
+	u32 Rate;
+	u32 PktDuration;
+	u32 ChSel;
+	u32 RateFlags;
 };
 
 #define CHANNEL_CW_INT    0x00002
@@ -452,7 +443,6 @@ struct hal_channel {
 
 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
-#define CHANNEL_PUREG       (CHANNEL_2GHZ|CHANNEL_OFDM)
 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
@@ -469,39 +459,27 @@ struct hal_channel {
 	 CHANNEL_HT40PLUS |			\
 	 CHANNEL_HT40MINUS)
 
-struct hal_channel_internal {
-	u_int16_t channel;
-	u_int32_t channelFlags;
-	u_int8_t privFlags;
+struct ath9k_channel {
+	u16 channel;
+	u32 channelFlags;
+	u8 privFlags;
 	int8_t maxRegTxPower;
 	int8_t maxTxPower;
 	int8_t minTxPower;
-	bool bssSendHere;
-	u_int8_t gainI;
-	bool iqCalValid;
+	u32 chanmode;
 	int32_t CalValid;
 	bool oneTimeCalsDone;
 	int8_t iCoff;
 	int8_t qCoff;
 	int16_t rawNoiseFloor;
-	int16_t noiseFloorAdjust;
 	int8_t antennaMax;
-	u_int32_t regDmnFlags;
-	u_int32_t conformanceTestLimit;
-	u_int64_t ah_tsf_last;
-	u_int64_t ah_channel_time;
-	u_int16_t mainSpur;
-	u_int64_t dfsTsf;
+	u32 regDmnFlags;
+	u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
 #ifdef ATH_NF_PER_CHAN
-	struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
+	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 #endif
 };
 
-#define HAL_SPUR_VAL_MASK       0x3FFF
-#define HAL_SPUR_CHAN_WIDTH     87
-#define HAL_BIN_WIDTH_BASE_100HZ    3125
-#define HAL_MAX_BINS_ALLOWED        28
-
 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
        (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
        (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
@@ -511,8 +489,6 @@ struct hal_channel_internal {
        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
-#define IS_CHAN_PUREG(_c) \
-	(((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
@@ -520,40 +496,46 @@ struct hal_channel_internal {
 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
-#define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
-#define IS_CHAN_HT40(_c) ((((_c)->channelFlags & CHANNEL_HT40PLUS) != 0) \
-			  || (((_c)->channelFlags & CHANNEL_HT40MINUS) != 0))
+
+/* These macros check chanmode and not channelFlags */
+#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) ||	\
+			  ((_c)->chanmode == CHANNEL_G_HT20))
+#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||	\
+			  ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||	\
+			  ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||	\
+			  ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
+
 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
-#define IS_CHAN_A_5MHZ_SPACED(_c) \
-	((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
-	(((_c)->channel % 20) != 0) &&	\
-	(((_c)->channel % 10) != 0))
-
-struct hal_keyval {
-	u_int8_t kv_type;
-	u_int8_t kv_pad;
-	u_int16_t kv_len;
-	u_int8_t kv_val[16];
-	u_int8_t kv_mic[8];
-	u_int8_t kv_txmic[8];
+#define IS_CHAN_A_5MHZ_SPACED(_c)			\
+	((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&	\
+	 (((_c)->channel % 20) != 0) &&			\
+	 (((_c)->channel % 10) != 0))
+
+struct ath9k_keyval {
+	u8 kv_type;
+	u8 kv_pad;
+	u16 kv_len;
+	u8 kv_val[16];
+	u8 kv_mic[8];
+	u8 kv_txmic[8];
 };
 
-enum hal_key_type {
-	HAL_KEY_TYPE_CLEAR,
-	HAL_KEY_TYPE_WEP,
-	HAL_KEY_TYPE_AES,
-	HAL_KEY_TYPE_TKIP,
+enum ath9k_key_type {
+	ATH9K_KEY_TYPE_CLEAR,
+	ATH9K_KEY_TYPE_WEP,
+	ATH9K_KEY_TYPE_AES,
+	ATH9K_KEY_TYPE_TKIP,
 };
 
-enum hal_cipher {
-	HAL_CIPHER_WEP = 0,
-	HAL_CIPHER_AES_OCB = 1,
-	HAL_CIPHER_AES_CCM = 2,
-	HAL_CIPHER_CKIP = 3,
-	HAL_CIPHER_TKIP = 4,
-	HAL_CIPHER_CLR = 5,
-	HAL_CIPHER_MIC = 127
+enum ath9k_cipher {
+	ATH9K_CIPHER_WEP = 0,
+	ATH9K_CIPHER_AES_OCB = 1,
+	ATH9K_CIPHER_AES_CCM = 2,
+	ATH9K_CIPHER_CKIP = 3,
+	ATH9K_CIPHER_TKIP = 4,
+	ATH9K_CIPHER_CLR = 5,
+	ATH9K_CIPHER_MIC = 127
 };
 
 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
@@ -596,10 +578,8 @@ enum hal_cipher {
 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 
-enum {
-	CTRY_DEBUG = 0x1ff,
-	CTRY_DEFAULT = 0
-};
+#define CTRY_DEBUG 0x1ff
+#define	CTRY_DEFAULT 0
 
 enum reg_ext_bitmap {
 	REG_EXT_JAPAN_MIDBAND = 1,
@@ -608,13 +588,13 @@ enum reg_ext_bitmap {
 	REG_EXT_JAPAN_DFS_HT40 = 4
 };
 
-struct hal_country_entry {
-	u_int16_t countryCode;
-	u_int16_t regDmnEnum;
-	u_int16_t regDmn5G;
-	u_int16_t regDmn2G;
-	u_int8_t isMultidomain;
-	u_int8_t iso[3];
+struct ath9k_country_entry {
+	u16 countryCode;
+	u16 regDmnEnum;
+	u16 regDmn5G;
+	u16 regDmn2G;
+	u8 isMultidomain;
+	u8 iso[3];
 };
 
 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
@@ -632,10 +612,10 @@ struct hal_country_entry {
 #define REG_CLR_BIT(_a, _r, _f) \
 	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
 
-#define HAL_COMP_BUF_MAX_SIZE   9216
-#define HAL_COMP_BUF_ALIGN_SIZE 512
+#define ATH9K_COMP_BUF_MAX_SIZE   9216
+#define ATH9K_COMP_BUF_ALIGN_SIZE 512
 
-#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001
+#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001
 
 #define INIT_AIFS       2
 #define INIT_CWMIN      15
@@ -667,47 +647,22 @@ struct hal_country_entry {
 #define MAX_RATE_POWER 63
 
 #define LE_READ_2(p)							\
-	((u_int16_t)							\
-	 ((((const u_int8_t *)(p))[0]) | \
-		(((const u_int8_t *)(p))[1] << 8)))
+	((u16)							\
+	 ((((const u8 *)(p))[0]) | \
+		(((const u8 *)(p))[1] << 8)))
 
 #define LE_READ_4(p)							\
-	((u_int32_t)							\
-	 ((((const u_int8_t *)(p))[0]) | \
-		(((const u_int8_t *)(p))[1] << 8) | \
-		(((const u_int8_t *)(p))[2] << 16) | \
-			(((const u_int8_t *)(p))[3] << 24)))
-
-enum hal_status {
-	HAL_OK = 0,
-	HAL_ENXIO,
-	HAL_ENOMEM,
-	HAL_EIO,
-	HAL_EEMAGIC,
-	HAL_EEVERSION,
-	HAL_EELOCKED,
-	HAL_EEBADSUM,
-	HAL_EEREAD,
-	HAL_EEBADMAC,
-	HAL_EESIZE,
-	HAL_EEWRITE,
-	HAL_EINVAL,
-	HAL_ENOTSUPP,
-	HAL_ESELFTEST,
-	HAL_EINPROGRESS
-};
-
-enum hal_power_mode {
-	HAL_PM_AWAKE = 0,
-	HAL_PM_FULL_SLEEP,
-	HAL_PM_NETWORK_SLEEP,
-	HAL_PM_UNDEFINED
-};
-
-enum hal_rfgain {
-	HAL_RFGAIN_INACTIVE = 0,
-	HAL_RFGAIN_READ_REQUESTED,
-	HAL_RFGAIN_NEED_CHANGE
+	((u32)							\
+	 ((((const u8 *)(p))[0]) | \
+		(((const u8 *)(p))[1] << 8) | \
+		(((const u8 *)(p))[2] << 16) | \
+			(((const u8 *)(p))[3] << 24)))
+
+enum ath9k_power_mode {
+	ATH9K_PM_AWAKE = 0,
+	ATH9K_PM_FULL_SLEEP,
+	ATH9K_PM_NETWORK_SLEEP,
+	ATH9K_PM_UNDEFINED
 };
 
 #define HAL_ANTENNA_MIN_MODE  0
@@ -715,47 +670,44 @@ enum hal_rfgain {
 #define HAL_ANTENNA_FIXED_B   2
 #define HAL_ANTENNA_MAX_MODE  3
 
-struct hal_mib_stats {
-	u_int32_t ackrcv_bad;
-	u_int32_t rts_bad;
-	u_int32_t rts_good;
-	u_int32_t fcs_bad;
-	u_int32_t beacons;
-};
-
-enum hal_ant_setting {
-	HAL_ANT_VARIABLE = 0,
-	HAL_ANT_FIXED_A,
-	HAL_ANT_FIXED_B
+struct ath9k_mib_stats {
+	u32 ackrcv_bad;
+	u32 rts_bad;
+	u32 rts_good;
+	u32 fcs_bad;
+	u32 beacons;
 };
 
-enum hal_opmode {
-	HAL_M_STA = 1,
-	HAL_M_IBSS = 0,
-	HAL_M_HOSTAP = 6,
-	HAL_M_MONITOR = 8
+enum ath9k_ant_setting {
+	ATH9K_ANT_VARIABLE = 0,
+	ATH9K_ANT_FIXED_A,
+	ATH9K_ANT_FIXED_B
 };
 
-enum {
-	HAL_SLOT_TIME_6 = 6,
-	HAL_SLOT_TIME_9 = 9,
-	HAL_SLOT_TIME_20 = 20,
+enum ath9k_opmode {
+	ATH9K_M_STA = 1,
+	ATH9K_M_IBSS = 0,
+	ATH9K_M_HOSTAP = 6,
+	ATH9K_M_MONITOR = 8
 };
 
+#define ATH9K_SLOT_TIME_6 6
+#define ATH9K_SLOT_TIME_9 9
+#define ATH9K_SLOT_TIME_20 20
 
-enum hal_ht_macmode {
-	HAL_HT_MACMODE_20 = 0,
-	HAL_HT_MACMODE_2040 = 1,
+enum ath9k_ht_macmode {
+	ATH9K_HT_MACMODE_20 = 0,
+	ATH9K_HT_MACMODE_2040 = 1,
 };
 
-enum hal_ht_extprotspacing {
-	HAL_HT_EXTPROTSPACING_20 = 0,
-	HAL_HT_EXTPROTSPACING_25 = 1,
+enum ath9k_ht_extprotspacing {
+	ATH9K_HT_EXTPROTSPACING_20 = 0,
+	ATH9K_HT_EXTPROTSPACING_25 = 1,
 };
 
-struct hal_ht_cwm {
-	enum hal_ht_macmode ht_macmode;
-	enum hal_ht_extprotspacing ht_extprotspacing;
+struct ath9k_ht_cwm {
+	enum ath9k_ht_macmode ht_macmode;
+	enum ath9k_ht_extprotspacing ht_extprotspacing;
 };
 
 enum hal_freq_band {
@@ -763,25 +715,16 @@ enum hal_freq_band {
 	HAL_FREQ_BAND_2GHZ = 1,
 };
 
-enum {
-	HAL_TRUE_CHIP = 1
-};
-
-enum hal_bus_type {
-	HAL_BUS_TYPE_PCI,
-	HAL_BUS_TYPE_AHB
-};
-
-enum hal_ani_cmd {
-	HAL_ANI_PRESENT = 0x1,
-	HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
-	HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
-	HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
-	HAL_ANI_FIRSTEP_LEVEL = 0x10,
-	HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
-	HAL_ANI_MODE = 0x40,
-	HAL_ANI_PHYERR_RESET = 0x80,
-	HAL_ANI_ALL = 0xff
+enum ath9k_ani_cmd {
+	ATH9K_ANI_PRESENT = 0x1,
+	ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
+	ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
+	ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
+	ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
+	ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
+	ATH9K_ANI_MODE = 0x40,
+	ATH9K_ANI_PHYERR_RESET = 0x80,
+	ATH9K_ANI_ALL = 0xff
 };
 
 enum phytype {
@@ -800,12 +743,12 @@ enum start_adhoc_option {
 	START_ADHOC_IN_11B,
 };
 
-enum hal_tp_scale {
-	HAL_TP_SCALE_MAX = 0,
-	HAL_TP_SCALE_50,
-	HAL_TP_SCALE_25,
-	HAL_TP_SCALE_12,
-	HAL_TP_SCALE_MIN
+enum ath9k_tp_scale {
+	ATH9K_TP_SCALE_MAX = 0,
+	ATH9K_TP_SCALE_50,
+	ATH9K_TP_SCALE_25,
+	ATH9K_TP_SCALE_12,
+	ATH9K_TP_SCALE_MIN
 };
 
 enum ser_reg_mode {
@@ -820,97 +763,95 @@ enum ser_reg_mode {
 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT     3
 #define AR_PHY_CCA_FILTERWINDOW_LENGTH          5
 
-#define HAL_NF_CAL_HIST_MAX             5
+#define ATH9K_NF_CAL_HIST_MAX           5
 #define NUM_NF_READINGS                 6
 
-struct hal_nfcal_hist {
-	int16_t nfCalBuffer[HAL_NF_CAL_HIST_MAX];
-	u_int8_t currIndex;
+struct ath9k_nfcal_hist {
+	int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
+	u8 currIndex;
 	int16_t privNF;
-	u_int8_t invalidNFcount;
+	u8 invalidNFcount;
 };
 
-struct hal_beacon_state {
-	u_int32_t bs_nexttbtt;
-	u_int32_t bs_nextdtim;
-	u_int32_t bs_intval;
-#define HAL_BEACON_PERIOD       0x0000ffff
-#define HAL_BEACON_ENA          0x00800000
-#define HAL_BEACON_RESET_TSF    0x01000000
-	u_int32_t bs_dtimperiod;
-	u_int16_t bs_cfpperiod;
-	u_int16_t bs_cfpmaxduration;
-	u_int32_t bs_cfpnext;
-	u_int16_t bs_timoffset;
-	u_int16_t bs_bmissthreshold;
-	u_int32_t bs_sleepduration;
+struct ath9k_beacon_state {
+	u32 bs_nexttbtt;
+	u32 bs_nextdtim;
+	u32 bs_intval;
+#define ATH9K_BEACON_PERIOD       0x0000ffff
+#define ATH9K_BEACON_ENA          0x00800000
+#define ATH9K_BEACON_RESET_TSF    0x01000000
+	u32 bs_dtimperiod;
+	u16 bs_cfpperiod;
+	u16 bs_cfpmaxduration;
+	u32 bs_cfpnext;
+	u16 bs_timoffset;
+	u16 bs_bmissthreshold;
+	u32 bs_sleepduration;
 };
 
-struct hal_node_stats {
-	u_int32_t ns_avgbrssi;
-	u_int32_t ns_avgrssi;
-	u_int32_t ns_avgtxrssi;
-	u_int32_t ns_avgtxrate;
+struct ath9k_node_stats {
+	u32 ns_avgbrssi;
+	u32 ns_avgrssi;
+	u32 ns_avgtxrssi;
+	u32 ns_avgtxrate;
 };
 
-#define HAL_RSSI_EP_MULTIPLIER  (1<<7)
-#define HAL_RATE_EP_MULTIPLIER  (1<<7)
+#define ATH9K_RSSI_EP_MULTIPLIER  (1<<7)
 
-enum hal_gpio_output_mux_type {
-	HAL_GPIO_OUTPUT_MUX_AS_OUTPUT,
-	HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
-	HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
-	HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
-	HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
-	HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
+enum ath9k_gpio_output_mux_type {
+	ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,
+	ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
+	ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
+	ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
+	ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
+	ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
 };
 
 enum {
-	HAL_RESET_POWER_ON,
-	HAL_RESET_WARM,
-	HAL_RESET_COLD,
+	ATH9K_RESET_POWER_ON,
+	ATH9K_RESET_WARM,
+	ATH9K_RESET_COLD,
 };
 
 #define AH_USE_EEPROM   0x1
-#define AH_IS_HB63      0x2
 
 struct ath_hal {
-	u_int32_t ah_magic;
-	u_int16_t ah_devid;
-	u_int16_t ah_subvendorid;
+	u32 ah_magic;
+	u16 ah_devid;
+	u16 ah_subvendorid;
 	struct ath_softc *ah_sc;
 	void __iomem *ah_sh;
-	u_int16_t ah_countryCode;
-	u_int32_t ah_macVersion;
-	u_int16_t ah_macRev;
-	u_int16_t ah_phyRev;
-	u_int16_t ah_analog5GhzRev;
-	u_int16_t ah_analog2GhzRev;
-	u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
-	u_int32_t ah_flags;
-	enum hal_opmode ah_opmode;
+	u16 ah_countryCode;
+	u32 ah_macVersion;
+	u16 ah_macRev;
+	u16 ah_phyRev;
+	u16 ah_analog5GhzRev;
+	u16 ah_analog2GhzRev;
+	u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
+	u32 ah_flags;
+	enum ath9k_opmode ah_opmode;
 	struct hal_ops_config ah_config;
 	struct hal_capabilities ah_caps;
 	int16_t ah_powerLimit;
-	u_int16_t ah_maxPowerLevel;
-	u_int ah_tpScale;
-	u_int16_t ah_currentRD;
-	u_int16_t ah_currentRDExt;
-	u_int16_t ah_currentRDInUse;
-	u_int16_t ah_currentRD5G;
-	u_int16_t ah_currentRD2G;
+	u16 ah_maxPowerLevel;
+	u32 ah_tpScale;
+	u16 ah_currentRD;
+	u16 ah_currentRDExt;
+	u16 ah_currentRDInUse;
+	u16 ah_currentRD5G;
+	u16 ah_currentRD2G;
 	char ah_iso[4];
 	enum start_adhoc_option ah_adHocMode;
 	bool ah_commonMode;
-	struct hal_channel_internal ah_channels[150];
-	u_int ah_nchan;
-	struct hal_channel_internal *ah_curchan;
-	u_int16_t ah_rfsilent;
+	struct ath9k_channel ah_channels[150];
+	u32 ah_nchan;
+	struct ath9k_channel *ah_curchan;
+	u16 ah_rfsilent;
 	bool ah_rfkillEnabled;
 	bool ah_isPciExpress;
-	u_int16_t ah_txTrigLevel;
+	u16 ah_txTrigLevel;
 #ifndef ATH_NF_PER_CHAN
-	struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
+	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 #endif
 };
 
@@ -946,199 +887,195 @@ enum {
 };
 
 struct chan_centers {
-	u_int16_t synth_center;
-	u_int16_t ctl_center;
-	u_int16_t ext_center;
+	u16 synth_center;
+	u16 ctl_center;
+	u16 ext_center;
 };
 
-enum hal_status ath_hal_getcapability(struct ath_hal *ah,
-				      enum hal_capability_type type,
-				      u_int32_t capability,
-				      u_int32_t *result);
-const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
-						   u_int mode);
+int ath_hal_getcapability(struct ath_hal *ah,
+			  enum hal_capability_type type,
+			  u32 capability,
+			  u32 *result);
+const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
+						     u32 mode);
 void ath9k_hw_detach(struct ath_hal *ah);
-struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+struct ath_hal *ath9k_hw_attach(u16 devid,
 				struct ath_softc *sc,
 				void __iomem *mem,
-				enum hal_status *error);
+				int *error);
 bool ath9k_regd_init_channels(struct ath_hal *ah,
-			      struct hal_channel *chans,
-			      u_int maxchans, u_int *nchans,
-			      u_int8_t *regclassids,
-			      u_int maxregids, u_int *nregids,
-			      u_int16_t cc, u_int32_t modeSelect,
+			      u32 maxchans, u32 *nchans,
+			      u8 *regclassids,
+			      u32 maxregids, u32 *nregids,
+			      u16 cc, u32 modeSelect,
 			      bool enableOutdoor,
 			      bool enableExtendedChannels);
-u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
-enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
-				     enum hal_int ints);
-bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-		    struct hal_channel *chan,
-		    enum hal_ht_macmode macmode,
-		    u_int8_t txchainmask, u_int8_t rxchainmask,
-		    enum hal_ht_extprotspacing extprotspacing,
+u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
+enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
+				     enum ath9k_int ints);
+bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
+		    struct ath9k_channel *chan,
+		    enum ath9k_ht_macmode macmode,
+		    u8 txchainmask, u8 rxchainmask,
+		    enum ath9k_ht_extprotspacing extprotspacing,
 		    bool bChannelChange,
-		    enum hal_status *status);
+		    int *status);
 bool ath9k_hw_phy_disable(struct ath_hal *ah);
-void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
+void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
 			     bool *isCalDone);
 void ath9k_hw_ani_monitor(struct ath_hal *ah,
-			  const struct hal_node_stats *stats,
-			  struct hal_channel *chan);
+			  const struct ath9k_node_stats *stats,
+			  struct ath9k_channel *chan);
 bool ath9k_hw_calibrate(struct ath_hal *ah,
-			struct hal_channel *chan,
-			u_int8_t rxchainmask,
+			struct ath9k_channel *chan,
+			u8 rxchainmask,
 			bool longcal,
 			bool *isCalDone);
 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
-			       struct hal_channel *chan);
-void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
-			    u_int16_t assocId);
-void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
-void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
-			    u_int16_t assocId);
-bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
+			       struct ath9k_channel *chan);
+void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
+			    u16 assocId);
+void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
+void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
+			    u16 assocId);
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
 void ath9k_hw_reset_tsf(struct ath_hal *ah);
-bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
-bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
-			const u_int8_t *mac);
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
+bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
+			const u8 *mac);
 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
-				 u_int16_t entry,
-				 const struct hal_keyval *k,
-				 const u_int8_t *mac,
+				 u16 entry,
+				 const struct ath9k_keyval *k,
+				 const u8 *mac,
 				 int xorKey);
 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
-			    u_int32_t setting);
+			    u32 setting);
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
 bool ath9k_hw_intrpend(struct ath_hal *ah);
-bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
+bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
 				bool bIncTrigLevel);
 void ath9k_hw_procmibevent(struct ath_hal *ah,
-			   const struct hal_node_stats *stats);
+			   const struct ath9k_node_stats *stats);
 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
-void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
+void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
 bool ath9k_hw_phycounters(struct ath_hal *ah);
-bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
 bool ath9k_hw_getcapability(struct ath_hal *ah,
 			    enum hal_capability_type type,
-			    u_int32_t capability,
-			    u_int32_t *result);
+			    u32 capability,
+			    u32 *result);
 bool ath9k_hw_setcapability(struct ath_hal *ah,
 			    enum hal_capability_type type,
-			    u_int32_t capability,
-			    u_int32_t setting,
-			    enum hal_status *status);
-u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
-void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
+			    u32 capability,
+			    u32 setting,
+			    int *status);
+u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
+void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
+void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
-			   const u_int8_t *mask);
+			   const u8 *mask);
 bool ath9k_hw_setpower(struct ath_hal *ah,
-		       enum hal_power_mode mode);
-enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
-u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
-u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
+		       enum ath9k_power_mode mode);
+enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
+u64 ath9k_hw_gettsf64(struct ath_hal *ah);
+u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
+bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
-			       enum hal_ant_setting settings,
-			       struct hal_channel *chan,
-			       u_int8_t *tx_chainmask,
-			       u_int8_t *rx_chainmask,
-			       u_int8_t *antenna_cfgd);
-void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
-enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
-					  u_int32_t cfg);
-bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
-		       u_int32_t txdp);
-bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
-u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
-				 const struct hal_rate_table *rates,
-				 u_int32_t frameLen, u_int16_t rateix,
+			       enum ath9k_ant_setting settings,
+			       struct ath9k_channel *chan,
+			       u8 *tx_chainmask,
+			       u8 *rx_chainmask,
+			       u8 *antenna_cfgd);
+void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
+int ath9k_hw_select_antconfig(struct ath_hal *ah,
+			      u32 cfg);
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
+		       u32 txdp);
+bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
+u16 ath9k_hw_computetxtime(struct ath_hal *ah,
+				 const struct ath9k_rate_table *rates,
+				 u32 frameLen, u16 rateix,
 				 bool shortPreamble);
 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 				  struct ath_desc *lastds,
-				  u_int durUpdateEn, u_int rtsctsRate,
-				  u_int rtsctsDuration,
-				  struct hal_11n_rate_series series[],
-				  u_int nseries, u_int flags);
+				  u32 durUpdateEn, u32 rtsctsRate,
+				  u32 rtsctsDuration,
+				  struct ath9k_11n_rate_series series[],
+				  u32 nseries, u32 flags);
 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
 				   struct ath_desc *ds,
-				   u_int burstDuration);
+				   u32 burstDuration);
 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
-u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
-bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
-u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
-u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
-				     struct hal_channel *chan);
-u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
+u32 ath9k_hw_reverse_bits(u32 val, u32 n);
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
+u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
+u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
+				     struct ath9k_channel *chan);
+u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
 bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
-			      struct hal_txq_info *qInfo);
+			      struct ath9k_txq_info *qInfo);
 bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
-			      const struct hal_txq_info *qInfo);
-struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
-					      const struct hal_channel *c);
+			      const struct ath9k_txq_info *qInfo);
+struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
+					      const struct ath9k_channel *c);
 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
-			    u_int pktLen, enum hal_pkt_type type,
-			    u_int txPower, u_int keyIx,
-			    enum hal_key_type keyType, u_int flags);
+			    u32 pktLen, enum ath9k_pkt_type type,
+			    u32 txPower, u32 keyIx,
+			    enum ath9k_key_type keyType, u32 flags);
 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
-			 u_int segLen, bool firstSeg,
+			 u32 segLen, bool firstSeg,
 			 bool lastSeg,
 			 const struct ath_desc *ds0);
-u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
-					u_int32_t *rxc_pcnt,
-					u_int32_t *rxf_pcnt,
-					u_int32_t *txf_pcnt);
+u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
+					u32 *rxc_pcnt,
+					u32 *rxf_pcnt,
+					u32 *txf_pcnt);
 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
 void ath9k_hw_beaconinit(struct ath_hal *ah,
-			 u_int32_t next_beacon, u_int32_t beacon_period);
+			 u32 next_beacon, u32 beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
-				    const struct hal_beacon_state *bs);
+				    const struct ath9k_beacon_state *bs);
 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
-			  u_int32_t size, u_int flags);
-void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
+			  u32 size, u32 flags);
+void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
 void ath9k_hw_rxena(struct ath_hal *ah);
 void ath9k_hw_setopmode(struct ath_hal *ah);
-bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
-void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
-			     u_int32_t filter1);
-u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
+bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
+void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
+			     u32 filter1);
+u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
 void ath9k_hw_startpcureceive(struct ath_hal *ah);
 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
-enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
-				    struct ath_desc *ds, u_int32_t pa,
-				    struct ath_desc *nds, u_int64_t tsf);
-u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q);
-enum hal_status ath9k_hw_txprocdesc(struct ath_hal *ah,
-				    struct ath_desc *ds);
+int ath9k_hw_rxprocdesc(struct ath_hal *ah,
+			struct ath_desc *ds, u32 pa,
+			struct ath_desc *nds, u64 tsf);
+u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
+int ath9k_hw_txprocdesc(struct ath_hal *ah,
+			struct ath_desc *ds);
 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
-				 u_int numDelims);
+				 u32 numDelims);
 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
-				u_int aggrLen);
+				u32 aggrLen);
 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
-bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
-void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
+void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
-				     struct ath_desc *ds, u_int vmf);
-bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
+				     struct ath_desc *ds, u32 vmf);
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
-int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
-			  const struct hal_txq_info *qInfo);
-u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
-const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
+int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
+			  const struct ath9k_txq_info *qInfo);
+u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
+const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 bool ath9k_hw_disable(struct ath_hal *ah);
 void ath9k_hw_rfdetach(struct ath_hal *ah);
 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
-				  struct hal_channel_internal *chan,
+				  struct ath9k_channel *chan,
 				  struct chan_centers *centers);
 bool ath9k_get_channel_edges(struct ath_hal *ah,
-			     u_int16_t flags, u_int16_t *low,
-			     u_int16_t *high);
-bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
-				    struct hal_channel *chans,
-				    u_int32_t nchans);
+			     u16 flags, u16 *low,
+			     u16 *high);
 #endif
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c b/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
index 596591ec5..ff803279f 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
@@ -29,10 +29,10 @@
 static int ath_beaconq_config(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	struct hal_txq_info qi;
+	struct ath9k_txq_info qi;
 
 	ath9k_hw_gettxqueueprops(ah, sc->sc_bhalq, &qi);
-	if (sc->sc_opmode == HAL_M_HOSTAP) {
+	if (sc->sc_opmode == ATH9K_M_HOSTAP) {
 		/* Always burst out beacon and CAB traffic. */
 		qi.tqi_aifs = 1;
 		qi.tqi_cwmin = 0;
@@ -70,11 +70,11 @@ static void ath_beacon_setup(struct ath_softc *sc,
 	struct ath_hal *ah = sc->sc_ah;
 	struct ath_desc *ds;
 	int flags, antenna;
-	const struct hal_rate_table *rt;
-	u_int8_t rix, rate;
+	const struct ath9k_rate_table *rt;
+	u8 rix, rate;
 	int ctsrate = 0;
 	int ctsduration = 0;
-	struct hal_11n_rate_series  series[4];
+	struct ath9k_11n_rate_series  series[4];
 
 	DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
 		__func__, skb, skb->len);
@@ -82,11 +82,11 @@ static void ath_beacon_setup(struct ath_softc *sc,
 	/* setup descriptors */
 	ds = bf->bf_desc;
 
-	flags = HAL_TXDESC_NOACK;
+	flags = ATH9K_TXDESC_NOACK;
 
-	if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
+	if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport) {
 		ds->ds_link = bf->bf_daddr; /* self-linked */
-		flags |= HAL_TXDESC_VEOL;
+		flags |= ATH9K_TXDESC_VEOL;
 		/* Let hardware handle antenna switching. */
 		antenna = 0;
 	} else {
@@ -114,10 +114,10 @@ static void ath_beacon_setup(struct ath_softc *sc,
 
 	ath9k_hw_set11n_txdesc(ah, ds
 			      , skb->len + FCS_LEN /* frame length */
-			      , HAL_PKT_TYPE_BEACON /* Atheros packet type */
+			      , ATH9K_PKT_TYPE_BEACON /* Atheros packet type */
 			      , avp->av_btxctl.txpower /* txpower XXX */
-			      , HAL_TXKEYIX_INVALID /* no encryption */
-			      , HAL_KEY_TYPE_CLEAR /* no encryption */
+			      , ATH9K_TXKEYIX_INVALID /* no encryption */
+			      , ATH9K_KEY_TYPE_CLEAR /* no encryption */
 			      , flags /* no ack, veol for beacons */
 		);
 
@@ -129,11 +129,11 @@ static void ath_beacon_setup(struct ath_softc *sc,
 			   , ds /* first descriptor */
 		);
 
-	memzero(series, sizeof(struct hal_11n_rate_series) * 4);
+	memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
 	series[0].Tries = 1;
 	series[0].Rate = rate;
 	series[0].ChSel = sc->sc_tx_chainmask;
-	series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
+	series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
 	ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
 		ctsrate, ctsduration, series, 4, 0);
 }
@@ -325,7 +325,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
 /*
  *  Setup a h/w transmit queue for beacons.
  *
- *  This function allocates an information structure (struct hal_txq_info)
+ *  This function allocates an information structure (struct ath9k_txq_info)
  *  on the stack, sets some specific parameters (zero out channel width
  *  min/max, and enable aifs). The info structure does not need to be
  *  persistant.
@@ -333,14 +333,14 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
 
 int ath_beaconq_setup(struct ath_hal *ah)
 {
-	struct hal_txq_info qi;
+	struct ath9k_txq_info qi;
 
 	memzero(&qi, sizeof(qi));
 	qi.tqi_aifs = 1;
 	qi.tqi_cwmin = 0;
 	qi.tqi_cwmax = 0;
 	/* NB: don't enable any interrupts */
-	return ath9k_hw_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
+	return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
 }
 
 
@@ -373,7 +373,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 				struct ath_buf, list);
 		list_del(&avp->av_bcbuf->list);
 
-		if (sc->sc_opmode == HAL_M_HOSTAP ||
+		if (sc->sc_opmode == ATH9K_M_HOSTAP ||
 			!sc->sc_ah->ah_caps.halVEOLSupport) {
 			int slot;
 			/*
@@ -433,7 +433,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 	 * following the header.
 	 */
 	if (avp->av_bslot > 0) {
-		u_int64_t tsfadjust;
+		u64 tsfadjust;
 		__le64 val;
 		int intval;
 
@@ -539,19 +539,19 @@ void ath_beacon_free(struct ath_softc *sc)
 void ath9k_beacon_tasklet(unsigned long data)
 {
 #define TSF_TO_TU(_h,_l)					\
-	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
+	((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 
 	struct ath_softc *sc = (struct ath_softc *)data;
 	struct ath_hal *ah = sc->sc_ah;
 	struct ath_buf *bf = NULL;
 	int slot, if_id;
-	u_int32_t bfaddr;
-	u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
-	u_int32_t show_cycles = 0;
-	u_int32_t bc = 0; /* beacon count */
-	u_int64_t tsf;
-	u_int32_t tsftu;
-	u_int16_t intval;
+	u32 bfaddr;
+	u32 rx_clear = 0, rx_frame = 0, tx_frame = 0;
+	u32 show_cycles = 0;
+	u32 bc = 0; /* beacon count */
+	u64 tsf;
+	u32 tsftu;
+	u16 intval;
 
 	if (sc->sc_noreset) {
 		show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
@@ -739,11 +739,11 @@ void ath_bstuck_process(struct ath_softc *sc)
 void ath_beacon_config(struct ath_softc *sc, int if_id)
 {
 #define TSF_TO_TU(_h,_l)					\
-	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
+	((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 	struct ath_hal *ah = sc->sc_ah;
-	u_int32_t nexttbtt, intval;
+	u32 nexttbtt, intval;
 	struct ath_beacon_config conf;
-	enum hal_opmode av_opmode;
+	enum ath9k_opmode av_opmode;
 
 	if (if_id != ATH_IF_ID_ANY)
 		av_opmode = sc->sc_vaps[if_id]->av_opmode;
@@ -768,7 +768,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 	nexttbtt = TSF_TO_TU(LE_READ_4(conf.u.last_tstamp + 4),
 			     LE_READ_4(conf.u.last_tstamp));
 	/* XXX conditionalize multi-bss support? */
-	if (sc->sc_opmode == HAL_M_HOSTAP) {
+	if (sc->sc_opmode == ATH9K_M_HOSTAP) {
 		/*
 		 * For multi-bss ap support beacons are either staggered
 		 * evenly over N slots or burst together.  For the former
@@ -776,10 +776,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		 * Slots that are not occupied will generate nothing.
 		 */
 		/* NB: the beacon interval is kept internally in TU's */
-		intval = conf.beacon_interval & HAL_BEACON_PERIOD;
+		intval = conf.beacon_interval & ATH9K_BEACON_PERIOD;
 		intval /= ATH_BCBUF;    /* for staggered beacons */
 	} else {
-		intval = conf.beacon_interval & HAL_BEACON_PERIOD;
+		intval = conf.beacon_interval & ATH9K_BEACON_PERIOD;
 	}
 
 	if (nexttbtt == 0)      /* e.g. for ap mode */
@@ -788,11 +788,11 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		nexttbtt = roundup(nexttbtt, intval);
 	DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
 		__func__, nexttbtt, intval, conf.beacon_interval);
-	/* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
-	if (sc->sc_opmode == HAL_M_STA) {
-		struct hal_beacon_state bs;
-		u_int64_t tsf;
-		u_int32_t tsftu;
+	/* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */
+	if (sc->sc_opmode == ATH9K_M_STA) {
+		struct ath9k_beacon_state bs;
+		u64 tsf;
+		u32 tsftu;
 		int dtimperiod, dtimcount, sleepduration;
 		int cfpperiod, cfpcount;
 
@@ -901,24 +901,24 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 
 		ath9k_hw_set_interrupts(ah, 0);
 		ath9k_hw_set_sta_beacon_timers(ah, &bs);
-		sc->sc_imask |= HAL_INT_BMISS;
+		sc->sc_imask |= ATH9K_INT_BMISS;
 		ath9k_hw_set_interrupts(ah, sc->sc_imask);
 	} else {
-		u_int64_t tsf;
-		u_int32_t tsftu;
+		u64 tsf;
+		u32 tsftu;
 		ath9k_hw_set_interrupts(ah, 0);
 		if (nexttbtt == intval)
-			intval |= HAL_BEACON_RESET_TSF;
-		if (sc->sc_opmode == HAL_M_IBSS) {
+			intval |= ATH9K_BEACON_RESET_TSF;
+		if (sc->sc_opmode == ATH9K_M_IBSS) {
 			/*
 			 * Pull nexttbtt forward to reflect the current
 			 * TSF .
 			 */
 #define FUDGE   2
-			if (!(intval & HAL_BEACON_RESET_TSF)) {
+			if (!(intval & ATH9K_BEACON_RESET_TSF)) {
 				tsf = ath9k_hw_gettsf64(ah);
-				tsftu = TSF_TO_TU((u_int32_t)(tsf>>32),
-					(u_int32_t)tsf) + FUDGE;
+				tsftu = TSF_TO_TU((u32)(tsf>>32),
+					(u32)tsf) + FUDGE;
 				do {
 					nexttbtt += intval;
 				} while (nexttbtt < tsftu);
@@ -927,7 +927,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 			DPRINTF(sc, ATH_DBG_BEACON,
 				"%s: IBSS nexttbtt %u intval %u (%u)\n",
 				__func__, nexttbtt,
-				intval & ~HAL_BEACON_RESET_TSF,
+				intval & ~ATH9K_BEACON_RESET_TSF,
 				conf.beacon_interval);
 
 			/*
@@ -937,17 +937,17 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 			 * self-linked tx descriptor and let the hardware
 			 * deal with things.
 			 */
-			intval |= HAL_BEACON_ENA;
+			intval |= ATH9K_BEACON_ENA;
 			if (!ah->ah_caps.halVEOLSupport)
-				sc->sc_imask |= HAL_INT_SWBA;
+				sc->sc_imask |= ATH9K_INT_SWBA;
 			ath_beaconq_config(sc);
-		} else if (sc->sc_opmode == HAL_M_HOSTAP) {
+		} else if (sc->sc_opmode == ATH9K_M_HOSTAP) {
 			/*
 			 * In AP mode we enable the beacon timers and
 			 * SWBA interrupts to prepare beacon frames.
 			 */
-			intval |= HAL_BEACON_ENA;
-			sc->sc_imask |= HAL_INT_SWBA;   /* beacon prepare */
+			intval |= ATH9K_BEACON_ENA;
+			sc->sc_imask |= ATH9K_INT_SWBA;   /* beacon prepare */
 			ath_beaconq_config(sc);
 		}
 		ath9k_hw_beaconinit(ah, nexttbtt, intval);
@@ -957,7 +957,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		 * When using a self-linked beacon descriptor in
 		 * ibss mode load it once here.
 		 */
-		if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
+		if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport)
 			ath_beacon_start_adhoc(sc, 0);
 	}
 #undef TSF_TO_TU
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/core.c b/package/ath9k/src/drivers/net/wireless/ath9k/core.c
index 587f307b8..322570593 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/core.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/core.c
@@ -21,23 +21,23 @@
 
 static int ath_outdoor;		/* enable outdoor use */
 
-static const u_int8_t ath_bcast_mac[ETH_ALEN] =
+static const u8 ath_bcast_mac[ETH_ALEN] =
     { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 
-static u_int32_t ath_chainmask_sel_up_rssi_thres =
+static u32 ath_chainmask_sel_up_rssi_thres =
 	ATH_CHAINMASK_SEL_UP_RSSI_THRES;
-static u_int32_t ath_chainmask_sel_down_rssi_thres =
+static u32 ath_chainmask_sel_down_rssi_thres =
 	ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
-static u_int32_t ath_chainmask_sel_period =
+static u32 ath_chainmask_sel_period =
 	ATH_CHAINMASK_SEL_TIMEOUT;
 
 /* return bus cachesize in 4B word units */
 
 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
 {
-	u_int8_t u8tmp;
+	u8 u8tmp;
 
-	pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u_int8_t *)&u8tmp);
+	pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
 	*csz = (int)u8tmp;
 
 	/*
@@ -60,7 +60,7 @@ static void bus_read_cachesize(struct ath_softc *sc, int *csz)
 
 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
 {
-	const struct hal_rate_table *rt;
+	const struct ath9k_rate_table *rt;
 	int i;
 
 	memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
@@ -68,11 +68,11 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
 	BUG_ON(!rt);
 
 	for (i = 0; i < rt->rateCount; i++)
-		sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;
+		sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
 
 	memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
 	for (i = 0; i < 256; i++) {
-		u_int8_t ix = rt->rateCodeToIndex[i];
+		u8 ix = rt->rateCodeToIndex[i];
 
 		if (ix == 0xff)
 			continue;
@@ -110,7 +110,7 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
 static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	const struct hal_rate_table *rt;
+	const struct ath9k_rate_table *rt;
 
 	switch (mode) {
 	case WIRELESS_MODE_11a:
@@ -168,60 +168,89 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
 
 /*
  *  Set up channel list
- *
- *  Determines the proper set of channelflags based on the selected mode,
- *  allocates a channel array, and passes it to the HAL for initialization.
- *  If successful, the list is passed to the upper layer, then de-allocated.
-*/
-
-static int ath_getchannels(struct ath_softc *sc,
-			   u_int cc,
-			   bool outDoor,
-			   bool xchanMode)
+ */
+static int ath_setup_channels(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	struct hal_channel *chans;
-	int nchan;
-	u_int8_t regclassids[ATH_REGCLASSIDS_MAX];
-	u_int nregclass = 0;
-
-	chans = kmalloc(ATH_CHAN_MAX * sizeof(struct hal_channel), GFP_KERNEL);
-	if (chans == NULL) {
-		DPRINTF(sc, ATH_DBG_FATAL,
-			"%s: unable to allocate channel table\n", __func__);
-		return -ENOMEM;
-	}
-
+	int nchan, i, a = 0, b = 0;
+	u8 regclassids[ATH_REGCLASSIDS_MAX];
+	u32 nregclass = 0;
+	struct ieee80211_supported_band *band_2ghz;
+	struct ieee80211_supported_band *band_5ghz;
+	struct ieee80211_channel *chan_2ghz;
+	struct ieee80211_channel *chan_5ghz;
+	struct ath9k_channel *c;
+
+	/* Fill in ah->ah_channels */
 	if (!ath9k_regd_init_channels(ah,
-				      chans,
 				      ATH_CHAN_MAX,
-				      (u_int *)&nchan,
+				      (u32 *)&nchan,
 				      regclassids,
 				      ATH_REGCLASSIDS_MAX,
 				      &nregclass,
-				      cc,
+				      CTRY_DEFAULT,
 				      ATH9K_MODE_SEL_ALL,
-				      outDoor,
-				      xchanMode)) {
-		u_int32_t rd = ah->ah_currentRD;
+				      false,
+				      1)) {
+		u32 rd = ah->ah_currentRD;
 
 		DPRINTF(sc, ATH_DBG_FATAL,
-			"%s: unable to collect channel list from hal; "
+			"%s: unable to collect channel list; "
 			"regdomain likely %u country code %u\n",
-			__func__, rd, cc);
-		kfree(chans);
+			__func__, rd, CTRY_DEFAULT);
 		return -EINVAL;
 	}
 
-	ath_setup_channel_list(sc,
-			       CLIST_UPDATE,
-			       chans,
-			       nchan,
-			       regclassids,
-			       nregclass,
-			       CTRY_DEFAULT);
+	band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
+	band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
+	chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
+	chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
+
+	for (i = 0; i < nchan; i++) {
+		c = &ah->ah_channels[i];
+		if (IS_CHAN_2GHZ(c)) {
+			chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
+			chan_2ghz[a].center_freq = c->channel;
+			chan_2ghz[a].max_power = c->maxTxPower;
+
+			if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
+				chan_2ghz[a].flags |=
+					IEEE80211_CHAN_NO_IBSS;
+			if (c->channelFlags & CHANNEL_PASSIVE)
+				chan_2ghz[a].flags |=
+					IEEE80211_CHAN_PASSIVE_SCAN;
+
+			band_2ghz->n_channels = ++a;
+
+			DPRINTF(sc, ATH_DBG_CONFIG,
+				"%s: 2MHz channel: %d, "
+				"channelFlags: 0x%x\n",
+				__func__,
+				c->channel,
+				c->channelFlags);
+		} else if (IS_CHAN_5GHZ(c)) {
+			chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
+			chan_5ghz[b].center_freq = c->channel;
+			chan_5ghz[b].max_power = c->maxTxPower;
+
+			if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
+				chan_5ghz[b].flags |=
+					IEEE80211_CHAN_NO_IBSS;
+			if (c->channelFlags & CHANNEL_PASSIVE)
+				chan_5ghz[b].flags |=
+					IEEE80211_CHAN_PASSIVE_SCAN;
+
+			band_5ghz->n_channels = ++b;
+
+			DPRINTF(sc, ATH_DBG_CONFIG,
+				"%s: 5MHz channel: %d, "
+				"channelFlags: 0x%x\n",
+				__func__,
+				c->channel,
+				c->channelFlags);
+		}
+	}
 
-	kfree(chans);
 	return 0;
 }
 
@@ -233,29 +262,25 @@ static int ath_getchannels(struct ath_softc *sc,
  *  exist, the lowest mode (11b) is selected.
 */
 
-static enum wireless_mode ath_chan2mode(struct hal_channel *chan)
+static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
 {
-	if ((chan->channelFlags & CHANNEL_A) == CHANNEL_A)
+	if (chan->chanmode == CHANNEL_A)
 		return WIRELESS_MODE_11a;
-	else if ((chan->channelFlags & CHANNEL_G) == CHANNEL_G)
+	else if (chan->chanmode == CHANNEL_G)
 		return WIRELESS_MODE_11g;
-	else if ((chan->channelFlags & CHANNEL_B) == CHANNEL_B)
+	else if (chan->chanmode == CHANNEL_B)
 		return WIRELESS_MODE_11b;
-	else if ((chan->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)
+	else if (chan->chanmode == CHANNEL_A_HT20)
 		return WIRELESS_MODE_11NA_HT20;
-	else if ((chan->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)
+	else if (chan->chanmode == CHANNEL_G_HT20)
 		return WIRELESS_MODE_11NG_HT20;
-	else if ((chan->channelFlags & CHANNEL_A_HT40PLUS) ==
-		 CHANNEL_A_HT40PLUS)
+	else if (chan->chanmode == CHANNEL_A_HT40PLUS)
 		return WIRELESS_MODE_11NA_HT40PLUS;
-	else if ((chan->channelFlags & CHANNEL_A_HT40MINUS) ==
-		 CHANNEL_A_HT40MINUS)
+	else if (chan->chanmode == CHANNEL_A_HT40MINUS)
 		return WIRELESS_MODE_11NA_HT40MINUS;
-	else if ((chan->channelFlags & CHANNEL_G_HT40PLUS) ==
-		 CHANNEL_G_HT40PLUS)
+	else if (chan->chanmode == CHANNEL_G_HT40PLUS)
 		return WIRELESS_MODE_11NG_HT40PLUS;
-	else if ((chan->channelFlags & CHANNEL_G_HT40MINUS) ==
-		 CHANNEL_G_HT40MINUS)
+	else if (chan->chanmode == CHANNEL_G_HT40MINUS)
 		return WIRELESS_MODE_11NG_HT40MINUS;
 
 	/* NB: should not get here */
@@ -269,7 +294,7 @@ static enum wireless_mode ath_chan2mode(struct hal_channel *chan)
  *  the current operating mode for the new channel.
 */
 
-static void ath_chan_change(struct ath_softc *sc, struct hal_channel *chan)
+static void ath_chan_change(struct ath_softc *sc, struct ath9k_channel *chan)
 {
 	enum wireless_mode mode;
 
@@ -332,8 +357,8 @@ static int ath_stop(struct ath_softc *sc)
 void ath_scan_start(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	u_int32_t rfilt;
-	u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
+	u32 rfilt;
+	u32 now = (u32) jiffies_to_msecs(get_timestamp());
 
 	sc->sc_scanning = 1;
 	rfilt = ath_calcrxfilter(sc);
@@ -357,8 +382,8 @@ void ath_scan_start(struct ath_softc *sc)
 void ath_scan_end(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	u_int32_t rfilt;
-	u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
+	u32 rfilt;
+	u32 now = (u32) jiffies_to_msecs(get_timestamp());
 
 	sc->sc_scanning = 0;
 	/* Request for a full reset due to rx packet filter changes */
@@ -378,11 +403,11 @@ void ath_scan_end(struct ath_softc *sc)
  * by reseting the chip.  To accomplish this we must first cleanup any pending
  * DMA, then restart stuff after a la ath_init.
 */
-int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
+int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	bool fastcc = true, stopped;
-	enum hal_ht_macmode ht_macmode;
+	enum ath9k_ht_macmode ht_macmode;
 
 	if (sc->sc_invalid)	/* if the device is invalid or removed */
 		return -EIO;
@@ -401,7 +426,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 	if (hchan->channel != sc->sc_curchan.channel ||
 	    hchan->channelFlags != sc->sc_curchan.channelFlags ||
 	    sc->sc_update_chainmask || sc->sc_full_reset) {
-		enum hal_status status;
+		int status;
 		/*
 		 * This is only performed if the channel settings have
 		 * actually changed.
@@ -580,7 +605,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	struct ath_vap *avp;
-	u_int32_t rfilt = 0;
+	u32 rfilt = 0;
 	DECLARE_MAC_BUF(mac);
 
 	avp = sc->sc_vaps[if_id];
@@ -595,12 +620,12 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 #endif
 
 	/* update ratectrl about the new state */
-	ath_rate_newstate(sc, avp, 0);
+	ath_rate_newstate(sc, avp);
 
 	rfilt = ath_calcrxfilter(sc);
 	ath9k_hw_setrxfilter(ah, rfilt);
 
-	if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS) {
+	if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
 		memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
 		ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
 	} else
@@ -616,8 +641,8 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 	 * Disable BMISS interrupt when we're not associated
 	 */
 	ath9k_hw_set_interrupts(ah,
-		sc->sc_imask & ~(HAL_INT_SWBA | HAL_INT_BMISS));
-	sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
+		sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
+	sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
 	/* need to reconfigure the beacons when it moves to RUN */
 	sc->sc_beacons = 0;
 
@@ -627,7 +652,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
-		   enum hal_opmode opmode)
+		   enum ath9k_opmode opmode)
 {
 	struct ath_vap *avp;
 
@@ -638,11 +663,11 @@ int ath_vap_attach(struct ath_softc *sc,
 	}
 
 	switch (opmode) {
-	case HAL_M_STA:
-	case HAL_M_IBSS:
-	case HAL_M_MONITOR:
+	case ATH9K_M_STA:
+	case ATH9K_M_IBSS:
+	case ATH9K_M_MONITOR:
 		break;
-	case HAL_M_HOSTAP:
+	case ATH9K_M_HOSTAP:
 		/* XXX not right, beacon buffer is allocated on RUN trans */
 		if (list_empty(&sc->sc_bbuf))
 			return -ENOMEM;
@@ -737,12 +762,12 @@ int ath_vap_config(struct ath_softc *sc,
 /* Core */
 /********/
 
-int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
+int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	enum hal_status status;
+	int status;
 	int error = 0;
-	enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
+	enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
 
 	DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
 
@@ -801,32 +826,32 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 		goto done;
 	}
 	/* Setup our intr mask. */
-	sc->sc_imask = HAL_INT_RX | HAL_INT_TX
-		| HAL_INT_RXEOL | HAL_INT_RXORN
-		| HAL_INT_FATAL | HAL_INT_GLOBAL;
+	sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
+		| ATH9K_INT_RXEOL | ATH9K_INT_RXORN
+		| ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
 
 	if (ah->ah_caps.halGTTSupport)
-		sc->sc_imask |= HAL_INT_GTT;
+		sc->sc_imask |= ATH9K_INT_GTT;
 
 	if (ah->ah_caps.halHTSupport)
-		sc->sc_imask |= HAL_INT_CST;
+		sc->sc_imask |= ATH9K_INT_CST;
 
 	/*
 	 * Enable MIB interrupts when there are hardware phy counters.
 	 * Note we only do this (at the moment) for station mode.
 	 */
 	if (ath9k_hw_phycounters(ah) &&
-	    ((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
-		sc->sc_imask |= HAL_INT_MIB;
+	    ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
+		sc->sc_imask |= ATH9K_INT_MIB;
 	/*
 	 * Some hardware processes the TIM IE and fires an
 	 * interrupt when the TIM bit is set.  For hardware
 	 * that does, if not overridden by configuration,
 	 * enable the TIM interrupt when operating as station.
 	 */
-	if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == HAL_M_STA &&
+	if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == ATH9K_M_STA &&
 		!sc->sc_config.swBeaconProcess)
-		sc->sc_imask |= HAL_INT_TIM;
+		sc->sc_imask |= ATH9K_INT_TIM;
 	/*
 	 *  Don't enable interrupts here as we've not yet built our
 	 *  vap and node data structures, which will be needed as soon
@@ -849,7 +874,7 @@ done:
  * and to reset the hardware when rf gain settings must be reset.
  */
 
-static int ath_reset_start(struct ath_softc *sc, u_int32_t flag)
+static int ath_reset_start(struct ath_softc *sc, u32 flag)
 {
 	struct ath_hal *ah = sc->sc_ah;
 
@@ -861,7 +886,7 @@ static int ath_reset_start(struct ath_softc *sc, u_int32_t flag)
 	return 0;
 }
 
-static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
+static int ath_reset_end(struct ath_softc *sc, u32 flag)
 {
 	struct ath_hal *ah = sc->sc_ah;
 
@@ -885,7 +910,7 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
 	/* Restart the txq */
 	if (flag & RESET_RETRY_TXQ) {
 		int i;
-		for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+		for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 			if (ATH_TXQ_SETUP(sc, i)) {
 				spin_lock_bh(&sc->sc_txq[i].axq_lock);
 				ath_txq_schedule(sc, &sc->sc_txq[i]);
@@ -899,9 +924,9 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
 int ath_reset(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	enum hal_status status;
+	int status;
 	int error = 0;
-	enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
+	enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
 
 	/* NB: indicate channel change so we do a full reset */
 	spin_lock_bh(&sc->sc_resetlock);
@@ -949,7 +974,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 {
 	struct ath_softc *sc = dev;
 	struct ath_hal *ah = sc->sc_ah;
-	enum hal_int status;
+	enum ath9k_int status;
 	bool sched = false;
 
 	do {
@@ -985,18 +1010,18 @@ irqreturn_t ath_isr(int irq, void *dev)
 
 		sc->sc_intrstatus = status;
 
-		if (status & HAL_INT_FATAL) {
+		if (status & ATH9K_INT_FATAL) {
 			/* need a chip reset */
 			sched = true;
-		} else if (status & HAL_INT_RXORN) {
+		} else if (status & ATH9K_INT_RXORN) {
 			/* need a chip reset */
 			sched = true;
 		} else {
-			if (status & HAL_INT_SWBA) {
+			if (status & ATH9K_INT_SWBA) {
 				/* schedule a tasklet for beacon handling */
 				tasklet_schedule(&sc->bcon_tasklet);
 			}
-			if (status & HAL_INT_RXEOL) {
+			if (status & ATH9K_INT_RXEOL) {
 				/*
 				 * NB: the hardware should re-read the link when
 				 *     RXE bit is written, but it doesn't work
@@ -1005,20 +1030,20 @@ irqreturn_t ath_isr(int irq, void *dev)
 				sched = true;
 			}
 
-			if (status & HAL_INT_TXURN)
+			if (status & ATH9K_INT_TXURN)
 				/* bump tx trigger level */
 				ath9k_hw_updatetxtriglevel(ah, true);
 			/* XXX: optimize this */
-			if (status & HAL_INT_RX)
+			if (status & ATH9K_INT_RX)
 				sched = true;
-			if (status & HAL_INT_TX)
+			if (status & ATH9K_INT_TX)
 				sched = true;
-			if (status & HAL_INT_BMISS)
+			if (status & ATH9K_INT_BMISS)
 				sched = true;
 			/* carrier sense timeout */
-			if (status & HAL_INT_CST)
+			if (status & ATH9K_INT_CST)
 				sched = true;
-			if (status & HAL_INT_MIB) {
+			if (status & ATH9K_INT_MIB) {
 				/*
 				 * Disable interrupts until we service the MIB
 				 * interrupt; otherwise it will continue to
@@ -1033,7 +1058,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 				ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 				ath9k_hw_set_interrupts(ah, sc->sc_imask);
 			}
-			if (status & HAL_INT_TIM_TIMER) {
+			if (status & ATH9K_INT_TIM_TIMER) {
 				if (!ah->ah_caps.halAutoSleepSupport) {
 					/* Clear RxAbort bit so that we can
 					 * receive frames */
@@ -1046,7 +1071,7 @@ irqreturn_t ath_isr(int irq, void *dev)
 
 	if (sched) {
 		/* turn off every interrupt except SWBA */
-		ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
+		ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 		tasklet_schedule(&sc->intr_tq);
 	}
 
@@ -1058,20 +1083,21 @@ irqreturn_t ath_isr(int irq, void *dev)
 static void ath9k_tasklet(unsigned long data)
 {
 	struct ath_softc *sc = (struct ath_softc *)data;
-	u_int32_t status = sc->sc_intrstatus;
+	u32 status = sc->sc_intrstatus;
 
-	if (status & HAL_INT_FATAL) {
+	if (status & ATH9K_INT_FATAL) {
 		/* need a chip reset */
 		ath_internal_reset(sc);
 		return;
 	} else {
 
-		if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
+		if (status &
+		    (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 			/* XXX: fill me in */
 			/*
-			if (status & HAL_INT_RXORN) {
+			if (status & ATH9K_INT_RXORN) {
 			}
-			if (status & HAL_INT_RXEOL) {
+			if (status & ATH9K_INT_RXEOL) {
 			}
 			*/
 			spin_lock_bh(&sc->sc_rxflushlock);
@@ -1079,16 +1105,16 @@ static void ath9k_tasklet(unsigned long data)
 			spin_unlock_bh(&sc->sc_rxflushlock);
 		}
 		/* XXX: optimize this */
-		if (status & HAL_INT_TX)
+		if (status & ATH9K_INT_TX)
 			ath_tx_tasklet(sc);
 		/* XXX: fill me in */
 		/*
-		if (status & HAL_INT_BMISS) {
+		if (status & ATH9K_INT_BMISS) {
 		}
-		if (status & (HAL_INT_TIM | HAL_INT_DTIMSYNC)) {
-			if (status & HAL_INT_TIM) {
+		if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
+			if (status & ATH9K_INT_TIM) {
 			}
-			if (status & HAL_INT_DTIMSYNC) {
+			if (status & ATH9K_INT_DTIMSYNC) {
 			}
 		}
 		*/
@@ -1098,13 +1124,13 @@ static void ath9k_tasklet(unsigned long data)
 	ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 }
 
-int ath_init(u_int16_t devid, struct ath_softc *sc)
+int ath_init(u16 devid, struct ath_softc *sc)
 {
 	struct ath_hal *ah = NULL;
-	enum hal_status status;
+	int status;
 	int error = 0, i;
 	int csz = 0;
-	u_int32_t rd;
+	u32 rd;
 
 	/* XXX: hardware will not be ready until ath_open() being called */
 	sc->sc_invalid = 1;
@@ -1154,7 +1180,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	 * reset the contents on initial power up.
 	 */
 	for (i = 0; i < sc->sc_keymax; i++)
-		ath9k_hw_keyreset(ah, (u_int16_t) i);
+		ath9k_hw_keyreset(ah, (u16) i);
 	/*
 	 * Mark key cache slots associated with global keys
 	 * as in use.  If we knew TKIP was not to be used we
@@ -1175,15 +1201,12 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	 */
 	rd = ah->ah_currentRD;
 
-	error = ath_getchannels(sc,
-				CTRY_DEFAULT,
-				ath_outdoor,
-				1);
+	error = ath_setup_channels(sc);
 	if (error)
 		goto bad;
 
 	/* default to STA mode */
-	sc->sc_opmode = HAL_M_MONITOR;
+	sc->sc_opmode = ATH9K_M_MONITOR;
 
 	/* Setup rate tables for all potential media types. */
 	/* 11g encompasses b,g */
@@ -1207,7 +1230,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 		error = -EIO;
 		goto bad2;
 	}
-	sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
+	sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
 	if (sc->sc_cabq == NULL) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup CAB xmit queue\n", __func__);
@@ -1223,7 +1246,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 
 	/* Setup data queues */
 	/* NB: ensure BK queue is the lowest priority h/w queue */
-	if (!ath_tx_setup(sc, HAL_WME_AC_BK)) {
+	if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for BK traffic\n",
 			__func__);
@@ -1231,21 +1254,21 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 		goto bad2;
 	}
 
-	if (!ath_tx_setup(sc, HAL_WME_AC_BE)) {
+	if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for BE traffic\n",
 			__func__);
 		error = -EIO;
 		goto bad2;
 	}
-	if (!ath_tx_setup(sc, HAL_WME_AC_VI)) {
+	if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for VI traffic\n",
 			__func__);
 		error = -EIO;
 		goto bad2;
 	}
-	if (!ath_tx_setup(sc, HAL_WME_AC_VO)) {
+	if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for VO traffic\n",
 			__func__);
@@ -1259,7 +1282,8 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 		goto bad2;
 	}
 
-	if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_TKIP, NULL)) {
+	if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
+				   ATH9K_CIPHER_TKIP, NULL)) {
 		/*
 		 * Whether we should enable h/w TKIP MIC.
 		 * XXX: if we don't support WME TKIP MIC, then we wouldn't
@@ -1275,14 +1299,16 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	 * With split mic keys the number of stations is limited
 	 * to 27 otherwise 59.
 	 */
-	if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_TKIP, NULL)
-	    && ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_MIC, NULL)
-	    && ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT, 0, NULL))
+	if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
+				   ATH9K_CIPHER_TKIP, NULL)
+	    && ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
+				      ATH9K_CIPHER_MIC, NULL)
+	    && ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT,
+				      0, NULL))
 		sc->sc_splitmic = 1;
 
 	/* turn on mcast key search if possible */
-	if (ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL)
-					== HAL_OK)
+	if (!ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL))
 		(void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1,
 					     1, NULL);
 
@@ -1314,7 +1340,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 		ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
 		ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
 	}
-	sc->sc_slottime = HAL_SLOT_TIME_9;	/* default to short slot time */
+	sc->sc_slottime = ATH9K_SLOT_TIME_9;	/* default to short slot time */
 
 	/* initialize beacon slots */
 	for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
@@ -1331,7 +1357,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	return 0;
 bad2:
 	/* cleanup tx queues */
-	for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
+	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 		if (ATH_TXQ_SETUP(sc, i))
 			ath_tx_cleanupq(sc, &sc->sc_txq[i]);
 bad:
@@ -1349,10 +1375,10 @@ void ath_deinit(struct ath_softc *sc)
 
 	ath_stop(sc);
 	if (!sc->sc_invalid)
-		ath9k_hw_setpower(sc->sc_ah, HAL_PM_AWAKE);
+		ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 	ath_rate_detach(sc->sc_rc);
 	/* cleanup tx queues */
-	for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
+	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 		if (ATH_TXQ_SETUP(sc, i))
 			ath_tx_cleanupq(sc, &sc->sc_txq[i]);
 	ath9k_hw_detach(ah);
@@ -1488,7 +1514,7 @@ void ath_newassoc(struct ath_softc *sc,
 /* Encryption */
 /**************/
 
-void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
+void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 {
 	ath9k_hw_keyreset(sc->sc_ah, keyix);
 	if (freeslot)
@@ -1496,9 +1522,9 @@ void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
 }
 
 int ath_keyset(struct ath_softc *sc,
-	       u_int16_t keyix,
-	       struct hal_keyval *hk,
-	       const u_int8_t mac[ETH_ALEN])
+	       u16 keyix,
+	       struct ath9k_keyval *hk,
+	       const u8 mac[ETH_ALEN])
 {
 	bool status;
 
@@ -1522,7 +1548,7 @@ int ath_keyset(struct ath_softc *sc,
 void ath_update_txpow(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	u_int32_t txpow;
+	u32 txpow;
 
 	if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 		ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
@@ -1534,7 +1560,7 @@ void ath_update_txpow(struct ath_softc *sc)
 
 /* Return the current country and domain information */
 void ath_get_currentCountry(struct ath_softc *sc,
-	struct hal_country_entry *ctry)
+	struct ath9k_country_entry *ctry)
 {
 	ath9k_regd_get_current_country(sc->sc_ah, ctry);
 
@@ -1572,8 +1598,8 @@ void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
 }
 
 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
-			    u_int8_t num_antcfg,
-			    const u_int8_t *bssid)
+			    u8 num_antcfg,
+			    const u8 *bssid)
 {
 	antdiv->antdiv_num_antcfg =
 		num_antcfg < ATH_ANT_DIV_MAX_CFG ?
@@ -1594,10 +1620,10 @@ void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
 }
 
 static int32_t ath_find_max_val(int32_t *val,
-	u_int8_t num_val, u_int8_t *max_index)
+	u8 num_val, u8 *max_index)
 {
-	u_int32_t MaxVal = *val++;
-	u_int32_t cur_index = 0;
+	u32 MaxVal = *val++;
+	u32 cur_index = 0;
 
 	*max_index = 0;
 	while (++cur_index < num_val) {
@@ -1618,8 +1644,8 @@ void ath_slow_ant_div(struct ath_antdiv *antdiv,
 {
 	struct ath_softc *sc = antdiv->antdiv_sc;
 	struct ath_hal *ah = sc->sc_ah;
-	u_int64_t curtsf = 0;
-	u_int8_t bestcfg, curcfg = antdiv->antdiv_curcfg;
+	u64 curtsf = 0;
+	u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
 	__le16 fc = hdr->frame_control;
 
 	if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
@@ -1642,7 +1668,7 @@ void ath_slow_ant_div(struct ath_antdiv *antdiv,
 			if (curcfg == antdiv->antdiv_num_antcfg)
 				curcfg = 0;
 
-			if (HAL_OK == ath9k_hw_select_antconfig(ah, curcfg)) {
+			if (!ath9k_hw_select_antconfig(ah, curcfg)) {
 				antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
 				antdiv->antdiv_curcfg = curcfg;
 				antdiv->antdiv_laststatetsf = curtsf;
@@ -1663,14 +1689,14 @@ void ath_slow_ant_div(struct ath_antdiv *antdiv,
 		if (curcfg == antdiv->antdiv_bestcfg) {
 			ath_find_max_val(antdiv->antdiv_lastbrssi,
 				   antdiv->antdiv_num_antcfg, &bestcfg);
-			if (HAL_OK == ath9k_hw_select_antconfig(ah, bestcfg)) {
+			if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
 				antdiv->antdiv_bestcfg = bestcfg;
 				antdiv->antdiv_curcfg = bestcfg;
 				antdiv->antdiv_laststatetsf = curtsf;
 				antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
 			}
 		} else {
-			if (HAL_OK == ath9k_hw_select_antconfig(ah, curcfg)) {
+			if (!ath9k_hw_select_antconfig(ah, curcfg)) {
 				antdiv->antdiv_curcfg = curcfg;
 				antdiv->antdiv_laststatetsf = curtsf;
 				antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
@@ -1730,9 +1756,9 @@ int ath_descdma_setup(struct ath_softc *sc,
 	 * one skipped descriptor per 4K page.
 	 */
 	if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
-		u_int32_t ndesc_skipped =
+		u32 ndesc_skipped =
 			ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
-		u_int32_t dma_len;
+		u32 dma_len;
 
 		while (ndesc_skipped) {
 			dma_len = ndesc_skipped * sizeof(struct ath_desc);
@@ -1752,8 +1778,8 @@ int ath_descdma_setup(struct ath_softc *sc,
 	}
 	ds = dd->dd_desc;
 	DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
-		__func__, dd->dd_name, ds, (u_int32_t) dd->dd_desc_len,
-		ito64(dd->dd_desc_paddr), /*XXX*/(u_int32_t) dd->dd_desc_len);
+		__func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
+		ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 
 	/* allocate buffers */
 	bsize = sizeof(struct ath_buf) * nbuf;
@@ -1838,40 +1864,40 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
 
 	switch (queue) {
 	case 0:
-		qnum = sc->sc_haltype2q[HAL_WME_AC_VO];
+		qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
 		break;
 	case 1:
-		qnum = sc->sc_haltype2q[HAL_WME_AC_VI];
+		qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
 		break;
 	case 2:
-		qnum = sc->sc_haltype2q[HAL_WME_AC_BE];
+		qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
 		break;
 	case 3:
-		qnum = sc->sc_haltype2q[HAL_WME_AC_BK];
+		qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
 		break;
 	default:
-		qnum = sc->sc_haltype2q[HAL_WME_AC_BE];
+		qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
 		break;
 	}
 
 	return qnum;
 }
 
-int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc)
+int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
 {
 	int qnum;
 
 	switch (queue) {
-	case HAL_WME_AC_VO:
+	case ATH9K_WME_AC_VO:
 		qnum = 0;
 		break;
-	case HAL_WME_AC_VI:
+	case ATH9K_WME_AC_VI:
 		qnum = 1;
 		break;
-	case HAL_WME_AC_BE:
+	case ATH9K_WME_AC_BE:
 		qnum = 2;
 		break;
-	case HAL_WME_AC_BK:
+	case ATH9K_WME_AC_BK:
 		qnum = 3;
 		break;
 	default:
@@ -1890,9 +1916,9 @@ int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc)
  *  a full 64-bit TSF using the current h/w TSF.
 */
 
-u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp)
+u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
 {
-	u_int64_t tsf;
+	u64 tsf;
 
 	tsf = ath9k_hw_gettsf64(sc->sc_ah);
 	if ((tsf & 0x7fff) < rstamp)
@@ -1907,7 +1933,7 @@ u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp)
  *  MIMO technology.
 */
 
-void ath_setdefantenna(void *context, u_int antenna)
+void ath_setdefantenna(void *context, u32 antenna)
 {
 	struct ath_softc *sc = (struct ath_softc *)context;
 	struct ath_hal *ah = sc->sc_ah;
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/core.h b/package/ath9k/src/drivers/net/wireless/ath9k/core.h
index b2713438e..ddf430438 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/core.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/core.h
@@ -213,11 +213,11 @@ enum ATH_DEBUG {
 /* Per-instance load-time (note: NOT run-time) configurations
  * for Atheros Device */
 struct ath_config {
-	u_int32_t   ath_aggr_prot;
-	u_int16_t   txpowlimit;
-	u_int16_t   txpowlimit_override;
-	u_int8_t    cabqReadytime; /* Cabq Readytime % */
-	u_int8_t    swBeaconProcess; /* Process received beacons
+	u32   ath_aggr_prot;
+	u16   txpowlimit;
+	u16   txpowlimit_override;
+	u8    cabqReadytime; /* Cabq Readytime % */
+	u8    swBeaconProcess; /* Process received beacons
 					in SW (vs HW) */
 };
 
@@ -269,8 +269,8 @@ chains is due to FF aggregation in the driver. */
 
 struct ath_buf_state {
 	int bfs_nframes;	/* # frames in aggregate */
-	u_int16_t bfs_al;	/* length of aggregate */
-	u_int16_t bfs_frmlen;	/* length of frame */
+	u16 bfs_al;	/* length of aggregate */
+	u16 bfs_frmlen;	/* length of frame */
 	int bfs_seqno;		/* sequence number */
 	int bfs_tidno;		/* tid of this frame */
 	int bfs_retries;	/* current retries */
@@ -289,7 +289,8 @@ struct ath_buf_state {
 				when set for tx frame */
 	int bfs_rifsburst_elem;	/* RIFS burst/bar */
 	int bfs_nrifsubframes;	/* # of elements in burst */
-	enum hal_key_type bfs_keytype;	/* key type use to encrypt this frame */
+	/* key type use to encrypt this frame */
+	enum ath9k_key_type bfs_keytype;
 };
 
 #define bf_nframes      	bf_state.bfs_nframes
@@ -332,8 +333,8 @@ struct ath_buf {
 	struct ath_desc *bf_desc;	/* virtual addr of desc */
 	dma_addr_t bf_daddr;		/* physical addr of desc */
 	dma_addr_t bf_buf_addr;		/* physical addr of data buffer */
-	u_int32_t bf_status;
-	u_int16_t bf_flags;		/* tx descriptor flags */
+	u32 bf_status;
+	u16 bf_flags;		/* tx descriptor flags */
 	struct ath_buf_state bf_state;	/* buffer state */
 	dma_addr_t bf_dmacontext;
 };
@@ -360,7 +361,7 @@ struct ath_descdma {
 	const char *dd_name;
 	struct ath_desc *dd_desc;	/* descriptors  */
 	dma_addr_t dd_desc_paddr;	/* physical addr of dd_desc  */
-	u_int32_t dd_desc_len;		/* size of dd_desc  */
+	u32 dd_desc_len;		/* size of dd_desc  */
 	struct ath_buf *dd_bufptr;	/* associated buffers */
 	dma_addr_t dd_dmacontext;
 };
@@ -402,13 +403,13 @@ enum ATH_RX_TYPE {
 
 /* per frame rx status block */
 struct ath_recv_status {
-	u_int64_t tsf;		/* mac tsf */
+	u64 tsf;		/* mac tsf */
 	int8_t rssi;		/* RSSI (noise floor ajusted) */
 	int8_t rssictl[ATH_MAX_ANTENNA];	/* RSSI (noise floor ajusted) */
 	int8_t rssiextn[ATH_MAX_ANTENNA];	/* RSSI (noise floor ajusted) */
 	int8_t abs_rssi;	/* absolute RSSI */
-	u_int8_t rateieee;	/* data rate received (IEEE rate code) */
-	u_int8_t ratecode;	/* phy rate code */
+	u8 rateieee;	/* data rate received (IEEE rate code) */
+	u8 ratecode;	/* phy rate code */
 	int rateKbps;		/* data rate received (Kbps) */
 	int antenna;		/* rx antenna */
 	int flags;		/* status of associated skb */
@@ -442,8 +443,8 @@ struct ath_arx_tid {
 	int                 baw_tail;   /* tail of block-ack window */
 	int                 seq_reset;  /* need to reset start sequence */
 	int         	    addba_exchangecomplete;
-	u_int16_t           seq_next;   /* next expected sequence */
-	u_int16_t           baw_size;   /* block-ack window size */
+	u16           seq_next;   /* next expected sequence */
+	u16           baw_size;   /* block-ack window size */
 };
 
 /* Per-node receiver aggregate state */
@@ -454,7 +455,7 @@ struct ath_arx {
 int ath_startrecv(struct ath_softc *sc);
 bool ath_stoprecv(struct ath_softc *sc);
 void ath_flushrecv(struct ath_softc *sc);
-u_int32_t ath_calcrxfilter(struct ath_softc *sc);
+u32 ath_calcrxfilter(struct ath_softc *sc);
 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
@@ -471,7 +472,7 @@ int ath_rx_input(struct ath_softc *sc,
 int ath__rx_indicate(struct ath_softc *sc,
 		    struct sk_buff *skb,
 		    struct ath_recv_status *status,
-		    u_int16_t keyix);
+		    u16 keyix);
 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
 		    struct ath_recv_status *status);
 
@@ -520,15 +521,15 @@ enum ATH_SM_PWRSAV{
  * hardware queue).
  */
 struct ath_txq {
-	u_int			axq_qnum;	/* hardware q number */
-	u_int32_t		*axq_link;	/* link ptr in last TX desc */
+	u32			axq_qnum;	/* hardware q number */
+	u32		*axq_link;	/* link ptr in last TX desc */
 	struct list_head	axq_q;		/* transmit queue */
 	spinlock_t		axq_lock;	/* lock on q and link */
 	unsigned long		axq_lockflags;	/* intr state when must cli */
-	u_int			axq_depth;	/* queue depth */
-	u_int8_t                axq_aggr_depth; /* aggregates queued */
-	u_int32_t		axq_totalqueued;/* total ever queued */
-	u_int			axq_intrcnt;	/* count to determine
+	u32			axq_depth;	/* queue depth */
+	u8                axq_aggr_depth; /* aggregates queued */
+	u32		axq_totalqueued;/* total ever queued */
+	u32			axq_intrcnt;	/* count to determine
 						if descriptor should generate
 						int on this txq. */
 	bool			stopped;	/* Is mac80211 queue
@@ -550,9 +551,9 @@ struct ath_atx_tid {
 	struct ath_node         *an;        /* parent node structure */
 	struct ath_atx_ac       *ac;        /* parent access category */
 	struct ath_buf          *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */
-	u_int16_t               seq_start;  /* starting seq of BA window */
-	u_int16_t               seq_next;   /* next seq to be used */
-	u_int16_t               baw_size;   /* BA window size */
+	u16               seq_start;  /* starting seq of BA window */
+	u16               seq_next;   /* next seq to be used */
+	u16               baw_size;   /* BA window size */
 	int                     tidno;      /* TID number */
 	int                     baw_head;   /* first un-acked tx buffer */
 	int                     baw_tail;   /* next unused tx buffer slot */
@@ -560,7 +561,7 @@ struct ath_atx_tid {
 	int                     paused;     /* TID is paused */
 	int                     cleanup_inprogress; /* aggr of this TID is
 						being teared down */
-	u_int32_t               addba_exchangecomplete:1; /* ADDBA state */
+	u32               addba_exchangecomplete:1; /* ADDBA state */
 	int32_t                 addba_exchangeinprogress;
 	int                     addba_exchangeattempts;
 };
@@ -585,21 +586,21 @@ struct ath_tx_control {
 	struct ath_node *an;	/* destination to sent to */
 	int if_id;		/* only valid for cab traffic */
 	int qnum;		/* h/w queue number */
-	u_int ht:1;             /* if it can be transmitted using HT */
-	u_int ps:1;             /* if one or more stations are in PS mode */
-	u_int use_minrate:1;	/* if this frame should transmitted using
+	u32 ht:1;             /* if it can be transmitted using HT */
+	u32 ps:1;             /* if one or more stations are in PS mode */
+	u32 use_minrate:1;	/* if this frame should transmitted using
 				minimum rate */
-	enum hal_pkt_type atype;	/* Atheros packet type */
-	enum hal_key_type keytype;	/* key type */
-	u_int flags;		/* HAL flags */
-	u_int16_t seqno;	/* sequence number */
-	u_int16_t tidno;	/* tid number */
-	u_int16_t txpower;	/* transmit power */
-	u_int16_t frmlen;       /* frame length */
-	u_int32_t keyix;        /* key index */
+	enum ath9k_pkt_type atype;	/* Atheros packet type */
+	enum ath9k_key_type keytype;	/* key type */
+	u32 flags;		/* HAL flags */
+	u16 seqno;	/* sequence number */
+	u16 tidno;	/* tid number */
+	u16 txpower;	/* transmit power */
+	u16 frmlen;       /* frame length */
+	u32 keyix;        /* key index */
 	int min_rate;		/* minimum rate */
 	int mcast_rate;		/* multicast rate */
-	u_int16_t nextfraglen;	/* next fragment length */
+	u16 nextfraglen;	/* next fragment length */
 	/* below is set only by ath_dev */
 	struct ath_softc *dev;	/* device handle */
 	dma_addr_t dmacontext;
@@ -627,7 +628,7 @@ struct ath_tx_stat {
 #define ATH_TX_CHAIN_RSSI_VALID 0x01
 /* if extn chain rssis are valid */
 #define ATH_TX_RSSI_EXTN_VALID  0x02
-	u_int32_t airtime;	/* time on air per final tx rate */
+	u32 airtime;	/* time on air per final tx rate */
 };
 
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
@@ -644,12 +645,12 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 int ath_tx_init(struct ath_softc *sc, int nbufs);
 int ath_tx_cleanup(struct ath_softc *sc);
 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
-int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *q);
+int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_txq_info *q);
 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
 void ath_tx_tasklet(struct ath_softc *sc);
-u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum);
-u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
-void ath_notify_txq_status(struct ath_softc *sc, u_int16_t queue_depth);
+u32 ath_txq_depth(struct ath_softc *sc, int qnum);
+u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
+void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 		     struct ath_xmit_status *tx_status, struct ath_node *an);
 
@@ -733,8 +734,8 @@ struct ath_node {
 	atomic_t		an_refcnt;
 	struct ath_chainmask_sel an_chainmask_sel;
 	struct ath_node_aggr 	an_aggr; /* A-MPDU aggregation state */
-	u_int8_t             	an_smmode; /* SM Power save mode */
-	u_int8_t         	an_flags;
+	u8             	an_smmode; /* SM Power save mode */
+	u8         	an_flags;
 	u8	 		an_addr[ETH_ALEN];
 };
 
@@ -743,9 +744,9 @@ void ath_tx_resume_tid(struct ath_softc *sc,
 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
 	struct ath_node *an, u8 tidno);
 void ath_tx_aggr_teardown(struct ath_softc *sc,
-	struct ath_node *an, u_int8_t tidno);
+	struct ath_node *an, u8 tidno);
 void ath_rx_aggr_teardown(struct ath_softc *sc,
-	struct ath_node *an, u_int8_t tidno);
+	struct ath_node *an, u8 tidno);
 int ath_rx_aggr_start(struct ath_softc *sc,
 		      const u8 *addr,
 		      u16 tid,
@@ -763,11 +764,11 @@ int ath_tx_aggr_stop(struct ath_softc *sc,
 void ath_newassoc(struct ath_softc *sc,
 	struct ath_node *node, int isnew, int isuapsd);
 struct ath_node *ath_node_attach(struct ath_softc *sc,
-	u_int8_t addr[ETH_ALEN], int if_id);
+	u8 addr[ETH_ALEN], int if_id);
 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
-struct ath_node *ath_node_get(struct ath_softc *sc, u_int8_t addr[ETH_ALEN]);
+struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
-struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
+struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
 
 /*******************/
 /* Beacon Handling */
@@ -789,22 +790,22 @@ struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
 
 /* beacon configuration */
 struct ath_beacon_config {
-	u_int16_t beacon_interval;
-	u_int16_t listen_interval;
-	u_int16_t dtim_period;
-	u_int16_t bmiss_timeout;
-	u_int8_t dtim_count;
-	u_int8_t tim_offset;
+	u16 beacon_interval;
+	u16 listen_interval;
+	u16 dtim_period;
+	u16 bmiss_timeout;
+	u8 dtim_count;
+	u8 tim_offset;
 	union {
-		u_int64_t last_tsf;
-		u_int8_t last_tstamp[8];
+		u64 last_tsf;
+		u8 last_tstamp[8];
 	} u; /* last received beacon/probe response timestamp of this BSS. */
 };
 
 /* offsets in a beacon frame for
  * quick acess of beacon content by low-level driver */
 struct ath_beacon_offset {
-	u_int8_t *bo_tim;	/* start of atim/dtim */
+	u8 *bo_tim;	/* start of atim/dtim */
 };
 
 void ath9k_beacon_tasklet(unsigned long data);
@@ -851,15 +852,15 @@ int ath_update_beacon(struct ath_softc *sc,
 
 /* VAP configuration (from protocol layer) */
 struct ath_vap_config {
-	u_int32_t av_fixed_rateset;
-	u_int32_t av_fixed_retryset;
+	u32 av_fixed_rateset;
+	u32 av_fixed_retryset;
 };
 
 /* driver-specific vap state */
 struct ath_vap {
 	struct ieee80211_vif            *av_if_data; /* interface(vap)
 				instance from 802.11 protocal layer */
-	enum hal_opmode                 av_opmode;  /* VAP operational mode */
+	enum ath9k_opmode                 av_opmode;  /* VAP operational mode */
 	struct ath_buf                  *av_bcbuf;  /* beacon buffer */
 	struct ath_beacon_offset        av_boff;    /* dynamic update state */
 	struct ath_tx_control           av_btxctl;  /* tx control information
@@ -869,12 +870,13 @@ struct ath_vap {
 						transmit queue */
 	struct ath_vap_config           av_config;  /* vap configuration
 					parameters from 802.11 protocol layer*/
+	struct ath_rate_node            *rc_node;
 };
 
 int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
-		   enum hal_opmode opmode);
+		   enum ath9k_opmode opmode);
 int ath_vap_detach(struct ath_softc *sc, int if_id);
 int ath_vap_config(struct ath_softc *sc,
 	int if_id, struct ath_vap_config *if_config);
@@ -895,28 +897,28 @@ enum ATH_ANT_DIV_STATE{
 
 struct ath_antdiv {
 	struct ath_softc *antdiv_sc;
-	u_int8_t antdiv_start;
+	u8 antdiv_start;
 	enum ATH_ANT_DIV_STATE antdiv_state;
-	u_int8_t antdiv_num_antcfg;
-	u_int8_t antdiv_curcfg;
-	u_int8_t antdiv_bestcfg;
+	u8 antdiv_num_antcfg;
+	u8 antdiv_curcfg;
+	u8 antdiv_bestcfg;
 	int32_t antdivf_rssitrig;
 	int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
-	u_int64_t antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
-	u_int64_t antdiv_laststatetsf;
-	u_int8_t antdiv_bssid[ETH_ALEN];
+	u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
+	u64 antdiv_laststatetsf;
+	u8 antdiv_bssid[ETH_ALEN];
 };
 
 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
 	struct ath_softc *sc, int32_t rssitrig);
 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
-			    u_int8_t num_antcfg,
-			    const u_int8_t *bssid);
+			    u8 num_antcfg,
+			    const u8 *bssid);
 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
 void ath_slow_ant_div(struct ath_antdiv *antdiv,
 		      struct ieee80211_hdr *wh,
 		      struct ath_rx_status *rx_stats);
-void ath_setdefantenna(void *sc, u_int antenna);
+void ath_setdefantenna(void *sc, u32 antenna);
 
 /********************/
 /* Main driver core */
@@ -947,7 +949,6 @@ void ath_setdefantenna(void *sc, u_int antenna);
  * up to ATH_KEYMAX entries (could dynamically allocate state).
  */
 #define	ATH_KEYMAX	        128        /* max key cache size we handle */
-#define	ATH_KEYBYTES	        (ATH_KEYMAX/NBBY) /* storage space in bytes */
 
 #define RESET_RETRY_TXQ         0x00000001
 #define ATH_IF_ID_ANY   	0xff
@@ -984,12 +985,6 @@ enum PROT_MODE {
 	PROT_M_CTSONLY
 };
 
-enum ieee80211_clist_cmd {
-	CLIST_UPDATE,
-	CLIST_DFS_UPDATE,
-	CLIST_NEW_COUNTRY
-};
-
 enum RATE_TYPE {
 	NORMAL_RATE = 0,
 	HALF_RATE,
@@ -997,10 +992,10 @@ enum RATE_TYPE {
 };
 
 struct ath_ht_info {
-	enum hal_ht_macmode tx_chan_width;
-	u_int16_t maxampdu;
-	u_int8_t mpdudensity;
-	u_int8_t ext_chan_offset;
+	enum ath9k_ht_macmode tx_chan_width;
+	u16 maxampdu;
+	u8 mpdudensity;
+	u8 ext_chan_offset;
 };
 
 struct ath_softc {
@@ -1014,52 +1009,52 @@ struct ath_softc {
 	int                     sc_debug;   /* Debug masks */
 	struct ath_hal          *sc_ah;     /* HAL Instance */
 	struct ath_rate_softc    *sc_rc;     /* tx rate control support */
-	u_int32_t               sc_intrstatus; /* HAL_STATUS */
-	enum hal_opmode         sc_opmode;  /* current operating mode */
+	u32               sc_intrstatus; /* HAL_STATUS */
+	enum ath9k_opmode         sc_opmode;  /* current operating mode */
 
 	/* Properties, Config */
-	u_int8_t                sc_invalid;	/* being detached */
-	u_int8_t                sc_beacons;	/* beacons running */
-	u_int8_t                sc_scanning;	/* scanning active */
-	u_int8_t                sc_txaggr;	/* enable 11n tx aggregation */
-	u_int8_t                sc_rxaggr;	/* enable 11n rx aggregation */
-	u_int8_t                sc_update_chainmask;	/* change chain mask */
-	u_int8_t                sc_full_reset;		/* force full reset */
+	u8                sc_invalid;	/* being detached */
+	u8                sc_beacons;	/* beacons running */
+	u8                sc_scanning;	/* scanning active */
+	u8                sc_txaggr;	/* enable 11n tx aggregation */
+	u8                sc_rxaggr;	/* enable 11n rx aggregation */
+	u8                sc_update_chainmask;	/* change chain mask */
+	u8                sc_full_reset;		/* force full reset */
 	enum wireless_mode      sc_curmode;     /* current phy mode */
-	u_int16_t               sc_curtxpow;    /* current tx power limit */
-	u_int16_t               sc_curaid;      /* current association id */
-	u_int8_t                sc_curbssid[ETH_ALEN];
-	u_int8_t                sc_myaddr[ETH_ALEN];
+	u16               sc_curtxpow;    /* current tx power limit */
+	u16               sc_curaid;      /* current association id */
+	u8                sc_curbssid[ETH_ALEN];
+	u8                sc_myaddr[ETH_ALEN];
 	enum PROT_MODE          sc_protmode;    /* protection mode */
-	u_int8_t                sc_mcastantenna;/* Multicast antenna number */
-	u_int8_t                sc_txantenna;   /* data tx antenna
+	u8                sc_mcastantenna;/* Multicast antenna number */
+	u8                sc_txantenna;   /* data tx antenna
 						(fixed or auto) */
-	u_int8_t                sc_nbcnvaps;    /* # of vaps sending beacons */
-	u_int16_t               sc_nvaps;       /* # of active virtual ap's */
+	u8                sc_nbcnvaps;    /* # of vaps sending beacons */
+	u16               sc_nvaps;       /* # of active virtual ap's */
 	struct ath_vap          *sc_vaps[ATH_BCBUF]; /* interface id
 						to avp map */
-	enum hal_int            sc_imask;       /* interrupt mask copy */
-	u_int8_t                sc_bssidmask[ETH_ALEN];
-	u_int8_t                sc_defant;      /* current default antenna */
-	u_int8_t                sc_rxotherant;  /* rx's on non-default antenna*/
-	u_int16_t               sc_cachelsz;    /* cache line size */
+	enum ath9k_int            sc_imask;       /* interrupt mask copy */
+	u8                sc_bssidmask[ETH_ALEN];
+	u8                sc_defant;      /* current default antenna */
+	u8                sc_rxotherant;  /* rx's on non-default antenna*/
+	u16               sc_cachelsz;    /* cache line size */
 	int                     sc_slotupdate;  /* slot to next advance fsm */
 	int                     sc_slottime;    /* slot time */
-	u_int8_t                sc_noreset;
+	u8                sc_noreset;
 	int                     sc_bslot[ATH_BCBUF];/* beacon xmit slots */
-	struct hal_node_stats   sc_halstats;    /* station-mode rssi stats */
+	struct ath9k_node_stats   sc_halstats;    /* station-mode rssi stats */
 	struct list_head        node_list;
 	struct ath_ht_info      sc_ht_info;
 	int16_t                 sc_noise_floor; /* signal noise floor in dBm */
-	enum hal_ht_extprotspacing   sc_ht_extprotspacing;
-	u_int8_t                sc_tx_chainmask;
-	u_int8_t                sc_rx_chainmask;
-	u_int8_t                sc_rxchaindetect_ref;
-	u_int8_t                sc_rxchaindetect_thresh5GHz;
-	u_int8_t                sc_rxchaindetect_thresh2GHz;
-	u_int8_t                sc_rxchaindetect_delta5GHz;
-	u_int8_t                sc_rxchaindetect_delta2GHz;
-	u_int32_t               sc_rtsaggrlimit; /* Chipset specific
+	enum ath9k_ht_extprotspacing   sc_ht_extprotspacing;
+	u8                sc_tx_chainmask;
+	u8                sc_rx_chainmask;
+	u8                sc_rxchaindetect_ref;
+	u8                sc_rxchaindetect_thresh5GHz;
+	u8                sc_rxchaindetect_thresh2GHz;
+	u8                sc_rxchaindetect_delta5GHz;
+	u8                sc_rxchaindetect_delta2GHz;
+	u32               sc_rtsaggrlimit; /* Chipset specific
 						aggr limit */
 	u32                     sc_flags;
 #ifdef CONFIG_SLOW_ANT_DIV
@@ -1073,56 +1068,56 @@ struct ath_softc {
 	} sc_updateslot;            /* slot time update fsm */
 
 	/* Crypto */
-	u_int                   sc_keymax;      /* size of key cache */
-	DECLARE_BITMAP		(sc_keymap, ATH_KEYBYTES);/* key use bit map */
-	u_int8_t		sc_splitmic;	/* split TKIP MIC keys */
+	u32                   sc_keymax;      /* size of key cache */
+	DECLARE_BITMAP		(sc_keymap, ATH_KEYMAX);/* key use bit map */
+	u8		sc_splitmic;	/* split TKIP MIC keys */
 	int                     sc_keytype;     /* type of the key being used */
 
 	/* RX */
 	struct list_head	sc_rxbuf;       /* receive buffer */
 	struct ath_descdma      sc_rxdma;       /* RX descriptors */
 	int                     sc_rxbufsize;   /* rx size based on mtu */
-	u_int32_t               *sc_rxlink;     /* link ptr in last RX desc */
-	u_int32_t               sc_rxflush;     /* rx flush in progress */
-	u_int64_t               sc_lastrx;      /* tsf of last rx'd frame */
+	u32               *sc_rxlink;     /* link ptr in last RX desc */
+	u32               sc_rxflush;     /* rx flush in progress */
+	u64               sc_lastrx;      /* tsf of last rx'd frame */
 
 	/* TX */
 	struct list_head	sc_txbuf;       /* transmit buffer */
-	struct ath_txq          sc_txq[HAL_NUM_TX_QUEUES];
+	struct ath_txq          sc_txq[ATH9K_NUM_TX_QUEUES];
 	struct ath_descdma      sc_txdma;       /* TX descriptors */
-	u_int                   sc_txqsetup;    /* h/w queues setup */
-	u_int                   sc_txintrperiod;/* tx interrupt batching */
-	int                     sc_haltype2q[HAL_WME_AC_VO+1]; /* HAL WME
+	u32                   sc_txqsetup;    /* h/w queues setup */
+	u32                   sc_txintrperiod;/* tx interrupt batching */
+	int                     sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME
 							AC -> h/w qnum */
-	u_int32_t               sc_ant_tx[8];   /* recent tx frames/antenna */
+	u32               sc_ant_tx[8];   /* recent tx frames/antenna */
 
 	/* Beacon */
-	struct hal_txq_info     sc_beacon_qi;   /* adhoc only: beacon
+	struct ath9k_txq_info     sc_beacon_qi;   /* adhoc only: beacon
 						queue parameters */
 	struct ath_descdma      sc_bdma;        /* beacon descriptors */
 	struct ath_txq          *sc_cabq;       /* tx q for cab frames */
 	struct list_head	sc_bbuf;	/* beacon buffers */
-	u_int                   sc_bhalq;       /* HAL q for outgoing beacons */
-	u_int                   sc_bmisscount;  /* missed beacon transmits */
-	u_int32_t               ast_be_xmit; /* beacons transmitted */
+	u32                   sc_bhalq;       /* HAL q for outgoing beacons */
+	u32                   sc_bmisscount;  /* missed beacon transmits */
+	u32               ast_be_xmit; /* beacons transmitted */
 
 	/* Rate */
 	struct ieee80211_rate          rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
-	const struct hal_rate_table    *sc_rates[WIRELESS_MODE_MAX];
-	const struct hal_rate_table    *sc_currates;   /* current rate table */
-	u_int8_t                       sc_rixmap[256]; /* IEEE to h/w
+	const struct ath9k_rate_table    *sc_rates[WIRELESS_MODE_MAX];
+	const struct ath9k_rate_table    *sc_currates; /* current rate table */
+	u8                       sc_rixmap[256]; /* IEEE to h/w
 						rate table ix */
-	u_int8_t                       sc_minrateix;   /* min h/w rate index */
-	u_int8_t                       sc_protrix; /* protection rate index */
+	u8                       sc_minrateix;   /* min h/w rate index */
+	u8                       sc_protrix; /* protection rate index */
 	struct {
-		u_int32_t rateKbps;      /* transfer rate in kbs */
-		u_int8_t ieeerate;       /* IEEE rate */
+		u32 rateKbps;      /* transfer rate in kbs */
+		u8 ieeerate;       /* IEEE rate */
 	} sc_hwmap[256];         /* h/w rate ix mappings */
 
 	/* Channel, Band */
 	struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
 	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
-	struct hal_channel              sc_curchan; /* current h/w channel */
+	struct ath9k_channel            sc_curchan; /* current h/w channel */
 
 	/* Locks */
 	spinlock_t              sc_rxflushlock; /* lock of RX flush */
@@ -1132,46 +1127,39 @@ struct ath_softc {
 	spinlock_t              node_lock;
 };
 
-int ath_init(u_int16_t devid, struct ath_softc *sc);
+int ath_init(u16 devid, struct ath_softc *sc);
 void ath_deinit(struct ath_softc *sc);
-int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
+int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
 int ath_suspend(struct ath_softc *sc);
 irqreturn_t ath_isr(int irq, void *dev);
 int ath_reset(struct ath_softc *sc);
 void ath_scan_start(struct ath_softc *sc);
 void ath_scan_end(struct ath_softc *sc);
-int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan);
-void ath_setup_channel_list(struct ath_softc *sc,
-			    enum ieee80211_clist_cmd cmd,
-			    const struct hal_channel *chans,
-			    int nchan,
-			    const u_int8_t *regclassids,
-			    u_int nregclass,
-			    int countrycode);
+int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
 void ath_setup_rate(struct ath_softc *sc,
 		    enum wireless_mode wMode,
 		    enum RATE_TYPE type,
-		    const struct hal_rate_table *rt);
+		    const struct ath9k_rate_table *rt);
 
 /*********************/
 /* Utility Functions */
 /*********************/
 
-void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
+void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
 int ath_keyset(struct ath_softc *sc,
-	       u_int16_t keyix,
-	       struct hal_keyval *hk,
-	       const u_int8_t mac[ETH_ALEN]);
+	       u16 keyix,
+	       struct ath9k_keyval *hk,
+	       const u8 mac[ETH_ALEN]);
 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
-int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
+int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 void ath_setslottime(struct ath_softc *sc);
 void ath_update_txpow(struct ath_softc *sc);
 int ath_cabq_update(struct ath_softc *);
 void ath_get_currentCountry(struct ath_softc *sc,
-	struct hal_country_entry *ctry);
-u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp);
+	struct ath9k_country_entry *ctry);
+u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
 void ath_internal_reset(struct ath_softc *sc);
-u_int32_t ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
+u32 ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
 dma_addr_t ath_skb_map_single(struct ath_softc *sc,
 			      struct sk_buff *skb,
 			      int direction,
@@ -1180,7 +1168,7 @@ void ath_skb_unmap_single(struct ath_softc *sc,
 			  struct sk_buff *skb,
 			  int direction,
 			  dma_addr_t *pa);
-void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
-enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
+void ath_mcast_merge(struct ath_softc *sc, u32 mfilt[2]);
+enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
 
 #endif /* CORE_H */
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/hw.c b/package/ath9k/src/drivers/net/wireless/ath9k/hw.c
index a16dbfbd4..78c049599 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/hw.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/hw.c
@@ -23,15 +23,15 @@
 #include "initvals.h"
 
 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
-static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains);
+static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
-					   u_int8_t numChains);
+					   u8 numChains);
 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
-					 u_int8_t numChains);
+					 u8 numChains);
 
-static const u_int8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
+static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
 
 static const struct hal_percal_data iq_cal_multi_sample = {
@@ -107,7 +107,7 @@ static const struct ath_hal ar5416hal = {
 	},
 };
 
-static struct hal_rate_table ar5416_11a_table = {
+static struct ath9k_rate_table ar5416_11a_table = {
 	8,
 	{0},
 	{
@@ -122,7 +122,7 @@ static struct hal_rate_table ar5416_11a_table = {
 	},
 };
 
-static struct hal_rate_table ar5416_11b_table = {
+static struct ath9k_rate_table ar5416_11b_table = {
 	4,
 	{0},
 	{
@@ -133,7 +133,7 @@ static struct hal_rate_table ar5416_11b_table = {
 	},
 };
 
-static struct hal_rate_table ar5416_11g_table = {
+static struct ath9k_rate_table ar5416_11g_table = {
 	12,
 	{0},
 	{
@@ -153,7 +153,7 @@ static struct hal_rate_table ar5416_11g_table = {
 	},
 };
 
-static struct hal_rate_table ar5416_11ng_table = {
+static struct ath9k_rate_table ar5416_11ng_table = {
 	28,
 	{0},
 	{
@@ -189,7 +189,7 @@ static struct hal_rate_table ar5416_11ng_table = {
 	},
 };
 
-static struct hal_rate_table ar5416_11na_table = {
+static struct ath9k_rate_table ar5416_11na_table = {
 	24,
 	{0},
 	{
@@ -221,7 +221,7 @@ static struct hal_rate_table ar5416_11na_table = {
 };
 
 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
-				       const struct hal_channel *chan)
+				       const struct ath9k_channel *chan)
 {
 	if (IS_CHAN_CCK(chan))
 		return WIRELESS_MODE_11b;
@@ -231,9 +231,9 @@ static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
 }
 
 static bool ath9k_hw_wait(struct ath_hal *ah,
-			  u_int reg,
-			  u_int32_t mask,
-			  u_int32_t val)
+			  u32 reg,
+			  u32 mask,
+			  u32 val)
 {
 	int i;
 
@@ -249,8 +249,8 @@ static bool ath9k_hw_wait(struct ath_hal *ah,
 	return false;
 }
 
-static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
-				 u_int16_t *data)
+static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
+				 u16 *data)
 {
 	(void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 
@@ -267,7 +267,7 @@ static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
 	return true;
 }
 
-static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
+static int ath9k_hw_flash_map(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -276,14 +276,14 @@ static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
 	if (!ahp->ah_cal_mem) {
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: cannot remap eeprom region \n", __func__);
-		return HAL_EIO;
+		return -EIO;
 	}
 
-	return HAL_OK;
+	return 0;
 }
 
-static bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
-				u_int16_t *data)
+static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
+				u16 *data)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -293,7 +293,7 @@ static bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
 
 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 {
-	u_int32_t val;
+	u32 val;
 
 	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 
@@ -318,9 +318,9 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah)
 	}
 }
 
-u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n)
+u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 {
-	u_int32_t retval;
+	u32 retval;
 	int i;
 
 	for (i = 0, retval = 0; i < n; i++) {
@@ -371,7 +371,7 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah)
 }
 
 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
-					 struct hal_channel *chan)
+					 struct ath9k_channel *chan)
 {
 	if (!AR_SREV_5416_V20_OR_LATER(ah)
 	    || AR_SREV_9280_10_OR_LATER(ah))
@@ -381,9 +381,9 @@ static inline void ath9k_hw_override_ini(struct ath_hal *ah,
 }
 
 static inline void ath9k_hw_init_bb(struct ath_hal *ah,
-				    struct hal_channel *chan)
+				    struct ath9k_channel *chan)
 {
-	u_int32_t synthDelay;
+	u32 synthDelay;
 
 	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 	if (IS_CHAN_CCK(chan))
@@ -397,7 +397,7 @@ static inline void ath9k_hw_init_bb(struct ath_hal *ah,
 }
 
 static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
-						 enum hal_opmode opmode)
+						 enum ath9k_opmode opmode)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -414,7 +414,7 @@ static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
 
 	ahp->ah_maskReg |= AR_IMR_TXOK;
 
-	if (opmode == HAL_M_HOSTAP)
+	if (opmode == ATH9K_M_HOSTAP)
 		ahp->ah_maskReg |= AR_IMR_MIB;
 
 	REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
@@ -445,12 +445,12 @@ static inline void ath9k_hw_init_qos(struct ath_hal *ah)
 }
 
 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
-				      u_int reg,
-				      u_int32_t mask,
-				      u_int32_t shift,
-				      u_int32_t val)
+				      u32 reg,
+				      u32 mask,
+				      u32 shift,
+				      u32 val)
 {
-	u_int32_t regVal;
+	u32 regVal;
 
 	regVal = REG_READ(ah, reg) & ~mask;
 	regVal |= (val << shift) & mask;
@@ -463,14 +463,14 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
 	return;
 }
 
-static u_int8_t ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
+static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
 					    enum hal_freq_band freq_band)
 {
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 	struct modal_eep_header *pModal =
 		&(eep->modalHeader[HAL_FREQ_BAND_2GHZ == freq_band]);
 	struct base_eep_header *pBase = &eep->baseEepHeader;
-	u_int8_t num_ant_config;
+	u8 num_ant_config;
 
 	num_ant_config = 1;
 
@@ -481,11 +481,11 @@ static u_int8_t ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
 	return num_ant_config;
 }
 
-static enum hal_status
+static int
 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
-				struct hal_channel_internal *chan,
-				u_int8_t index,
-				u_int16_t *config)
+				struct ath9k_channel *chan,
+				u8 index,
+				u16 *config)
 {
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
 	struct modal_eep_header *pModal =
@@ -495,13 +495,13 @@ ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 	switch (index) {
 	case 0:
 		*config = pModal->antCtrlCommon & 0xFFFF;
-		return HAL_OK;
+		return 0;
 	case 1:
 		if (pBase->version >= 0x0E0D) {
 			if (pModal->useAnt1) {
 				*config =
 				((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
-				return HAL_OK;
+				return 0;
 			}
 		}
 		break;
@@ -509,12 +509,12 @@ ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 		break;
 	}
 
-	return HAL_EINVAL;
+	return -EINVAL;
 }
 
 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
-				       u_int off,
-				       u_int16_t *data)
+				       u32 off,
+				       u16 *data)
 {
 	if (ath9k_hw_use_flash(ah))
 		return ath9k_hw_flash_read(ah, off, data);
@@ -526,7 +526,7 @@ static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
-	u_int16_t *eep_data;
+	u16 *eep_data;
 	int addr, ar5416_eep_start_loc = 0;
 
 	if (!ath9k_hw_use_flash(ah)) {
@@ -537,9 +537,9 @@ static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 	if (AR_SREV_9100(ah))
 		ar5416_eep_start_loc = 256;
 
-	eep_data = (u_int16_t *) eep;
+	eep_data = (u16 *) eep;
 	for (addr = 0;
-	     addr < sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
+	     addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
 	     addr++) {
 		if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 					 eep_data)) {
@@ -556,14 +556,14 @@ static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 /* XXX: Clean me up, make me more legible */
 static bool
 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
-				 struct hal_channel_internal *chan)
+				 struct ath9k_channel *chan)
 {
 	struct modal_eep_header *pModal;
 	int i, regChainOffset;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
-	u_int8_t txRxAttenLocal;
-	u_int16_t ant_config;
+	u8 txRxAttenLocal;
+	u16 ant_config;
 
 	pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 
@@ -789,10 +789,10 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 	return true;
 }
 
-static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
+static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)
 {
-	u_int32_t sum = 0, el;
-	u_int16_t *eepdata;
+	u32 sum = 0, el;
+	u16 *eepdata;
 	int i;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	bool need_swap = false;
@@ -800,7 +800,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 		(struct ar5416_eeprom *) &ahp->ah_eeprom;
 
 	if (!ath9k_hw_use_flash(ah)) {
-		u_int16_t magic, magic2;
+		u16 magic, magic2;
 		int addr;
 
 		if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
@@ -817,13 +817,13 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 
 			if (magic2 == AR5416_EEPROM_MAGIC) {
 				need_swap = true;
-				eepdata = (u_int16_t *) (&ahp->ah_eeprom);
+				eepdata = (u16 *) (&ahp->ah_eeprom);
 
 				for (addr = 0;
 				     addr <
 					     sizeof(struct ar5416_eeprom) /
-					     sizeof(u_int16_t); addr++) {
-					u_int16_t temp;
+					     sizeof(u16); addr++) {
+					u16 temp;
 
 					temp = swab16(*eepdata);
 					*eepdata = temp;
@@ -840,7 +840,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 				DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 					 "Invalid EEPROM Magic. "
 					"endianness missmatch.\n");
-				return HAL_EEBADSUM;
+				return -EINVAL;
 			}
 		}
 	}
@@ -853,18 +853,18 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 		el = ahp->ah_eeprom.baseEepHeader.length;
 
 	if (el > sizeof(struct ar5416_eeprom))
-		el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
+		el = sizeof(struct ar5416_eeprom) / sizeof(u16);
 	else
-		el = el / sizeof(u_int16_t);
+		el = el / sizeof(u16);
 
-	eepdata = (u_int16_t *) (&ahp->ah_eeprom);
+	eepdata = (u16 *) (&ahp->ah_eeprom);
 
 	for (i = 0; i < el; i++)
 		sum ^= *eepdata++;
 
 	if (need_swap) {
-		u_int32_t integer, j;
-		u_int16_t word;
+		u32 integer, j;
+		u16 word;
 
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "EEPROM Endianness is not native.. Changing \n");
@@ -916,25 +916,25 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 			 sum, ar5416_get_eep_ver(ahp));
-		return HAL_EEBADSUM;
+		return -EINVAL;
 	}
 
-	return HAL_OK;
+	return 0;
 }
 
 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 {
-	u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
-	u_int32_t regHold[2];
-	u_int32_t patternData[4] = { 0x55555555,
+	u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
+	u32 regHold[2];
+	u32 patternData[4] = { 0x55555555,
 				     0xaaaaaaaa,
 				     0x66666666,
 				     0x99999999 };
 	int i, j;
 
 	for (i = 0; i < 2; i++) {
-		u_int32_t addr = regAddr[i];
-		u_int32_t wrData, rdData;
+		u32 addr = regAddr[i];
+		u32 wrData, rdData;
 
 		regHold[i] = REG_READ(ah, addr);
 		for (j = 0; j < 0x100; j++) {
@@ -967,27 +967,27 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
 	return true;
 }
 
-u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
+u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
 {
-	u_int32_t bits = REG_READ(ah, AR_RX_FILTER);
-	u_int32_t phybits = REG_READ(ah, AR_PHY_ERR);
+	u32 bits = REG_READ(ah, AR_RX_FILTER);
+	u32 phybits = REG_READ(ah, AR_PHY_ERR);
 
 	if (phybits & AR_PHY_ERR_RADAR)
-		bits |= HAL_RX_FILTER_PHYRADAR;
+		bits |= ATH9K_RX_FILTER_PHYRADAR;
 	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
-		bits |= HAL_RX_FILTER_PHYERR;
+		bits |= ATH9K_RX_FILTER_PHYERR;
 	return bits;
 }
 
-void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
+void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
 {
-	u_int32_t phybits;
+	u32 phybits;
 
 	REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
 	phybits = 0;
-	if (bits & HAL_RX_FILTER_PHYRADAR)
+	if (bits & ATH9K_RX_FILTER_PHYRADAR)
 		phybits |= AR_PHY_ERR_RADAR;
-	if (bits & HAL_RX_FILTER_PHYERR)
+	if (bits & ATH9K_RX_FILTER_PHYERR)
 		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
 	REG_WRITE(ah, AR_PHY_ERR, phybits);
 
@@ -1001,12 +1001,12 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
 
 bool ath9k_hw_setcapability(struct ath_hal *ah,
 			    enum hal_capability_type type,
-			    u_int32_t capability,
-			    u_int32_t setting,
-			    enum hal_status *status)
+			    u32 capability,
+			    u32 setting,
+			    int *status)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t v;
+	u32 v;
 
 	switch (type) {
 	case HAL_CAP_TKIP_MIC:
@@ -1044,9 +1044,9 @@ bool ath9k_hw_setcapability(struct ath_hal *ah,
 
 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
 {
-	u_int32_t val[ATH9K_NUM_DMA_DEBUG_REGS];
+	u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
 	int qcuOffset = 0, dcuOffset = 0;
-	u_int32_t *qcuBase = &val[0], *dcuBase = &val[4];
+	u32 *qcuBase = &val[0], *dcuBase = &val[4];
 	int i;
 
 	REG_WRITE(ah, AR_MACMISC,
@@ -1059,7 +1059,7 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
 		if (i % 4 == 0)
 			DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
 
-		val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
+		val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
 		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
 	}
 
@@ -1114,18 +1114,18 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
 		"AR_CR 0x%x \n", REG_READ(ah, AR_CR));
 }
 
-u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
-					u_int32_t *rxc_pcnt,
-					u_int32_t *rxf_pcnt,
-					u_int32_t *txf_pcnt)
+u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
+					u32 *rxc_pcnt,
+					u32 *rxf_pcnt,
+					u32 *txf_pcnt)
 {
-	static u_int32_t cycles, rx_clear, rx_frame, tx_frame;
-	u_int32_t good = 1;
+	static u32 cycles, rx_clear, rx_frame, tx_frame;
+	u32 good = 1;
 
-	u_int32_t rc = REG_READ(ah, AR_RCCNT);
-	u_int32_t rf = REG_READ(ah, AR_RFCNT);
-	u_int32_t tf = REG_READ(ah, AR_TFCNT);
-	u_int32_t cc = REG_READ(ah, AR_CCCNT);
+	u32 rc = REG_READ(ah, AR_RCCNT);
+	u32 rf = REG_READ(ah, AR_RFCNT);
+	u32 tf = REG_READ(ah, AR_TFCNT);
+	u32 cc = REG_READ(ah, AR_CCCNT);
 
 	if (cycles == 0 || cycles > cc) {
 		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
@@ -1133,10 +1133,10 @@ u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
 			 __func__);
 		good = 0;
 	} else {
-		u_int32_t cc_d = cc - cycles;
-		u_int32_t rc_d = rc - rx_clear;
-		u_int32_t rf_d = rf - rx_frame;
-		u_int32_t tf_d = tf - tx_frame;
+		u32 cc_d = cc - cycles;
+		u32 rc_d = rc - rx_clear;
+		u32 rf_d = rf - rx_frame;
+		u32 tf_d = tf - tx_frame;
 
 		if (cc_d != 0) {
 			*rxc_pcnt = rc_d * 100 / cc_d;
@@ -1155,11 +1155,11 @@ u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
 	return good;
 }
 
-void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode)
+void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
 {
-	u_int32_t macmode;
+	u32 macmode;
 
-	if (mode == HAL_HT_MACMODE_2040 &&
+	if (mode == ATH9K_HT_MACMODE_2040 &&
 	    !ah->ah_config.ath_hal_cwmIgnoreExtCCA)
 		macmode = AR_2040_JOINED_RX_CLEAR;
 	else
@@ -1174,12 +1174,12 @@ static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
 }
 
 
-static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
+static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 					      struct ath_softc *sc,
 					      void __iomem *mem,
-					      enum hal_status *status)
+					      int *status)
 {
-	static const u_int8_t defbssidmask[ETH_ALEN] =
+	static const u8 defbssidmask[ETH_ALEN] =
 		{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 	struct ath_hal_5416 *ahp;
 	struct ath_hal *ah;
@@ -1189,7 +1189,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
 		DPRINTF(sc, ATH_DBG_FATAL,
 			 "%s: cannot allocate memory for state block\n",
 			 __func__);
-		*status = HAL_ENOMEM;
+		*status = -ENOMEM;
 		return NULL;
 	}
 
@@ -1210,7 +1210,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
 		ah->ah_flags = AH_USE_EEPROM;
 
 	ah->ah_powerLimit = MAX_RATE_POWER;
-	ah->ah_tpScale = HAL_TP_SCALE_MAX;
+	ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 
 	ahp->ah_atimWindow = 0;
 	ahp->ah_diversityControl = ah->ah_config.ath_hal_diversityControl;
@@ -1220,10 +1220,10 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
 	ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 	ahp->ah_beaconInterval = 100;
 	ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
-	ahp->ah_slottime = (u_int) -1;
-	ahp->ah_acktimeout = (u_int) -1;
-	ahp->ah_ctstimeout = (u_int) -1;
-	ahp->ah_globaltxtimeout = (u_int) -1;
+	ahp->ah_slottime = (u32) -1;
+	ahp->ah_acktimeout = (u32) -1;
+	ahp->ah_ctstimeout = (u32) -1;
+	ahp->ah_globaltxtimeout = (u32) -1;
 	memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 
 	ahp->ah_gBeaconRate = 0;
@@ -1231,22 +1231,22 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
 	return ahp;
 }
 
-static enum hal_status ath9k_hw_eeprom_attach(struct ath_hal *ah)
+static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
 {
-	enum hal_status status;
+	int status;
 
 	if (ath9k_hw_use_flash(ah))
 		ath9k_hw_flash_map(ah);
 
 	if (!ath9k_hw_fill_eeprom(ah))
-		return HAL_EIO;
+		return -EIO;
 
 	status = ath9k_hw_check_eeprom(ah);
 
 	return status;
 }
 
-u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
+u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
 			      enum eeprom_param param)
 {
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
@@ -1295,7 +1295,7 @@ u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
 
 static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
 {
-	u_int32_t val;
+	u32 val;
 	int i;
 
 	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
@@ -1306,11 +1306,11 @@ static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
 	return ath9k_hw_reverse_bits(val, 8);
 }
 
-static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
+static inline int ath9k_hw_init_macaddr(struct ath_hal *ah)
 {
-	u_int32_t sum;
+	u32 sum;
 	int i;
-	u_int16_t eeval;
+	u16 eeval;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	DECLARE_MAC_BUF(mac);
 
@@ -1325,15 +1325,15 @@ static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: mac address read failed: %s\n", __func__,
 			 print_mac(mac, ahp->ah_macaddr));
-		return HAL_EEBADMAC;
+		return -EADDRNOTAVAIL;
 	}
 
-	return HAL_OK;
+	return 0;
 }
 
-static inline int16_t ath9k_hw_interpolate(u_int16_t target,
-					   u_int16_t srcLeft,
-					   u_int16_t srcRight,
+static inline int16_t ath9k_hw_interpolate(u16 target,
+					   u16 srcLeft,
+					   u16 srcRight,
 					   int16_t targetLeft,
 					   int16_t targetRight)
 {
@@ -1349,24 +1349,24 @@ static inline int16_t ath9k_hw_interpolate(u_int16_t target,
 	return rv;
 }
 
-static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
+static inline u16 ath9k_hw_fbin2freq(u8 fbin,
 					   bool is2GHz)
 {
 
 	if (fbin == AR5416_BCHAN_UNUSED)
 		return fbin;
 
-	return (u_int16_t) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
+	return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
 }
 
-static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
-					       u_int16_t i,
+static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
+					       u16 i,
 					       bool is2GHz)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416_eeprom *eep =
 		(struct ar5416_eeprom *) &ahp->ah_eeprom;
-	u_int16_t spur_val = AR_NO_SPUR;
+	u16 spur_val = AR_NO_SPUR;
 
 	DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 		 "Getting spur idx %d is2Ghz. %d val %x\n",
@@ -1388,10 +1388,10 @@ static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
 	return spur_val;
 }
 
-static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
+static inline int ath9k_hw_rfattach(struct ath_hal *ah)
 {
 	bool rfStatus = false;
-	enum hal_status ecode = HAL_OK;
+	int ecode = 0;
 
 	rfStatus = ath9k_hw_init_rf(ah, &ecode);
 	if (!rfStatus) {
@@ -1401,12 +1401,12 @@ static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
 		return ecode;
 	}
 
-	return HAL_OK;
+	return 0;
 }
 
-static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
+static int ath9k_hw_rf_claim(struct ath_hal *ah)
 {
-	u_int32_t val;
+	u32 val;
 
 	REG_WRITE(ah, AR_PHY(0), 0x00000007);
 
@@ -1425,18 +1425,18 @@ static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
 			 "%s: 5G Radio Chip Rev 0x%02X is not "
 			"supported by this driver\n",
 			 __func__, ah->ah_analog5GhzRev);
-		return HAL_ENOTSUPP;
+		return -EOPNOTSUPP;
 	}
 
 	ah->ah_analog5GhzRev = val;
 
-	return HAL_OK;
+	return 0;
 }
 
 static inline void ath9k_hw_init_pll(struct ath_hal *ah,
-				     struct hal_channel *chan)
+				     struct ath9k_channel *chan)
 {
-	u_int32_t pll;
+	u32 pll;
 
 	if (AR_SREV_9100(ah)) {
 		if (chan && IS_CHAN_5GHZ(chan))
@@ -1494,17 +1494,17 @@ static inline void ath9k_hw_init_pll(struct ath_hal *ah,
 				pll |= SM(0xb, AR_RTC_PLL_DIV);
 		}
 	}
-	REG_WRITE(ah, (u_int16_t) (AR_RTC_PLL_CONTROL), pll);
+	REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
 
 	udelay(RTC_PLL_SETTLE_DELAY);
 
 	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 }
 
-static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
-			      enum hal_ht_macmode macmode)
+static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
+			      enum ath9k_ht_macmode macmode)
 {
-	u_int32_t phymode;
+	u32 phymode;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
@@ -1513,10 +1513,11 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
 	if (IS_CHAN_HT40(chan)) {
 		phymode |= AR_PHY_FC_DYN2040_EN;
 
-		if (chan->channelFlags & CHANNEL_HT40PLUS)
+		if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
+		    (chan->chanmode == CHANNEL_G_HT40PLUS))
 			phymode |= AR_PHY_FC_DYN2040_PRI_CH;
 
-		if (ahp->ah_extprotspacing == HAL_HT_EXTPROTSPACING_25)
+		if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
 			phymode |= AR_PHY_FC_DYN2040_EXT_CH;
 	}
 	REG_WRITE(ah, AR_PHY_TURBO, phymode);
@@ -1529,32 +1530,32 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
 
 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
 {
-	u_int32_t val;
+	u32 val;
 
 	val = REG_READ(ah, AR_STA_ID1);
 	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 	switch (opmode) {
-	case HAL_M_HOSTAP:
+	case ATH9K_M_HOSTAP:
 		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 			  | AR_STA_ID1_KSRCH_MODE);
 		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 		break;
-	case HAL_M_IBSS:
+	case ATH9K_M_IBSS:
 		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 			  | AR_STA_ID1_KSRCH_MODE);
 		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 		break;
-	case HAL_M_STA:
-	case HAL_M_MONITOR:
+	case ATH9K_M_STA:
+	case ATH9K_M_MONITOR:
 		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 		break;
 	}
 }
 
 static inline void
-ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
+ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
 {
-	u_int32_t rfMode = 0;
+	u32 rfMode = 0;
 
 	if (chan == NULL)
 		return;
@@ -1574,8 +1575,8 @@ ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
 
 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 {
-	u_int32_t rst_flags;
-	u_int32_t tmpReg;
+	u32 rst_flags;
+	u32 tmpReg;
 
 	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 		  AR_RTC_FORCE_WAKE_ON_INT);
@@ -1595,15 +1596,15 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 		}
 
 		rst_flags = AR_RTC_RC_MAC_WARM;
-		if (type == HAL_RESET_COLD)
+		if (type == ATH9K_RESET_COLD)
 			rst_flags |= AR_RTC_RC_MAC_COLD;
 	}
 
-	REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), rst_flags);
+	REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
 	udelay(50);
 
-	REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
-	if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
+	REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
+	if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			"%s: RTC stuck in MAC reset\n",
 			__func__);
@@ -1626,8 +1627,8 @@ static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
 	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 		  AR_RTC_FORCE_WAKE_ON_INT);
 
-	REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 0);
-	REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 1);
+	REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
+	REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
 
 	if (!ath9k_hw_wait(ah,
 			   AR_RTC_STATUS,
@@ -1640,21 +1641,21 @@ static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
 
 	ath9k_hw_read_revisions(ah);
 
-	return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
+	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
 }
 
 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
-				   u_int32_t type)
+				   u32 type)
 {
 	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
 		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
 
 	switch (type) {
-	case HAL_RESET_POWER_ON:
+	case ATH9K_RESET_POWER_ON:
 		return ath9k_hw_set_reset_power_on(ah);
 		break;
-	case HAL_RESET_WARM:
-	case HAL_RESET_COLD:
+	case ATH9K_RESET_WARM:
+	case ATH9K_RESET_COLD:
 		return ath9k_hw_set_reset(ah, type);
 		break;
 	default:
@@ -1662,10 +1663,11 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
 	}
 }
 
-static inline struct hal_channel_internal *ath9k_hw_check_chan(
-			struct ath_hal *ah, struct hal_channel *chan)
+static inline
+struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
+					  struct ath9k_channel *chan)
 {
-	if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
+	if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
 		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u/0x%x; not marked as "
 			 "2GHz or 5GHz\n", __func__, chan->channel,
@@ -1673,15 +1675,14 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
 		return NULL;
 	}
 
-	if ((IS(chan, CHANNEL_OFDM)
-	     ^ IS(chan, CHANNEL_CCK)
-	     ^ IS(chan, CHANNEL_HT20)
-	     ^ IS(chan, CHANNEL_HT40PLUS)
-	     ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
+	if (!IS_CHAN_OFDM(chan) &&
+	      !IS_CHAN_CCK(chan) &&
+	      !IS_CHAN_HT20(chan) &&
+	      !IS_CHAN_HT40(chan)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
-			 "%s: invalid channel %u/0x%x; not marked as "
-			 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
-			 __func__, chan->channel, chan->channelFlags);
+			"%s: invalid channel %u/0x%x; not marked as "
+			"OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
+			__func__, chan->channel, chan->channelFlags);
 		return NULL;
 	}
 
@@ -1689,20 +1690,20 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
 }
 
 static inline bool
-ath9k_hw_get_lower_upper_index(u_int8_t target,
-			       u_int8_t *pList,
-			       u_int16_t listSize,
-			       u_int16_t *indexL,
-			       u_int16_t *indexR)
+ath9k_hw_get_lower_upper_index(u8 target,
+			       u8 *pList,
+			       u16 listSize,
+			       u16 *indexL,
+			       u16 *indexR)
 {
-	u_int16_t i;
+	u16 i;
 
 	if (target <= pList[0]) {
 		*indexL = *indexR = 0;
 		return true;
 	}
 	if (target >= pList[listSize - 1]) {
-		*indexL = *indexR = (u_int16_t) (listSize - 1);
+		*indexL = *indexR = (u16) (listSize - 1);
 		return true;
 	}
 
@@ -1713,7 +1714,7 @@ ath9k_hw_get_lower_upper_index(u_int8_t target,
 		}
 		if (target < pList[i + 1]) {
 			*indexL = i;
-			*indexR = (u_int16_t) (i + 1);
+			*indexR = (u16) (i + 1);
 			return false;
 		}
 	}
@@ -1723,14 +1724,14 @@ ath9k_hw_get_lower_upper_index(u_int8_t target,
 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
 {
 	int16_t nfval;
-	int16_t sort[HAL_NF_CAL_HIST_MAX];
+	int16_t sort[ATH9K_NF_CAL_HIST_MAX];
 	int i, j;
 
-	for (i = 0; i < HAL_NF_CAL_HIST_MAX; i++)
+	for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
 		sort[i] = nfCalBuffer[i];
 
-	for (i = 0; i < HAL_NF_CAL_HIST_MAX - 1; i++) {
-		for (j = 1; j < HAL_NF_CAL_HIST_MAX - i; j++) {
+	for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
+		for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
 			if (sort[j] > sort[j - 1]) {
 				nfval = sort[j];
 				sort[j] = sort[j - 1];
@@ -1738,12 +1739,12 @@ static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
 			}
 		}
 	}
-	nfval = sort[(HAL_NF_CAL_HIST_MAX - 1) >> 1];
+	nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
 
 	return nfval;
 }
 
-static void ath9k_hw_update_nfcal_hist_buffer(struct hal_nfcal_hist *h,
+static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
 					      int16_t *nfarray)
 {
 	int i;
@@ -1751,13 +1752,13 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct hal_nfcal_hist *h,
 	for (i = 0; i < NUM_NF_READINGS; i++) {
 		h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
 
-		if (++h[i].currIndex >= HAL_NF_CAL_HIST_MAX)
+		if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
 			h[i].currIndex = 0;
 
 		if (h[i].invalidNFcount > 0) {
 			if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
 			    || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
-				h[i].invalidNFcount = HAL_NF_CAL_HIST_MAX;
+				h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
 			} else {
 				h[i].invalidNFcount--;
 				h[i].privNF = nfarray[i];
@@ -1848,12 +1849,12 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
 static bool
 getNoiseFloorThresh(struct ath_hal *ah,
-		    const struct hal_channel_internal *chan,
+		    const struct ath9k_channel *chan,
 		    int16_t *nft)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	switch (chan->channelFlags & CHANNEL_ALL) {
+	switch (chan->chanmode) {
 	case CHANNEL_A:
 	case CHANNEL_A_HT20:
 	case CHANNEL_A_HT40PLUS:
@@ -1886,12 +1887,12 @@ static void ath9k_hw_start_nfcal(struct ath_hal *ah)
 }
 
 static void
-ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
+ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
 {
-	struct hal_nfcal_hist *h;
+	struct ath9k_nfcal_hist *h;
 	int i, j;
 	int32_t val;
-	const u_int32_t ar5416_cca_regs[6] = {
+	const u32 ar5416_cca_regs[6] = {
 		AR_PHY_CCA,
 		AR_PHY_CH1_CCA,
 		AR_PHY_CH2_CCA,
@@ -1899,7 +1900,7 @@ ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
 		AR_PHY_CH1_EXT_CCA,
 		AR_PHY_CH2_EXT_CCA
 	};
-	u_int8_t chainmask;
+	u8 chainmask;
 
 	if (AR_SREV_9280(ah))
 		chainmask = 0x1B;
@@ -1916,7 +1917,7 @@ ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
 		if (chainmask & (1 << i)) {
 			val = REG_READ(ah, ar5416_cca_regs[i]);
 			val &= 0xFFFFFE00;
-			val |= (((u_int32_t) (h[i].privNF) << 1) & 0x1ff);
+			val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
 			REG_WRITE(ah, ar5416_cca_regs[i], val);
 		}
 	}
@@ -1938,19 +1939,19 @@ ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
 		if (chainmask & (1 << i)) {
 			val = REG_READ(ah, ar5416_cca_regs[i]);
 			val &= 0xFFFFFE00;
-			val |= (((u_int32_t) (-50) << 1) & 0x1ff);
+			val |= (((u32) (-50) << 1) & 0x1ff);
 			REG_WRITE(ah, ar5416_cca_regs[i], val);
 		}
 	}
 }
 
 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
-			      struct hal_channel_internal *chan)
+			      struct ath9k_channel *chan)
 {
 	int16_t nf, nfThresh;
 	int16_t nfarray[NUM_NF_READINGS] = { 0 };
-	struct hal_nfcal_hist *h;
-	u_int8_t chainmask;
+	struct ath9k_nfcal_hist *h;
+	u8 chainmask;
 
 	if (AR_SREV_9280(ah))
 		chainmask = 0x1B;
@@ -1991,7 +1992,7 @@ static int16_t ath9k_hw_getnf(struct ath_hal *ah,
 }
 
 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
-			      struct hal_mib_stats *stats)
+			      struct ath9k_mib_stats *stats)
 {
 	stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
 	stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
@@ -2032,7 +2033,7 @@ static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
 }
 
 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
-					struct hal_channel_internal *chan)
+					struct ath9k_channel *chan)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	int i;
@@ -2061,23 +2062,23 @@ static void ath9k_hw_ani_attach(struct ath_hal *ah)
 
 	memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
 	for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
-		ahp->ah_ani[i].ofdmTrigHigh = HAL_ANI_OFDM_TRIG_HIGH;
-		ahp->ah_ani[i].ofdmTrigLow = HAL_ANI_OFDM_TRIG_LOW;
-		ahp->ah_ani[i].cckTrigHigh = HAL_ANI_CCK_TRIG_HIGH;
-		ahp->ah_ani[i].cckTrigLow = HAL_ANI_CCK_TRIG_LOW;
-		ahp->ah_ani[i].rssiThrHigh = HAL_ANI_RSSI_THR_HIGH;
-		ahp->ah_ani[i].rssiThrLow = HAL_ANI_RSSI_THR_LOW;
+		ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
+		ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
+		ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
+		ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
+		ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
+		ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
 		ahp->ah_ani[i].ofdmWeakSigDetectOff =
-			!HAL_ANI_USE_OFDM_WEAK_SIG;
+			!ATH9K_ANI_USE_OFDM_WEAK_SIG;
 		ahp->ah_ani[i].cckWeakSigThreshold =
-			HAL_ANI_CCK_WEAK_SIG_THR;
-		ahp->ah_ani[i].spurImmunityLevel = HAL_ANI_SPUR_IMMUNE_LVL;
-		ahp->ah_ani[i].firstepLevel = HAL_ANI_FIRSTEP_LVL;
+			ATH9K_ANI_CCK_WEAK_SIG_THR;
+		ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
+		ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
 		if (ahp->ah_hasHwPhyCounters) {
 			ahp->ah_ani[i].ofdmPhyErrBase =
-				AR_PHY_COUNTMAX - HAL_ANI_OFDM_TRIG_HIGH;
+				AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
 			ahp->ah_ani[i].cckPhyErrBase =
-				AR_PHY_COUNTMAX - HAL_ANI_CCK_TRIG_HIGH;
+				AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
 		}
 	}
 	if (ahp->ah_hasHwPhyCounters) {
@@ -2091,7 +2092,7 @@ static void ath9k_hw_ani_attach(struct ath_hal *ah)
 		REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
 		ath9k_enable_mib_counters(ah);
 	}
-	ahp->ah_aniPeriod = HAL_ANI_PERIOD;
+	ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
 	if (ah->ah_config.ath_hal_enableANI)
 		ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
 }
@@ -2128,14 +2129,14 @@ static void ath9k_hw_ani_detach(struct ath_hal *ah)
 
 
 static bool ath9k_hw_ani_control(struct ath_hal *ah,
-				 enum hal_ani_cmd cmd, int param)
+				 enum ath9k_ani_cmd cmd, int param)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416AniState *aniState = ahp->ah_curani;
 
 	switch (cmd & ahp->ah_ani_function) {
-	case HAL_ANI_NOISE_IMMUNITY_LEVEL:{
-		u_int level = param;
+	case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
+		u32 level = param;
 
 		if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
 			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -2166,14 +2167,14 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
 		aniState->noiseImmunityLevel = level;
 		break;
 	}
-	case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
+	case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 		const int m1ThreshLow[] = { 127, 50 };
 		const int m2ThreshLow[] = { 127, 40 };
 		const int m1Thresh[] = { 127, 0x4d };
 		const int m2Thresh[] = { 127, 0x40 };
 		const int m2CountThr[] = { 31, 16 };
 		const int m2CountThrLow[] = { 63, 48 };
-		u_int on = param ? 1 : 0;
+		u32 on = param ? 1 : 0;
 
 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 			      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
@@ -2223,9 +2224,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
 		}
 		break;
 	}
-	case HAL_ANI_CCK_WEAK_SIGNAL_THR:{
+	case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
 		const int weakSigThrCck[] = { 8, 6 };
-		u_int high = param ? 1 : 0;
+		u32 high = param ? 1 : 0;
 
 		REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
 			      AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
@@ -2239,9 +2240,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
 		}
 		break;
 	}
-	case HAL_ANI_FIRSTEP_LEVEL:{
+	case ATH9K_ANI_FIRSTEP_LEVEL:{
 		const int firstep[] = { 0, 4, 8 };
-		u_int level = param;
+		u32 level = param;
 
 		if (level >= ARRAY_SIZE(firstep)) {
 			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -2260,10 +2261,10 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
 		aniState->firstepLevel = level;
 		break;
 	}
-	case HAL_ANI_SPUR_IMMUNITY_LEVEL:{
+	case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 		const int cycpwrThr1[] =
 			{ 2, 4, 6, 8, 10, 12, 14, 16 };
-		u_int level = param;
+		u32 level = param;
 
 		if (level >= ARRAY_SIZE(cycpwrThr1)) {
 			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -2283,7 +2284,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
 		aniState->spurImmunityLevel = level;
 		break;
 	}
-	case HAL_ANI_PRESENT:
+	case ATH9K_ANI_PRESENT:
 		break;
 	default:
 		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -2355,7 +2356,7 @@ static void ath9k_ani_restart(struct ath_hal *ah)
 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *chan = ah->ah_curchan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 	struct ar5416AniState *aniState;
 	enum wireless_mode mode;
 	int32_t rssi;
@@ -2366,22 +2367,22 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 	aniState = ahp->ah_curani;
 
 	if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
-		if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+		if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 					 aniState->noiseImmunityLevel + 1)) {
 			return;
 		}
 	}
 
 	if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
-		if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+		if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 					 aniState->spurImmunityLevel + 1)) {
 			return;
 		}
 	}
 
-	if (ah->ah_opmode == HAL_M_HOSTAP) {
+	if (ah->ah_opmode == ATH9K_M_HOSTAP) {
 		if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
-			ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+			ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 					     aniState->firstepLevel + 1);
 		}
 		return;
@@ -2390,38 +2391,38 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 	if (rssi > aniState->rssiThrHigh) {
 		if (!aniState->ofdmWeakSigDetectOff) {
 			if (ath9k_hw_ani_control(ah,
-					 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+					 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 					 false)) {
 				ath9k_hw_ani_control(ah,
-					HAL_ANI_SPUR_IMMUNITY_LEVEL,
+					ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 					0);
 				return;
 			}
 		}
 		if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
-			ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+			ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 					     aniState->firstepLevel + 1);
 			return;
 		}
 	} else if (rssi > aniState->rssiThrLow) {
 		if (aniState->ofdmWeakSigDetectOff)
 			ath9k_hw_ani_control(ah,
-					     HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-					     true);
+				     ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				     true);
 		if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
-			ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+			ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 					     aniState->firstepLevel + 1);
 		return;
 	} else {
-		mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
+		mode = ath9k_hw_chan2wmode(ah, chan);
 		if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
 			if (!aniState->ofdmWeakSigDetectOff)
 				ath9k_hw_ani_control(ah,
-					     HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-					     false);
+				     ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				     false);
 			if (aniState->firstepLevel > 0)
 				ath9k_hw_ani_control(ah,
-						     HAL_ANI_FIRSTEP_LEVEL,
+						     ATH9K_ANI_FIRSTEP_LEVEL,
 						     0);
 			return;
 		}
@@ -2431,7 +2432,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *chan = ah->ah_curchan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 	struct ar5416AniState *aniState;
 	enum wireless_mode mode;
 	int32_t rssi;
@@ -2441,14 +2442,14 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
 
 	aniState = ahp->ah_curani;
 	if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
-		if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+		if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 					 aniState->noiseImmunityLevel + 1)) {
 			return;
 		}
 	}
-	if (ah->ah_opmode == HAL_M_HOSTAP) {
+	if (ah->ah_opmode == ATH9K_M_HOSTAP) {
 		if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
-			ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+			ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 					     aniState->firstepLevel + 1);
 		}
 		return;
@@ -2456,14 +2457,14 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
 	rssi = BEACON_RSSI(ahp);
 	if (rssi > aniState->rssiThrLow) {
 		if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
-			ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+			ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 					     aniState->firstepLevel + 1);
 	} else {
-		mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
+		mode = ath9k_hw_chan2wmode(ah, chan);
 		if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
 			if (aniState->firstepLevel > 0)
 				ath9k_hw_ani_control(ah,
-						     HAL_ANI_FIRSTEP_LEVEL,
+						     ATH9K_ANI_FIRSTEP_LEVEL,
 						     0);
 		}
 	}
@@ -2473,7 +2474,7 @@ static void ath9k_ani_reset(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416AniState *aniState;
-	struct hal_channel_internal *chan = ah->ah_curchan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 	int index;
 
 	if (!DO_ANI(ah))
@@ -2483,24 +2484,24 @@ static void ath9k_ani_reset(struct ath_hal *ah)
 	aniState = &ahp->ah_ani[index];
 	ahp->ah_curani = aniState;
 
-	if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
-	    && ah->ah_opmode != HAL_M_IBSS) {
+	if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
+	    && ah->ah_opmode != ATH9K_M_IBSS) {
 		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 			 "%s: Reset ANI state opmode %u\n", __func__,
 			 ah->ah_opmode);
 		ahp->ah_stats.ast_ani_reset++;
-		ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
-		ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
-		ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
+		ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
+		ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
+		ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
 		ath9k_hw_ani_control(ah,
-				     HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-				     !HAL_ANI_USE_OFDM_WEAK_SIG);
-		ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
-				     HAL_ANI_CCK_WEAK_SIG_THR);
+				     ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				     !ATH9K_ANI_USE_OFDM_WEAK_SIG);
+		ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
+				     ATH9K_ANI_CCK_WEAK_SIG_THR);
 		ath9k_hw_setrxfilter(ah,
 				     ath9k_hw_getrxfilter(ah) |
-				     HAL_RX_FILTER_PHYERR);
-		if (ah->ah_opmode == HAL_M_HOSTAP) {
+				     ATH9K_RX_FILTER_PHYERR);
+		if (ah->ah_opmode == ATH9K_M_HOSTAP) {
 			ahp->ah_curani->ofdmTrigHigh =
 				ah->ah_config.ath_hal_ofdmTrigHigh;
 			ahp->ah_curani->ofdmTrigLow =
@@ -2515,25 +2516,25 @@ static void ath9k_ani_reset(struct ath_hal *ah)
 	}
 
 	if (aniState->noiseImmunityLevel != 0)
-		ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+		ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 				     aniState->noiseImmunityLevel);
 	if (aniState->spurImmunityLevel != 0)
-		ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+		ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 				     aniState->spurImmunityLevel);
 	if (aniState->ofdmWeakSigDetectOff)
 		ath9k_hw_ani_control(ah,
-				     HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				     ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 				     !aniState->ofdmWeakSigDetectOff);
 	if (aniState->cckWeakSigThreshold)
-		ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
+		ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
 				     aniState->cckWeakSigThreshold);
 	if (aniState->firstepLevel != 0)
-		ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+		ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 				     aniState->firstepLevel);
 	if (ahp->ah_hasHwPhyCounters) {
 		ath9k_hw_setrxfilter(ah,
 				     ath9k_hw_getrxfilter(ah) &
-				     ~HAL_RX_FILTER_PHYERR);
+				     ~ATH9K_RX_FILTER_PHYERR);
 		ath9k_ani_restart(ah);
 		REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
 		REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
@@ -2542,15 +2543,15 @@ static void ath9k_ani_reset(struct ath_hal *ah)
 		ath9k_ani_restart(ah);
 		ath9k_hw_setrxfilter(ah,
 				     ath9k_hw_getrxfilter(ah) |
-				     HAL_RX_FILTER_PHYERR);
+				     ATH9K_RX_FILTER_PHYERR);
 	}
 }
 
 void ath9k_hw_procmibevent(struct ath_hal *ah,
-			   const struct hal_node_stats *stats)
+			   const struct ath9k_node_stats *stats)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t phyCnt1, phyCnt2;
+	u32 phyCnt1, phyCnt2;
 
 	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
 
@@ -2570,7 +2571,7 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
 	if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
 	    ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
 		struct ar5416AniState *aniState = ahp->ah_curani;
-		u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
+		u32 ofdmPhyErrCnt, cckPhyErrCnt;
 
 		ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
 		ahp->ah_stats.ast_ani_ofdmerrs +=
@@ -2599,9 +2600,9 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 
 	aniState = ahp->ah_curani;
 
-	if (ah->ah_opmode == HAL_M_HOSTAP) {
+	if (ah->ah_opmode == ATH9K_M_HOSTAP) {
 		if (aniState->firstepLevel > 0) {
-			if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
+			if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
 						 aniState->firstepLevel - 1)) {
 				return;
 			}
@@ -2613,7 +2614,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 		} else if (rssi > aniState->rssiThrLow) {
 			if (aniState->ofdmWeakSigDetectOff) {
 				if (ath9k_hw_ani_control(ah,
-					 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+					 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
 					 true) ==
 				    true) {
 					return;
@@ -2621,7 +2622,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 			}
 			if (aniState->firstepLevel > 0) {
 				if (ath9k_hw_ani_control
-				    (ah, HAL_ANI_FIRSTEP_LEVEL,
+				    (ah, ATH9K_ANI_FIRSTEP_LEVEL,
 				     aniState->firstepLevel - 1) ==
 				    true) {
 					return;
@@ -2630,7 +2631,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 		} else {
 			if (aniState->firstepLevel > 0) {
 				if (ath9k_hw_ani_control
-				    (ah, HAL_ANI_FIRSTEP_LEVEL,
+				    (ah, ATH9K_ANI_FIRSTEP_LEVEL,
 				     aniState->firstepLevel - 1) ==
 				    true) {
 					return;
@@ -2640,14 +2641,14 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 	}
 
 	if (aniState->spurImmunityLevel > 0) {
-		if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+		if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
 					 aniState->spurImmunityLevel - 1)) {
 			return;
 		}
 	}
 
 	if (aniState->noiseImmunityLevel > 0) {
-		ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+		ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
 				     aniState->noiseImmunityLevel - 1);
 		return;
 	}
@@ -2657,7 +2658,7 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416AniState *aniState;
-	u_int32_t txFrameCount, rxFrameCount, cycleCount;
+	u32 txFrameCount, rxFrameCount, cycleCount;
 	int32_t listenTime;
 
 	txFrameCount = REG_READ(ah, AR_TFCNT);
@@ -2683,8 +2684,8 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
 }
 
 void ath9k_hw_ani_monitor(struct ath_hal *ah,
-			  const struct hal_node_stats *stats,
-			  struct hal_channel *chan)
+			  const struct ath9k_node_stats *stats,
+			  struct ath9k_channel *chan)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416AniState *aniState;
@@ -2703,8 +2704,8 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
 	aniState->listenTime += listenTime;
 
 	if (ahp->ah_hasHwPhyCounters) {
-		u_int32_t phyCnt1, phyCnt2;
-		u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
+		u32 phyCnt1, phyCnt2;
+		u32 ofdmPhyErrCnt, cckPhyErrCnt;
 
 		ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
 
@@ -2783,7 +2784,7 @@ static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
 		ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
 		ah->nfCalHist[i].invalidNFcount =
 			AR_PHY_CCA_FILTERWINDOW_LENGTH;
-		for (j = 0; j < HAL_NF_CAL_HIST_MAX; j++) {
+		for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
 			ah->nfCalHist[i].nfCalBuffer[j] =
 				AR_PHY_CCA_MAX_GOOD_VALUE;
 		}
@@ -2793,10 +2794,10 @@ static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
 #endif
 
 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
-					 u_int32_t gpio, u_int32_t type)
+					 u32 gpio, u32 type)
 {
 	int addr;
-	u_int32_t gpio_shift, tmp;
+	u32 gpio_shift, tmp;
 
 	if (gpio > 11)
 		addr = AR_GPIO_OUTPUT_MUX3;
@@ -2820,14 +2821,14 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
 	}
 }
 
-static bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
-				enum hal_gpio_output_mux_type
+static bool ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
+				enum ath9k_gpio_output_mux_type
 				halSignalType)
 {
-	u_int32_t ah_signal_type;
-	u_int32_t gpio_shift;
+	u32 ah_signal_type;
+	u32 gpio_shift;
 
-	static u_int32_t MuxSignalConversionTable[] = {
+	static u32 MuxSignalConversionTable[] = {
 
 		AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
 
@@ -2858,15 +2859,15 @@ static bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
 	return true;
 }
 
-static bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
-			      u_int32_t val)
+static bool ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio,
+			      u32 val)
 {
 	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
 		AR_GPIO_BIT(gpio));
 	return true;
 }
 
-static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
+static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
 {
 	if (gpio >= ah->ah_caps.halNumGpioPins)
 		return 0xffffffff;
@@ -2881,37 +2882,37 @@ static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
 	}
 }
 
-static inline enum hal_status ath9k_hw_post_attach(struct ath_hal *ah)
+static inline int ath9k_hw_post_attach(struct ath_hal *ah)
 {
-	enum hal_status ecode;
+	int ecode;
 
 	if (!ath9k_hw_chip_test(ah)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 			 "%s: hardware self-test failed\n", __func__);
-		return HAL_ESELFTEST;
+		return -ENODEV;
 	}
 
 	ecode = ath9k_hw_rf_claim(ah);
-	if (ecode != HAL_OK)
+	if (ecode != 0)
 		return ecode;
 
 	ecode = ath9k_hw_eeprom_attach(ah);
-	if (ecode != HAL_OK)
+	if (ecode != 0)
 		return ecode;
 	ecode = ath9k_hw_rfattach(ah);
-	if (ecode != HAL_OK)
+	if (ecode != 0)
 		return ecode;
 
 	if (!AR_SREV_9100(ah)) {
 		ath9k_hw_ani_setup(ah);
 		ath9k_hw_ani_attach(ah);
 	}
-	return HAL_OK;
+	return 0;
 }
 
-static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
+static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
 				    struct ar5416_eeprom *pEepData,
-				    u_int32_t reg, u_int32_t value)
+				    u32 reg, u32 value)
 {
 	struct base_eep_header *pBase = &(pEepData->baseEepHeader);
 
@@ -2946,7 +2947,7 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
-	u_int16_t capField = 0, eeval;
+	u16 capField = 0, eeval;
 
 	eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
 
@@ -2957,7 +2958,7 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 
 	capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
 
-	if (ah->ah_opmode != HAL_M_HOSTAP &&
+	if (ah->ah_opmode != ATH9K_M_HOSTAP &&
 	    ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
 		if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
 			ah->ah_currentRD += 5;
@@ -3031,7 +3032,7 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 		pCap->halTotalQueues =
 			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
 	else
-		pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
+		pCap->halTotalQueues = ATH9K_NUM_TX_QUEUES;
 
 	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
 		pCap->halKeyCacheSize =
@@ -3140,7 +3141,7 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
 		if (!AR_SREV_9100(ah))
 			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
 
-		REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
+		REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
 			    AR_RTC_RESET_EN);
 	}
 }
@@ -3164,13 +3165,13 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
 				     int setChip)
 {
-	u_int32_t val;
+	u32 val;
 	int i;
 
 	if (setChip) {
 		if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
 		    AR_RTC_STATUS_SHUTDOWN) {
-			if (ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)
+			if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
 			    != true) {
 				return false;
 			}
@@ -3204,7 +3205,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
 }
 
 bool ath9k_hw_setpower(struct ath_hal *ah,
-		       enum hal_power_mode mode)
+		       enum ath9k_power_mode mode)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	static const char *modes[] = {
@@ -3220,14 +3221,14 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
 		 setChip ? "set chip " : "");
 
 	switch (mode) {
-	case HAL_PM_AWAKE:
+	case ATH9K_PM_AWAKE:
 		status = ath9k_hw_set_power_awake(ah, setChip);
 		break;
-	case HAL_PM_FULL_SLEEP:
+	case ATH9K_PM_FULL_SLEEP:
 		ath9k_set_power_sleep(ah, setChip);
 		ahp->ah_chipFullSleep = true;
 		break;
-	case HAL_PM_NETWORK_SLEEP:
+	case ATH9K_PM_NETWORK_SLEEP:
 		ath9k_set_power_network_sleep(ah, setChip);
 		break;
 	default:
@@ -3239,17 +3240,17 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
 	return status;
 }
 
-static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
+static struct ath_hal *ath9k_hw_do_attach(u16 devid,
 					  struct ath_softc *sc,
 					  void __iomem *mem,
-					  enum hal_status *status)
+					  int *status)
 {
 	struct ath_hal_5416 *ahp;
 	struct ath_hal *ah;
-	enum hal_status ecode;
+	int ecode;
 #ifndef CONFIG_SLOW_ANT_DIV
-	u_int32_t i;
-	u_int32_t j;
+	u32 i;
+	u32 j;
 #endif
 
 	ahp = ath9k_hw_newstate(devid, sc, mem, status);
@@ -3263,17 +3264,17 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
 	if (ah->ah_config.ath_hal_intrMitigation != 0)
 		ahp->ah_intrMitigation = true;
 
-	if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)) {
+	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
 			 __func__);
-		ecode = HAL_EIO;
+		ecode = -EIO;
 		goto bad;
 	}
 
-	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE)) {
+	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
 			 __func__);
-		ecode = HAL_EIO;
+		ecode = -EIO;
 		goto bad;
 	}
 
@@ -3298,7 +3299,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
 			 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
 			 "this driver\n", __func__,
 			 ah->ah_macVersion, ah->ah_macRev);
-		ecode = HAL_ENOTSUPP;
+		ecode = -EOPNOTSUPP;
 		goto bad;
 	}
 
@@ -3333,13 +3334,13 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
 
 	if (AR_SREV_9160(ah)) {
 		ah->ah_config.ath_hal_enableANI = 1;
-		ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
-					HAL_ANI_FIRSTEP_LEVEL);
+		ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
+					ATH9K_ANI_FIRSTEP_LEVEL);
 	} else {
-		ahp->ah_ani_function = HAL_ANI_ALL;
+		ahp->ah_ani_function = ATH9K_ANI_ALL;
 		if (AR_SREV_9280_10_OR_LATER(ah)) {
 			ahp->ah_ani_function &=
-				~HAL_ANI_NOISE_IMMUNITY_LEVEL;
+				~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 		}
 	}
 
@@ -3458,16 +3459,16 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
 		ar5416DisablePciePhy(ah);
 
 	ecode = ath9k_hw_post_attach(ah);
-	if (ecode != HAL_OK)
+	if (ecode != 0)
 		goto bad;
 
 #ifndef CONFIG_SLOW_ANT_DIV
 	if (ah->ah_devid == AR9280_DEVID_PCI) {
 		for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
-			u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
+			u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 
 			for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
-				u_int32_t val = INI_RA(&ahp->ah_iniModes, i, j);
+				u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 
 				INI_RA(&ahp->ah_iniModes, i, j) =
 					ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
@@ -3480,12 +3481,12 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
 	if (!ath9k_hw_fill_cap_info(ah)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
-		ecode = HAL_EEREAD;
+		ecode = -EINVAL;
 		goto bad;
 	}
 
 	ecode = ath9k_hw_init_macaddr(ah);
-	if (ecode != HAL_OK) {
+	if (ecode != 0) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s: failed initializing mac address\n",
 			 __func__);
@@ -3518,13 +3519,13 @@ void ath9k_hw_detach(struct ath_hal *ah)
 		ath9k_hw_ani_detach(ah);
 	ath9k_hw_rfdetach(ah);
 
-	ath9k_hw_setpower(ah, HAL_PM_FULL_SLEEP);
+	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 	kfree(ah);
 }
 
 bool ath9k_get_channel_edges(struct ath_hal *ah,
-			     u_int16_t flags, u_int16_t *low,
-			     u_int16_t *high)
+			     u16 flags, u16 *low,
+			     u16 *high)
 {
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
@@ -3542,17 +3543,17 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
 	return false;
 }
 
-static inline bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
-					   u_int8_t pwrMax,
-					   u_int8_t *pPwrList,
-					   u_int8_t *pVpdList,
-					   u_int16_t
+static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
+					   u8 pwrMax,
+					   u8 *pPwrList,
+					   u8 *pVpdList,
+					   u16
 					   numIntercepts,
-					   u_int8_t *pRetVpdList)
+					   u8 *pRetVpdList)
 {
-	u_int16_t i, k;
-	u_int8_t currPwr = pwrMin;
-	u_int16_t idxL = 0, idxR = 0;
+	u16 i, k;
+	u8 currPwr = pwrMin;
+	u16 idxL = 0, idxR = 0;
 
 	for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
 		ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
@@ -3561,18 +3562,18 @@ static inline bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
 		if (idxR < 1)
 			idxR = 1;
 		if (idxL == numIntercepts - 1)
-			idxL = (u_int16_t) (numIntercepts - 2);
+			idxL = (u16) (numIntercepts - 2);
 		if (pPwrList[idxL] == pPwrList[idxR])
 			k = pVpdList[idxL];
 		else
-			k = (u_int16_t) (((currPwr -
+			k = (u16) (((currPwr -
 					   pPwrList[idxL]) *
 					  pVpdList[idxR] +
 					  (pPwrList[idxR] -
 					   currPwr) * pVpdList[idxL]) /
 					 (pPwrList[idxR] -
 					  pPwrList[idxL]));
-		pRetVpdList[i] = (u_int8_t) k;
+		pRetVpdList[i] = (u8) k;
 		currPwr += 2;
 	}
 
@@ -3581,32 +3582,32 @@ static inline bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
 
 static inline void
 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
-				    struct hal_channel_internal *chan,
+				    struct ath9k_channel *chan,
 				    struct cal_data_per_freq *pRawDataSet,
-				    u_int8_t *bChans,
-				    u_int16_t availPiers,
-				    u_int16_t tPdGainOverlap,
+				    u8 *bChans,
+				    u16 availPiers,
+				    u16 tPdGainOverlap,
 				    int16_t *pMinCalPower,
-				    u_int16_t *pPdGainBoundaries,
-				    u_int8_t *pPDADCValues,
-				    u_int16_t numXpdGains)
+				    u16 *pPdGainBoundaries,
+				    u8 *pPDADCValues,
+				    u16 numXpdGains)
 {
 	int i, j, k;
 	int16_t ss;
-	u_int16_t idxL = 0, idxR = 0, numPiers;
-	static u_int8_t vpdTableL[AR5416_NUM_PD_GAINS]
+	u16 idxL = 0, idxR = 0, numPiers;
+	static u8 vpdTableL[AR5416_NUM_PD_GAINS]
 		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-	static u_int8_t vpdTableR[AR5416_NUM_PD_GAINS]
+	static u8 vpdTableR[AR5416_NUM_PD_GAINS]
 		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-	static u_int8_t vpdTableI[AR5416_NUM_PD_GAINS]
+	static u8 vpdTableI[AR5416_NUM_PD_GAINS]
 		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 
-	u_int8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-	u_int8_t minPwrT4[AR5416_NUM_PD_GAINS];
-	u_int8_t maxPwrT4[AR5416_NUM_PD_GAINS];
+	u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+	u8 minPwrT4[AR5416_NUM_PD_GAINS];
+	u8 maxPwrT4[AR5416_NUM_PD_GAINS];
 	int16_t vpdStep;
 	int16_t tmpVal;
-	u_int16_t sizeCurrVpdTable, maxIndex, tgtIndex;
+	u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 	bool match;
 	int16_t minDelta = 0;
 	struct chan_centers centers;
@@ -3618,7 +3619,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 			break;
 	}
 
-	match = ath9k_hw_get_lower_upper_index((u_int8_t)
+	match = ath9k_hw_get_lower_upper_index((u8)
 					       FREQ2FBIN(centers.
 							 synth_center,
 							 IS_CHAN_2GHZ
@@ -3662,8 +3663,8 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 
 			for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 				vpdTableI[i][j] =
-					(u_int8_t) (ath9k_hw_interpolate
-						    ((u_int16_t)
+					(u8) (ath9k_hw_interpolate
+						    ((u16)
 						     FREQ2FBIN(centers.
 							       synth_center,
 							       IS_CHAN_2GHZ
@@ -3682,14 +3683,14 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 	for (i = 0; i < numXpdGains; i++) {
 		if (i == (numXpdGains - 1))
 			pPdGainBoundaries[i] =
-				(u_int16_t) (maxPwrT4[i] / 2);
+				(u16) (maxPwrT4[i] / 2);
 		else
 			pPdGainBoundaries[i] =
-				(u_int16_t) ((maxPwrT4[i] +
+				(u16) ((maxPwrT4[i] +
 					      minPwrT4[i + 1]) / 4);
 
 		pPdGainBoundaries[i] =
-			min((u_int16_t) AR5416_MAX_RATE_POWER,
+			min((u16) AR5416_MAX_RATE_POWER,
 			    pPdGainBoundaries[i]);
 
 		if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
@@ -3715,13 +3716,13 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 		while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 			tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
 			pPDADCValues[k++] =
-				(u_int8_t) ((tmpVal < 0) ? 0 : tmpVal);
+				(u8) ((tmpVal < 0) ? 0 : tmpVal);
 			ss++;
 		}
 
 		sizeCurrVpdTable =
-			(u_int8_t) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-		tgtIndex = (u_int8_t) (pPdGainBoundaries[i] + tPdGainOverlap -
+			(u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
+		tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
 				       (minPwrT4[i] / 2));
 		maxIndex = (tgtIndex <
 			    sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
@@ -3742,7 +3743,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 						     [sizeCurrVpdTable -
 						      1] + (ss - maxIndex +
 							    1) * vpdStep));
-				pPDADCValues[k++] = (u_int8_t) ((tmpVal >
+				pPDADCValues[k++] = (u8) ((tmpVal >
 						 255) ? 255 : tmpVal);
 				ss++;
 			}
@@ -3764,19 +3765,19 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 static inline bool
 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 			     struct ar5416_eeprom *pEepData,
-			     struct hal_channel_internal *chan,
+			     struct ath9k_channel *chan,
 			     int16_t *pTxPowerIndexOffset)
 {
 	struct cal_data_per_freq *pRawDataset;
-	u_int8_t *pCalBChans = NULL;
-	u_int16_t pdGainOverlap_t2;
-	static u_int8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
-	u_int16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
-	u_int16_t numPiers, i, j;
+	u8 *pCalBChans = NULL;
+	u16 pdGainOverlap_t2;
+	static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
+	u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
+	u16 numPiers, i, j;
 	int16_t tMinCalPower;
-	u_int16_t numXpdGain, xpdMask;
-	u_int16_t xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
-	u_int32_t reg32, regOffset, regChainOffset;
+	u16 numXpdGain, xpdMask;
+	u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
+	u32 reg32, regOffset, regChainOffset;
 	int16_t modalIdx;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -3790,7 +3791,7 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 			pEepData->modalHeader[modalIdx].pdGainOverlap;
 	} else {
 		pdGainOverlap_t2 =
-			(u_int16_t) (MS
+			(u16) (MS
 				     (REG_READ(ah, AR_PHY_TPCRG5),
 				      AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 	}
@@ -3810,7 +3811,7 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 			if (numXpdGain >= AR5416_NUM_PD_GAINS)
 				break;
 			xpdGainValues[numXpdGain] =
-				(u_int16_t) (AR5416_PD_GAINS_IN_MASK - i);
+				(u16) (AR5416_PD_GAINS_IN_MASK - i);
 			numXpdGain++;
 		}
 	}
@@ -3901,7 +3902,7 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int8_t i;
+	u8 i;
 
 	if (ah->ah_isPciExpress != true)
 		return;
@@ -3966,17 +3967,17 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
 
 static inline void
 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
-				  struct hal_channel_internal *chan,
+				  struct ath9k_channel *chan,
 				  struct cal_target_power_leg *powInfo,
-				  u_int16_t numChannels,
+				  u16 numChannels,
 				  struct cal_target_power_leg *pNewPower,
-				  u_int16_t numRates,
+				  u16 numRates,
 				  bool isExtTarget)
 {
-	u_int16_t clo, chi;
+	u16 clo, chi;
 	int i;
 	int matchIndex = -1, lowIndex = -1;
-	u_int16_t freq;
+	u16 freq;
 	struct chan_centers centers;
 
 	ath9k_hw_get_channel_centers(ah, chan, &centers);
@@ -4019,7 +4020,7 @@ ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
 
 		for (i = 0; i < numRates; i++) {
 			pNewPower->tPow2x[i] =
-				(u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
+				(u8) ath9k_hw_interpolate(freq, clo, chi,
 								powInfo
 								[lowIndex].
 								tPow2x[i],
@@ -4032,17 +4033,17 @@ ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
 
 static inline void
 ath9k_hw_get_target_powers(struct ath_hal *ah,
-			   struct hal_channel_internal *chan,
+			   struct ath9k_channel *chan,
 			   struct cal_target_power_ht *powInfo,
-			   u_int16_t numChannels,
+			   u16 numChannels,
 			   struct cal_target_power_ht *pNewPower,
-			   u_int16_t numRates,
+			   u16 numRates,
 			   bool isHt40Target)
 {
-	u_int16_t clo, chi;
+	u16 clo, chi;
 	int i;
 	int matchIndex = -1, lowIndex = -1;
-	u_int16_t freq;
+	u16 freq;
 	struct chan_centers centers;
 
 	ath9k_hw_get_channel_centers(ah, chan, &centers);
@@ -4086,7 +4087,7 @@ ath9k_hw_get_target_powers(struct ath_hal *ah,
 
 		for (i = 0; i < numRates; i++) {
 			pNewPower->tPow2x[i] =
-				(u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
+				(u8) ath9k_hw_interpolate(freq, clo, chi,
 								powInfo
 								[lowIndex].
 								tPow2x[i],
@@ -4097,12 +4098,12 @@ ath9k_hw_get_target_powers(struct ath_hal *ah,
 	}
 }
 
-static inline u_int16_t
-ath9k_hw_get_max_edge_power(u_int16_t freq,
+static inline u16
+ath9k_hw_get_max_edge_power(u16 freq,
 			    struct cal_ctl_edges *pRdEdgesPower,
 			    bool is2GHz)
 {
-	u_int16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+	u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 	int i;
 
 	for (i = 0; (i < AR5416_NUM_BAND_EDGES)
@@ -4130,15 +4131,15 @@ ath9k_hw_get_max_edge_power(u_int16_t freq,
 static inline bool
 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 				  struct ar5416_eeprom *pEepData,
-				  struct hal_channel_internal *chan,
+				  struct ath9k_channel *chan,
 				  int16_t *ratesArray,
-				  u_int16_t cfgCtl,
-				  u_int8_t AntennaReduction,
-				  u_int8_t twiceMaxRegulatoryPower,
-				  u_int8_t powerLimit)
+				  u16 cfgCtl,
+				  u8 AntennaReduction,
+				  u8 twiceMaxRegulatoryPower,
+				  u8 powerLimit)
 {
-	u_int8_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
-	static const u_int16_t tpScaleReductionTable[5] =
+	u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+	static const u16 tpScaleReductionTable[5] =
 		{ 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 
 	int i;
@@ -4154,17 +4155,17 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 	struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 		0, {0, 0, 0, 0}
 	};
-	u_int8_t scaledPower = 0, minCtlPower, maxRegAllowedPower;
-	u_int16_t ctlModesFor11a[] =
+	u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
+	u16 ctlModesFor11a[] =
 		{ CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
-	u_int16_t ctlModesFor11g[] =
+	u16 ctlModesFor11g[] =
 		{ CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
 		  CTL_2GHT40
 		};
-	u_int16_t numCtlModes, *pCtlMode, ctlMode, freq;
+	u16 numCtlModes, *pCtlMode, ctlMode, freq;
 	struct chan_centers centers;
 	int tx_chainmask;
-	u_int8_t twiceMinEdgePower;
+	u8 twiceMinEdgePower;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	tx_chainmask = ahp->ah_txchainmask;
@@ -4177,7 +4178,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 		pEepData->modalHeader
 			[IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
 
-	twiceLargestAntenna = max((u_int8_t) twiceLargestAntenna,
+	twiceLargestAntenna = max((u8) twiceLargestAntenna,
 		pEepData->modalHeader
 			[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
 
@@ -4186,7 +4187,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 
 	maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 
-	if (ah->ah_tpScale != HAL_TP_SCALE_MAX) {
+	if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
 		maxRegAllowedPower -=
 			(tpScaleReductionTable[(ah->ah_tpScale)] * 2);
 	}
@@ -4313,12 +4314,11 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 		for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
 		     i++) {
 			DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
-				 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
+				"  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
 				"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
-				"chan %d chanctl 0x%x\n",
-				 i, cfgCtl, pCtlMode[ctlMode],
-				 pEepData->ctlIndex[i], chan->channel,
-				 chan->conformanceTestLimit);
+				"chan %d\n",
+				i, cfgCtl, pCtlMode[ctlMode],
+				pEepData->ctlIndex[i], chan->channel);
 
 			if ((((cfgCtl & ~CTL_MODE_M) |
 			      (pCtlMode[ctlMode] & CTL_MODE_M)) ==
@@ -4455,20 +4455,20 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 	return true;
 }
 
-static enum hal_status
+static int
 ath9k_hw_set_txpower(struct ath_hal *ah,
 		     struct ar5416_eeprom *pEepData,
-		     struct hal_channel_internal *chan,
-		     u_int16_t cfgCtl,
-		     u_int8_t twiceAntennaReduction,
-		     u_int8_t twiceMaxRegulatoryPower,
-		     u_int8_t powerLimit)
+		     struct ath9k_channel *chan,
+		     u16 cfgCtl,
+		     u8 twiceAntennaReduction,
+		     u8 twiceMaxRegulatoryPower,
+		     u8 powerLimit)
 {
 	struct modal_eep_header *pModal =
 		&(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
 	int16_t ratesArray[Ar5416RateSize];
 	int16_t txPowerIndexOffset = 0;
-	u_int8_t ht40PowerIncForPdadc = 2;
+	u8 ht40PowerIncForPdadc = 2;
 	int i;
 
 	memset(ratesArray, 0, sizeof(ratesArray));
@@ -4487,14 +4487,14 @@ ath9k_hw_set_txpower(struct ath_hal *ah,
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			"ath9k_hw_set_txpower: unable to set "
 			"tx power per rate table\n");
-		return HAL_EIO;
+		return -EIO;
 	}
 
 	if (!ath9k_hw_set_power_cal_table
 	    (ah, pEepData, chan, &txPowerIndexOffset)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "ath9k_hw_set_txpower: unable to set power table\n");
-		return HAL_EIO;
+		return -EIO;
 	}
 
 	for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
@@ -4597,15 +4597,15 @@ ath9k_hw_set_txpower(struct ath_hal *ah,
 	else
 		ah->ah_maxPowerLevel = ratesArray[i];
 
-	return HAL_OK;
+	return 0;
 }
 
 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
-						 u_int32_t coef_scaled,
-						 u_int32_t *coef_mantissa,
-						 u_int32_t *coef_exponent)
+						 u32 coef_scaled,
+						 u32 *coef_mantissa,
+						 u32 *coef_exponent)
 {
-	u_int32_t coef_exp, coef_man;
+	u32 coef_exp, coef_man;
 
 	for (coef_exp = 31; coef_exp > 0; coef_exp--)
 		if ((coef_scaled >> coef_exp) & 0x1)
@@ -4621,10 +4621,10 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
 
 static void
 ath9k_hw_set_delta_slope(struct ath_hal *ah,
-			 struct hal_channel_internal *chan)
+			 struct ath9k_channel *chan)
 {
-	u_int32_t coef_scaled, ds_coef_exp, ds_coef_man;
-	u_int32_t clockMhzScaled = 0x64000000;
+	u32 coef_scaled, ds_coef_exp, ds_coef_man;
+	u32 clockMhzScaled = 0x64000000;
 	struct chan_centers centers;
 
 	if (IS_CHAN_HALF_RATE(chan))
@@ -4655,8 +4655,7 @@ ath9k_hw_set_delta_slope(struct ath_hal *ah,
 }
 
 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
-					struct hal_channel *chan,
-					struct hal_channel_internal *ichan)
+					struct ath9k_channel *chan)
 {
 	int bb_spur = AR_NO_SPUR;
 	int freq;
@@ -4687,7 +4686,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
 	memset(&mask_m, 0, sizeof(int8_t) * 123);
 	memset(&mask_p, 0, sizeof(int8_t) * 123);
 
-	ath9k_hw_get_channel_centers(ah, ichan, &centers);
+	ath9k_hw_get_channel_centers(ah, chan, &centers);
 	freq = centers.synth_center;
 
 	ah->ah_config.ath_hal_spurMode = SPUR_ENABLE_EEPROM;
@@ -4903,7 +4902,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
 }
 
 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
-				   struct hal_channel *chan)
+				   struct ath9k_channel *chan)
 {
 	int bb_spur = AR_NO_SPUR;
 	int bin, cur_bin;
@@ -5141,12 +5140,12 @@ static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 }
 
 static void ath9k_hw_set_addac(struct ath_hal *ah,
-			       struct hal_channel_internal *chan)
+			       struct ath9k_channel *chan)
 {
 	struct modal_eep_header *pModal;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
-	u_int8_t biaslevel;
+	u8 biaslevel;
 
 	if (ah->ah_macVersion != AR_SREV_VERSION_9160)
 		return;
@@ -5160,7 +5159,7 @@ static void ath9k_hw_set_addac(struct ath_hal *ah,
 		biaslevel = pModal->xpaBiasLvl;
 	} else {
 
-		u_int16_t resetFreqBin, freqBin, freqCount = 0;
+		u16 resetFreqBin, freqBin, freqCount = 0;
 		struct chan_centers centers;
 
 		ath9k_hw_get_channel_centers(ah, chan, &centers);
@@ -5168,7 +5167,7 @@ static void ath9k_hw_set_addac(struct ath_hal *ah,
 		resetFreqBin =
 			FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
 		freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
-		biaslevel = (u_int8_t) (pModal->xpaBiasLvlFreq[0] >> 14);
+		biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
 
 		freqCount++;
 
@@ -5179,7 +5178,7 @@ static void ath9k_hw_set_addac(struct ath_hal *ah,
 			freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
 			if (resetFreqBin >= freqBin) {
 				biaslevel =
-					(u_int8_t) (pModal->
+					(u8) (pModal->
 						    xpaBiasLvlFreq[freqCount]
 						    >> 14);
 			} else {
@@ -5200,20 +5199,18 @@ static void ath9k_hw_set_addac(struct ath_hal *ah,
 	}
 }
 
-static u_int ath9k_hw_mac_usec(struct ath_hal *ah, u_int clks)
+static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
 {
-	const struct hal_channel *c =
-		(const struct hal_channel *) ah->ah_curchan;
-
-	if (c != NULL)
-		return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
+	if (ah->ah_curchan != NULL)
+		return clks /
+		CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
 	else
 		return clks / CLOCK_RATE[WIRELESS_MODE_11b];
 }
 
-static u_int ath9k_hw_mac_to_usec(struct ath_hal *ah, u_int clks)
+static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
 {
-	struct hal_channel_internal *chan = ah->ah_curchan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 
 	if (chan && IS_CHAN_HT40(chan))
 		return ath9k_hw_mac_usec(ah, clks) / 2;
@@ -5221,20 +5218,18 @@ static u_int ath9k_hw_mac_to_usec(struct ath_hal *ah, u_int clks)
 		return ath9k_hw_mac_usec(ah, clks);
 }
 
-static u_int ath9k_hw_mac_clks(struct ath_hal *ah, u_int usecs)
+static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
 {
-	const struct hal_channel *c =
-		(const struct hal_channel *) ah->ah_curchan;
-
-	if (c != NULL)
-		return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
+	if (ah->ah_curchan != NULL)
+		return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
+			ah->ah_curchan)];
 	else
 		return usecs * CLOCK_RATE[WIRELESS_MODE_11b];
 }
 
-static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
+static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
 {
-	struct hal_channel_internal *chan = ah->ah_curchan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 
 	if (chan && IS_CHAN_HT40(chan))
 		return ath9k_hw_mac_clks(ah, usecs) * 2;
@@ -5242,14 +5237,14 @@ static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
 		return ath9k_hw_mac_clks(ah, usecs);
 }
 
-static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
 			 __func__, us);
-		ahp->ah_acktimeout = (u_int) -1;
+		ahp->ah_acktimeout = (u32) -1;
 		return false;
 	} else {
 		REG_RMW_FIELD(ah, AR_TIME_OUT,
@@ -5259,14 +5254,14 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
 	}
 }
 
-static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
 			 __func__, us);
-		ahp->ah_ctstimeout = (u_int) -1;
+		ahp->ah_ctstimeout = (u32) -1;
 		return false;
 	} else {
 		REG_RMW_FIELD(ah, AR_TIME_OUT,
@@ -5276,14 +5271,14 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
 	}
 }
 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
-					  u_int tu)
+					  u32 tu)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (tu > 0xFFFF) {
 		DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
 			"%s: bad global tx timeout %u\n", __func__, tu);
-		ahp->ah_globaltxtimeout = (u_int) -1;
+		ahp->ah_globaltxtimeout = (u32) -1;
 		return false;
 	} else {
 		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
@@ -5292,14 +5287,14 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
 	}
 }
 
-bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
+bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	if (us < HAL_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
+	if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
 			 __func__, us);
-		ahp->ah_slottime = (u_int) -1;
+		ahp->ah_slottime = (u32) -1;
 		return false;
 	} else {
 		REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
@@ -5317,28 +5312,27 @@ static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)
 	if (ahp->ah_miscMode != 0)
 		REG_WRITE(ah, AR_PCU_MISC,
 			  REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
-	if (ahp->ah_slottime != (u_int) -1)
+	if (ahp->ah_slottime != (u32) -1)
 		ath9k_hw_setslottime(ah, ahp->ah_slottime);
-	if (ahp->ah_acktimeout != (u_int) -1)
+	if (ahp->ah_acktimeout != (u32) -1)
 		ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
-	if (ahp->ah_ctstimeout != (u_int) -1)
+	if (ahp->ah_ctstimeout != (u32) -1)
 		ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
-	if (ahp->ah_globaltxtimeout != (u_int) -1)
+	if (ahp->ah_globaltxtimeout != (u32) -1)
 		ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
 }
 
-static inline enum hal_status
+static inline int
 ath9k_hw_process_ini(struct ath_hal *ah,
-		     struct hal_channel *chan,
-		     struct hal_channel_internal *ichan,
-		     enum hal_ht_macmode macmode)
+		     struct ath9k_channel *chan,
+		     enum ath9k_ht_macmode macmode)
 {
 	int i, regWrites = 0;
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int modesIndex, freqIndex;
-	enum hal_status status;
+	u32 modesIndex, freqIndex;
+	int status;
 
-	switch (chan->channelFlags & CHANNEL_ALL) {
+	switch (chan->chanmode) {
 	case CHANNEL_A:
 	case CHANNEL_A_HT20:
 		modesIndex = 1;
@@ -5349,7 +5343,7 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 		modesIndex = 2;
 		freqIndex = 1;
 		break;
-	case CHANNEL_PUREG:
+	case CHANNEL_G:
 	case CHANNEL_G_HT20:
 	case CHANNEL_B:
 		modesIndex = 4;
@@ -5362,21 +5356,21 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 		break;
 
 	default:
-		return HAL_EINVAL;
+		return -EINVAL;
 	}
 
 	REG_WRITE(ah, AR_PHY(0), 0x00000007);
 
 	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
 
-	ath9k_hw_set_addac(ah, ichan);
+	ath9k_hw_set_addac(ah, chan);
 
 	if (AR_SREV_5416_V22_OR_LATER(ah)) {
 		REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
 	} else {
 		struct ar5416IniArray temp;
-		u_int32_t addacSize =
-			sizeof(u_int32_t) * ahp->ah_iniAddac.ia_rows *
+		u32 addacSize =
+			sizeof(u32) * ahp->ah_iniAddac.ia_rows *
 			ahp->ah_iniAddac.ia_columns;
 
 		memcpy(ahp->ah_addac5416_21,
@@ -5393,8 +5387,8 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
 
 	for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
-		u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
-		u_int32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
+		u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
+		u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
 
 #ifdef CONFIG_SLOW_ANT_DIV
 		if (ah->ah_devid == AR9280_DEVID_PCI)
@@ -5413,8 +5407,8 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 	}
 
 	for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
-		u_int32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
-		u_int32_t val = INI_RA(&ahp->ah_iniCommon, i, 1);
+		u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
+		u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
 
 		REG_WRITE(ah, reg, val);
 
@@ -5437,26 +5431,26 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 	ath9k_hw_set_regs(ah, chan, macmode);
 	ath9k_hw_init_chain_masks(ah);
 
-	status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
+	status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
 				      ath9k_regd_get_ctl(ah, chan),
 				      ath9k_regd_get_antenna_allowed(ah,
 								     chan),
-				      ichan->maxRegTxPower * 2,
-				      min((u_int32_t) MAX_RATE_POWER,
-					  (u_int32_t) ah->ah_powerLimit));
-	if (status != HAL_OK) {
+				      chan->maxRegTxPower * 2,
+				      min((u32) MAX_RATE_POWER,
+					  (u32) ah->ah_powerLimit));
+	if (status != 0) {
 		DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 			 "%s: error init'ing transmit power\n", __func__);
-		return HAL_EIO;
+		return -EIO;
 	}
 
-	if (!ath9k_hw_set_rf_regs(ah, ichan, freqIndex)) {
+	if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 			 "%s: ar5416SetRfRegs failed\n", __func__);
-		return HAL_EIO;
+		return -EIO;
 	}
 
-	return HAL_OK;
+	return 0;
 }
 
 static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
@@ -5517,8 +5511,8 @@ static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,
 
 static inline void
 ath9k_hw_per_calibration(struct ath_hal *ah,
-			 struct hal_channel_internal *ichan,
-			 u_int8_t rxchainmask,
+			 struct ath9k_channel *ichan,
+			 u8 rxchainmask,
 			 struct hal_cal_list *currCal,
 			 bool *isCalDone)
 {
@@ -5563,7 +5557,7 @@ static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
 					  int init_cal_count)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal ichan;
+	struct ath9k_channel ichan;
 	bool isCalDone;
 	struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 	const struct hal_percal_data *calData = currCal->calData;
@@ -5607,11 +5601,10 @@ static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
 
 static inline bool
 ath9k_hw_channel_change(struct ath_hal *ah,
-			struct hal_channel *chan,
-			struct hal_channel_internal *ichan,
-			enum hal_ht_macmode macmode)
+			struct ath9k_channel *chan,
+			enum ath9k_ht_macmode macmode)
 {
-	u_int32_t synthDelay, qnum;
+	u32 synthDelay, qnum;
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -5634,26 +5627,25 @@ ath9k_hw_channel_change(struct ath_hal *ah,
 	ath9k_hw_set_regs(ah, chan, macmode);
 
 	if (AR_SREV_9280_10_OR_LATER(ah)) {
-		if (!(ath9k_hw_ar9280_set_channel(ah, ichan))) {
+		if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
 			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 				 "%s: failed to set channel\n", __func__);
 			return false;
 		}
 	} else {
-		if (!(ath9k_hw_set_channel(ah, ichan))) {
+		if (!(ath9k_hw_set_channel(ah, chan))) {
 			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 				 "%s: failed to set channel\n", __func__);
 			return false;
 		}
 	}
 
-	if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
+	if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
 				 ath9k_regd_get_ctl(ah, chan),
 				 ath9k_regd_get_antenna_allowed(ah, chan),
-				 ichan->maxRegTxPower * 2,
-				 min((u_int32_t) MAX_RATE_POWER,
-				     (u_int32_t) ah->ah_powerLimit))
-	    != HAL_OK) {
+				 chan->maxRegTxPower * 2,
+				 min((u32) MAX_RATE_POWER,
+				     (u32) ah->ah_powerLimit)) != 0) {
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: error init'ing transmit power\n", __func__);
 		return false;
@@ -5670,28 +5662,28 @@ ath9k_hw_channel_change(struct ath_hal *ah,
 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 
 	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
-		ath9k_hw_set_delta_slope(ah, ichan);
+		ath9k_hw_set_delta_slope(ah, chan);
 
 	if (AR_SREV_9280_10_OR_LATER(ah))
-		ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
+		ath9k_hw_9280_spur_mitigate(ah, chan);
 	else
 		ath9k_hw_spur_mitigate(ah, chan);
 
-	if (!ichan->oneTimeCalsDone)
-		ichan->oneTimeCalsDone = true;
+	if (!chan->oneTimeCalsDone)
+		chan->oneTimeCalsDone = true;
 
 	return true;
 }
 
 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
-				struct hal_channel *chan)
+				struct ath9k_channel *chan)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM))
+	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
 		return false;
 
-	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
+	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
 		return false;
 
 	ahp->ah_chipFullSleep = false;
@@ -5705,7 +5697,7 @@ static bool ath9k_hw_chip_reset(struct ath_hal *ah,
 
 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
 {
-	u_int32_t regval;
+	u32 regval;
 
 	regval = REG_READ(ah, AR_AHB_MODE);
 	REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
@@ -5762,7 +5754,7 @@ void ath9k_hw_stoppcurecv(struct ath_hal *ah)
 }
 
 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
-				     struct hal_channel *chan,
+				     struct ath9k_channel *chan,
 				     enum hal_cal_types calType)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -5785,10 +5777,10 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
 }
 
 static inline bool ath9k_hw_init_cal(struct ath_hal *ah,
-				     struct hal_channel *chan)
+				     struct ath9k_channel *chan)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *ichan =
+	struct ath9k_channel *ichan =
 		ath9k_regd_check_channel(ah, chan);
 
 	REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -5846,22 +5838,21 @@ static inline bool ath9k_hw_init_cal(struct ath_hal *ah,
 }
 
 
-bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-		    struct hal_channel *chan,
-		    enum hal_ht_macmode macmode,
-		    u_int8_t txchainmask, u_int8_t rxchainmask,
-		    enum hal_ht_extprotspacing extprotspacing,
+bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
+		    struct ath9k_channel *chan,
+		    enum ath9k_ht_macmode macmode,
+		    u8 txchainmask, u8 rxchainmask,
+		    enum ath9k_ht_extprotspacing extprotspacing,
 		    bool bChannelChange,
-		    enum hal_status *status)
+		    int *status)
 {
 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
-	u_int32_t saveLedState;
+	u32 saveLedState;
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *ichan;
-	struct hal_channel_internal *curchan = ah->ah_curchan;
-	u_int32_t saveDefAntenna;
-	u_int32_t macStaId1;
-	enum hal_status ecode;
+	struct ath9k_channel *curchan = ah->ah_curchan;
+	u32 saveDefAntenna;
+	u32 macStaId1;
+	int ecode;
 	int i, rx_chainmask;
 
 	ahp->ah_extprotspacing = extprotspacing;
@@ -5873,15 +5864,14 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 		ahp->ah_rxchainmask &= 0x3;
 	}
 
-	ichan = ath9k_hw_check_chan(ah, chan);
-	if (ichan == NULL) {
+	if (ath9k_hw_check_chan(ah, chan) == NULL) {
 		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u/0x%x; no mapping\n",
 			 __func__, chan->channel, chan->channelFlags);
-		FAIL(HAL_EINVAL);
+		FAIL(-EINVAL);
 	}
 
-	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
+	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
 		return false;
 
 	if (curchan)
@@ -5897,14 +5887,9 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 				   !IS_CHAN_A_5MHZ_SPACED(ah->
 							  ah_curchan)))) {
 
-		if (ath9k_hw_channel_change(ah, chan, ichan, macmode)) {
-			chan->channelFlags = ichan->channelFlags;
-			chan->privFlags = ichan->privFlags;
-
+		if (ath9k_hw_channel_change(ah, chan, macmode)) {
 			ath9k_hw_loadnf(ah, ah->ah_curchan);
-
 			ath9k_hw_start_nfcal(ah);
-
 			return true;
 		}
 	}
@@ -5924,7 +5909,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 	if (!ath9k_hw_chip_reset(ah, chan)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
 			 __func__);
-		FAIL(HAL_EIO);
+		FAIL(-EIO);
 	}
 
 	if (AR_SREV_9280(ah)) {
@@ -5937,25 +5922,25 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 			else
 				ath9k_hw_set_gpio(ah, 9, 1);
 		}
-		ath9k_hw_cfg_output(ah, 9, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
+		ath9k_hw_cfg_output(ah, 9, ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT);
 	}
 
-	ecode = ath9k_hw_process_ini(ah, chan, ichan, macmode);
-	if (ecode != HAL_OK)
+	ecode = ath9k_hw_process_ini(ah, chan, macmode);
+	if (ecode != 0)
 		goto bad;
 
 	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
-		ath9k_hw_set_delta_slope(ah, ichan);
+		ath9k_hw_set_delta_slope(ah, chan);
 
 	if (AR_SREV_9280_10_OR_LATER(ah))
-		ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
+		ath9k_hw_9280_spur_mitigate(ah, chan);
 	else
 		ath9k_hw_spur_mitigate(ah, chan);
 
-	if (!ath9k_hw_eeprom_set_board_values(ah, ichan)) {
+	if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: error setting board options\n", __func__);
-		FAIL(HAL_EIO);
+		FAIL(-EIO);
 	}
 
 	ath9k_hw_decrease_chain_power(ah, chan);
@@ -5983,11 +5968,11 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
 
 	if (AR_SREV_9280_10_OR_LATER(ah)) {
-		if (!(ath9k_hw_ar9280_set_channel(ah, ichan)))
-			FAIL(HAL_EIO);
+		if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
+			FAIL(-EIO);
 	} else {
-		if (!(ath9k_hw_set_channel(ah, ichan)))
-			FAIL(HAL_EIO);
+		if (!(ath9k_hw_set_channel(ah, chan)))
+			FAIL(-EIO);
 	}
 
 	for (i = 0; i < AR_NUM_DCU; i++)
@@ -6020,7 +6005,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 	ath9k_hw_init_bb(ah, chan);
 
 	if (!ath9k_hw_init_cal(ah, chan))
-		FAIL(HAL_ESELFTEST);
+		FAIL(-ENODEV);
 
 	rx_chainmask = ahp->ah_rxchainmask;
 	if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
@@ -6031,7 +6016,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
 
 	if (AR_SREV_9100(ah)) {
-		u_int32_t mask;
+		u32 mask;
 		mask = REG_READ(ah, AR_CFG);
 		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
 			DPRINTF(ah->ah_sc, ATH_DBG_RESET,
@@ -6050,8 +6035,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 		REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
 #endif
 	}
-	chan->channelFlags = ichan->channelFlags;
-	chan->privFlags = ichan->privFlags;
+
 	return true;
 bad:
 	if (status)
@@ -6062,25 +6046,25 @@ bad:
 
 bool ath9k_hw_phy_disable(struct ath_hal *ah)
 {
-	return ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM);
+	return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
 }
 
 bool ath9k_hw_disable(struct ath_hal *ah)
 {
-	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
+	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
 		return false;
 
-	return ath9k_hw_set_reset_reg(ah, HAL_RESET_COLD);
+	return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
 }
 
 bool
-ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
-		   u_int8_t rxchainmask, bool longcal,
+ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
+		   u8 rxchainmask, bool longcal,
 		   bool *isCalDone)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
-	struct hal_channel_internal *ichan =
+	struct ath9k_channel *ichan =
 		ath9k_regd_check_channel(ah, chan);
 
 	*isCalDone = true;
@@ -6194,11 +6178,11 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
 	}
 }
 
-static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
+static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t powerMeasQ, powerMeasI, iqCorrMeas;
-	u_int32_t qCoffDenom, iCoffDenom;
+	u32 powerMeasQ, powerMeasI, iqCorrMeas;
+	u32 qCoffDenom, iCoffDenom;
 	int32_t qCoff, iCoff;
 	int iqCorrNeg, i;
 
@@ -6275,12 +6259,12 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
 }
 
 static void
-ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
+ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
+	u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
 		qEvenMeasOffset;
-	u_int32_t qGainMismatch, iGainMismatch, val, i;
+	u32 qGainMismatch, iGainMismatch, val, i;
 
 	for (i = 0; i < numChains; i++) {
 		iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
@@ -6335,14 +6319,14 @@ ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 }
 
 static void
-ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
+ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t iOddMeasOffset, iEvenMeasOffset, val, i;
+	u32 iOddMeasOffset, iEvenMeasOffset, val, i;
 	int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
 	const struct hal_percal_data *calData =
 		ahp->ah_cal_list_curr->calData;
-	u_int32_t numSamples =
+	u32 numSamples =
 		(1 << (calData->calCountMax + 5)) * calData->calNumSamples;
 
 	for (i = 0; i < numChains; i++) {
@@ -6393,22 +6377,20 @@ ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 		  AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 }
 
-bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *ichan = ah->ah_curchan;
-	struct hal_channel *chan = (struct hal_channel *) ichan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 
-	ah->ah_powerLimit = min(limit, (u_int32_t) MAX_RATE_POWER);
+	ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
 
-	if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
+	if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
 				 ath9k_regd_get_ctl(ah, chan),
 				 ath9k_regd_get_antenna_allowed(ah,
 								chan),
 				 chan->maxRegTxPower * 2,
-				 min((u_int32_t) MAX_RATE_POWER,
-				     (u_int32_t) ah->ah_powerLimit))
-	    != HAL_OK)
+				 min((u32) MAX_RATE_POWER,
+				     (u32) ah->ah_powerLimit)) != 0)
 		return false;
 
 	return true;
@@ -6416,7 +6398,7 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
 
 void
 ath9k_hw_get_channel_centers(struct ath_hal *ah,
-			     struct hal_channel_internal *chan,
+			     struct ath9k_channel *chan,
 			     struct chan_centers *centers)
 {
 	int8_t extoff;
@@ -6428,7 +6410,8 @@ ath9k_hw_get_channel_centers(struct ath_hal *ah,
 		return;
 	}
 
-	if (chan->channelFlags & CHANNEL_HT40PLUS) {
+	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
+	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 		centers->synth_center =
 			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 		extoff = 1;
@@ -6444,7 +6427,7 @@ ath9k_hw_get_channel_centers(struct ath_hal *ah,
 		((ahp->
 		ah_extprotspacing
 		==
-		HAL_HT_EXTPROTSPACING_20)
+		ATH9K_HT_EXTPROTSPACING_20)
 		?
 		HT40_CHANNEL_CENTER_SHIFT
 		: 15));
@@ -6452,11 +6435,11 @@ ath9k_hw_get_channel_centers(struct ath_hal *ah,
 }
 
 void
-ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
+ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
 			bool *isCalDone)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *ichan =
+	struct ath9k_channel *ichan =
 		ath9k_regd_check_channel(ah, chan);
 	struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 
@@ -6499,14 +6482,14 @@ ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
 	*isCalDone = false;
 }
 
-void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac)
+void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
 }
 
-bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac)
+bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -6514,7 +6497,7 @@ bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac)
 	return true;
 }
 
-void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask)
+void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -6522,7 +6505,7 @@ void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask)
 }
 
 bool
-ath9k_hw_setbssidmask(struct ath_hal *ah, const u_int8_t *mask)
+ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -6560,8 +6543,8 @@ static void ath9k_enable_rfkill(struct ath_hal *ah)
 #endif
 
 void
-ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
-		       u_int16_t assocId)
+ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
+		       u16 assocId)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -6573,9 +6556,9 @@ ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
 		  ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
 }
 
-u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah)
+u64 ath9k_hw_gettsf64(struct ath_hal *ah)
 {
-	u_int64_t tsf;
+	u64 tsf;
 
 	tsf = REG_READ(ah, AR_TSF_U32);
 	tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
@@ -6600,26 +6583,26 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
 	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
 }
 
-u_int ath9k_hw_getdefantenna(struct ath_hal *ah)
+u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
 {
 	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
 }
 
-void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna)
+void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
 {
 	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
 }
 
 bool
 ath9k_hw_setantennaswitch(struct ath_hal *ah,
-			  enum hal_ant_setting settings,
-			  struct hal_channel *chan,
-			  u_int8_t *tx_chainmask,
-			  u_int8_t *rx_chainmask,
-			  u_int8_t *antenna_cfgd)
+			  enum ath9k_ant_setting settings,
+			  struct ath9k_channel *chan,
+			  u8 *tx_chainmask,
+			  u8 *rx_chainmask,
+			  u8 *antenna_cfgd)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	static u_int8_t tx_chainmask_cfg, rx_chainmask_cfg;
+	static u8 tx_chainmask_cfg, rx_chainmask_cfg;
 
 	if (AR_SREV_9280(ah)) {
 		if (!tx_chainmask_cfg) {
@@ -6629,12 +6612,12 @@ ath9k_hw_setantennaswitch(struct ath_hal *ah,
 		}
 
 		switch (settings) {
-		case HAL_ANT_FIXED_A:
+		case ATH9K_ANT_FIXED_A:
 			*tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
 			*rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
 			*antenna_cfgd = true;
 			break;
-		case HAL_ANT_FIXED_B:
+		case ATH9K_ANT_FIXED_B:
 			if (ah->ah_caps.halTxChainMask >
 			    ATH9K_ANTENNA1_CHAINMASK) {
 				*tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
@@ -6642,7 +6625,7 @@ ath9k_hw_setantennaswitch(struct ath_hal *ah,
 			*rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
 			*antenna_cfgd = true;
 			break;
-		case HAL_ANT_VARIABLE:
+		case ATH9K_ANT_VARIABLE:
 			*tx_chainmask = tx_chainmask_cfg;
 			*rx_chainmask = rx_chainmask_cfg;
 			*antenna_cfgd = true;
@@ -6664,7 +6647,7 @@ void ath9k_hw_setopmode(struct ath_hal *ah)
 
 bool
 ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
-		       u_int32_t capability, u_int32_t *result)
+		       u32 capability, u32 *result)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	const struct hal_capabilities *pCap = &ah->ah_caps;
@@ -6672,12 +6655,12 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 	switch (type) {
 	case HAL_CAP_CIPHER:
 		switch (capability) {
-		case HAL_CIPHER_AES_CCM:
-		case HAL_CIPHER_AES_OCB:
-		case HAL_CIPHER_TKIP:
-		case HAL_CIPHER_WEP:
-		case HAL_CIPHER_MIC:
-		case HAL_CIPHER_CLR:
+		case ATH9K_CIPHER_AES_CCM:
+		case ATH9K_CIPHER_AES_OCB:
+		case ATH9K_CIPHER_TKIP:
+		case ATH9K_CIPHER_WEP:
+		case ATH9K_CIPHER_MIC:
+		case ATH9K_CIPHER_CLR:
 			return true;
 		default:
 			return false;
@@ -6695,9 +6678,9 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 		return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
 			false : true;
 	case HAL_CAP_WME_TKIPMIC:
-		return HAL_OK;
+		return 0;
 	case HAL_CAP_PHYCOUNTERS:
-		return ahp->ah_hasHwPhyCounters ? HAL_OK : HAL_ENXIO;
+		return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
 	case HAL_CAP_DIVERSITY:
 		return (REG_READ(ah, AR_PHY_CCK_DETECT) &
 			AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
@@ -6733,16 +6716,16 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 	case HAL_CAP_TXPOW:
 		switch (capability) {
 		case 0:
-			return HAL_OK;
+			return 0;
 		case 1:
 			*result = ah->ah_powerLimit;
-			return HAL_OK;
+			return 0;
 		case 2:
 			*result = ah->ah_maxPowerLevel;
-			return HAL_OK;
+			return 0;
 		case 3:
 			*result = ah->ah_tpScale;
-			return HAL_OK;
+			return 0;
 		}
 		return false;
 	default:
@@ -6750,34 +6733,33 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 	}
 }
 
-enum hal_status
-ath9k_hw_select_antconfig(struct ath_hal *ah, u_int32_t cfg)
+int
+ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_channel_internal *chan = ah->ah_curchan;
+	struct ath9k_channel *chan = ah->ah_curchan;
 	const struct hal_capabilities *pCap = &ah->ah_caps;
-	u_int16_t ant_config;
-	u_int32_t halNumAntConfig;
+	u16 ant_config;
+	u32 halNumAntConfig;
 
 	halNumAntConfig =
 		IS_CHAN_2GHZ(chan) ? pCap->halNumAntCfg2GHz : pCap->
 		halNumAntCfg5GHz;
 
 	if (cfg < halNumAntConfig) {
-		if (HAL_OK ==
-		    ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, cfg,
-						    &ant_config)) {
+		if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
+						     cfg, &ant_config)) {
 			REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
-			return HAL_OK;
+			return 0;
 		}
 	}
 
-	return HAL_EINVAL;
+	return -EINVAL;
 }
 
 bool ath9k_hw_intrpend(struct ath_hal *ah)
 {
-	u_int32_t host_isr;
+	u32 host_isr;
 
 	if (AR_SREV_9100(ah))
 		return true;
@@ -6794,12 +6776,12 @@ bool ath9k_hw_intrpend(struct ath_hal *ah)
 	return false;
 }
 
-bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
+bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
 {
-	u_int32_t isr = 0;
-	u_int32_t mask2 = 0;
+	u32 isr = 0;
+	u32 mask2 = 0;
 	struct hal_capabilities *pCap = &ah->ah_caps;
-	u_int32_t sync_cause = 0;
+	u32 sync_cause = 0;
 	bool fatal_int = false;
 
 	if (!AR_SREV_9100(ah)) {
@@ -6827,20 +6809,20 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 		struct ath_hal_5416 *ahp = AH5416(ah);
 
 		if (isr & AR_ISR_BCNMISC) {
-			u_int32_t isr2;
+			u32 isr2;
 			isr2 = REG_READ(ah, AR_ISR_S2);
 			if (isr2 & AR_ISR_S2_TIM)
-				mask2 |= HAL_INT_TIM;
+				mask2 |= ATH9K_INT_TIM;
 			if (isr2 & AR_ISR_S2_DTIM)
-				mask2 |= HAL_INT_DTIM;
+				mask2 |= ATH9K_INT_DTIM;
 			if (isr2 & AR_ISR_S2_DTIMSYNC)
-				mask2 |= HAL_INT_DTIMSYNC;
+				mask2 |= ATH9K_INT_DTIMSYNC;
 			if (isr2 & (AR_ISR_S2_CABEND))
-				mask2 |= HAL_INT_CABEND;
+				mask2 |= ATH9K_INT_CABEND;
 			if (isr2 & AR_ISR_S2_GTT)
-				mask2 |= HAL_INT_GTT;
+				mask2 |= ATH9K_INT_GTT;
 			if (isr2 & AR_ISR_S2_CST)
-				mask2 |= HAL_INT_CST;
+				mask2 |= ATH9K_INT_CST;
 		}
 
 		isr = REG_READ(ah, AR_ISR_RAC);
@@ -6849,22 +6831,22 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 			return false;
 		}
 
-		*masked = isr & HAL_INT_COMMON;
+		*masked = isr & ATH9K_INT_COMMON;
 
 		if (ahp->ah_intrMitigation) {
 
 			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
-				*masked |= HAL_INT_RX;
+				*masked |= ATH9K_INT_RX;
 		}
 
 		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
-			*masked |= HAL_INT_RX;
+			*masked |= ATH9K_INT_RX;
 		if (isr &
 		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
 		     AR_ISR_TXEOL)) {
-			u_int32_t s0_s, s1_s;
+			u32 s0_s, s1_s;
 
-			*masked |= HAL_INT_TX;
+			*masked |= ATH9K_INT_TX;
 
 			s0_s = REG_READ(ah, AR_ISR_S0_S);
 			ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
@@ -6883,9 +6865,9 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 
 		if (!AR_SREV_9100(ah)) {
 			if (!pCap->halAutoSleepSupport) {
-				u_int32_t isr5 = REG_READ(ah, AR_ISR_S5_S);
+				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
 				if (isr5 & AR_ISR_S5_TIM_TIMER)
-					*masked |= HAL_INT_TIM_TIMER;
+					*masked |= ATH9K_INT_TIM_TIMER;
 			}
 		}
 
@@ -6917,7 +6899,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 				 __func__);
 			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
 			REG_WRITE(ah, AR_RC, 0);
-			*masked |= HAL_INT_FATAL;
+			*masked |= ATH9K_INT_FATAL;
 		}
 		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
 			DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
@@ -6931,22 +6913,22 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 	return true;
 }
 
-enum hal_int ath9k_hw_intrget(struct ath_hal *ah)
+enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
 {
 	return AH5416(ah)->ah_maskReg;
 }
 
-enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
+enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t omask = ahp->ah_maskReg;
-	u_int32_t mask, mask2;
+	u32 omask = ahp->ah_maskReg;
+	u32 mask, mask2;
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
 	DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
 		 omask, ints);
 
-	if (omask & HAL_INT_GLOBAL) {
+	if (omask & ATH9K_INT_GLOBAL) {
 		DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
 			 __func__);
 		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
@@ -6960,10 +6942,10 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 		}
 	}
 
-	mask = ints & HAL_INT_COMMON;
+	mask = ints & ATH9K_INT_COMMON;
 	mask2 = 0;
 
-	if (ints & HAL_INT_TX) {
+	if (ints & ATH9K_INT_TX) {
 		if (ahp->ah_txOkInterruptMask)
 			mask |= AR_IMR_TXOK;
 		if (ahp->ah_txDescInterruptMask)
@@ -6973,7 +6955,7 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 		if (ahp->ah_txEolInterruptMask)
 			mask |= AR_IMR_TXEOL;
 	}
-	if (ints & HAL_INT_RX) {
+	if (ints & ATH9K_INT_RX) {
 		mask |= AR_IMR_RXERR;
 		if (ahp->ah_intrMitigation)
 			mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
@@ -6983,23 +6965,23 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 			mask |= AR_IMR_GENTMR;
 	}
 
-	if (ints & (HAL_INT_BMISC)) {
+	if (ints & (ATH9K_INT_BMISC)) {
 		mask |= AR_IMR_BCNMISC;
-		if (ints & HAL_INT_TIM)
+		if (ints & ATH9K_INT_TIM)
 			mask2 |= AR_IMR_S2_TIM;
-		if (ints & HAL_INT_DTIM)
+		if (ints & ATH9K_INT_DTIM)
 			mask2 |= AR_IMR_S2_DTIM;
-		if (ints & HAL_INT_DTIMSYNC)
+		if (ints & ATH9K_INT_DTIMSYNC)
 			mask2 |= AR_IMR_S2_DTIMSYNC;
-		if (ints & HAL_INT_CABEND)
+		if (ints & ATH9K_INT_CABEND)
 			mask2 |= (AR_IMR_S2_CABEND);
 	}
 
-	if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
+	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
 		mask |= AR_IMR_BCNMISC;
-		if (ints & HAL_INT_GTT)
+		if (ints & ATH9K_INT_GTT)
 			mask2 |= AR_IMR_S2_GTT;
-		if (ints & HAL_INT_CST)
+		if (ints & ATH9K_INT_CST)
 			mask2 |= AR_IMR_S2_CST;
 	}
 
@@ -7017,13 +6999,13 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 	ahp->ah_maskReg = ints;
 
 	if (!pCap->halAutoSleepSupport) {
-		if (ints & HAL_INT_TIM_TIMER)
+		if (ints & ATH9K_INT_TIM_TIMER)
 			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
 		else
 			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
 	}
 
-	if (ints & HAL_INT_GLOBAL) {
+	if (ints & ATH9K_INT_GLOBAL) {
 		DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
 			 __func__);
 		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
@@ -7047,7 +7029,7 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 
 void
 ath9k_hw_beaconinit(struct ath_hal *ah,
-		    u_int32_t next_beacon, u_int32_t beacon_period)
+		    u32 next_beacon, u32 beacon_period)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	int flags = 0;
@@ -7055,14 +7037,14 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
 	ahp->ah_beaconInterval = beacon_period;
 
 	switch (ah->ah_opmode) {
-	case HAL_M_STA:
-	case HAL_M_MONITOR:
+	case ATH9K_M_STA:
+	case ATH9K_M_MONITOR:
 		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
 		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
 		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
 		flags |= AR_TBTT_TIMER_EN;
 		break;
-	case HAL_M_IBSS:
+	case ATH9K_M_IBSS:
 		REG_SET_BIT(ah, AR_TXCFG,
 			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
 		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
@@ -7070,7 +7052,7 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
 				     (ahp->ah_atimWindow ? ahp->
 				      ah_atimWindow : 1)));
 		flags |= AR_NDP_TIMER_EN;
-	case HAL_M_HOSTAP:
+	case ATH9K_M_HOSTAP:
 		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
 		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
 			  TU_TO_USEC(next_beacon -
@@ -7090,9 +7072,9 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
 	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
 	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
 
-	beacon_period &= ~HAL_BEACON_ENA;
-	if (beacon_period & HAL_BEACON_RESET_TSF) {
-		beacon_period &= ~HAL_BEACON_RESET_TSF;
+	beacon_period &= ~ATH9K_BEACON_ENA;
+	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
+		beacon_period &= ~ATH9K_BEACON_RESET_TSF;
 		ath9k_hw_reset_tsf(ah);
 	}
 
@@ -7101,22 +7083,22 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
 
 void
 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
-			       const struct hal_beacon_state *bs)
+			       const struct ath9k_beacon_state *bs)
 {
-	u_int32_t nextTbtt, beaconintval, dtimperiod, beacontimeout;
+	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
 	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
 
 	REG_WRITE(ah, AR_BEACON_PERIOD,
-		  TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
+		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
 	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
-		  TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
+		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
 
 	REG_RMW_FIELD(ah, AR_RSSI_THR,
 		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
 
-	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
+	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
 
 	if (bs->bs_sleepduration > beaconintval)
 		beaconintval = bs->bs_sleepduration;
@@ -7164,19 +7146,19 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 
 }
 
-bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry)
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
 {
 	if (entry < ah->ah_caps.halKeyCacheSize) {
-		u_int32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
+		u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
 		if (val & AR_KEYTABLE_VALID)
 			return true;
 	}
 	return false;
 }
 
-bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
+bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
 {
-	u_int32_t keyType;
+	u32 keyType;
 
 	if (entry >= ah->ah_caps.halKeyCacheSize) {
 		DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
@@ -7195,7 +7177,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
 	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
 
 	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
-		u_int16_t micentry = entry + 64;
+		u16 micentry = entry + 64;
 
 		REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
 		REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
@@ -7211,10 +7193,10 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
 }
 
 bool
-ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
-		   const u_int8_t *mac)
+ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
+		   const u8 *mac)
 {
-	u_int32_t macHi, macLo;
+	u32 macHi, macLo;
 
 	if (entry >= ah->ah_caps.halKeyCacheSize) {
 		DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
@@ -7239,14 +7221,14 @@ ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
 }
 
 bool
-ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
-			    const struct hal_keyval *k,
-			    const u_int8_t *mac, int xorKey)
+ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
+			    const struct ath9k_keyval *k,
+			    const u8 *mac, int xorKey)
 {
 	const struct hal_capabilities *pCap = &ah->ah_caps;
-	u_int32_t key0, key1, key2, key3, key4;
-	u_int32_t keyType;
-	u_int32_t xorMask = xorKey ?
+	u32 key0, key1, key2, key3, key4;
+	u32 keyType;
+	u32 xorMask = xorKey ?
 		(ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
 		 | ATH9K_KEY_XOR) : 0;
 	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -7257,10 +7239,10 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		return false;
 	}
 	switch (k->kv_type) {
-	case HAL_CIPHER_AES_OCB:
+	case ATH9K_CIPHER_AES_OCB:
 		keyType = AR_KEYTABLE_TYPE_AES;
 		break;
-	case HAL_CIPHER_AES_CCM:
+	case ATH9K_CIPHER_AES_CCM:
 		if (!pCap->halCipherAesCcmSupport) {
 			DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 				 "%s: AES-CCM not supported by "
@@ -7270,7 +7252,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		}
 		keyType = AR_KEYTABLE_TYPE_CCM;
 		break;
-	case HAL_CIPHER_TKIP:
+	case ATH9K_CIPHER_TKIP:
 		keyType = AR_KEYTABLE_TYPE_TKIP;
 		if (ATH9K_IS_MIC_ENABLED(ah)
 		    && entry + 64 >= pCap->halKeyCacheSize) {
@@ -7280,7 +7262,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 			return false;
 		}
 		break;
-	case HAL_CIPHER_WEP:
+	case ATH9K_CIPHER_WEP:
 		if (k->kv_len < 40 / NBBY) {
 			DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 				 "%s: WEP key length %u too small\n",
@@ -7294,7 +7276,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		else
 			keyType = AR_KEYTABLE_TYPE_128;
 		break;
-	case HAL_CIPHER_CLR:
+	case ATH9K_CIPHER_CLR:
 		keyType = AR_KEYTABLE_TYPE_CLR;
 		break;
 	default:
@@ -7313,7 +7295,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		key4 &= 0xff;
 
 	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
-		u_int16_t micentry = entry + 64;
+		u16 micentry = entry + 64;
 
 		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
 		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
@@ -7324,7 +7306,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		(void) ath9k_hw_keysetmac(ah, entry, mac);
 
 		if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
-			u_int32_t mic0, mic1, mic2, mic3, mic4;
+			u32 mic0, mic1, mic2, mic3, mic4;
 
 			mic0 = LE_READ_4(k->kv_mic + 0);
 			mic2 = LE_READ_4(k->kv_mic + 4);
@@ -7340,7 +7322,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 				  AR_KEYTABLE_TYPE_CLR);
 
 		} else {
-			u_int32_t mic0, mic2;
+			u32 mic0, mic2;
 
 			mic0 = LE_READ_4(k->kv_mic + 0);
 			mic2 = LE_READ_4(k->kv_mic + 4);
@@ -7377,13 +7359,14 @@ bool
 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t txcfg, curLevel, newLevel;
-	enum hal_int omask;
+	u32 txcfg, curLevel, newLevel;
+	enum ath9k_int omask;
 
 	if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
 		return false;
 
-	omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~HAL_INT_GLOBAL);
+	omask = ath9k_hw_set_interrupts(ah,
+					ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
 
 	txcfg = REG_READ(ah, AR_TXCFG);
 	curLevel = MS(txcfg, AR_FTRIG);
@@ -7405,12 +7388,12 @@ ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
 }
 
 static bool ath9k_hw_set_txq_props(struct ath_hal *ah,
-				   struct hal_tx_queue_info *qi,
-				   const struct hal_txq_info *qInfo)
+				   struct ath9k_tx_queue_info *qi,
+				   const struct ath9k_txq_info *qInfo)
 {
-	u_int32_t cw;
+	u32 cw;
 
-	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
 			 __func__);
 		return false;
@@ -7422,18 +7405,18 @@ static bool ath9k_hw_set_txq_props(struct ath_hal *ah,
 	qi->tqi_subtype = qInfo->tqi_subtype;
 	qi->tqi_qflags = qInfo->tqi_qflags;
 	qi->tqi_priority = qInfo->tqi_priority;
-	if (qInfo->tqi_aifs != HAL_TXQ_USEDEFAULT)
+	if (qInfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
 		qi->tqi_aifs = min(qInfo->tqi_aifs, 255U);
 	else
 		qi->tqi_aifs = INIT_AIFS;
-	if (qInfo->tqi_cwmin != HAL_TXQ_USEDEFAULT) {
+	if (qInfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
 		cw = min(qInfo->tqi_cwmin, 1024U);
 		qi->tqi_cwmin = 1;
 		while (qi->tqi_cwmin < cw)
 			qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
 	} else
 		qi->tqi_cwmin = qInfo->tqi_cwmin;
-	if (qInfo->tqi_cwmax != HAL_TXQ_USEDEFAULT) {
+	if (qInfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
 		cw = min(qInfo->tqi_cwmax, 1024U);
 		qi->tqi_cwmax = 1;
 		while (qi->tqi_cwmax < cw)
@@ -7442,11 +7425,11 @@ static bool ath9k_hw_set_txq_props(struct ath_hal *ah,
 		qi->tqi_cwmax = INIT_CWMAX;
 
 	if (qInfo->tqi_shretry != 0)
-		qi->tqi_shretry = min((u_int32_t) qInfo->tqi_shretry, 15U);
+		qi->tqi_shretry = min((u32) qInfo->tqi_shretry, 15U);
 	else
 		qi->tqi_shretry = INIT_SH_RETRY;
 	if (qInfo->tqi_lgretry != 0)
-		qi->tqi_lgretry = min((u_int32_t) qInfo->tqi_lgretry, 15U);
+		qi->tqi_lgretry = min((u32) qInfo->tqi_lgretry, 15U);
 	else
 		qi->tqi_lgretry = INIT_LG_RETRY;
 	qi->tqi_cbrPeriod = qInfo->tqi_cbrPeriod;
@@ -7455,9 +7438,9 @@ static bool ath9k_hw_set_txq_props(struct ath_hal *ah,
 	qi->tqi_readyTime = qInfo->tqi_readyTime;
 
 	switch (qInfo->tqi_subtype) {
-	case HAL_WME_UPSD:
-		if (qi->tqi_type == HAL_TX_QUEUE_DATA)
-			qi->tqi_intFlags = HAL_TXQ_USE_LOCKOUT_BKOFF_DIS;
+	case ATH9K_WME_UPSD:
+		if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
+			qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
 		break;
 	default:
 		break;
@@ -7466,7 +7449,7 @@ static bool ath9k_hw_set_txq_props(struct ath_hal *ah,
 }
 
 bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
-			      const struct hal_txq_info *qInfo)
+			      const struct ath9k_txq_info *qInfo)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
@@ -7480,10 +7463,10 @@ bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
 }
 
 static bool ath9k_hw_get_txq_props(struct ath_hal *ah,
-				   struct hal_txq_info *qInfo,
-				   const struct hal_tx_queue_info *qi)
+				   struct ath9k_txq_info *qInfo,
+				   const struct ath9k_tx_queue_info *qi)
 {
-	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
 			 __func__);
 		return false;
@@ -7509,7 +7492,7 @@ static bool ath9k_hw_get_txq_props(struct ath_hal *ah,
 
 bool
 ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
-			 struct hal_txq_info *qInfo)
+			 struct ath9k_txq_info *qInfo)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
@@ -7523,31 +7506,31 @@ ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
 }
 
 int
-ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
-		      const struct hal_txq_info *qInfo)
+ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
+		      const struct ath9k_txq_info *qInfo)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	struct hal_tx_queue_info *qi;
+	struct ath9k_tx_queue_info *qi;
 	struct hal_capabilities *pCap = &ah->ah_caps;
 	int q;
 
 	switch (type) {
-	case HAL_TX_QUEUE_BEACON:
+	case ATH9K_TX_QUEUE_BEACON:
 		q = pCap->halTotalQueues - 1;
 		break;
-	case HAL_TX_QUEUE_CAB:
+	case ATH9K_TX_QUEUE_CAB:
 		q = pCap->halTotalQueues - 2;
 		break;
-	case HAL_TX_QUEUE_PSPOLL:
+	case ATH9K_TX_QUEUE_PSPOLL:
 		q = 1;
 		break;
-	case HAL_TX_QUEUE_UAPSD:
+	case ATH9K_TX_QUEUE_UAPSD:
 		q = pCap->halTotalQueues - 3;
 		break;
-	case HAL_TX_QUEUE_DATA:
+	case ATH9K_TX_QUEUE_DATA:
 		for (q = 0; q < pCap->halTotalQueues; q++)
 			if (ahp->ah_txq[q].tqi_type ==
-			    HAL_TX_QUEUE_INACTIVE)
+			    ATH9K_TX_QUEUE_INACTIVE)
 				break;
 		if (q == pCap->halTotalQueues) {
 			DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
@@ -7564,12 +7547,12 @@ ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
 	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
 
 	qi = &ahp->ah_txq[q];
-	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
+	if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 			 "%s: tx queue %u already active\n", __func__, q);
 		return -1;
 	}
-	memset(qi, 0, sizeof(struct hal_tx_queue_info));
+	memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
 	qi->tqi_type = type;
 	if (qInfo == NULL) {
 		qi->tqi_qflags =
@@ -7577,7 +7560,7 @@ ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
 			| TXQ_FLAG_TXERRINT_ENABLE
 			| TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
 		qi->tqi_aifs = INIT_AIFS;
-		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;
+		qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
 		qi->tqi_cwmax = INIT_CWMAX;
 		qi->tqi_shretry = INIT_SH_RETRY;
 		qi->tqi_lgretry = INIT_LG_RETRY;
@@ -7592,7 +7575,7 @@ ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
 
 static void
 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
-			    struct hal_tx_queue_info *qi)
+			    struct ath9k_tx_queue_info *qi)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -7612,11 +7595,11 @@ ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
 		      AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
 }
 
-bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
-	struct hal_tx_queue_info *qi;
+	struct ath9k_tx_queue_info *qi;
 
 	if (q >= pCap->halTotalQueues) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
@@ -7624,7 +7607,7 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
 		return false;
 	}
 	qi = &ahp->ah_txq[q];
-	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
 			 __func__, q);
 		return false;
@@ -7633,7 +7616,7 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
 	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
 		__func__, q);
 
-	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
+	qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
 	ahp->ah_txOkInterruptMask &= ~(1 << q);
 	ahp->ah_txErrInterruptMask &= ~(1 << q);
 	ahp->ah_txDescInterruptMask &= ~(1 << q);
@@ -7644,13 +7627,13 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
 	return true;
 }
 
-bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
-	struct hal_channel_internal *chan = ah->ah_curchan;
-	struct hal_tx_queue_info *qi;
-	u_int32_t cwMin, chanCwMin, value;
+	struct ath9k_channel *chan = ah->ah_curchan;
+	struct ath9k_tx_queue_info *qi;
+	u32 cwMin, chanCwMin, value;
 
 	if (q >= pCap->halTotalQueues) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
@@ -7658,7 +7641,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 		return false;
 	}
 	qi = &ahp->ah_txq[q];
-	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
 			 __func__, q);
 		return true;
@@ -7666,7 +7649,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 
 	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
 
-	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
+	if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
 		if (chan && IS_CHAN_B(chan))
 			chanCwMin = INIT_CWMIN_11B;
 		else
@@ -7705,7 +7688,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 					:
 					0));
 	}
-	if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
+	if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
 		REG_WRITE(ah, AR_QRDYTIMECFG(q),
 			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
 			  AR_Q_RDYTIMECFG_EN);
@@ -7735,7 +7718,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 			  AR_D_MISC_FRAG_BKOFF_EN);
 	}
 	switch (qi->tqi_type) {
-	case HAL_TX_QUEUE_BEACON:
+	case ATH9K_TX_QUEUE_BEACON:
 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
 			  | AR_Q_MISC_FSP_DBA_GATED
 			  | AR_Q_MISC_BEACON_USE
@@ -7747,7 +7730,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 			  | AR_D_MISC_BEACON_USE
 			  | AR_D_MISC_POST_FR_BKOFF_DIS);
 		break;
-	case HAL_TX_QUEUE_CAB:
+	case ATH9K_TX_QUEUE_CAB:
 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
 			  | AR_Q_MISC_FSP_DBA_GATED
 			  | AR_Q_MISC_CBR_INCR_DIS1
@@ -7764,12 +7747,12 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 			  | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
 			     AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
 		break;
-	case HAL_TX_QUEUE_PSPOLL:
+	case ATH9K_TX_QUEUE_PSPOLL:
 		REG_WRITE(ah, AR_QMISC(q),
 			  REG_READ(ah,
 				   AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
 		break;
-	case HAL_TX_QUEUE_UAPSD:
+	case ATH9K_TX_QUEUE_UAPSD:
 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
 			  | AR_D_MISC_POST_FR_BKOFF_DIS);
 		break;
@@ -7777,7 +7760,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 		break;
 	}
 
-	if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
+	if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
 		REG_WRITE(ah, AR_DMISC(q),
 			  REG_READ(ah, AR_DMISC(q)) |
 			  SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
@@ -7810,7 +7793,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 	return true;
 }
 
-void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
+void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	*txqs &= ahp->ah_intrTxqs;
@@ -7819,7 +7802,7 @@ void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
 
 bool
 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
-		    u_int segLen, bool firstSeg,
+		    u32 segLen, bool firstSeg,
 		    bool lastSeg, const struct ath_desc *ds0)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
@@ -7856,13 +7839,13 @@ void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
 	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
 }
 
-enum hal_status
+int
 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 
 	if ((ads->ds_txstatus9 & AR_TxDone) == 0)
-		return HAL_EINPROGRESS;
+		return -EINPROGRESS;
 
 	ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
 	ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
@@ -7927,13 +7910,13 @@ ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
 	ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
 	ds->ds_txstat.ts_antenna = 1;
 
-	return HAL_OK;
+	return 0;
 }
 
 void
 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
-		       u_int pktLen, enum hal_pkt_type type, u_int txPower,
-		       u_int keyIx, enum hal_key_type keyType, u_int flags)
+		       u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
+		       u32 keyIx, enum ath9k_key_type keyType, u32 flags)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -7943,19 +7926,19 @@ ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
 		txPower = 63;
 
 	ads->ds_ctl0 = (pktLen & AR_FrameLen)
-		| (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
+		| (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
 		| SM(txPower, AR_XmitPower)
-		| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
-		| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
-		| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
-		| (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
+		| (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
+		| (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
+		| (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
+		| (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
 
 	ads->ds_ctl1 =
-		(keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
+		(keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
 		| SM(type, AR_FrameType)
-		| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
-		| (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
-		| (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
+		| (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
+		| (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
+		| (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
 
 	ads->ds_ctl6 = SM(keyType, AR_EncrType);
 
@@ -7971,22 +7954,22 @@ ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
 void
 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 			     struct ath_desc *lastds,
-			     u_int durUpdateEn, u_int rtsctsRate,
-			     u_int rtsctsDuration,
-			     struct hal_11n_rate_series series[],
-			     u_int nseries, u_int flags)
+			     u32 durUpdateEn, u32 rtsctsRate,
+			     u32 rtsctsDuration,
+			     struct ath9k_11n_rate_series series[],
+			     u32 nseries, u32 flags)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 	struct ar5416_desc *last_ads = AR5416DESC(lastds);
-	u_int32_t ds_ctl0;
+	u32 ds_ctl0;
 
 	(void) nseries;
 	(void) rtsctsDuration;
 
-	if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
+	if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
 		ds_ctl0 = ads->ds_ctl0;
 
-		if (flags & HAL_TXDESC_RTSENA) {
+		if (flags & ATH9K_TXDESC_RTSENA) {
 			ds_ctl0 &= ~AR_CTSEnable;
 			ds_ctl0 |= AR_RTSEnable;
 		} else {
@@ -8029,7 +8012,7 @@ ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 
 void
 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
-			   u_int aggrLen)
+			   u32 aggrLen)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 
@@ -8041,7 +8024,7 @@ ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
 
 void
 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
-			    u_int numDelims)
+			    u32 numDelims)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 	unsigned int ctl6;
@@ -8072,7 +8055,7 @@ void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
 
 void
 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
-			      u_int burstDuration)
+			      u32 burstDuration)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 
@@ -8082,7 +8065,7 @@ ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
 
 void
 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
-				u_int vmf)
+				u32 vmf)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 
@@ -8092,7 +8075,7 @@ ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
 		ads->ds_ctl0 &= ~AR_VirtMoreFrag;
 }
 
-void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp)
+void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp)
 {
 	REG_WRITE(ah, AR_RXDP, rxdp);
 }
@@ -8111,7 +8094,7 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
 
 		if (!ath9k_hw_wait
 		    (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
-			u_int32_t reg;
+			u32 reg;
 
 			REG_CLR_BIT(ah, AR_DIAG_SW,
 				    (AR_DIAG_RX_DIS |
@@ -8133,8 +8116,8 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
 }
 
 void
-ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
-			u_int32_t filter1)
+ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
+			u32 filter1)
 {
 	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
 	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
@@ -8142,13 +8125,13 @@ ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
 
 bool
 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
-		     u_int32_t size, u_int flags)
+		     u32 size, u32 flags)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
 	ads->ds_ctl1 = size & AR_BufLen;
-	if (flags & HAL_RXDESC_INTREQ)
+	if (flags & ATH9K_RXDESC_INTREQ)
 		ads->ds_ctl1 |= AR_RxIntrReq;
 
 	ads->ds_rxstatus8 &= ~AR_RxDone;
@@ -8157,15 +8140,15 @@ ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
 	return true;
 }
 
-enum hal_status
+int
 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
-		    u_int32_t pa, struct ath_desc *nds, u_int64_t tsf)
+		    u32 pa, struct ath_desc *nds, u64 tsf)
 {
 	struct ar5416_desc ads;
 	struct ar5416_desc *adsp = AR5416DESC(ds);
 
 	if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
-		return HAL_EINPROGRESS;
+		return -EINPROGRESS;
 
 	ads.u.rx = adsp->u.rx;
 
@@ -8185,7 +8168,7 @@ ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
 	if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
 		ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
 	else
-		ds->ds_rxstat.rs_keyix = HAL_RXKEYIX_INVALID;
+		ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
 
 	ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
 	ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
@@ -8211,7 +8194,7 @@ ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
 		if (ads.ds_rxstatus8 & AR_CRCErr)
 			ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
 		else if (ads.ds_rxstatus8 & AR_PHYErr) {
-			u_int phyerr;
+			u32 phyerr;
 
 			ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
 			phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
@@ -8222,21 +8205,21 @@ ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
 			ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
 	}
 
-	return HAL_OK;
+	return 0;
 }
 
 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
-				      struct hal_rate_table *rt)
+				      struct ath9k_rate_table *rt)
 {
 	int i;
 
 	if (rt->rateCodeToIndex[0] != 0)
 		return;
 	for (i = 0; i < 256; i++)
-		rt->rateCodeToIndex[i] = (u_int8_t) -1;
+		rt->rateCodeToIndex[i] = (u8) -1;
 	for (i = 0; i < rt->rateCount; i++) {
-		u_int8_t code = rt->info[i].rateCode;
-		u_int8_t cix = rt->info[i].controlRate;
+		u8 code = rt->info[i].rateCode;
+		u8 cix = rt->info[i].controlRate;
 
 		rt->rateCodeToIndex[code] = i;
 		rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
@@ -8254,10 +8237,10 @@ static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
 	}
 }
 
-const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
-						   u_int mode)
+const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
+						   u32 mode)
 {
-	struct hal_rate_table *rt;
+	struct ath9k_rate_table *rt;
 	switch (mode) {
 	case ATH9K_MODE_SEL_11A:
 		rt = &ar5416_11a_table;
@@ -8287,7 +8270,7 @@ const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
 	return rt;
 }
 
-static const char *ath9k_hw_devname(u_int16_t devid)
+static const char *ath9k_hw_devname(u16 devid)
 {
 	switch (devid) {
 	case AR5416_DEVID_PCI:
@@ -8302,16 +8285,16 @@ static const char *ath9k_hw_devname(u_int16_t devid)
 	return NULL;
 }
 
-const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid)
+const char *ath9k_hw_probe(u16 vendorid, u16 devid)
 {
 	return vendorid == ATHEROS_VENDOR_ID ?
 		ath9k_hw_devname(devid) : NULL;
 }
 
-struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+struct ath_hal *ath9k_hw_attach(u16 devid,
 				struct ath_softc *sc,
 				void __iomem *mem,
-				enum hal_status *error)
+				int *error)
 {
 	struct ath_hal *ah = NULL;
 
@@ -8327,7 +8310,7 @@ struct ath_hal *ath9k_hw_attach(u_int16_t devid,
 		DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 			 "devid=0x%x not supported.\n", devid);
 		ah = NULL;
-		*error = HAL_ENXIO;
+		*error = -ENXIO;
 		break;
 	}
 	if (ah != NULL) {
@@ -8342,14 +8325,14 @@ struct ath_hal *ath9k_hw_attach(u_int16_t devid,
 	return ah;
 }
 
-u_int16_t
+u16
 ath9k_hw_computetxtime(struct ath_hal *ah,
-		       const struct hal_rate_table *rates,
-		       u_int32_t frameLen, u_int16_t rateix,
+		       const struct ath9k_rate_table *rates,
+		       u32 frameLen, u16 rateix,
 		       bool shortPreamble)
 {
-	u_int32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
-	u_int32_t kbps;
+	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
+	u32 kbps;
 
 	kbps = rates->info[rateix].rateKbps;
 
@@ -8405,7 +8388,7 @@ ath9k_hw_computetxtime(struct ath_hal *ah,
 	return txTime;
 }
 
-u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
+u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 {
 	if (flags & CHANNEL_2GHZ) {
 		if (freq == 2484)
@@ -8446,9 +8429,9 @@ u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
 }
 
 int16_t
-ath9k_hw_getchan_noise(struct ath_hal *ah, struct hal_channel *chan)
+ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
 {
-	struct hal_channel_internal *ichan;
+	struct ath9k_channel *ichan;
 
 	ichan = ath9k_regd_check_channel(ah, chan);
 	if (ichan == NULL) {
@@ -8464,7 +8447,7 @@ ath9k_hw_getchan_noise(struct ath_hal *ah, struct hal_channel *chan)
 		return ichan->rawNoiseFloor;
 }
 
-bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u_int32_t setting)
+bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -8482,20 +8465,20 @@ bool ath9k_hw_phycounters(struct ath_hal *ah)
 	return ahp->ah_hasHwPhyCounters ? true : false;
 }
 
-u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q)
+u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q)
 {
 	return REG_READ(ah, AR_QTXDP(q));
 }
 
-bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
-		       u_int32_t txdp)
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
+		       u32 txdp)
 {
 	REG_WRITE(ah, AR_QTXDP(q), txdp);
 
 	return true;
 }
 
-bool ath9k_hw_txstart(struct ath_hal *ah, u_int q)
+bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
 {
 	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
 
@@ -8504,9 +8487,9 @@ bool ath9k_hw_txstart(struct ath_hal *ah, u_int q)
 	return true;
 }
 
-u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q)
+u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
 {
-	u_int32_t npend;
+	u32 npend;
 
 	npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
 	if (npend == 0) {
@@ -8517,9 +8500,9 @@ u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q)
 	return npend;
 }
 
-bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
 {
-	u_int wait;
+	u32 wait;
 
 	REG_WRITE(ah, AR_Q_TXD, 1 << q);
 
@@ -8530,7 +8513,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
 	}
 
 	if (ath9k_hw_numtxpending(ah, q)) {
-		u_int32_t tsfLow, j;
+		u32 tsfLow, j;
 
 		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 			 "%s: Num of pending TX Frames %d on Q %d\n",
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/hw.h b/package/ath9k/src/drivers/net/wireless/ath9k/hw.h
index 1a77ed3b1..ae680f21b 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/hw.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/hw.h
@@ -21,43 +21,43 @@
 #include <linux/delay.h>
 
 struct ar5416_desc {
-	u_int32_t ds_link;
-	u_int32_t ds_data;
-	u_int32_t ds_ctl0;
-	u_int32_t ds_ctl1;
+	u32 ds_link;
+	u32 ds_data;
+	u32 ds_ctl0;
+	u32 ds_ctl1;
 	union {
 		struct {
-			u_int32_t ctl2;
-			u_int32_t ctl3;
-			u_int32_t ctl4;
-			u_int32_t ctl5;
-			u_int32_t ctl6;
-			u_int32_t ctl7;
-			u_int32_t ctl8;
-			u_int32_t ctl9;
-			u_int32_t ctl10;
-			u_int32_t ctl11;
-			u_int32_t status0;
-			u_int32_t status1;
-			u_int32_t status2;
-			u_int32_t status3;
-			u_int32_t status4;
-			u_int32_t status5;
-			u_int32_t status6;
-			u_int32_t status7;
-			u_int32_t status8;
-			u_int32_t status9;
+			u32 ctl2;
+			u32 ctl3;
+			u32 ctl4;
+			u32 ctl5;
+			u32 ctl6;
+			u32 ctl7;
+			u32 ctl8;
+			u32 ctl9;
+			u32 ctl10;
+			u32 ctl11;
+			u32 status0;
+			u32 status1;
+			u32 status2;
+			u32 status3;
+			u32 status4;
+			u32 status5;
+			u32 status6;
+			u32 status7;
+			u32 status8;
+			u32 status9;
 		} tx;
 		struct {
-			u_int32_t status0;
-			u_int32_t status1;
-			u_int32_t status2;
-			u_int32_t status3;
-			u_int32_t status4;
-			u_int32_t status5;
-			u_int32_t status6;
-			u_int32_t status7;
-			u_int32_t status8;
+			u32 status0;
+			u32 status1;
+			u32 status2;
+			u32 status3;
+			u32 status4;
+			u32 status5;
+			u32 status6;
+			u32 status7;
+			u32 status8;
 		} rx;
 	} u;
 } __packed;
@@ -326,13 +326,13 @@ struct ar5416_desc {
 
 #define set11nPktDurRTSCTS(_series, _index)				\
 	(SM((_series)[_index].PktDuration, AR_PacketDur##_index) |	\
-	((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS   ?	\
+	((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS   ?	\
 		AR_RTSCTSQual##_index : 0))
 
 #define set11nRateFlags(_series, _index)				\
-	(((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? \
+	(((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
 		AR_2040_##_index : 0) \
-	|((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? \
+	|((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
 		AR_GI##_index : 0) \
 	|SM((_series)[_index].ChSel, AR_ChainSel##_index))
 
@@ -350,27 +350,27 @@ struct ar5416_desc {
 #define CCK_OFDM_GAIN_DELTA         15
 
 struct ar5416AniState {
-	struct hal_channel c;
-	u_int8_t noiseImmunityLevel;
-	u_int8_t spurImmunityLevel;
-	u_int8_t firstepLevel;
-	u_int8_t ofdmWeakSigDetectOff;
-	u_int8_t cckWeakSigThreshold;
-	u_int32_t listenTime;
-	u_int32_t ofdmTrigHigh;
-	u_int32_t ofdmTrigLow;
+	struct ath9k_channel c;
+	u8 noiseImmunityLevel;
+	u8 spurImmunityLevel;
+	u8 firstepLevel;
+	u8 ofdmWeakSigDetectOff;
+	u8 cckWeakSigThreshold;
+	u32 listenTime;
+	u32 ofdmTrigHigh;
+	u32 ofdmTrigLow;
 	int32_t cckTrigHigh;
 	int32_t cckTrigLow;
 	int32_t rssiThrLow;
 	int32_t rssiThrHigh;
-	u_int32_t noiseFloor;
-	u_int32_t txFrameCount;
-	u_int32_t rxFrameCount;
-	u_int32_t cycleCount;
-	u_int32_t ofdmPhyErrCount;
-	u_int32_t cckPhyErrCount;
-	u_int32_t ofdmPhyErrBase;
-	u_int32_t cckPhyErrBase;
+	u32 noiseFloor;
+	u32 txFrameCount;
+	u32 rxFrameCount;
+	u32 cycleCount;
+	u32 ofdmPhyErrCount;
+	u32 cckPhyErrCount;
+	u32 ofdmPhyErrBase;
+	u32 cckPhyErrBase;
 	int16_t pktRssi[2];
 	int16_t ofdmErrRssi[2];
 	int16_t cckErrRssi[2];
@@ -384,23 +384,23 @@ struct ar5416AniState {
     ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
 
 struct ar5416Stats {
-	u_int32_t ast_ani_niup;
-	u_int32_t ast_ani_nidown;
-	u_int32_t ast_ani_spurup;
-	u_int32_t ast_ani_spurdown;
-	u_int32_t ast_ani_ofdmon;
-	u_int32_t ast_ani_ofdmoff;
-	u_int32_t ast_ani_cckhigh;
-	u_int32_t ast_ani_ccklow;
-	u_int32_t ast_ani_stepup;
-	u_int32_t ast_ani_stepdown;
-	u_int32_t ast_ani_ofdmerrs;
-	u_int32_t ast_ani_cckerrs;
-	u_int32_t ast_ani_reset;
-	u_int32_t ast_ani_lzero;
-	u_int32_t ast_ani_lneg;
-	struct hal_mib_stats ast_mibstats;
-	struct hal_node_stats ast_nodestats;
+	u32 ast_ani_niup;
+	u32 ast_ani_nidown;
+	u32 ast_ani_spurup;
+	u32 ast_ani_spurdown;
+	u32 ast_ani_ofdmon;
+	u32 ast_ani_ofdmoff;
+	u32 ast_ani_cckhigh;
+	u32 ast_ani_ccklow;
+	u32 ast_ani_stepup;
+	u32 ast_ani_stepdown;
+	u32 ast_ani_ofdmerrs;
+	u32 ast_ani_cckerrs;
+	u32 ast_ani_reset;
+	u32 ast_ani_lzero;
+	u32 ast_ani_lneg;
+	struct ath9k_mib_stats ast_mibstats;
+	struct ath9k_node_stats ast_nodestats;
 };
 
 #define AR5416_OPFLAGS_11A           0x01
@@ -495,100 +495,100 @@ enum ar5416_rates {
 };
 
 struct base_eep_header {
-	u_int16_t length;
-	u_int16_t checksum;
-	u_int16_t version;
-	u_int8_t opCapFlags;
-	u_int8_t eepMisc;
-	u_int16_t regDmn[2];
-	u_int8_t macAddr[6];
-	u_int8_t rxMask;
-	u_int8_t txMask;
-	u_int16_t rfSilent;
-	u_int16_t blueToothOptions;
-	u_int16_t deviceCap;
-	u_int32_t binBuildNumber;
-	u_int8_t deviceType;
-	u_int8_t pwdclkind;
-	u_int8_t futureBase[32];
+	u16 length;
+	u16 checksum;
+	u16 version;
+	u8 opCapFlags;
+	u8 eepMisc;
+	u16 regDmn[2];
+	u8 macAddr[6];
+	u8 rxMask;
+	u8 txMask;
+	u16 rfSilent;
+	u16 blueToothOptions;
+	u16 deviceCap;
+	u32 binBuildNumber;
+	u8 deviceType;
+	u8 pwdclkind;
+	u8 futureBase[32];
 } __packed;
 
 struct spur_chan {
-	u_int16_t spurChan;
-	u_int8_t spurRangeLow;
-	u_int8_t spurRangeHigh;
+	u16 spurChan;
+	u8 spurRangeLow;
+	u8 spurRangeHigh;
 } __packed;
 
 struct modal_eep_header {
-	u_int32_t antCtrlChain[AR5416_MAX_CHAINS];
-	u_int32_t antCtrlCommon;
-	u_int8_t antennaGainCh[AR5416_MAX_CHAINS];
-	u_int8_t switchSettling;
-	u_int8_t txRxAttenCh[AR5416_MAX_CHAINS];
-	u_int8_t rxTxMarginCh[AR5416_MAX_CHAINS];
-	u_int8_t adcDesiredSize;
-	u_int8_t pgaDesiredSize;
-	u_int8_t xlnaGainCh[AR5416_MAX_CHAINS];
-	u_int8_t txEndToXpaOff;
-	u_int8_t txEndToRxOn;
-	u_int8_t txFrameToXpaOn;
-	u_int8_t thresh62;
-	u_int8_t noiseFloorThreshCh[AR5416_MAX_CHAINS];
-	u_int8_t xpdGain;
-	u_int8_t xpd;
-	u_int8_t iqCalICh[AR5416_MAX_CHAINS];
-	u_int8_t iqCalQCh[AR5416_MAX_CHAINS];
-	u_int8_t pdGainOverlap;
-	u_int8_t ob;
-	u_int8_t db;
-	u_int8_t xpaBiasLvl;
-	u_int8_t pwrDecreaseFor2Chain;
-	u_int8_t pwrDecreaseFor3Chain;
-	u_int8_t txFrameToDataStart;
-	u_int8_t txFrameToPaOn;
-	u_int8_t ht40PowerIncForPdadc;
-	u_int8_t bswAtten[AR5416_MAX_CHAINS];
-	u_int8_t bswMargin[AR5416_MAX_CHAINS];
-	u_int8_t swSettleHt40;
-	u_int8_t xatten2Db[AR5416_MAX_CHAINS];
-	u_int8_t xatten2Margin[AR5416_MAX_CHAINS];
-	u_int8_t ob_ch1;
-	u_int8_t db_ch1;
-	u_int8_t useAnt1:1,
+	u32 antCtrlChain[AR5416_MAX_CHAINS];
+	u32 antCtrlCommon;
+	u8 antennaGainCh[AR5416_MAX_CHAINS];
+	u8 switchSettling;
+	u8 txRxAttenCh[AR5416_MAX_CHAINS];
+	u8 rxTxMarginCh[AR5416_MAX_CHAINS];
+	u8 adcDesiredSize;
+	u8 pgaDesiredSize;
+	u8 xlnaGainCh[AR5416_MAX_CHAINS];
+	u8 txEndToXpaOff;
+	u8 txEndToRxOn;
+	u8 txFrameToXpaOn;
+	u8 thresh62;
+	u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
+	u8 xpdGain;
+	u8 xpd;
+	u8 iqCalICh[AR5416_MAX_CHAINS];
+	u8 iqCalQCh[AR5416_MAX_CHAINS];
+	u8 pdGainOverlap;
+	u8 ob;
+	u8 db;
+	u8 xpaBiasLvl;
+	u8 pwrDecreaseFor2Chain;
+	u8 pwrDecreaseFor3Chain;
+	u8 txFrameToDataStart;
+	u8 txFrameToPaOn;
+	u8 ht40PowerIncForPdadc;
+	u8 bswAtten[AR5416_MAX_CHAINS];
+	u8 bswMargin[AR5416_MAX_CHAINS];
+	u8 swSettleHt40;
+	u8 xatten2Db[AR5416_MAX_CHAINS];
+	u8 xatten2Margin[AR5416_MAX_CHAINS];
+	u8 ob_ch1;
+	u8 db_ch1;
+	u8 useAnt1:1,
 	    force_xpaon:1,
 	    local_bias:1,
 	    femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
-	u_int8_t futureModalar9280;
-	u_int16_t xpaBiasLvlFreq[3];
-	u_int8_t futureModal[6];
+	u8 futureModalar9280;
+	u16 xpaBiasLvlFreq[3];
+	u8 futureModal[6];
 
 	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct cal_data_per_freq {
-	u_int8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
-	u_int8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+	u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+	u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 } __packed;
 
 struct cal_target_power_leg {
-	u_int8_t bChannel;
-	u_int8_t tPow2x[4];
+	u8 bChannel;
+	u8 tPow2x[4];
 } __packed;
 
 struct cal_target_power_ht {
-	u_int8_t bChannel;
-	u_int8_t tPow2x[8];
+	u8 bChannel;
+	u8 tPow2x[8];
 } __packed;
 
 #ifdef __BIG_ENDIAN_BITFIELD
 struct cal_ctl_edges {
-	u_int8_t bChannel;
-	u_int8_t flag:2, tPower:6;
+	u8 bChannel;
+	u8 flag:2, tPower:6;
 } __packed;
 #else
 struct cal_ctl_edges {
-	u_int8_t bChannel;
-	u_int8_t tPower:6, flag:2;
+	u8 bChannel;
+	u8 tPower:6, flag:2;
 } __packed;
 #endif
 
@@ -599,10 +599,10 @@ struct cal_ctl_data {
 
 struct ar5416_eeprom {
 	struct base_eep_header baseEepHeader;
-	u_int8_t custData[64];
+	u8 custData[64];
 	struct modal_eep_header modalHeader[2];
-	u_int8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
-	u_int8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
+	u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
+	u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 	struct cal_data_per_freq
 	 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 	struct cal_data_per_freq
@@ -621,19 +621,19 @@ struct ar5416_eeprom {
 	 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 	struct cal_target_power_ht
 	 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
-	u_int8_t ctlIndex[AR5416_NUM_CTLS];
+	u8 ctlIndex[AR5416_NUM_CTLS];
 	struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
-	u_int8_t padding;
+	u8 padding;
 } __packed;
 
 struct ar5416IniArray {
-	u_int32_t *ia_array;
-	u_int32_t ia_rows;
-	u_int32_t ia_columns;
+	u32 *ia_array;
+	u32 ia_rows;
+	u32 ia_columns;
 };
 
 #define INIT_INI_ARRAY(iniarray, array, rows, columns) do {	\
-		(iniarray)->ia_array = (u_int32_t *)(array);    \
+		(iniarray)->ia_array = (u32 *)(array);    \
 		(iniarray)->ia_rows = (rows);			\
 		(iniarray)->ia_columns = (columns);		\
 	} while (0)
@@ -681,10 +681,10 @@ enum hal_cal_state {
 
 struct hal_percal_data {
 	enum hal_cal_types calType;
-	u_int32_t calNumSamples;
-	u_int32_t calCountMax;
+	u32 calNumSamples;
+	u32 calCountMax;
 	void (*calCollect) (struct ath_hal *);
-	void (*calPostProc) (struct ath_hal *, u_int8_t);
+	void (*calPostProc) (struct ath_hal *, u8);
 };
 
 struct hal_cal_list {
@@ -696,25 +696,25 @@ struct hal_cal_list {
 struct ath_hal_5416 {
 	struct ath_hal ah;
 	struct ar5416_eeprom ah_eeprom;
-	u_int8_t ah_macaddr[ETH_ALEN];
-	u_int8_t ah_bssid[ETH_ALEN];
-	u_int8_t ah_bssidmask[ETH_ALEN];
-	u_int16_t ah_assocId;
+	u8 ah_macaddr[ETH_ALEN];
+	u8 ah_bssid[ETH_ALEN];
+	u8 ah_bssidmask[ETH_ALEN];
+	u16 ah_assocId;
 	int16_t ah_curchanRadIndex;
-	u_int32_t ah_maskReg;
+	u32 ah_maskReg;
 	struct ar5416Stats ah_stats;
-	u_int32_t ah_txDescMask;
-	u_int32_t ah_txOkInterruptMask;
-	u_int32_t ah_txErrInterruptMask;
-	u_int32_t ah_txDescInterruptMask;
-	u_int32_t ah_txEolInterruptMask;
-	u_int32_t ah_txUrnInterruptMask;
-	struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
-	enum hal_power_mode ah_powerMode;
+	u32 ah_txDescMask;
+	u32 ah_txOkInterruptMask;
+	u32 ah_txErrInterruptMask;
+	u32 ah_txDescInterruptMask;
+	u32 ah_txEolInterruptMask;
+	u32 ah_txUrnInterruptMask;
+	struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
+	enum ath9k_power_mode ah_powerMode;
 	bool ah_chipFullSleep;
-	u_int32_t ah_atimWindow;
-	enum hal_ant_setting ah_diversityControl;
-	u_int16_t ah_antennaSwitchSwap;
+	u32 ah_atimWindow;
+	enum ath9k_ant_setting ah_diversityControl;
+	u16 ah_antennaSwitchSwap;
 	enum hal_cal_types ah_suppCals;
 	struct hal_cal_list ah_iqCalData;
 	struct hal_cal_list ah_adcGainCalData;
@@ -735,73 +735,73 @@ struct ath_hal_5416 {
 #define ah_totalAdcDcOffsetQOddPhase  ah_Meas2.sign
 #define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
 	union {
-		u_int32_t unsign[AR5416_MAX_CHAINS];
+		u32 unsign[AR5416_MAX_CHAINS];
 		int32_t sign[AR5416_MAX_CHAINS];
 	} ah_Meas0;
 	union {
-		u_int32_t unsign[AR5416_MAX_CHAINS];
+		u32 unsign[AR5416_MAX_CHAINS];
 		int32_t sign[AR5416_MAX_CHAINS];
 	} ah_Meas1;
 	union {
-		u_int32_t unsign[AR5416_MAX_CHAINS];
+		u32 unsign[AR5416_MAX_CHAINS];
 		int32_t sign[AR5416_MAX_CHAINS];
 	} ah_Meas2;
 	union {
-		u_int32_t unsign[AR5416_MAX_CHAINS];
+		u32 unsign[AR5416_MAX_CHAINS];
 		int32_t sign[AR5416_MAX_CHAINS];
 	} ah_Meas3;
-	u_int16_t ah_CalSamples;
-	u_int32_t ah_tx6PowerInHalfDbm;
-	u_int32_t ah_staId1Defaults;
-	u_int32_t ah_miscMode;
+	u16 ah_CalSamples;
+	u32 ah_tx6PowerInHalfDbm;
+	u32 ah_staId1Defaults;
+	u32 ah_miscMode;
 	bool ah_tpcEnabled;
-	u_int32_t ah_beaconInterval;
+	u32 ah_beaconInterval;
 	enum {
 		AUTO_32KHZ,
 		USE_32KHZ,
 		DONT_USE_32KHZ,
 	} ah_enable32kHzClock;
-	u_int32_t *ah_analogBank0Data;
-	u_int32_t *ah_analogBank1Data;
-	u_int32_t *ah_analogBank2Data;
-	u_int32_t *ah_analogBank3Data;
-	u_int32_t *ah_analogBank6Data;
-	u_int32_t *ah_analogBank6TPCData;
-	u_int32_t *ah_analogBank7Data;
-	u_int32_t *ah_addac5416_21;
-	u_int32_t *ah_bank6Temp;
-	u_int32_t ah_ofdmTxPower;
+	u32 *ah_analogBank0Data;
+	u32 *ah_analogBank1Data;
+	u32 *ah_analogBank2Data;
+	u32 *ah_analogBank3Data;
+	u32 *ah_analogBank6Data;
+	u32 *ah_analogBank6TPCData;
+	u32 *ah_analogBank7Data;
+	u32 *ah_addac5416_21;
+	u32 *ah_bank6Temp;
+	u32 ah_ofdmTxPower;
 	int16_t ah_txPowerIndexOffset;
-	u_int ah_slottime;
-	u_int ah_acktimeout;
-	u_int ah_ctstimeout;
-	u_int ah_globaltxtimeout;
-	u_int8_t ah_gBeaconRate;
-	u_int32_t ah_gpioSelect;
-	u_int32_t ah_polarity;
-	u_int32_t ah_gpioBit;
+	u32 ah_slottime;
+	u32 ah_acktimeout;
+	u32 ah_ctstimeout;
+	u32 ah_globaltxtimeout;
+	u8 ah_gBeaconRate;
+	u32 ah_gpioSelect;
+	u32 ah_polarity;
+	u32 ah_gpioBit;
 	bool ah_eepEnabled;
-	u_int32_t ah_procPhyErr;
+	u32 ah_procPhyErr;
 	bool ah_hasHwPhyCounters;
-	u_int32_t ah_aniPeriod;
+	u32 ah_aniPeriod;
 	struct ar5416AniState *ah_curani;
 	struct ar5416AniState ah_ani[255];
 	int ah_totalSizeDesired[5];
 	int ah_coarseHigh[5];
 	int ah_coarseLow[5];
 	int ah_firpwr[5];
-	u_int16_t ah_ratesArray[16];
-	u_int32_t ah_intrTxqs;
+	u16 ah_ratesArray[16];
+	u32 ah_intrTxqs;
 	bool ah_intrMitigation;
-	u_int32_t ah_cycleCount;
-	u_int32_t ah_ctlBusy;
-	u_int32_t ah_extBusy;
-	enum hal_ht_extprotspacing ah_extprotspacing;
-	u_int8_t ah_txchainmask;
-	u_int8_t ah_rxchainmask;
+	u32 ah_cycleCount;
+	u32 ah_ctlBusy;
+	u32 ah_extBusy;
+	enum ath9k_ht_extprotspacing ah_extprotspacing;
+	u8 ah_txchainmask;
+	u8 ah_rxchainmask;
 	int ah_hwp;
 	void __iomem *ah_cal_mem;
-	enum hal_ani_cmd ah_ani_function;
+	enum ath9k_ani_cmd ah_ani_function;
 	struct ar5416IniArray ah_iniModes;
 	struct ar5416IniArray ah_iniCommon;
 	struct ar5416IniArray ah_iniBank0;
@@ -853,8 +853,8 @@ struct ath_hal_5416 {
 #define HT40_CHANNEL_CENTER_SHIFT   10
 
 #define ar5416CheckOpMode(_opmode)					\
-	((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) ||		\
-	 (_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR))
+	((_opmode == ATH9K_M_STA) || (_opmode == ATH9K_M_IBSS) ||	\
+	 (_opmode == ATH9K_M_HOSTAP) || (_opmode == ATH9K_M_MONITOR))
 
 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
 
@@ -894,18 +894,18 @@ struct ath_hal_5416 {
 #define HAL_SPUR_IMMUNE_MAX             7
 #define HAL_FIRST_STEP_MAX              2
 
-#define HAL_ANI_OFDM_TRIG_HIGH          500
-#define HAL_ANI_OFDM_TRIG_LOW           200
-#define HAL_ANI_CCK_TRIG_HIGH           200
-#define HAL_ANI_CCK_TRIG_LOW            100
-#define HAL_ANI_NOISE_IMMUNE_LVL        4
-#define HAL_ANI_USE_OFDM_WEAK_SIG       true
-#define HAL_ANI_CCK_WEAK_SIG_THR        false
-#define HAL_ANI_SPUR_IMMUNE_LVL         7
-#define HAL_ANI_FIRSTEP_LVL             0
-#define HAL_ANI_RSSI_THR_HIGH           40
-#define HAL_ANI_RSSI_THR_LOW            7
-#define HAL_ANI_PERIOD                  100
+#define ATH9K_ANI_OFDM_TRIG_HIGH          500
+#define ATH9K_ANI_OFDM_TRIG_LOW           200
+#define ATH9K_ANI_CCK_TRIG_HIGH           200
+#define ATH9K_ANI_CCK_TRIG_LOW            100
+#define ATH9K_ANI_NOISE_IMMUNE_LVL        4
+#define ATH9K_ANI_USE_OFDM_WEAK_SIG       true
+#define ATH9K_ANI_CCK_WEAK_SIG_THR        false
+#define ATH9K_ANI_SPUR_IMMUNE_LVL         7
+#define ATH9K_ANI_FIRSTEP_LVL             0
+#define ATH9K_ANI_RSSI_THR_HIGH           40
+#define ATH9K_ANI_RSSI_THR_LOW            7
+#define ATH9K_ANI_PERIOD                  100
 
 #define AR_GPIOD_MASK                   0x00001FFF
 #define AR_GPIO_BIT(_gpio)              (1 << (_gpio))
@@ -916,7 +916,7 @@ struct ath_hal_5416 {
 	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
 #define BEACON_RSSI(ahp) \
 	HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
-		HAL_RSSI_EP_MULTIPLIER)
+		ATH9K_RSSI_EP_MULTIPLIER)
 
 #define ah_mibStats     ah_stats.ast_mibstats
 
@@ -963,7 +963,7 @@ struct ath_hal_5416 {
 #define OFDM_PLCP_BITS_QUARTER      22
 #define OFDM_SYMBOL_TIME_QUARTER    16
 
-u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
+u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
 			      enum eeprom_param param);
 
 #endif
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/initvals.h b/package/ath9k/src/drivers/net/wireless/ath9k/initvals.h
index c05873b8f..3dd381594 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/initvals.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/initvals.h
@@ -14,7 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-static const u_int32_t ar5416Modes_9100[][6] = {
+static const u32 ar5416Modes_9100[][6] = {
     { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
     { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
     { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -78,7 +78,7 @@ static const u_int32_t ar5416Modes_9100[][6] = {
     { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
 };
 
-static const u_int32_t ar5416Common_9100[][2] = {
+static const u32 ar5416Common_9100[][2] = {
     { 0x0000000c, 0x00000000 },
     { 0x00000030, 0x00020015 },
     { 0x00000034, 0x00000005 },
@@ -456,12 +456,12 @@ static const u_int32_t ar5416Common_9100[][2] = {
     { 0x0000a3e0, 0x000001ce },
 };
 
-static const u_int32_t ar5416Bank0_9100[][2] = {
+static const u32 ar5416Bank0_9100[][2] = {
     { 0x000098b0, 0x1e5795e5 },
     { 0x000098e0, 0x02008020 },
 };
 
-static const u_int32_t ar5416BB_RfGain_9100[][3] = {
+static const u32 ar5416BB_RfGain_9100[][3] = {
     { 0x00009a00, 0x00000000, 0x00000000 },
     { 0x00009a04, 0x00000040, 0x00000040 },
     { 0x00009a08, 0x00000080, 0x00000080 },
@@ -528,21 +528,21 @@ static const u_int32_t ar5416BB_RfGain_9100[][3] = {
     { 0x00009afc, 0x000000f9, 0x000000f9 },
 };
 
-static const u_int32_t ar5416Bank1_9100[][2] = {
+static const u32 ar5416Bank1_9100[][2] = {
     { 0x000098b0, 0x02108421 },
     { 0x000098ec, 0x00000008 },
 };
 
-static const u_int32_t ar5416Bank2_9100[][2] = {
+static const u32 ar5416Bank2_9100[][2] = {
     { 0x000098b0, 0x0e73ff17 },
     { 0x000098e0, 0x00000420 },
 };
 
-static const u_int32_t ar5416Bank3_9100[][3] = {
+static const u32 ar5416Bank3_9100[][3] = {
     { 0x000098f0, 0x01400018, 0x01c00018 },
 };
 
-static const u_int32_t ar5416Bank6_9100[][3] = {
+static const u32 ar5416Bank6_9100[][3] = {
 
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
@@ -579,7 +579,7 @@ static const u_int32_t ar5416Bank6_9100[][3] = {
     { 0x000098d0, 0x0000000f, 0x0010000f },
 };
 
-static const u_int32_t ar5416Bank6TPC_9100[][3] = {
+static const u32 ar5416Bank6TPC_9100[][3] = {
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
@@ -615,13 +615,13 @@ static const u_int32_t ar5416Bank6TPC_9100[][3] = {
     { 0x000098d0, 0x0000000f, 0x0010000f },
 };
 
-static const u_int32_t ar5416Bank7_9100[][2] = {
+static const u32 ar5416Bank7_9100[][2] = {
     { 0x0000989c, 0x00000500 },
     { 0x0000989c, 0x00000800 },
     { 0x000098cc, 0x0000000e },
 };
 
-static const u_int32_t ar5416Addac_9100[][2] = {
+static const u32 ar5416Addac_9100[][2] = {
     {0x0000989c,  0x00000000 },
     {0x0000989c,  0x00000003 },
     {0x0000989c,  0x00000000 },
@@ -661,7 +661,7 @@ static const u_int32_t ar5416Addac_9100[][2] = {
     {0x000098c4,  0x00000000 },
 };
 
-static const u_int32_t ar5416Modes[][6] = {
+static const u32 ar5416Modes[][6] = {
     { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
     { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
     { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -735,7 +735,7 @@ static const u_int32_t ar5416Modes[][6] = {
     { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
 };
 
-static const u_int32_t ar5416Common[][2] = {
+static const u32 ar5416Common[][2] = {
     { 0x0000000c, 0x00000000 },
     { 0x00000030, 0x00020015 },
     { 0x00000034, 0x00000005 },
@@ -1109,12 +1109,12 @@ static const u_int32_t ar5416Common[][2] = {
     { 0x0000a3e0, 0x000001ce },
 };
 
-static const u_int32_t ar5416Bank0[][2] = {
+static const u32 ar5416Bank0[][2] = {
     { 0x000098b0, 0x1e5795e5 },
     { 0x000098e0, 0x02008020 },
 };
 
-static const u_int32_t ar5416BB_RfGain[][3] = {
+static const u32 ar5416BB_RfGain[][3] = {
     { 0x00009a00, 0x00000000, 0x00000000 },
     { 0x00009a04, 0x00000040, 0x00000040 },
     { 0x00009a08, 0x00000080, 0x00000080 },
@@ -1181,21 +1181,21 @@ static const u_int32_t ar5416BB_RfGain[][3] = {
     { 0x00009afc, 0x000000f9, 0x000000f9 },
 };
 
-static const u_int32_t ar5416Bank1[][2] = {
+static const u32 ar5416Bank1[][2] = {
     { 0x000098b0, 0x02108421},
     { 0x000098ec, 0x00000008},
 };
 
-static const u_int32_t ar5416Bank2[][2] = {
+static const u32 ar5416Bank2[][2] = {
     { 0x000098b0, 0x0e73ff17},
     { 0x000098e0, 0x00000420},
 };
 
-static const u_int32_t ar5416Bank3[][3] = {
+static const u32 ar5416Bank3[][3] = {
     { 0x000098f0, 0x01400018, 0x01c00018 },
 };
 
-static const u_int32_t ar5416Bank6[][3] = {
+static const u32 ar5416Bank6[][3] = {
 
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
@@ -1233,7 +1233,7 @@ static const u_int32_t ar5416Bank6[][3] = {
 };
 
 
-static const u_int32_t ar5416Bank6TPC[][3] = {
+static const u32 ar5416Bank6TPC[][3] = {
 
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
@@ -1270,13 +1270,13 @@ static const u_int32_t ar5416Bank6TPC[][3] = {
     { 0x000098d0, 0x0000000f, 0x0010000f },
 };
 
-static const u_int32_t ar5416Bank7[][2] = {
+static const u32 ar5416Bank7[][2] = {
     { 0x0000989c, 0x00000500 },
     { 0x0000989c, 0x00000800 },
     { 0x000098cc, 0x0000000e },
 };
 
-static const u_int32_t ar5416Addac[][2] = {
+static const u32 ar5416Addac[][2] = {
     {0x0000989c, 0x00000000 },
     {0x0000989c, 0x00000000 },
     {0x0000989c, 0x00000000 },
@@ -1312,7 +1312,7 @@ static const u_int32_t ar5416Addac[][2] = {
 };
 
 
-static const u_int32_t ar5416Modes_9160[][6] = {
+static const u32 ar5416Modes_9160[][6] = {
     { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
     { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
     { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -1376,7 +1376,7 @@ static const u_int32_t ar5416Modes_9160[][6] = {
     { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
 };
 
-static const u_int32_t ar5416Common_9160[][2] = {
+static const u32 ar5416Common_9160[][2] = {
     { 0x0000000c, 0x00000000 },
     { 0x00000030, 0x00020015 },
     { 0x00000034, 0x00000005 },
@@ -1755,12 +1755,12 @@ static const u_int32_t ar5416Common_9160[][2] = {
     { 0x0000a3e0, 0x000001ce },
 };
 
-static const u_int32_t ar5416Bank0_9160[][2] = {
+static const u32 ar5416Bank0_9160[][2] = {
     { 0x000098b0, 0x1e5795e5 },
     { 0x000098e0, 0x02008020 },
 };
 
-static const u_int32_t ar5416BB_RfGain_9160[][3] = {
+static const u32 ar5416BB_RfGain_9160[][3] = {
     { 0x00009a00, 0x00000000, 0x00000000 },
     { 0x00009a04, 0x00000040, 0x00000040 },
     { 0x00009a08, 0x00000080, 0x00000080 },
@@ -1827,21 +1827,21 @@ static const u_int32_t ar5416BB_RfGain_9160[][3] = {
     { 0x00009afc, 0x000000f9, 0x000000f9 },
 };
 
-static const u_int32_t ar5416Bank1_9160[][2] = {
+static const u32 ar5416Bank1_9160[][2] = {
     { 0x000098b0, 0x02108421 },
     { 0x000098ec, 0x00000008 },
 };
 
-static const u_int32_t ar5416Bank2_9160[][2] = {
+static const u32 ar5416Bank2_9160[][2] = {
     { 0x000098b0, 0x0e73ff17 },
     { 0x000098e0, 0x00000420 },
 };
 
-static const u_int32_t ar5416Bank3_9160[][3] = {
+static const u32 ar5416Bank3_9160[][3] = {
     { 0x000098f0, 0x01400018, 0x01c00018 },
 };
 
-static const u_int32_t ar5416Bank6_9160[][3] = {
+static const u32 ar5416Bank6_9160[][3] = {
 
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
@@ -1878,7 +1878,7 @@ static const u_int32_t ar5416Bank6_9160[][3] = {
     { 0x000098d0, 0x0000000f, 0x0010000f },
 };
 
-static const u_int32_t ar5416Bank6TPC_9160[][3] = {
+static const u32 ar5416Bank6TPC_9160[][3] = {
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
     { 0x0000989c, 0x00000000, 0x00000000 },
@@ -1914,14 +1914,14 @@ static const u_int32_t ar5416Bank6TPC_9160[][3] = {
     { 0x000098d0, 0x0000000f, 0x0010000f },
 };
 
-static const u_int32_t ar5416Bank7_9160[][2] = {
+static const u32 ar5416Bank7_9160[][2] = {
     { 0x0000989c, 0x00000500 },
     { 0x0000989c, 0x00000800 },
     { 0x000098cc, 0x0000000e },
 };
 
 
-static u_int32_t ar5416Addac_9160[][2] = {
+static u32 ar5416Addac_9160[][2] = {
     {0x0000989c,  0x00000000 },
     {0x0000989c,  0x00000000 },
     {0x0000989c,  0x00000000 },
@@ -1957,7 +1957,7 @@ static u_int32_t ar5416Addac_9160[][2] = {
 };
 
 
-static u_int32_t ar5416Addac_91601_1[][2] = {
+static u32 ar5416Addac_91601_1[][2] = {
     {0x0000989c,  0x00000000 },
     {0x0000989c,  0x00000000 },
     {0x0000989c,  0x00000000 },
@@ -1994,7 +1994,7 @@ static u_int32_t ar5416Addac_91601_1[][2] = {
 
 
 
-static const u_int32_t ar9280Modes_9280[][6] = {
+static const u32 ar9280Modes_9280[][6] = {
     { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
     { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
     { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -2196,7 +2196,7 @@ static const u_int32_t ar9280Modes_9280[][6] = {
     { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
 };
 
-static const u_int32_t ar9280Common_9280[][2] = {
+static const u32 ar9280Common_9280[][2] = {
     { 0x0000000c, 0x00000000 },
     { 0x00000030, 0x00020015 },
     { 0x00000034, 0x00000005 },
@@ -2546,7 +2546,7 @@ static const u_int32_t ar9280Common_9280[][2] = {
 
 
 
-static const u_int32_t ar9280Modes_9280_2[][6] = {
+static const u32 ar9280Modes_9280_2[][6] = {
     { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
     { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
     { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -2750,7 +2750,7 @@ static const u_int32_t ar9280Modes_9280_2[][6] = {
     { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
 };
 
-static const u_int32_t ar9280Common_9280_2[][2] = {
+static const u32 ar9280Common_9280_2[][2] = {
     { 0x0000000c, 0x00000000 },
     { 0x00000030, 0x00020015 },
     { 0x00000034, 0x00000005 },
@@ -3098,7 +3098,7 @@ static const u_int32_t ar9280Common_9280_2[][2] = {
     { 0x00007898, 0x2a850160 },
 };
 
-static const u_int32_t ar9280Modes_fast_clock_9280_2[][3] = {
+static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
     { 0x00001030, 0x00000268, 0x000004d0 },
     { 0x00001070, 0x0000018c, 0x00000318 },
     { 0x000010b0, 0x00000fd0, 0x00001fa0 },
@@ -3117,7 +3117,7 @@ static const u_int32_t ar9280Modes_fast_clock_9280_2[][3] = {
 
 
 
-static const u_int32_t ar9280PciePhy_clkreq_off_L1_9280[][2] = {
+static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
     {0x00004040,  0x9248fd00 },
     {0x00004040,  0x24924924 },
     {0x00004040,  0xa8000019 },
@@ -3132,7 +3132,7 @@ static const u_int32_t ar9280PciePhy_clkreq_off_L1_9280[][2] = {
 
 
 
-static const u_int32_t ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
+static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
     {0x00004040,  0x9248fd00 },
     {0x00004040,  0x24924924 },
     {0x00004040,  0xa8000019 },
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/main.c b/package/ath9k/src/drivers/net/wireless/ath9k/main.c
index 7ef0d58a3..954952463 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/main.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/main.c
@@ -41,44 +41,60 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = {
 	{ 0 }
 };
 
-static int test_update_chan(enum ieee80211_band band,
-			    const struct hal_channel *chan,
-			    struct ath_softc *sc)
+static int ath_get_channel(struct ath_softc *sc,
+			   struct ieee80211_channel *chan)
 {
 	int i;
 
-	for (i = 0; i < sc->sbands[band].n_channels; i++) {
-		if (sc->channels[band][i].center_freq == chan->channel)
-			return 1;
+	for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
+		if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
+			return i;
 	}
 
-	return 0;
+	return -1;
 }
 
-static int ath_check_chanflags(struct ieee80211_channel *chan,
-			       u_int32_t mode,
-			       struct ath_softc *sc)
+static u32 ath_get_extchanmode(struct ath_softc *sc,
+				     struct ieee80211_channel *chan)
 {
-	struct ieee80211_hw *hw = sc->hw;
-	struct ieee80211_supported_band *band;
-	struct ieee80211_channel *band_channel;
-	int i;
-
-	band = hw->wiphy->bands[chan->band];
-
-	for (i = 0; i < band->n_channels; i++) {
-		band_channel = &band->channels[i];
-
-		if ((band_channel->center_freq == chan->center_freq) &&
-		    ((band_channel->hw_value & mode) == mode))
-			return 1;
+	u32 chanmode = 0;
+	u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
+	enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
+
+	switch (chan->band) {
+	case IEEE80211_BAND_2GHZ:
+		if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
+		    (tx_chan_width == ATH9K_HT_MACMODE_20))
+			chanmode = CHANNEL_G_HT20;
+		if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
+		    (tx_chan_width == ATH9K_HT_MACMODE_2040))
+			chanmode = CHANNEL_G_HT40PLUS;
+		if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
+		    (tx_chan_width == ATH9K_HT_MACMODE_2040))
+			chanmode = CHANNEL_G_HT40MINUS;
+		break;
+	case IEEE80211_BAND_5GHZ:
+		if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
+		    (tx_chan_width == ATH9K_HT_MACMODE_20))
+			chanmode = CHANNEL_A_HT20;
+		if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
+		    (tx_chan_width == ATH9K_HT_MACMODE_2040))
+			chanmode = CHANNEL_A_HT40PLUS;
+		if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
+		    (tx_chan_width == ATH9K_HT_MACMODE_2040))
+			chanmode = CHANNEL_A_HT40MINUS;
+		break;
+	default:
+		break;
 	}
-	return 0;
+
+	return chanmode;
 }
 
+
 static int ath_setkey_tkip(struct ath_softc *sc,
 			   struct ieee80211_key_conf *key,
-			   struct hal_keyval *hk,
+			   struct ath9k_keyval *hk,
 			   const u8 *addr)
 {
 	u8 *key_rxmic = NULL;
@@ -123,7 +139,7 @@ static int ath_key_config(struct ath_softc *sc,
 			  struct ieee80211_key_conf *key)
 {
 	struct ieee80211_vif *vif;
-	struct hal_keyval hk;
+	struct ath9k_keyval hk;
 	const u8 *mac = NULL;
 	int ret = 0;
 	enum ieee80211_if_types opmode;
@@ -132,13 +148,13 @@ static int ath_key_config(struct ath_softc *sc,
 
 	switch (key->alg) {
 	case ALG_WEP:
-		hk.kv_type = HAL_CIPHER_WEP;
+		hk.kv_type = ATH9K_CIPHER_WEP;
 		break;
 	case ALG_TKIP:
-		hk.kv_type = HAL_CIPHER_TKIP;
+		hk.kv_type = ATH9K_CIPHER_TKIP;
 		break;
 	case ALG_CCMP:
-		hk.kv_type = HAL_CIPHER_AES_CCM;
+		hk.kv_type = ATH9K_CIPHER_AES_CCM;
 		break;
 	default:
 		return -EINVAL;
@@ -266,10 +282,11 @@ static void ath9k_rx_prepare(struct ath_softc *sc,
 	rx_status->mactime = status->tsf;
 	rx_status->band = curchan->band;
 	rx_status->freq =  curchan->center_freq;
-	rx_status->signal = (status->rssi * 64) / 100;
 	rx_status->noise = ATH_DEFAULT_NOISE_FLOOR;
+	rx_status->signal = rx_status->noise + status->rssi;
 	rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
 	rx_status->antenna = status->antenna;
+	rx_status->qual = status->rssi * 100 / 64;
 
 	if (status->flags & ATH_RX_MIC_ERROR)
 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
@@ -279,7 +296,7 @@ static void ath9k_rx_prepare(struct ath_softc *sc,
 	rx_status->flag |= RX_FLAG_TSFT;
 }
 
-static u_int8_t parse_mpdudensity(u_int8_t mpdudensity)
+static u8 parse_mpdudensity(u8 mpdudensity)
 {
 	/*
 	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
@@ -318,19 +335,24 @@ static int ath9k_start(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	struct ieee80211_channel *curchan = hw->conf.channel;
-	struct hal_channel hchan;
-	int error = 0;
+	int error = 0, pos;
 
 	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
 		"initial channel: %d MHz\n", __func__, curchan->center_freq);
 
 	/* setup initial channel */
 
-	hchan.channel = curchan->center_freq;
-	hchan.channelFlags = ath_chan2flags(curchan, sc);
+	pos = ath_get_channel(sc, curchan);
+	if (pos == -1) {
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
+		return -EINVAL;
+	}
+
+	sc->sc_ah->ah_channels[pos].chanmode =
+		(curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
 
 	/* open ath_dev */
-	error = ath_open(sc, &hchan);
+	error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
 	if (error) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to complete ath_open\n", __func__);
@@ -399,10 +421,10 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
 
 	switch (conf->type) {
 	case IEEE80211_IF_TYPE_STA:
-		ic_opmode = HAL_M_STA;
+		ic_opmode = ATH9K_M_STA;
 		break;
 	case IEEE80211_IF_TYPE_IBSS:
-		ic_opmode = HAL_M_IBSS;
+		ic_opmode = ATH9K_M_IBSS;
 		break;
 	default:
 		DPRINTF(sc, ATH_DBG_FATAL,
@@ -447,17 +469,17 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
 #endif
 
 	/* Update ratectrl */
-	ath_rate_newstate(sc, avp, 0);
+	ath_rate_newstate(sc, avp);
 
 	/* Reclaim beacon resources */
-	if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
+	if (sc->sc_opmode == ATH9K_M_HOSTAP || sc->sc_opmode == ATH9K_M_IBSS) {
 		ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
 		ath_beacon_return(sc, avp);
 	}
 
 	/* Set interrupt mask */
-	sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
-	ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~HAL_INT_GLOBAL);
+	sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
+	ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
 	sc->sc_beacons = 0;
 
 	error = ath_vap_detach(sc, 0);
@@ -472,18 +494,24 @@ static int ath9k_config(struct ieee80211_hw *hw,
 {
 	struct ath_softc *sc = hw->priv;
 	struct ieee80211_channel *curchan = hw->conf.channel;
-	struct hal_channel hchan;
+	int pos;
 
 	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
 		__func__,
 		curchan->center_freq);
 
-	hchan.channel = curchan->center_freq;
-	hchan.channelFlags = ath_chan2flags(curchan, sc);
+	pos = ath_get_channel(sc, curchan);
+	if (pos == -1) {
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
+		return -EINVAL;
+	}
+
+	sc->sc_ah->ah_channels[pos].chanmode =
+		(curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
 	sc->sc_config.txpowlimit = 2 * conf->power_level;
 
 	/* set h/w channel */
-	if (ath_set_channel(sc, &hchan) < 0)
+	if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 		DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
 			__func__);
 
@@ -496,7 +524,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
 {
 	struct ath_softc *sc = hw->priv;
 	struct ath_vap *avp;
-	u_int32_t rfilt = 0;
+	u32 rfilt = 0;
 	int error, i;
 	DECLARE_MAC_BUF(mac);
 
@@ -513,7 +541,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
 		case IEEE80211_IF_TYPE_STA:
 		case IEEE80211_IF_TYPE_IBSS:
 			/* Update ratectrl about the new state */
-			ath_rate_newstate(sc, avp, 0);
+			ath_rate_newstate(sc, avp);
 
 			/* Set rx filter */
 			rfilt = ath_calcrxfilter(sc);
@@ -541,9 +569,9 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
 
 			/* Disable BMISS interrupt when we're not associated */
 			ath9k_hw_set_interrupts(sc->sc_ah,
-						sc->sc_imask &
-						~(HAL_INT_SWBA | HAL_INT_BMISS));
-			sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
+					sc->sc_imask &
+					~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
+			sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
 
 			DPRINTF(sc, ATH_DBG_CONFIG,
 				"%s: RX filter 0x%x bssid %s aid 0x%x\n",
@@ -581,9 +609,9 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
 	/* Check for WLAN_CAPABILITY_PRIVACY ? */
 	if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
 		for (i = 0; i < IEEE80211_WEP_NKID; i++)
-			if (ath9k_hw_keyisvalid(sc->sc_ah, (u_int16_t)i))
+			if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
 				ath9k_hw_keysetmac(sc->sc_ah,
-						   (u_int16_t)i,
+						   (u16)i,
 						   sc->sc_curbssid);
 	}
 
@@ -672,7 +700,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
 			 const struct ieee80211_tx_queue_params *params)
 {
 	struct ath_softc *sc = hw->priv;
-	struct hal_txq_info qi;
+	struct ath9k_txq_info qi;
 	int ret = 0, qnum;
 
 	if (queue >= WME_NUM_AC)
@@ -728,7 +756,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
 	case DISABLE_KEY:
 		ath_key_delete(sc, key);
 		clear_bit(key->keyidx, sc->sc_keymap);
-		sc->sc_keytype = HAL_CIPHER_CLR;
+		sc->sc_keytype = ATH9K_CIPHER_CLR;
 		break;
 	default:
 		ret = -EINVAL;
@@ -752,9 +780,9 @@ static void ath9k_ht_conf(struct ath_softc *sc,
 			IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
 			    (bss_conf->ht_bss_conf->bss_cap &
 				IEEE80211_HT_IE_CHA_WIDTH))
-			ht_info->tx_chan_width = HAL_HT_MACMODE_2040;
+			ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
 		else
-			ht_info->tx_chan_width = HAL_HT_MACMODE_20;
+			ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
 
 		ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
 		ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
@@ -772,8 +800,8 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
 {
 	struct ieee80211_hw *hw = sc->hw;
 	struct ieee80211_channel *curchan = hw->conf.channel;
-	struct hal_channel hchan;
 	struct ath_vap *avp;
+	int pos;
 	DECLARE_MAC_BUF(mac);
 
 	if (bss_conf->assoc) {
@@ -788,11 +816,8 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
 			return;
 		}
 
-		/* Update ratectrl about the new state */
-		ath_rate_newstate(sc, avp, 1);
-
 		/* New association, store aid */
-		if (avp->av_opmode == HAL_M_STA) {
+		if (avp->av_opmode == ATH9K_M_STA) {
 			sc->sc_curaid = bss_conf->aid;
 			ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 					       sc->sc_curaid);
@@ -820,14 +845,30 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
 			__func__,
 			curchan->center_freq);
 
-		hchan.channel = curchan->center_freq;
-		hchan.channelFlags = ath_chan2flags(curchan, sc);
+		pos = ath_get_channel(sc, curchan);
+		if (pos == -1) {
+			DPRINTF(sc, ATH_DBG_FATAL,
+				"%s: Invalid channel\n", __func__);
+			return;
+		}
+
+		if (hw->conf.ht_conf.ht_supported)
+			sc->sc_ah->ah_channels[pos].chanmode =
+				ath_get_extchanmode(sc, curchan);
+		else
+			sc->sc_ah->ah_channels[pos].chanmode =
+				(curchan->band == IEEE80211_BAND_2GHZ) ?
+				CHANNEL_G : CHANNEL_A;
 
 		/* set h/w channel */
-		if (ath_set_channel(sc, &hchan) < 0)
+		if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Unable to set channel\n",
 				__func__);
+
+		ath_rate_newstate(sc, avp);
+		/* Update ratectrl about the new state */
+		ath_rc_node_update(hw, avp->rc_node);
 	} else {
 		DPRINTF(sc, ATH_DBG_CONFIG,
 		"%s: Bss Info DISSOC\n", __func__);
@@ -880,7 +921,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
 
 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
 {
-	u_int64_t tsf;
+	u64 tsf;
 	struct ath_softc *sc = hw->priv;
 	struct ath_hal *ah = sc->sc_ah;
 
@@ -974,143 +1015,6 @@ static struct ieee80211_ops ath9k_ops = {
 	.ampdu_action       = ath9k_ampdu_action
 };
 
-u_int32_t ath_chan2flags(struct ieee80211_channel *chan,
-				struct ath_softc *sc)
-{
-	struct ieee80211_hw *hw = sc->hw;
-	struct ath_ht_info *ht_info = &sc->sc_ht_info;
-
-	if (sc->sc_scanning) {
-		if (chan->band == IEEE80211_BAND_5GHZ) {
-			if (ath_check_chanflags(chan, CHANNEL_A_HT20, sc))
-				return CHANNEL_A_HT20;
-			else
-				return CHANNEL_A;
-		} else {
-			if (ath_check_chanflags(chan, CHANNEL_G_HT20, sc))
-				return CHANNEL_G_HT20;
-			else if (ath_check_chanflags(chan, CHANNEL_G, sc))
-				return CHANNEL_G;
-			else
-				return CHANNEL_B;
-		}
-	} else {
-		if (chan->band == IEEE80211_BAND_2GHZ) {
-			if (!hw->conf.ht_conf.ht_supported) {
-				if (ath_check_chanflags(chan, CHANNEL_G, sc))
-					return CHANNEL_G;
-				else
-					return CHANNEL_B;
-			}
-			if ((ht_info->ext_chan_offset ==
-			     IEEE80211_HT_IE_CHA_SEC_NONE) &&
-			    (ht_info->tx_chan_width == HAL_HT_MACMODE_20))
-				return CHANNEL_G_HT20;
-			if ((ht_info->ext_chan_offset ==
-			     IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
-			    (ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
-				return CHANNEL_G_HT40PLUS;
-			if ((ht_info->ext_chan_offset ==
-			     IEEE80211_HT_IE_CHA_SEC_BELOW) &&
-			    (ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
-				return CHANNEL_G_HT40MINUS;
-			return CHANNEL_B;
-		} else {
-			if (!hw->conf.ht_conf.ht_supported)
-				return CHANNEL_A;
-			if ((ht_info->ext_chan_offset ==
-			     IEEE80211_HT_IE_CHA_SEC_NONE) &&
-			    (ht_info->tx_chan_width == HAL_HT_MACMODE_20))
-				return CHANNEL_A_HT20;
-			if ((ht_info->ext_chan_offset ==
-			     IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
-			    (ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
-				return CHANNEL_A_HT40PLUS;
-			if ((ht_info->ext_chan_offset ==
-			     IEEE80211_HT_IE_CHA_SEC_BELOW) &&
-			    (ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
-				return CHANNEL_A_HT40MINUS;
-			return CHANNEL_A;
-		}
-	}
-}
-
-void ath_setup_channel_list(struct ath_softc *sc,
-			    enum ieee80211_clist_cmd cmd,
-			    const struct hal_channel *chans,
-			    int nchan,
-			    const u_int8_t *regclassids,
-			    u_int nregclass,
-			    int countrycode)
-{
-	const struct hal_channel *c;
-	int i, a = 0, b = 0, flags;
-
-	if (countrycode == CTRY_DEFAULT) {
-		for (i = 0; i < nchan; i++) {
-			c = &chans[i];
-			flags = 0;
-			/* XXX: Ah! make more readable, and
-			 * idententation friendly */
-			if (IS_CHAN_2GHZ(c) &&
-			    !test_update_chan(IEEE80211_BAND_2GHZ, c, sc)) {
-				sc->channels[IEEE80211_BAND_2GHZ][a].band =
-					IEEE80211_BAND_2GHZ;
-				sc->channels[IEEE80211_BAND_2GHZ][a].
-					center_freq =
-					c->channel;
-				sc->channels[IEEE80211_BAND_2GHZ][a].max_power =
-					c->maxTxPower;
-				sc->channels[IEEE80211_BAND_2GHZ][a].hw_value =
-					c->channelFlags;
-
-				if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
-					flags |= IEEE80211_CHAN_NO_IBSS;
-				if (IS_CHAN_PASSIVE(c))
-					flags |= IEEE80211_CHAN_PASSIVE_SCAN;
-
-				sc->channels[IEEE80211_BAND_2GHZ][a].flags =
-					flags;
-				sc->sbands[IEEE80211_BAND_2GHZ].n_channels++;
-				a++;
-				DPRINTF(sc, ATH_DBG_CONFIG,
-					"%s: 2MHz channel: %d, "
-					"channelFlags: 0x%x\n",
-					__func__,
-					c->channel,
-					c->channelFlags);
-			} else if (IS_CHAN_5GHZ(c) &&
-			 !test_update_chan(IEEE80211_BAND_5GHZ, c, sc)) {
-				sc->channels[IEEE80211_BAND_5GHZ][b].band =
-					IEEE80211_BAND_5GHZ;
-				sc->channels[IEEE80211_BAND_5GHZ][b].
-					center_freq =
-					c->channel;
-				sc->channels[IEEE80211_BAND_5GHZ][b].max_power =
-					c->maxTxPower;
-				sc->channels[IEEE80211_BAND_5GHZ][b].hw_value =
-					c->channelFlags;
-
-				if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
-					flags |= IEEE80211_CHAN_NO_IBSS;
-				if (IS_CHAN_PASSIVE(c))
-					flags |= IEEE80211_CHAN_PASSIVE_SCAN;
-
-				sc->channels[IEEE80211_BAND_5GHZ][b].
-					flags = flags;
-				sc->sbands[IEEE80211_BAND_5GHZ].n_channels++;
-				b++;
-				DPRINTF(sc, ATH_DBG_CONFIG,
-					"%s: 5MHz channel: %d, "
-					"channelFlags: 0x%x\n",
-					__func__,
-					c->channel,
-					c->channelFlags);
-			}
-		}
-	}
-}
-
 void ath_get_beaconconfig(struct ath_softc *sc,
 			  int if_id,
 			  struct ath_beacon_config *conf)
@@ -1168,7 +1072,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 int ath__rx_indicate(struct ath_softc *sc,
 		     struct sk_buff *skb,
 		     struct ath_recv_status *status,
-		     u_int16_t keyix)
+		     u16 keyix)
 {
 	struct ieee80211_hw *hw = sc->hw;
 	struct ath_node *an = NULL;
@@ -1191,7 +1095,7 @@ int ath__rx_indicate(struct ath_softc *sc,
 	/* Prepare rx status */
 	ath9k_rx_prepare(sc, skb, status, &rx_status);
 
-	if (!(keyix == HAL_RXKEYIX_INVALID) &&
+	if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
 	    !(status->flags & ATH_RX_DECRYPT_ERROR)) {
 		rx_status.flag |= RX_FLAG_DECRYPTED;
 	} else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
@@ -1236,7 +1140,7 @@ int ath_rx_subframe(struct ath_node *an,
 	return 0;
 }
 
-enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
+enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
 {
 	return sc->sc_ht_info.tx_chan_width;
 }
@@ -1244,7 +1148,7 @@ enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
 void ath_setup_rate(struct ath_softc *sc,
 		    enum wireless_mode wMode,
 		    enum RATE_TYPE type,
-		    const struct hal_rate_table *rt)
+		    const struct ath9k_rate_table *rt)
 {
 	int i, maxrates, a = 0, b = 0;
 	struct ieee80211_supported_band *band_2ghz;
@@ -1335,7 +1239,7 @@ static int ath_detach(struct ath_softc *sc)
 	return 0;
 }
 
-static int ath_attach(u_int16_t devid,
+static int ath_attach(u16 devid,
 		      struct ath_softc *sc)
 {
 	struct ieee80211_hw *hw = sc->hw;
@@ -1432,7 +1336,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	struct ath_softc *sc;
 	struct ieee80211_hw *hw;
 	const char *athname;
-	u_int8_t csz;
+	u8 csz;
 	u32 val;
 	int ret = 0;
 
@@ -1459,7 +1363,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		 * DMA to work so force a reasonable value here if it
 		 * comes up zero.
 		 */
-		csz = L1_CACHE_BYTES / sizeof(u_int32_t);
+		csz = L1_CACHE_BYTES / sizeof(u32);
 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 	}
 	/*
@@ -1499,6 +1403,9 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		goto bad2;
 	}
 
+	hw->flags = IEEE80211_HW_SIGNAL_DBM |
+		IEEE80211_HW_NOISE_DBM;
+
 	SET_IEEE80211_DEV(hw, &pdev->dev);
 	pci_set_drvdata(pdev, hw);
 
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/phy.c b/package/ath9k/src/drivers/net/wireless/ath9k/phy.c
index 6751bedbf..eb9121fdf 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/phy.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/phy.c
@@ -20,7 +20,7 @@
 #include "phy.h"
 
 void
-ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex,
 		    int regWrites)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -29,20 +29,20 @@ ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
 }
 
 bool
-ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
+ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
 {
-	u_int32_t channelSel = 0;
-	u_int32_t bModeSynth = 0;
-	u_int32_t aModeRefSel = 0;
-	u_int32_t reg32 = 0;
-	u_int16_t freq;
+	u32 channelSel = 0;
+	u32 bModeSynth = 0;
+	u32 aModeRefSel = 0;
+	u32 reg32 = 0;
+	u16 freq;
 	struct chan_centers centers;
 
 	ath9k_hw_get_channel_centers(ah, chan, &centers);
 	freq = centers.synth_center;
 
 	if (freq < 4800) {
-		u_int32_t txctl;
+		u32 txctl;
 
 		if (((freq - 2192) % 5) == 0) {
 			channelSel = ((freq - 672) * 2 - 3040) / 10;
@@ -105,12 +105,12 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 
 bool
 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
-			    struct hal_channel_internal *chan)
+			    struct ath9k_channel *chan)
 {
-	u_int16_t bMode, fracMode, aModeRefSel = 0;
-	u_int32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
+	u16 bMode, fracMode, aModeRefSel = 0;
+	u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 	struct chan_centers centers;
-	u_int32_t refDivA = 24;
+	u32 refDivA = 24;
 
 	ath9k_hw_get_channel_centers(ah, chan, &centers);
 	freq = centers.synth_center;
@@ -119,7 +119,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 	reg32 &= 0xc0000000;
 
 	if (freq < 4800) {
-		u_int32_t txctl;
+		u32 txctl;
 
 		bMode = 1;
 		fracMode = 1;
@@ -175,11 +175,11 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 }
 
 static void
-ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
-			   u_int32_t numBits, u_int32_t firstBit,
-			   u_int32_t column)
+ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
+			   u32 numBits, u32 firstBit,
+			   u32 column)
 {
-	u_int32_t tmp32, mask, arrayEntry, lastBit;
+	u32 tmp32, mask, arrayEntry, lastBit;
 	int32_t bitPosition, bitsLeft;
 
 	tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
@@ -202,14 +202,14 @@ ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
 }
 
 bool
-ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
-		     u_int16_t modesIndex)
+ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
+		     u16 modesIndex)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	u_int32_t eepMinorRev;
-	u_int32_t ob5GHz = 0, db5GHz = 0;
-	u_int32_t ob2GHz = 0, db2GHz = 0;
+	u32 eepMinorRev;
+	u32 ob5GHz = 0, db5GHz = 0;
+	u32 ob2GHz = 0, db2GHz = 0;
 	int regWrites = 0;
 
 	if (AR_SREV_9280_10_OR_LATER(ah))
@@ -312,47 +312,32 @@ ath9k_hw_rfdetach(struct ath_hal *ah)
 	}
 }
 
-bool
-ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
-			       struct hal_channel *chans, u_int32_t nchans)
-{
-	bool retVal = true;
-	int i;
-
-	for (i = 0; i < nchans; i++) {
-		chans[i].maxTxPower = AR5416_MAX_RATE_POWER;
-		chans[i].minTxPower = AR5416_MAX_RATE_POWER;
-	}
-	return retVal;
-}
-
-
-bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
+bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (!AR_SREV_9280_10_OR_LATER(ah)) {
 
 		ahp->ah_analogBank0Data =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
 		ahp->ah_analogBank1Data =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
 		ahp->ah_analogBank2Data =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
 		ahp->ah_analogBank3Data =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
 		ahp->ah_analogBank6Data =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 		ahp->ah_analogBank6TPCData =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
 		ahp->ah_analogBank7Data =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
 
 		if (ahp->ah_analogBank0Data == NULL
@@ -365,30 +350,30 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate RF banks\n",
 				 __func__);
-			*status = HAL_ENOMEM;
+			*status = -ENOMEM;
 			return false;
 		}
 
 		ahp->ah_addac5416_21 =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniAddac.ia_rows *
 			     ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
 		if (ahp->ah_addac5416_21 == NULL) {
 			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate ah_addac5416_21\n",
 				 __func__);
-			*status = HAL_ENOMEM;
+			*status = -ENOMEM;
 			return false;
 		}
 
 		ahp->ah_bank6Temp =
-		    kzalloc((sizeof(u_int32_t) *
+		    kzalloc((sizeof(u32) *
 			     ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 		if (ahp->ah_bank6Temp == NULL) {
 			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate ah_bank6Temp\n",
 				 __func__);
-			*status = HAL_ENOMEM;
+			*status = -ENOMEM;
 			return false;
 		}
 	}
@@ -397,27 +382,27 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 }
 
 void
-ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct hal_channel *chan)
+ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
 {
 	int i, regWrites = 0;
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	u_int32_t bank6SelMask;
-	u_int32_t *bank6Temp = ahp->ah_bank6Temp;
+	u32 bank6SelMask;
+	u32 *bank6Temp = ahp->ah_bank6Temp;
 
 	switch (ahp->ah_diversityControl) {
-	case HAL_ANT_FIXED_A:
+	case ATH9K_ANT_FIXED_A:
 		bank6SelMask =
 		    (ahp->
 		     ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
 		    REDUCE_CHAIN_1;
 		break;
-	case HAL_ANT_FIXED_B:
+	case ATH9K_ANT_FIXED_B:
 		bank6SelMask =
 		    (ahp->
 		     ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
 		    REDUCE_CHAIN_0;
 		break;
-	case HAL_ANT_VARIABLE:
+	case ATH9K_ANT_VARIABLE:
 		return;
 		break;
 	default:
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/phy.h b/package/ath9k/src/drivers/net/wireless/ath9k/phy.h
index 6c05257a0..0cd399a53 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/phy.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/phy.h
@@ -18,19 +18,19 @@
 #define PHY_H
 
 bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
-					  struct hal_channel_internal
+					  struct ath9k_channel
 					  *chan);
 bool ath9k_hw_set_channel(struct ath_hal *ah,
-				   struct hal_channel_internal *chan);
-void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
-			 u_int freqIndex, int regWrites);
+				   struct ath9k_channel *chan);
+void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex,
+			 u32 freqIndex, int regWrites);
 bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
-				   struct hal_channel_internal *chan,
-				   u_int16_t modesIndex);
+				   struct ath9k_channel *chan,
+				   u16 modesIndex);
 void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
-				   struct hal_channel *chan);
+				   struct ath9k_channel *chan);
 bool ath9k_hw_init_rf(struct ath_hal *ah,
-			       enum hal_status *status);
+			       int *status);
 
 #define AR_PHY_BASE     0x9800
 #define AR_PHY(_n)      (AR_PHY_BASE + ((_n)<<2))
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/rc.c b/package/ath9k/src/drivers/net/wireless/ath9k/rc.c
index 22b6550c5..e5a632532 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/rc.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/rc.c
@@ -22,7 +22,7 @@
 #include "core.h"
 #include "../net/mac80211/rate.h"
 
-static u_int32_t    tx_triglevel_max;
+static u32 tx_triglevel_max;
 
 static struct ath_rate_table ar5416_11na_ratetable = {
 	42,
@@ -159,13 +159,13 @@ static struct ath_rate_table ar5416_11na_ratetable = {
 	WLAN_RC_HT_FLAG,  /* Phy rates allowed initially */
 };
 
-	/* TRUE_ALL - valid for 20/40/Legacy,
-	 * TRUE - Legacy only,
-	 * TRUE_20 - HT 20 only,
-	 * TRUE_40 - HT 40 only */
+/* TRUE_ALL - valid for 20/40/Legacy,
+ * TRUE - Legacy only,
+ * TRUE_20 - HT 20 only,
+ * TRUE_40 - HT 40 only */
 
-	/* 4ms frame limit not used for NG mode.  The values filled
-	 * for HT are the 64K max aggregate limit */
+/* 4ms frame limit not used for NG mode.  The values filled
+ * for HT are the 64K max aggregate limit */
 
 static struct ath_rate_table ar5416_11ng_ratetable = {
 	46,
@@ -541,19 +541,17 @@ static inline int8_t median(int8_t a, int8_t b, int8_t c)
 }
 
 static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
-					struct ath_tx_ratectrl *rate_ctrl)
+				   struct ath_tx_ratectrl *rate_ctrl)
 {
-	u_int8_t i, j, idx, idx_next;
+	u8 i, j, idx, idx_next;
 
 	for (i = rate_ctrl->max_valid_rate - 1; i > 0; i--) {
 		for (j = 0; j <= i-1; j++) {
-
 			idx = rate_ctrl->valid_rate_index[j];
 			idx_next = rate_ctrl->valid_rate_index[j+1];
 
 			if (rate_table->info[idx].ratekbps >
 				rate_table->info[idx_next].ratekbps) {
-
 				rate_ctrl->valid_rate_index[j] = idx_next;
 				rate_ctrl->valid_rate_index[j+1] = idx;
 			}
@@ -565,34 +563,34 @@ static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
 
 static void ath_rc_init_valid_txmask(struct ath_tx_ratectrl *rate_ctrl)
 {
-	u_int8_t     i;
+	u8 i;
 
 	for (i = 0; i < rate_ctrl->rate_table_size; i++)
 		rate_ctrl->valid_rate_index[i] = FALSE;
 }
 
 static inline void ath_rc_set_valid_txmask(struct ath_tx_ratectrl *rate_ctrl,
-					u_int8_t index, int valid_tx_rate)
+					   u8 index, int valid_tx_rate)
 {
 	ASSERT(index <= rate_ctrl->rate_table_size);
 	rate_ctrl->valid_rate_index[index] = valid_tx_rate ? TRUE : FALSE;
 }
 
 static inline int ath_rc_isvalid_txmask(struct ath_tx_ratectrl *rate_ctrl,
-					u_int8_t index)
+					u8 index)
 {
 	ASSERT(index <= rate_ctrl->rate_table_size);
 	return rate_ctrl->valid_rate_index[index];
 }
 
 /* Iterators for valid_txrate_mask */
-static inline int ath_rc_get_nextvalid_txrate(
-	const struct ath_rate_table *rate_table,
-	struct ath_tx_ratectrl *rate_ctrl,
-	u_int8_t cur_valid_txrate,
-	u_int8_t *next_idx)
+static inline int
+ath_rc_get_nextvalid_txrate(const struct ath_rate_table *rate_table,
+			    struct ath_tx_ratectrl *rate_ctrl,
+			    u8 cur_valid_txrate,
+			    u8 *next_idx)
 {
-	u_int8_t i;
+	u8 i;
 
 	for (i = 0; i < rate_ctrl->max_valid_rate - 1; i++) {
 		if (rate_ctrl->valid_rate_index[i] == cur_valid_txrate) {
@@ -608,7 +606,7 @@ static inline int ath_rc_get_nextvalid_txrate(
 
 /* Return true only for single stream */
 
-static int ath_rc_valid_phyrate(u_int32_t phy, u_int32_t capflag, int ignore_cw)
+static int ath_rc_valid_phyrate(u32 phy, u32 capflag, int ignore_cw)
 {
 	if (WLAN_RC_PHY_HT(phy) & !(capflag & WLAN_RC_HT_FLAG))
 		return FALSE;
@@ -624,10 +622,10 @@ static int ath_rc_valid_phyrate(u_int32_t phy, u_int32_t capflag, int ignore_cw)
 	return TRUE;
 }
 
-static inline int ath_rc_get_nextlowervalid_txrate(
-				const struct ath_rate_table *rate_table,
-				struct ath_tx_ratectrl *rate_ctrl,
-				u_int8_t cur_valid_txrate, u_int8_t *next_idx)
+static inline int
+ath_rc_get_nextlowervalid_txrate(const struct ath_rate_table *rate_table,
+				 struct ath_tx_ratectrl *rate_ctrl,
+				 u8 cur_valid_txrate, u8 *next_idx)
 {
 	int8_t i;
 
@@ -643,13 +641,14 @@ static inline int ath_rc_get_nextlowervalid_txrate(
 /*
  * Initialize the Valid Rate Index from valid entries in Rate Table
  */
-static u_int8_t ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
-					const struct ath_rate_table *rate_table,
-					u_int32_t capflag)
+static u8
+ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
+			   const struct ath_rate_table *rate_table,
+			   u32 capflag)
 {
 	struct ath_tx_ratectrl *rate_ctrl;
-	u_int8_t i, hi = 0;
-	u_int32_t valid;
+	u8 i, hi = 0;
+	u32 valid;
 
 	rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv);
 	for (i = 0; i < rate_table->rate_cnt; i++) {
@@ -657,8 +656,8 @@ static u_int8_t ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
 				rate_table->info[i].valid_single_stream :
 				rate_table->info[i].valid);
 		if (valid == TRUE) {
-			u_int32_t phy = rate_table->info[i].phy;
-			u_int8_t valid_rate_count = 0;
+			u32 phy = rate_table->info[i].phy;
+			u8 valid_rate_count = 0;
 
 			if (!ath_rc_valid_phyrate(phy, capflag, FALSE))
 				continue;
@@ -677,21 +676,22 @@ static u_int8_t ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
 /*
  * Initialize the Valid Rate Index from Rate Set
  */
-static u_int8_t ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
-					const struct ath_rate_table *rate_table,
-					struct ath_rateset *rateset,
-					u_int32_t capflag)
+static u8
+ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
+			  const struct ath_rate_table *rate_table,
+			  struct ath_rateset *rateset,
+			  u32 capflag)
 {
 	/* XXX: Clean me up and make identation friendly */
-	u_int8_t i, j, hi = 0;
+	u8 i, j, hi = 0;
 	struct ath_tx_ratectrl *rate_ctrl =
 		(struct ath_tx_ratectrl *)(ath_rc_priv);
 
 	/* Use intersection of working rates and valid rates */
 	for (i = 0; i < rateset->rs_nrates; i++) {
 		for (j = 0; j < rate_table->rate_cnt; j++) {
-			u_int32_t phy = rate_table->info[j].phy;
-			u_int32_t valid = (ath_rc_priv->single_stream ?
+			u32 phy = rate_table->info[j].phy;
+			u32 valid = (ath_rc_priv->single_stream ?
 				rate_table->info[j].valid_single_stream :
 				rate_table->info[j].valid);
 
@@ -707,7 +707,7 @@ static u_int8_t ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
 				WLAN_RC_CAP_MODE(capflag)) &&
 				!WLAN_RC_PHY_HT(phy)) {
 
-				u_int8_t valid_rate_count = 0;
+				u8 valid_rate_count = 0;
 
 				if (!ath_rc_valid_phyrate(phy, capflag, FALSE))
 					continue;
@@ -726,19 +726,20 @@ static u_int8_t ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
 	return hi;
 }
 
-static u_int8_t ath_rc_sib_setvalid_htrates(struct ath_rate_node *ath_rc_priv,
-				const struct ath_rate_table *rate_table,
-				u_int8_t *mcs_set, u_int32_t capflag)
+static u8
+ath_rc_sib_setvalid_htrates(struct ath_rate_node *ath_rc_priv,
+			    const struct ath_rate_table *rate_table,
+			    u8 *mcs_set, u32 capflag)
 {
-	u_int8_t i, j, hi = 0;
+	u8 i, j, hi = 0;
 	struct ath_tx_ratectrl *rate_ctrl =
 		(struct ath_tx_ratectrl *)(ath_rc_priv);
 
 	/* Use intersection of working rates and valid rates */
 	for (i = 0; i <  ((struct ath_rateset *)mcs_set)->rs_nrates; i++) {
 		for (j = 0; j < rate_table->rate_cnt; j++) {
-			u_int32_t phy = rate_table->info[j].phy;
-			u_int32_t valid = (ath_rc_priv->single_stream ?
+			u32 phy = rate_table->info[j].phy;
+			u32 valid = (ath_rc_priv->single_stream ?
 				rate_table->info[j].valid_single_stream :
 				rate_table->info[j].valid);
 
@@ -785,8 +786,8 @@ struct ath_rate_softc *ath_rate_attach(struct ath_hal *ah)
 }
 
 static struct ath_rate_node *ath_rate_node_alloc(struct ath_vap *avp,
-						struct ath_rate_softc *rsc,
-						gfp_t gfp)
+						 struct ath_rate_softc *rsc,
+						 gfp_t gfp)
 {
 	struct ath_rate_node *anode;
 
@@ -796,6 +797,8 @@ static struct ath_rate_node *ath_rate_node_alloc(struct ath_vap *avp,
 
 	anode->avp = avp;
 	anode->asc = rsc;
+	avp->rc_node = anode;
+
 	return anode;
 }
 
@@ -811,8 +814,8 @@ void ath_rate_detach(struct ath_rate_softc *asc)
 		kfree(asc);
 }
 
-u_int8_t ath_rate_findrateix(struct ath_softc *sc,
-				u_int8_t dot11rate)
+u8 ath_rate_findrateix(struct ath_softc *sc,
+			     u8 dot11rate)
 {
 	const struct ath_rate_table *ratetable;
 	struct ath_rate_softc *rsc = sc->sc_rc;
@@ -824,10 +827,10 @@ u_int8_t ath_rate_findrateix(struct ath_softc *sc,
 		return 0;
 
 	for (i = 0; i < ratetable->rate_cnt; i++) {
-		if ((ratetable->info[i].dot11rate & 0x7f) ==
-				(dot11rate & 0x7f))
+		if ((ratetable->info[i].dot11rate & 0x7f) == (dot11rate & 0x7f))
 			return i;
 	}
+
 	return 0;
 }
 
@@ -837,7 +840,7 @@ u_int8_t ath_rate_findrateix(struct ath_softc *sc,
  * with an AP.  Otherwise this gets called, for example, when
  * the we transition to run state when operating as an AP.
  */
-void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up)
+void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp)
 {
 	struct ath_rate_softc *asc = sc->sc_rc;
 
@@ -862,24 +865,25 @@ void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up)
 	}
 }
 
-static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
-		struct ath_rate_node *ath_rc_priv,
-		const struct ath_rate_table *rate_table,
-		int probe_allowed, int *is_probing, int is_retry)
+static u8 ath_rc_ratefind_ht(struct ath_softc *sc,
+				   struct ath_rate_node *ath_rc_priv,
+				   const struct ath_rate_table *rate_table,
+				   int probe_allowed, int *is_probing,
+				   int is_retry)
 {
-	u_int32_t dt, best_thruput, this_thruput, now_msec;
-	u_int8_t rate, next_rate, best_rate, maxindex, minindex;
+	u32 dt, best_thruput, this_thruput, now_msec;
+	u8 rate, next_rate, best_rate, maxindex, minindex;
 	int8_t  rssi_last, rssi_reduce = 0, index = 0;
 	struct ath_tx_ratectrl  *rate_ctrl = NULL;
 
 	rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv ?
-		(ath_rc_priv) : NULL);
+					       (ath_rc_priv) : NULL);
 
 	*is_probing = FALSE;
 
-	rssi_last   = median(rate_ctrl->rssi_last,
-			rate_ctrl->rssi_last_prev,
-			rate_ctrl->rssi_last_prev2);
+	rssi_last = median(rate_ctrl->rssi_last,
+			   rate_ctrl->rssi_last_prev,
+			   rate_ctrl->rssi_last_prev2);
 
 	/*
 	 * Age (reduce) last ack rssi based on how old it is.
@@ -896,7 +900,7 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
 	if (dt >= 185)
 		rssi_reduce = 10;
 	else if (dt >= 25)
-		rssi_reduce = (u_int8_t)((dt - 25) >> 4);
+		rssi_reduce = (u8)((dt - 25) >> 4);
 
 	/* Now reduce rssi_last by rssi_reduce */
 	if (rssi_last < rssi_reduce)
@@ -910,20 +914,19 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
 	 */
 
 	best_thruput = 0;
-	maxindex    = rate_ctrl->max_valid_rate-1;
+	maxindex = rate_ctrl->max_valid_rate-1;
+
+	minindex = 0;
+	best_rate = minindex;
 
-	minindex    = 0;
-	best_rate    = minindex;
 	/*
 	 * Try the higher rate first. It will reduce memory moving time
 	 * if we have very good channel characteristics.
 	 */
-
 	for (index = maxindex; index >= minindex ; index--) {
-		u_int8_t per_thres;
+		u8 per_thres;
 
 		rate = rate_ctrl->valid_rate_index[index];
-
 		if (rate > rate_ctrl->rate_max_phy)
 			continue;
 
@@ -967,21 +970,20 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
 	 */
 
 	if (rate >= rate_ctrl->rate_max_phy && probe_allowed) {
-
 		rate = rate_ctrl->rate_max_phy;
 
 		/* Probe the next allowed phy state */
 		/* FIXME:XXXX Check to make sure ratMax is checked properly */
 		if (ath_rc_get_nextvalid_txrate(rate_table,
-				rate_ctrl, rate, &next_rate) &&
-				(now_msec - rate_ctrl->probe_time >
-					rate_table->probe_interval) &&
-				(rate_ctrl->hw_maxretry_pktcnt >= 1)) {
-			rate                  = next_rate;
-			rate_ctrl->probe_rate        = rate;
-			rate_ctrl->probe_time        = now_msec;
+						rate_ctrl, rate, &next_rate) &&
+		    (now_msec - rate_ctrl->probe_time >
+		     rate_table->probe_interval) &&
+		    (rate_ctrl->hw_maxretry_pktcnt >= 1)) {
+			rate = next_rate;
+			rate_ctrl->probe_rate = rate;
+			rate_ctrl->probe_time = now_msec;
 			rate_ctrl->hw_maxretry_pktcnt = 0;
-			*is_probing            = TRUE;
+			*is_probing = TRUE;
 		}
 	}
 
@@ -1002,29 +1004,32 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
 }
 
 static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table ,
-		struct ath_rc_series *series, u_int8_t tries, u_int8_t rix,
-		int rtsctsenable)
+				   struct ath_rc_series *series,
+				   u8 tries,
+				   u8 rix,
+				   int rtsctsenable)
 {
 	series->tries = tries;
 	series->flags = (rtsctsenable? ATH_RC_RTSCTS_FLAG : 0) |
 		(WLAN_RC_PHY_DS(rate_table->info[rix].phy) ?
-			ATH_RC_DS_FLAG : 0) |
+		 ATH_RC_DS_FLAG : 0) |
 		(WLAN_RC_PHY_40(rate_table->info[rix].phy) ?
-			ATH_RC_CW40_FLAG : 0) |
+		 ATH_RC_CW40_FLAG : 0) |
 		(WLAN_RC_PHY_SGI(rate_table->info[rix].phy) ?
-			ATH_RC_SGI_FLAG : 0);
+		 ATH_RC_SGI_FLAG : 0);
 
 	series->rix = rate_table->info[rix].base_index;
 	series->max_4ms_framelen = rate_table->info[rix].max_4ms_framelen;
 }
 
-static u_int8_t ath_rc_rate_getidx(struct ath_softc *sc,
-		struct ath_rate_node *ath_rc_priv,
-		const struct ath_rate_table *rate_table,
-		u_int8_t rix, u_int16_t stepdown, u_int16_t min_rate)
+static u8 ath_rc_rate_getidx(struct ath_softc *sc,
+				   struct ath_rate_node *ath_rc_priv,
+				   const struct ath_rate_table *rate_table,
+				   u8 rix, u16 stepdown,
+				   u16 min_rate)
 {
-	u_int32_t j;
-	u_int8_t nextindex;
+	u32 j;
+	u8 nextindex;
 	struct ath_tx_ratectrl *rate_ctrl =
 		(struct ath_tx_ratectrl *)(ath_rc_priv);
 
@@ -1049,11 +1054,12 @@ static u_int8_t ath_rc_rate_getidx(struct ath_softc *sc,
 }
 
 static void ath_rc_ratefind(struct ath_softc *sc,
-		struct ath_rate_node *ath_rc_priv,
-		int num_tries, int num_rates, unsigned int rcflag,
-		struct ath_rc_series series[], int *is_probe, int is_retry)
+			    struct ath_rate_node *ath_rc_priv,
+			    int num_tries, int num_rates, unsigned int rcflag,
+			    struct ath_rc_series series[], int *is_probe,
+			    int is_retry)
 {
-	u_int8_t try_per_rate = 0, i = 0, rix, nrix;
+	u8 try_per_rate = 0, i = 0, rix, nrix;
 	struct ath_rate_softc  *asc = (struct ath_rate_softc *)sc->sc_rc;
 	struct ath_rate_table *rate_table;
 
@@ -1087,10 +1093,10 @@ static void ath_rc_ratefind(struct ath_softc *sc,
 
 	/* Fill in the other rates for multirate retry */
 	for ( ; i < num_rates; i++) {
-		u_int8_t try_num;
-		u_int8_t min_rate;
+		u8 try_num;
+		u8 min_rate;
 
-		try_num  = ((i + 1) == num_rates) ?
+		try_num = ((i + 1) == num_rates) ?
 			num_tries - (try_per_rate * i) : try_per_rate ;
 		min_rate = (((i + 1) == num_rates) &&
 			(rcflag & ATH_RC_MINRATE_LASTRATE)) ? 1 : 0;
@@ -1120,8 +1126,8 @@ static void ath_rc_ratefind(struct ath_softc *sc,
 	if ((sc->sc_curmode == WIRELESS_MODE_11NG_HT20) ||
 			(sc->sc_curmode == WIRELESS_MODE_11NG_HT40PLUS) ||
 			(sc->sc_curmode == WIRELESS_MODE_11NG_HT40MINUS)) {
-		u_int8_t  dot11rate = rate_table->info[rix].dot11rate;
-		u_int8_t phy = rate_table->info[rix].phy;
+		u8  dot11rate = rate_table->info[rix].dot11rate;
+		u8 phy = rate_table->info[rix].phy;
 		if (i == 4 &&
 		    ((dot11rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) ||
 		    (dot11rate == 3 && phy == WLAN_RC_PHY_HT_20_SS))) {
@@ -1135,19 +1141,16 @@ static void ath_rc_ratefind(struct ath_softc *sc,
 /*
  * Return the Tx rate series.
  */
-
-
 void ath_rate_findrate(struct ath_softc *sc,
-		struct ath_rate_node *ath_rc_priv,
-		int num_tries,
-		int num_rates,
-		unsigned int rcflag,
-		struct ath_rc_series series[],
-		int *is_probe,
-		int is_retry
-		)
+		       struct ath_rate_node *ath_rc_priv,
+		       int num_tries,
+		       int num_rates,
+		       unsigned int rcflag,
+		       struct ath_rc_series series[],
+		       int *is_probe,
+		       int is_retry)
 {
-	struct ath_vap         *avp = ath_rc_priv->avp;
+	struct ath_vap *avp = ath_rc_priv->avp;
 
 	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	if (!num_rates || !num_tries)
@@ -1159,8 +1162,8 @@ void ath_rate_findrate(struct ath_softc *sc,
 	} else {
 		/* Fixed rate */
 		int idx;
-		u_int8_t flags;
-		u_int32_t rix;
+		u8 flags;
+		u32 rix;
 		struct ath_rate_softc *asc = ath_rc_priv->asc;
 		struct ath_rate_table *rate_table;
 
@@ -1169,7 +1172,7 @@ void ath_rate_findrate(struct ath_softc *sc,
 
 		for (idx = 0; idx < 4; idx++) {
 			unsigned int    mcs;
-			u_int8_t series_rix = 0;
+			u8 series_rix = 0;
 
 			series[idx].tries =
 				IEEE80211_RATE_IDX_ENTRY(
@@ -1222,14 +1225,14 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 			     int tx_rate, int xretries, int retries)
 {
 	struct ath_tx_ratectrl *rate_ctrl;
-	u_int32_t now_msec = jiffies_to_msecs(jiffies);
+	u32 now_msec = jiffies_to_msecs(jiffies);
 	int state_change = FALSE, rate, count;
-	u_int8_t last_per;
+	u8 last_per;
 	struct ath_rate_softc  *asc = (struct ath_rate_softc *)sc->sc_rc;
 	struct ath_rate_table *rate_table =
 		(struct ath_rate_table *)asc->hw_rate_table[sc->sc_curmode];
 
-	static u_int32_t nretry_to_per_lookup[10] = {
+	static u32 nretry_to_per_lookup[10] = {
 		100 * 0 / 1,
 		100 * 1 / 4,
 		100 * 1 / 2,
@@ -1265,7 +1268,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 			rate_ctrl->state[tx_rate].per += 30;
 			if (rate_ctrl->state[tx_rate].per > 100)
 				rate_ctrl->state[tx_rate].per = 100;
-
 		} else {
 			/* xretries == 2 */
 			count = sizeof(nretry_to_per_lookup) /
@@ -1274,7 +1276,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 				retries = count - 1;
 			/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
 			rate_ctrl->state[tx_rate].per =
-				(u_int8_t)(rate_ctrl->state[tx_rate].per -
+				(u8)(rate_ctrl->state[tx_rate].per -
 				(rate_ctrl->state[tx_rate].per >> 3) +
 				((100) >> 3));
 		}
@@ -1285,7 +1287,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 			rate_ctrl->probe_rate = 0;
 
 	} else {	/* xretries == 0 */
-
 		/* Update the PER. */
 		/* Make sure it doesn't index out of array's bounds. */
 		count = sizeof(nretry_to_per_lookup) /
@@ -1308,7 +1309,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 			 */
 			if (info_priv->n_frames > 0)
 				rate_ctrl->state[tx_rate].per
-				      = (u_int8_t)
+				      = (u8)
 					(rate_ctrl->state[tx_rate].per -
 					(rate_ctrl->state[tx_rate].per >> 3) +
 					((100*(retries*info_priv->n_frames +
@@ -1318,7 +1319,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 		} else {
 			/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
 
-			rate_ctrl->state[tx_rate].per = (u_int8_t)
+			rate_ctrl->state[tx_rate].per = (u8)
 				(rate_ctrl->state[tx_rate].per -
 				(rate_ctrl->state[tx_rate].per >> 3) +
 				(nretry_to_per_lookup[retries] >> 3));
@@ -1326,8 +1327,8 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 
 		rate_ctrl->rssi_last_prev2 = rate_ctrl->rssi_last_prev;
 		rate_ctrl->rssi_last_prev  = rate_ctrl->rssi_last;
-		rate_ctrl->rssi_last      = info_priv->tx.ts_rssi;
-		rate_ctrl->rssi_time      = now_msec;
+		rate_ctrl->rssi_last = info_priv->tx.ts_rssi;
+		rate_ctrl->rssi_time = now_msec;
 
 		/*
 		 * If we got at most one retry then increase the max rate if
@@ -1346,7 +1347,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 				 */
 				rate_ctrl->probe_rate = 0;
 			} else {
-				u_int8_t probe_rate = 0;
+				u8 probe_rate = 0;
 
 				rate_ctrl->rate_max_phy = rate_ctrl->probe_rate;
 				probe_rate = rate_ctrl->probe_rate;
@@ -1427,7 +1428,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 		}
 	}
 
-
 	/* For all cases */
 
 	/*
@@ -1438,7 +1438,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
 			rate_table->info[tx_rate].ratekbps <=
 			rate_table->info[rate_ctrl->rate_max_phy].ratekbps) {
 		ath_rc_get_nextlowervalid_txrate(rate_table, rate_ctrl,
-				(u_int8_t) tx_rate, &rate_ctrl->rate_max_phy);
+				(u8) tx_rate, &rate_ctrl->rate_max_phy);
 
 		/* Don't probe for a little while. */
 		rate_ctrl->probe_time = now_msec;
@@ -1555,16 +1555,16 @@ static void ath_rc_update_ht(struct ath_softc *sc,
  * the status of previous frames.
  */
 static void ath_rc_update(struct ath_softc *sc,
-		struct ath_rate_node *ath_rc_priv,
-		struct ath_tx_info_priv *info_priv, int final_ts_idx,
-		int xretries, int long_retry)
+			  struct ath_rate_node *ath_rc_priv,
+			  struct ath_tx_info_priv *info_priv, int final_ts_idx,
+			  int xretries, int long_retry)
 {
 	struct ath_rate_softc  *asc = (struct ath_rate_softc *)sc->sc_rc;
 	struct ath_rate_table *rate_table;
 	struct ath_tx_ratectrl *rate_ctrl;
 	struct ath_rc_series rcs[4];
-	u_int8_t flags;
-	u_int32_t series = 0, rix;
+	u8 flags;
+	u32 series = 0, rix;
 
 	memcpy(rcs, info_priv->rcs, 4 * sizeof(rcs[0]));
 	rate_table = (struct ath_rate_table *)
@@ -1577,7 +1577,6 @@ static void ath_rc_update(struct ath_softc *sc,
 	 * are intermediate rate failures to be processed.
 	 */
 	if (final_ts_idx != 0) {
-
 		/* Process intermediate rates that failed.*/
 		for (series = 0; series < final_ts_idx ; series++) {
 			if (rcs[series].tries != 0) {
@@ -1641,10 +1640,10 @@ static void ath_rc_update(struct ath_softc *sc,
 /*
  * Process a tx descriptor for a completed transmit (success or failure).
  */
-
 static void ath_rate_tx_complete(struct ath_softc *sc,
-		struct ath_node *an, struct ath_rate_node *rc_priv,
-		struct ath_tx_info_priv *info_priv)
+				 struct ath_node *an,
+				 struct ath_rate_node *rc_priv,
+				 struct ath_tx_info_priv *info_priv)
 {
 	int final_ts_idx = info_priv->tx.ts_rateindex;
 	int tx_status = 0, is_underrun = 0;
@@ -1678,8 +1677,8 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
 		tx_status = 1;
 
 	ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status,
-			(is_underrun) ? ATH_11N_TXMAXTRY
-			:info_priv->tx.ts_longretry);
+		      (is_underrun) ? ATH_11N_TXMAXTRY :
+		      info_priv->tx.ts_longretry);
 }
 
 
@@ -1692,18 +1691,18 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
  *  It will determine which rates are valid for use.
  */
 static void ath_rc_sib_update(struct ath_softc *sc,
-			struct ath_rate_node *ath_rc_priv,
-			u_int32_t capflag, int keep_state,
-			struct ath_rateset *negotiated_rates,
-			struct ath_rateset *negotiated_htrates)
+			      struct ath_rate_node *ath_rc_priv,
+			      u32 capflag, int keep_state,
+			      struct ath_rateset *negotiated_rates,
+			      struct ath_rateset *negotiated_htrates)
 {
 	struct ath_rate_table *rate_table = NULL;
 	struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
 	struct ath_rateset *rateset = negotiated_rates;
-	u_int8_t *ht_mcs = (u_int8_t *)negotiated_htrates;
+	u8 *ht_mcs = (u8 *)negotiated_htrates;
 	struct ath_tx_ratectrl *rate_ctrl  = (struct ath_tx_ratectrl *)
 		(ath_rc_priv);
-	u_int8_t i, j, k, hi = 0, hthi = 0;
+	u8 i, j, k, hi = 0, hthi = 0;
 
 	rate_table = (struct ath_rate_table *)
 		asc->hw_rate_table[sc->sc_curmode];
@@ -1716,7 +1715,7 @@ static void ath_rc_sib_update(struct ath_softc *sc,
 	for (i = 0 ; (i < rate_ctrl->rate_table_size) && (!keep_state); i++) {
 		rate_ctrl->state[i].rssi_thres =
 			rate_table->info[i].rssi_ack_validmin;
-		rate_ctrl->state[i].per       = 0;
+		rate_ctrl->state[i].per = 0;
 	}
 
 	/* Determine the valid rates */
@@ -1739,10 +1738,12 @@ static void ath_rc_sib_update(struct ath_softc *sc,
 	} else {
 		/* Use intersection of working rates and valid rates */
 		hi = ath_rc_sib_setvalid_rates(ath_rc_priv, rate_table,
-						rateset, capflag);
+					       rateset, capflag);
 		if (capflag & WLAN_RC_HT_FLAG) {
 			hthi = ath_rc_sib_setvalid_htrates(ath_rc_priv,
-						rate_table, ht_mcs, capflag);
+							   rate_table,
+							   ht_mcs,
+							   capflag);
 		}
 		hi = A_MAX(hi, hthi);
 	}
@@ -1758,7 +1759,7 @@ static void ath_rc_sib_update(struct ath_softc *sc,
 		}
 
 		if (!ath_rc_valid_phyrate(i, rate_table->initial_ratemax, TRUE)
-				      || !rate_ctrl->valid_phy_ratecnt[i])
+		    || !rate_ctrl->valid_phy_ratecnt[i])
 			continue;
 
 		rate_ctrl->rate_max_phy = rate_ctrl->valid_phy_rateidx[i][j-1];
@@ -1780,10 +1781,10 @@ static void ath_rc_sib_update(struct ath_softc *sc,
  * Update rate-control state on station associate/reassociate.
  */
 static int ath_rate_newassoc(struct ath_softc *sc,
-		struct ath_rate_node *ath_rc_priv,
-		unsigned int capflag,
-		struct ath_rateset *negotiated_rates,
-		struct ath_rateset *negotiated_htrates)
+			     struct ath_rate_node *ath_rc_priv,
+			     unsigned int capflag,
+			     struct ath_rateset *negotiated_rates,
+			     struct ath_rateset *negotiated_htrates)
 {
 
 
@@ -1794,7 +1795,7 @@ static int ath_rate_newassoc(struct ath_softc *sc,
 		((capflag & ATH_RC_CW40_FLAG) ? WLAN_RC_40_FLAG : 0);
 
 	ath_rc_sib_update(sc, ath_rc_priv, ath_rc_priv->ht_cap, 0,
-			negotiated_rates, negotiated_htrates);
+			  negotiated_rates, negotiated_htrates);
 
 	return 0;
 }
@@ -1834,15 +1835,14 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta)
 	rc_priv->neg_rates.rs_nrates = j;
 }
 
-static void ath_rc_node_update(struct ieee80211_hw *hw,
-				struct ath_rate_node *rc_priv)
+void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv)
 {
 	struct ath_softc *sc = hw->priv;
-	u_int32_t capflag = 0;
+	u32 capflag = 0;
 
 	if (hw->conf.ht_conf.ht_supported) {
 		capflag |= ATH_RC_HT_FLAG | ATH_RC_DS_FLAG;
-		if (sc->sc_ht_info.tx_chan_width == HAL_HT_MACMODE_2040)
+		if (sc->sc_ht_info.tx_chan_width == ATH9K_HT_MACMODE_2040)
 			capflag |= ATH_RC_CW40_FLAG;
 	}
 
@@ -2027,8 +2027,8 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 }
 
 static void ath_rate_init(void *priv, void *priv_sta,
-			    struct ieee80211_local *local,
-			    struct sta_info *sta)
+			  struct ieee80211_local *local,
+			  struct sta_info *sta)
 {
 	struct ieee80211_supported_band *sband;
 	struct ieee80211_hw *hw = local_to_hw(local);
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/rc.h b/package/ath9k/src/drivers/net/wireless/ath9k/rc.h
index 3ed04b2f2..7642a44bf 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/rc.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/rc.h
@@ -149,31 +149,31 @@ struct ath_rate_table {
 		int valid;            /* Valid for use in rate control */
 		int valid_single_stream;/* Valid for use in rate control
 					for single stream operation */
-		u_int8_t phy;              /* CCK/OFDM/TURBO/XR */
-		u_int32_t ratekbps;         /* Rate in Kbits per second */
-		u_int32_t user_ratekbps;     /* User rate in KBits per second */
-		u_int8_t ratecode;         /* rate that goes into
+		u8 phy;              /* CCK/OFDM/TURBO/XR */
+		u32 ratekbps;         /* Rate in Kbits per second */
+		u32 user_ratekbps;     /* User rate in KBits per second */
+		u8 ratecode;         /* rate that goes into
 					hw descriptors */
-		u_int8_t short_preamble;    /* Mask for enabling short preamble
+		u8 short_preamble;    /* Mask for enabling short preamble
 						in rate code for CCK */
-		u_int8_t dot11rate;        /* Value that goes into supported
+		u8 dot11rate;        /* Value that goes into supported
 					rates info element of MLME */
-		u_int8_t ctrl_rate;      /* Index of next lower basic rate,
+		u8 ctrl_rate;      /* Index of next lower basic rate,
 					used for duration computation */
 		int8_t rssi_ack_validmin;  /* Rate control related */
 		int8_t rssi_ack_deltamin;  /* Rate control related */
-		u_int8_t base_index;        /* base rate index */
-		u_int8_t cw40index;        /* 40cap rate index */
-		u_int8_t sgi_index;         /* shortgi rate index */
-		u_int8_t ht_index;          /* shortgi rate index */
-		u_int32_t max_4ms_framelen;   /* Maximum frame length(bytes)
+		u8 base_index;        /* base rate index */
+		u8 cw40index;        /* 40cap rate index */
+		u8 sgi_index;         /* shortgi rate index */
+		u8 ht_index;          /* shortgi rate index */
+		u32 max_4ms_framelen;   /* Maximum frame length(bytes)
 						for 4ms tx duration */
 	} info[RATE_TABLE_SIZE];
-	u_int32_t probe_interval;        /* interval for ratectrl to
+	u32 probe_interval;        /* interval for ratectrl to
 					probe for other rates */
-	u_int32_t rssi_reduce_interval;   /* interval for ratectrl
+	u32 rssi_reduce_interval;   /* interval for ratectrl
 						to reduce RSSI */
-	u_int8_t initial_ratemax;   /* the initial ratemax value used
+	u8 initial_ratemax;   /* the initial ratemax value used
 					in ath_rc_sib_update() */
 };
 
@@ -182,10 +182,10 @@ struct ath_rate_table {
 #define ATH_RC_SHORT_PREAMBLE           0x00000004
 
 struct ath_rc_series {
-	u_int8_t    rix;
-	u_int8_t    tries;
-	u_int8_t    flags;
-	u_int32_t   max_4ms_framelen;
+	u8    rix;
+	u8    tries;
+	u8    flags;
+	u32   max_4ms_framelen;
 };
 
 /* rcs_flags definition */
@@ -203,7 +203,7 @@ struct ath_rc_series {
 
 struct ath_tx_ratectrl_state {
 	int8_t rssi_thres; /* required rssi for this rate (dB) */
-	u_int8_t per; /* recent estimate of packet error rate (%) */
+	u8 per; /* recent estimate of packet error rate (%) */
 };
 
 struct ath_tx_ratectrl {
@@ -215,34 +215,34 @@ struct ath_tx_ratectrl {
 	int32_t rssi_sum_cnt;        /* count of rssi_sum for averaging */
 	int32_t rssi_sum_rate;       /* rate that we are averaging */
 	int32_t rssi_sum;           /* running sum of rssi for averaging */
-	u_int32_t valid_txrate_mask;   /* mask of valid rates */
-	u_int8_t rate_table_size;      /* rate table size */
-	u_int8_t rate_max;            /* max rate that has recently worked */
-	u_int8_t probe_rate;          /* rate we are probing at */
-	u_int32_t rssi_time;          /* msec timestamp for last ack rssi */
-	u_int32_t rssi_down_time;      /* msec timestamp for last down step */
-	u_int32_t probe_time;         /* msec timestamp for last probe */
-	u_int8_t hw_maxretry_pktcnt;   /* num packets since we got
+	u32 valid_txrate_mask;   /* mask of valid rates */
+	u8 rate_table_size;      /* rate table size */
+	u8 rate_max;            /* max rate that has recently worked */
+	u8 probe_rate;          /* rate we are probing at */
+	u32 rssi_time;          /* msec timestamp for last ack rssi */
+	u32 rssi_down_time;      /* msec timestamp for last down step */
+	u32 probe_time;         /* msec timestamp for last probe */
+	u8 hw_maxretry_pktcnt;   /* num packets since we got
 					HW max retry error */
-	u_int8_t max_valid_rate;       /* maximum number of valid rate */
-	u_int8_t valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */
-	u_int32_t per_down_time;       /* msec timstamp for last
+	u8 max_valid_rate;       /* maximum number of valid rate */
+	u8 valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */
+	u32 per_down_time;       /* msec timstamp for last
 					PER down step */
 
 	/* 11n state */
-	u_int8_t  valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */
-	u_int8_t  valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL];
-	u_int8_t  rc_phy_mode;
-	u_int8_t  rate_max_phy;        /* Phy index for the max rate */
-	u_int32_t rate_max_lastused;   /* msec timstamp of when we
+	u8  valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */
+	u8  valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL];
+	u8  rc_phy_mode;
+	u8  rate_max_phy;        /* Phy index for the max rate */
+	u32 rate_max_lastused;   /* msec timstamp of when we
 					last used rateMaxPhy */
-	u_int32_t probe_interval;     /* interval for ratectrl to probe
+	u32 probe_interval;     /* interval for ratectrl to probe
 					for other rates */
 };
 
 struct ath_rateset {
-	u_int8_t rs_nrates;
-	u_int8_t rs_rates[ATH_RATE_MAX];
+	u8 rs_nrates;
+	u8 rs_rates[ATH_RATE_MAX];
 };
 
 /* per-device state */
@@ -255,18 +255,18 @@ struct ath_rate_softc {
 /* per-node state */
 struct ath_rate_node {
 	struct ath_tx_ratectrl tx_ratectrl;	/* rate control state proper */
-	u_int32_t prev_data_rix;	/* rate idx of last data frame */
+	u32 prev_data_rix;	/* rate idx of last data frame */
 
 	/* map of rate ix -> negotiated rate set ix */
-	u_int8_t rixmap[MAX_TX_RATE_TBL];
+	u8 rixmap[MAX_TX_RATE_TBL];
 
 	/* map of ht rate ix -> negotiated rate set ix */
-	u_int8_t ht_rixmap[MAX_TX_RATE_TBL];
+	u8 ht_rixmap[MAX_TX_RATE_TBL];
 
-	u_int8_t ht_cap;		/* ht capabilities */
-	u_int8_t ant_tx;		/* current transmit antenna */
+	u8 ht_cap;		/* ht capabilities */
+	u8 ant_tx;		/* current transmit antenna */
 
-	u_int8_t single_stream;   /* When TRUE, only single
+	u8 single_stream;   /* When TRUE, only single
 				stream Tx possible */
 	struct ath_rateset neg_rates;	/* Negotiated rates */
 	struct ath_rateset neg_ht_rates;	/* Negotiated HT rates */
@@ -280,7 +280,7 @@ struct ath_tx_info_priv {
 	struct ath_tx_status tx;
 	int n_frames;
 	int n_bad_frames;
-	u_int8_t min_rate;
+	u8 min_rate;
 };
 
 /*
@@ -294,7 +294,8 @@ void ath_rate_detach(struct ath_rate_softc *asc);
  * Important mostly as the analog to ath_rate_newassoc when operating
  * in station mode.
  */
-void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up);
+void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv);
+void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp);
 
 /*
  * Return the tx rate series.
@@ -306,8 +307,8 @@ void ath_rate_findrate(struct ath_softc *sc, struct ath_rate_node *ath_rc_priv,
 /*
  * Return rate index for given Dot11 Rate.
  */
-u_int8_t ath_rate_findrateix(struct ath_softc *sc,
-			     u_int8_t dot11_rate);
+u8 ath_rate_findrateix(struct ath_softc *sc,
+			     u8 dot11_rate);
 
 /* Routines to register/unregister rate control algorithm */
 int ath_rate_control_register(void);
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/recv.c b/package/ath9k/src/drivers/net/wireless/ath9k/recv.c
index 6aefe59f4..8e14e643e 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/recv.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/recv.c
@@ -75,7 +75,7 @@ static int ath_bar_rx(struct ath_softc *sc,
 	struct sk_buff *tskb;
 	struct ath_recv_status *rx_status;
 	int tidno, index, cindex;
-	u_int16_t seqno;
+	u16 seqno;
 
 	/* look at BAR contents	 */
 
@@ -148,8 +148,8 @@ static int ath_ampdu_input(struct ath_softc *sc,
 	struct ieee80211_hdr *hdr;
 	struct ath_arx_tid *rxtid;
 	struct ath_rxbuf *rxbuf;
-	u_int8_t type, subtype;
-	u_int16_t rxseq;
+	u8 type, subtype;
+	u16 rxseq;
 	int tid = 0, index, cindex, rxdiff;
 	__le16 fc;
 	u8 *qc;
@@ -184,7 +184,7 @@ static int ath_ampdu_input(struct ath_softc *sc,
 		tid = qc[0] & 0xf;
 	}
 
-	if (sc->sc_opmode == HAL_M_STA) {
+	if (sc->sc_opmode == ATH9K_M_STA) {
 		/* Drop the frame not belonging to me. */
 		if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) {
 			dev_kfree_skb(skb);
@@ -386,10 +386,10 @@ static void ath_rx_flush_tid(struct ath_softc *sc,
 }
 
 static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
-	u_int32_t len)
+	u32 len)
 {
 	struct sk_buff *skb;
-	u_int off;
+	u32 off;
 
 	/*
 	 * Cache-line-align.  This is important (for the
@@ -441,7 +441,7 @@ static void ath_rx_requeue(struct ath_softc *sc, struct sk_buff *skb)
 static int ath_rx_indicate(struct ath_softc *sc,
 			   struct sk_buff *skb,
 			   struct ath_recv_status *status,
-			   u_int16_t keyix)
+			   u16 keyix)
 {
 	struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
 	struct sk_buff *nskb;
@@ -471,7 +471,7 @@ static int ath_rx_indicate(struct ath_softc *sc,
 static void ath_opmode_init(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	u_int32_t rfilt, mfilt[2];
+	u32 rfilt, mfilt[2];
 
 	/* configure rx filter */
 	rfilt = ath_calcrxfilter(sc);
@@ -515,7 +515,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
 		 */
 		sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN,
 					   min(sc->sc_cachelsz,
-					       (u_int16_t)64));
+					       (u16)64));
 
 		DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
 			__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
@@ -594,34 +594,34 @@ void ath_rx_cleanup(struct ath_softc *sc)
  *   - when scanning
  */
 
-u_int32_t ath_calcrxfilter(struct ath_softc *sc)
+u32 ath_calcrxfilter(struct ath_softc *sc)
 {
-#define	RX_FILTER_PRESERVE	(HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR)
-	u_int32_t rfilt;
+#define	RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
+	u32 rfilt;
 
 	rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
-		| HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST
-		| HAL_RX_FILTER_MCAST;
+		| ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
+		| ATH9K_RX_FILTER_MCAST;
 
 	/* If not a STA, enable processing of Probe Requests */
-	if (sc->sc_opmode != HAL_M_STA)
-		rfilt |= HAL_RX_FILTER_PROBEREQ;
+	if (sc->sc_opmode != ATH9K_M_STA)
+		rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 
 	/* Can't set HOSTAP into promiscous mode */
-	if (sc->sc_opmode == HAL_M_MONITOR) {
-		rfilt |= HAL_RX_FILTER_PROM;
+	if (sc->sc_opmode == ATH9K_M_MONITOR) {
+		rfilt |= ATH9K_RX_FILTER_PROM;
 		/* ??? To prevent from sending ACK */
-		rfilt &= ~HAL_RX_FILTER_UCAST;
+		rfilt &= ~ATH9K_RX_FILTER_UCAST;
 	}
 
-	if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS ||
+	if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS ||
 	    sc->sc_scanning)
-		rfilt |= HAL_RX_FILTER_BEACON;
+		rfilt |= ATH9K_RX_FILTER_BEACON;
 
 	/* If in HOSTAP mode, want to enable reception of PSPOLL frames
 	   & beacon frames */
-	if (sc->sc_opmode == HAL_M_HOSTAP)
-		rfilt |= (HAL_RX_FILTER_BEACON | HAL_RX_FILTER_PSPOLL);
+	if (sc->sc_opmode == ATH9K_M_HOSTAP)
+		rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
 	return rfilt;
 #undef RX_FILTER_PRESERVE
 }
@@ -677,7 +677,7 @@ start_recv:
 bool ath_stoprecv(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	u_int64_t tsf;
+	u64 tsf;
 	bool stopped;
 
 	ath9k_hw_stoppcurecv(ah);	/* disable PCU */
@@ -743,9 +743,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 	struct ath_recv_status rx_status;
 	struct ath_hal *ah = sc->sc_ah;
 	int type, rx_processed = 0;
-	u_int phyerr;
-	u_int8_t chainreset = 0;
-	enum hal_status retval;
+	u32 phyerr;
+	u8 chainreset = 0;
+	int retval;
 	__le16 fc;
 
 	do {
@@ -812,7 +812,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 					     bf->bf_daddr,
 					     PA2DESC(sc, ds->ds_link),
 					     0);
-		if (HAL_EINPROGRESS == retval) {
+		if (retval == -EINPROGRESS) {
 			struct ath_buf *tbf;
 			struct ath_desc *tds;
 
@@ -838,7 +838,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 			retval = ath9k_hw_rxprocdesc(ah,
 				tds, tbf->bf_daddr,
 				PA2DESC(sc, tds->ds_link), 0);
-			if (HAL_EINPROGRESS == retval) {
+			if (retval == -EINPROGRESS) {
 				spin_unlock_bh(&sc->sc_rxbuflock);
 				break;
 			}
@@ -900,7 +900,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 			 * Enable this if you want to see
 			 * error frames in Monitor mode.
 			 */
-			if (sc->sc_opmode != HAL_M_MONITOR)
+			if (sc->sc_opmode != ATH9K_M_MONITOR)
 				goto rx_next;
 #endif
 			/* fall thru for monitor mode handling... */
@@ -945,7 +945,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 			 * decryption and MIC failures. For monitor mode,
 			 * we also ignore the CRC error.
 			 */
-			if (sc->sc_opmode == HAL_M_MONITOR) {
+			if (sc->sc_opmode == ATH9K_M_MONITOR) {
 				if (ds->ds_rxstat.rs_status &
 				    ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
 					ATH9K_RXERR_CRC))
@@ -1199,7 +1199,7 @@ int ath_rx_aggr_stop(struct ath_softc *sc,
 /* Rx aggregation tear down */
 
 void ath_rx_aggr_teardown(struct ath_softc *sc,
-	struct ath_node *an, u_int8_t tid)
+	struct ath_node *an, u8 tid)
 {
 	struct ath_arx_tid *rxtid = &an->an_aggr.rx.tid[tid];
 
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/regd.c b/package/ath9k/src/drivers/net/wireless/ath9k/regd.c
index 8a99365ab..7b0176e3e 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/regd.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/regd.c
@@ -17,13 +17,14 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include "core.h"
+#include "hw.h"
 #include "regd.h"
 #include "regd_common.h"
 
 static int ath9k_regd_chansort(const void *a, const void *b)
 {
-	const struct hal_channel_internal *ca = a;
-	const struct hal_channel_internal *cb = b;
+	const struct ath9k_channel *ca = a;
+	const struct ath9k_channel *cb = b;
 
 	return (ca->channel == cb->channel) ?
 	    (ca->channelFlags & CHAN_FLAGS) -
@@ -31,26 +32,26 @@ static int ath9k_regd_chansort(const void *a, const void *b)
 }
 
 static void
-ath9k_regd_sort(void *a, u_int32_t n, u_int32_t size, ath_hal_cmp_t *cmp)
+ath9k_regd_sort(void *a, u32 n, u32 size, ath_hal_cmp_t *cmp)
 {
-	u_int8_t *aa = a;
-	u_int8_t *ai, *t;
+	u8 *aa = a;
+	u8 *ai, *t;
 
 	for (ai = aa + size; --n >= 1; ai += size)
 		for (t = ai; t > aa; t -= size) {
-			u_int8_t *u = t - size;
+			u8 *u = t - size;
 			if (cmp(u, t) <= 0)
 				break;
 			swap(u, t, size);
 		}
 }
 
-static u_int16_t ath9k_regd_get_eepromRD(struct ath_hal *ah)
+static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah)
 {
 	return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG;
 }
 
-static bool ath9k_regd_is_chan_bm_zero(u_int64_t *bitmask)
+static bool ath9k_regd_is_chan_bm_zero(u64 *bitmask)
 {
 	int i;
 
@@ -63,11 +64,11 @@ static bool ath9k_regd_is_chan_bm_zero(u_int64_t *bitmask)
 
 static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
 {
-	u_int16_t rd = ath9k_regd_get_eepromRD(ah);
+	u16 rd = ath9k_regd_get_eepromRD(ah);
 	int i;
 
 	if (rd & COUNTRY_ERD_FLAG) {
-		u_int16_t cc = rd & ~COUNTRY_ERD_FLAG;
+		u16 cc = rd & ~COUNTRY_ERD_FLAG;
 		for (i = 0; i < ARRAY_SIZE(allCountries); i++)
 			if (allCountries[i].countryCode == cc)
 				return true;
@@ -84,7 +85,7 @@ static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
 
 static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
 {
-	u_int32_t regcap;
+	u32 regcap;
 
 	regcap = ah->ah_caps.halRegCap;
 
@@ -95,9 +96,9 @@ static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
 }
 
 static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
-				      u_int16_t cc)
+				      u16 cc)
 {
-	u_int16_t rd;
+	u16 rd;
 	int i;
 
 	if (cc == CTRY_DEFAULT)
@@ -130,12 +131,12 @@ static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
 	return false;
 }
 
-static u_int
+static u32
 ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
 			   struct country_code_to_enum_rd *country,
 			   struct regDomain *rd5GHz)
 {
-	u_int modesAvail;
+	u32 modesAvail;
 
 	modesAvail = ah->ah_caps.halWirelessModes;
 
@@ -174,7 +175,7 @@ ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
 
 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
 {
-	u_int16_t rd;
+	u16 rd;
 
 	rd = ath9k_regd_get_eepromRD(ah);
 
@@ -192,7 +193,7 @@ bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
 }
 
 static struct country_code_to_enum_rd*
-ath9k_regd_find_country(u_int16_t countryCode)
+ath9k_regd_find_country(u16 countryCode)
 {
 	int i;
 
@@ -203,15 +204,15 @@ ath9k_regd_find_country(u_int16_t countryCode)
 	return NULL;
 }
 
-static u_int16_t ath9k_regd_get_default_country(struct ath_hal *ah)
+static u16 ath9k_regd_get_default_country(struct ath_hal *ah)
 {
-	u_int16_t rd;
+	u16 rd;
 	int i;
 
 	rd = ath9k_regd_get_eepromRD(ah);
 	if (rd & COUNTRY_ERD_FLAG) {
 		struct country_code_to_enum_rd *country = NULL;
-		u_int16_t cc = rd & ~COUNTRY_ERD_FLAG;
+		u16 cc = rd & ~COUNTRY_ERD_FLAG;
 
 		country = ath9k_regd_find_country(cc);
 		if (country != NULL)
@@ -260,16 +261,16 @@ static bool ath9k_regd_is_valid_reg_domainPair(int regDmnPair)
 
 static bool
 ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
-			       u_int16_t channelFlag, struct regDomain *rd)
+			       u16 channelFlag, struct regDomain *rd)
 {
 	int i, found;
-	u_int64_t flags = NO_REQ;
+	u64 flags = NO_REQ;
 	struct reg_dmn_pair_mapping *regPair = NULL;
 	int regOrg;
 
 	regOrg = regDmn;
 	if (regDmn == CTRY_DEFAULT) {
-		u_int16_t rdnum;
+		u16 rdnum;
 		rdnum = ath9k_regd_get_eepromRD(ah);
 
 		if (!(rdnum & COUNTRY_ERD_FLAG)) {
@@ -323,14 +324,14 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 	}
 }
 
-static bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
+static bool ath9k_regd_is_bit_set(int bit, u64 *bitmask)
 {
 	int byteOffset, bitnum;
-	u_int64_t val;
+	u64 val;
 
 	byteOffset = bit / 64;
 	bitnum = bit - byteOffset * 64;
-	val = ((u_int64_t) 1) << bitnum;
+	val = ((u64) 1) << bitnum;
 	if (bitmask[byteOffset] & val)
 		return true;
 	else
@@ -338,8 +339,8 @@ static bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
 }
 
 static void
-ath9k_regd_add_reg_classid(u_int8_t *regclassids, u_int maxregids,
-			   u_int *nregids, u_int8_t regclassid)
+ath9k_regd_add_reg_classid(u8 *regclassids, u32 maxregids,
+			   u32 *nregids, u8 regclassid)
 {
 	int i;
 
@@ -372,7 +373,7 @@ ath9k_regd_get_eeprom_reg_ext_bits(struct ath_hal *ah,
 
 #ifdef ATH_NF_PER_CHAN
 
-static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
+static void ath9k_regd_init_rf_buffer(struct ath9k_channel *ichans,
 				      int nchans)
 {
 	int i, j, next;
@@ -384,7 +385,7 @@ static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
 			    AR_PHY_CCA_MAX_GOOD_VALUE;
 			ichans[next].nfCalHist[i].invalidNFcount =
 			    AR_PHY_CCA_FILTERWINDOW_LENGTH;
-			for (j = 0; j < HAL_NF_CAL_HIST_MAX; j++) {
+			for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
 				ichans[next].nfCalHist[i].nfCalBuffer[j] =
 				    AR_PHY_CCA_MAX_GOOD_VALUE;
 			}
@@ -393,22 +394,40 @@ static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
 }
 #endif
 
+static int ath9k_regd_is_chan_present(struct ath_hal *ah,
+				      u16 c)
+{
+	int i;
+
+	for (i = 0; i < 150; i++) {
+		if (!ah->ah_channels[i].channel)
+			return -1;
+		else if (ah->ah_channels[i].channel == c)
+			return i;
+	}
+
+	return -1;
+}
+
 static bool
 ath9k_regd_add_channel(struct ath_hal *ah,
-		       u_int16_t c,
-		       u_int16_t c_lo,
-		       u_int16_t c_hi,
-		       u_int16_t maxChan,
-		       u_int8_t ctl,
+		       u16 c,
+		       u16 c_lo,
+		       u16 c_hi,
+		       u16 maxChan,
+		       u8 ctl,
 		       int pos,
 		       struct regDomain rd5GHz,
 		       struct RegDmnFreqBand *fband,
 		       struct regDomain *rd,
 		       const struct cmode *cm,
-		       struct hal_channel_internal *ichans,
+		       struct ath9k_channel *ichans,
 		       bool enableExtendedChannels)
 {
-	struct hal_channel_internal icv;
+	struct ath9k_channel *chan;
+	int ret;
+	u32 channelFlags = 0;
+	u8 privFlags = 0;
 
 	if (!(c_lo <= c && c <= c_hi)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
@@ -445,7 +464,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
 		return false;
 	}
 
-	if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == HAL_M_HOSTAP)) {
+	if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == ATH9K_M_HOSTAP)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 			"Skipping HOSTAP channel\n");
 		return false;
@@ -478,54 +497,50 @@ ath9k_regd_add_channel(struct ath_hal *ah,
 		return false;
 	}
 
-	memset(&icv, 0, sizeof(icv));
-	icv.channel = c;
-	icv.channelFlags = cm->flags;
+	/* Calculate channel flags */
+
+	channelFlags = cm->flags;
 
 	switch (fband->channelBW) {
 	case CHANNEL_HALF_BW:
-		icv.channelFlags |= CHANNEL_HALF;
+		channelFlags |= CHANNEL_HALF;
 		break;
 	case CHANNEL_QUARTER_BW:
-		icv.channelFlags |= CHANNEL_QUARTER;
+		channelFlags |= CHANNEL_QUARTER;
 		break;
 	}
 
-	icv.maxRegTxPower = fband->powerDfs;
-	icv.antennaMax = fband->antennaMax;
-	icv.regDmnFlags = rd->flags;
-	icv.conformanceTestLimit = ctl;
 	if (fband->usePassScan & rd->pscan)
-		icv.channelFlags |= CHANNEL_PASSIVE;
+		channelFlags |= CHANNEL_PASSIVE;
 	else
-		icv.channelFlags &= ~CHANNEL_PASSIVE;
+		channelFlags &= ~CHANNEL_PASSIVE;
 	if (fband->useDfs & rd->dfsMask)
-		icv.privFlags = CHANNEL_DFS;
+		privFlags = CHANNEL_DFS;
 	else
-		icv.privFlags = 0;
+		privFlags = 0;
 	if (rd->flags & LIMIT_FRAME_4MS)
-		icv.privFlags |= CHANNEL_4MS_LIMIT;
-	if (icv.privFlags & CHANNEL_DFS)
-		icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
-	if (icv.regDmnFlags & ADHOC_PER_11D)
-		icv.privFlags |= CHANNEL_PER_11D_ADHOC;
-
-	if (icv.channelFlags & CHANNEL_PASSIVE) {
-		if ((icv.channel < 2412) || (icv.channel > 2462)) {
+		privFlags |= CHANNEL_4MS_LIMIT;
+	if (privFlags & CHANNEL_DFS)
+		privFlags |= CHANNEL_DISALLOW_ADHOC;
+	if (rd->flags & ADHOC_PER_11D)
+		privFlags |= CHANNEL_PER_11D_ADHOC;
+
+	if (channelFlags & CHANNEL_PASSIVE) {
+		if ((c < 2412) || (c > 2462)) {
 			if (rd5GHz.regDmnEnum == MKK1 ||
 			    rd5GHz.regDmnEnum == MKK2) {
-				u_int32_t regcap = ah->ah_caps.halRegCap;
+				u32 regcap = ah->ah_caps.halRegCap;
 				if (!(regcap &
 				      (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
 				       AR_EEPROM_EEREGCAP_EN_KK_U2 |
 				       AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) &&
-				    isUNII1OddChan(icv.channel)) {
-					icv.channelFlags &= ~CHANNEL_PASSIVE;
+				    isUNII1OddChan(c)) {
+					channelFlags &= ~CHANNEL_PASSIVE;
 				} else {
-					icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+					privFlags |= CHANNEL_DISALLOW_ADHOC;
 				}
 			} else {
-				icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+				privFlags |= CHANNEL_DISALLOW_ADHOC;
 			}
 		}
 	}
@@ -534,14 +549,39 @@ ath9k_regd_add_channel(struct ath_hal *ah,
 			ATH9K_MODE_SEL_11NA_HT20 |
 			ATH9K_MODE_SEL_11NA_HT40PLUS |
 			ATH9K_MODE_SEL_11NA_HT40MINUS)) {
-		if (icv.regDmnFlags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
-			icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+		if (rd->flags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
+			privFlags |= CHANNEL_DISALLOW_ADHOC;
+	}
+
+	/* Fill in channel details */
+
+	ret = ath9k_regd_is_chan_present(ah, c);
+	if (ret == -1) {
+		chan = &ah->ah_channels[pos];
+		chan->channel = c;
+		chan->maxRegTxPower = fband->powerDfs;
+		chan->antennaMax = fband->antennaMax;
+		chan->regDmnFlags = rd->flags;
+		chan->maxTxPower = AR5416_MAX_RATE_POWER;
+		chan->minTxPower = AR5416_MAX_RATE_POWER;
+		chan->channelFlags = channelFlags;
+		chan->privFlags = privFlags;
+	} else {
+		chan = &ah->ah_channels[ret];
+		chan->channelFlags |= channelFlags;
+		chan->privFlags |= privFlags;
 	}
 
-	memcpy(&ichans[pos], &icv,
-	       sizeof(struct hal_channel_internal));
+	/* Set CTLs */
 
-	return true;
+	if ((cm->flags & CHANNEL_ALL) == CHANNEL_A)
+		chan->conformanceTestLimit[0] = ctl;
+	else if ((cm->flags & CHANNEL_ALL) == CHANNEL_B)
+		chan->conformanceTestLimit[1] = ctl;
+	else if ((cm->flags & CHANNEL_ALL) == CHANNEL_G)
+		chan->conformanceTestLimit[2] = ctl;
+
+	return (ret == -1) ? true : false;
 }
 
 static bool ath9k_regd_japan_check(struct ath_hal *ah,
@@ -550,7 +590,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
 {
 	bool skipband = false;
 	int i;
-	u_int32_t regcap;
+	u32 regcap;
 
 	for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
 		if (j_bandcheck[i].freqbandbit == b) {
@@ -575,22 +615,22 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
 
 bool
 ath9k_regd_init_channels(struct ath_hal *ah,
-			 struct hal_channel *chans, u_int maxchans,
-			 u_int *nchans, u_int8_t *regclassids,
-			 u_int maxregids, u_int *nregids, u_int16_t cc,
-			 u_int32_t modeSelect, bool enableOutdoor,
+			 u32 maxchans,
+			 u32 *nchans, u8 *regclassids,
+			 u32 maxregids, u32 *nregids, u16 cc,
+			 u32 modeSelect, bool enableOutdoor,
 			 bool enableExtendedChannels)
 {
-	u_int modesAvail;
-	u_int16_t maxChan = 7000;
+	u32 modesAvail;
+	u16 maxChan = 7000;
 	struct country_code_to_enum_rd *country = NULL;
 	struct regDomain rd5GHz, rd2GHz;
 	const struct cmode *cm;
-	struct hal_channel_internal *ichans = &ah->ah_channels[0];
+	struct ath9k_channel *ichans = &ah->ah_channels[0];
 	int next = 0, b;
-	u_int8_t ctl;
+	u8 ctl;
 	int regdmn;
-	u_int16_t chanSep;
+	u16 chanSep;
 
 	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u mode 0x%x%s%s\n",
 		 __func__, cc, modeSelect,
@@ -699,8 +739,8 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 		maxchans = ARRAY_SIZE(ah->ah_channels);
 
 	for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) {
-		u_int16_t c, c_hi, c_lo;
-		u_int64_t *channelBM = NULL;
+		u16 c, c_hi, c_lo;
+		u64 *channelBM = NULL;
 		struct regDomain *rd = NULL;
 		struct RegDmnFreqBand *fband = NULL, *freqs;
 		int8_t low_adj = 0, hi_adj = 0;
@@ -843,26 +883,17 @@ done:
 		ath9k_regd_init_rf_buffer(ichans, next);
 #endif
 		ath9k_regd_sort(ichans, next,
-				sizeof(struct hal_channel_internal),
+				sizeof(struct ath9k_channel),
 				ath9k_regd_chansort);
+
 		ah->ah_nchan = next;
 
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Channel list:\n");
 		for (i = 0; i < next; i++) {
 			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 				"chan: %d flags: 0x%x\n",
-				ichans[i].channel,
-				ichans[i].channelFlags);
-			chans[i].channel = ichans[i].channel;
-			chans[i].channelFlags = ichans[i].channelFlags;
-			chans[i].privFlags = ichans[i].privFlags;
-			chans[i].maxRegTxPower = ichans[i].maxRegTxPower;
-		}
-
-		ath9k_hw_get_chip_power_limits(ah, chans, next);
-		for (i = 0; i < next; i++) {
-			ichans[i].maxTxPower = chans[i].maxTxPower;
-			ichans[i].minTxPower = chans[i].minTxPower;
+				ah->ah_channels[i].channel,
+				ah->ah_channels[i].channelFlags);
 		}
 	}
 	*nchans = next;
@@ -883,11 +914,11 @@ done:
 	return next != 0;
 }
 
-struct hal_channel_internal*
+struct ath9k_channel*
 ath9k_regd_check_channel(struct ath_hal *ah,
-			 const struct hal_channel *c)
+			 const struct ath9k_channel *c)
 {
-	struct hal_channel_internal *base, *cc;
+	struct ath9k_channel *base, *cc;
 
 	int flags = c->channelFlags & CHAN_FLAGS;
 	int n, lim;
@@ -936,11 +967,11 @@ ath9k_regd_check_channel(struct ath_hal *ah,
 	return NULL;
 }
 
-u_int
+u32
 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
-			       struct hal_channel *chan)
+			       struct ath9k_channel *chan)
 {
-	struct hal_channel_internal *ichan = NULL;
+	struct ath9k_channel *ichan = NULL;
 
 	ichan = ath9k_regd_check_channel(ah, chan);
 	if (!ichan)
@@ -949,10 +980,10 @@ ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
 	return ichan->antennaMax;
 }
 
-u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan)
+u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan)
 {
-	u_int ctl = NO_CTL;
-	struct hal_channel_internal *ichan;
+	u32 ctl = NO_CTL;
+	struct ath9k_channel *ichan;
 
 	if (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
 		if (IS_CHAN_B(chan))
@@ -964,9 +995,15 @@ u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan)
 	} else {
 		ichan = ath9k_regd_check_channel(ah, chan);
 		if (ichan != NULL) {
-			ctl = ichan->conformanceTestLimit;
-
-			if (IS_CHAN_PUREG(chan) && (ctl & 0xf) == CTL_11B)
+			/* FIXME */
+			if (IS_CHAN_A(ichan))
+				ctl = ichan->conformanceTestLimit[0];
+			else if (IS_CHAN_B(ichan))
+				ctl = ichan->conformanceTestLimit[1];
+			else if (IS_CHAN_G(ichan))
+				ctl = ichan->conformanceTestLimit[2];
+
+			if (IS_CHAN_G(chan) && (ctl & 0xf) == CTL_11B)
 				ctl = (ctl & ~0xf) | CTL_11G;
 		}
 	}
@@ -974,9 +1011,9 @@ u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan)
 }
 
 void ath9k_regd_get_current_country(struct ath_hal *ah,
-				    struct hal_country_entry *ctry)
+				    struct ath9k_country_entry *ctry)
 {
-	u_int16_t rd = ath9k_regd_get_eepromRD(ah);
+	u16 rd = ath9k_regd_get_eepromRD(ah);
 
 	ctry->isMultidomain = false;
 	if (rd == CTRY_DEFAULT)
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/regd.h b/package/ath9k/src/drivers/net/wireless/ath9k/regd.h
index 125941cb6..ae77496bf 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/regd.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/regd.h
@@ -20,57 +20,57 @@
 #include "ath9k.h"
 
 #define BMLEN 2
-#define BMZERO {(u_int64_t) 0, (u_int64_t) 0}
+#define BMZERO {(u64) 0, (u64) 0}
 
 #define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
 	{((((_fa >= 0) && (_fa < 64)) ? \
-		(((u_int64_t) 1) << _fa) : (u_int64_t) 0) | \
+		(((u64) 1) << _fa) : (u64) 0) | \
 	(((_fb >= 0) && (_fb < 64)) ? \
-		(((u_int64_t) 1) << _fb) : (u_int64_t) 0) | \
+		(((u64) 1) << _fb) : (u64) 0) | \
 	(((_fc >= 0) && (_fc < 64)) ? \
-		(((u_int64_t) 1) << _fc) : (u_int64_t) 0) | \
+		(((u64) 1) << _fc) : (u64) 0) | \
 	(((_fd >= 0) && (_fd < 64)) ? \
-		(((u_int64_t) 1) << _fd) : (u_int64_t) 0) | \
+		(((u64) 1) << _fd) : (u64) 0) | \
 	(((_fe >= 0) && (_fe < 64)) ? \
-		(((u_int64_t) 1) << _fe) : (u_int64_t) 0) | \
+		(((u64) 1) << _fe) : (u64) 0) | \
 	(((_ff >= 0) && (_ff < 64)) ? \
-		(((u_int64_t) 1) << _ff) : (u_int64_t) 0) | \
+		(((u64) 1) << _ff) : (u64) 0) | \
 	(((_fg >= 0) && (_fg < 64)) ? \
-		(((u_int64_t) 1) << _fg) : (u_int64_t) 0) | \
+		(((u64) 1) << _fg) : (u64) 0) | \
 	(((_fh >= 0) && (_fh < 64)) ? \
-		(((u_int64_t) 1) << _fh) : (u_int64_t) 0) | \
+		(((u64) 1) << _fh) : (u64) 0) | \
 	(((_fi >= 0) && (_fi < 64)) ? \
-		(((u_int64_t) 1) << _fi) : (u_int64_t) 0) | \
+		(((u64) 1) << _fi) : (u64) 0) | \
 	(((_fj >= 0) && (_fj < 64)) ? \
-		(((u_int64_t) 1) << _fj) : (u_int64_t) 0) | \
+		(((u64) 1) << _fj) : (u64) 0) | \
 	(((_fk >= 0) && (_fk < 64)) ? \
-		(((u_int64_t) 1) << _fk) : (u_int64_t) 0) | \
+		(((u64) 1) << _fk) : (u64) 0) | \
 	(((_fl >= 0) && (_fl < 64)) ? \
-		(((u_int64_t) 1) << _fl) : (u_int64_t) 0) | \
+		(((u64) 1) << _fl) : (u64) 0) | \
 			((((_fa > 63) && (_fa < 128)) ? \
-			(((u_int64_t) 1) << (_fa - 64)) : (u_int64_t) 0) | \
+			(((u64) 1) << (_fa - 64)) : (u64) 0) | \
 	(((_fb > 63) && (_fb < 128)) ? \
-		(((u_int64_t) 1) << (_fb - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fb - 64)) : (u64) 0) | \
 	(((_fc > 63) && (_fc < 128)) ? \
-		(((u_int64_t) 1) << (_fc - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fc - 64)) : (u64) 0) | \
 	(((_fd > 63) && (_fd < 128)) ? \
-		(((u_int64_t) 1) << (_fd - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fd - 64)) : (u64) 0) | \
 	(((_fe > 63) && (_fe < 128)) ? \
-		(((u_int64_t) 1) << (_fe - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fe - 64)) : (u64) 0) | \
 	(((_ff > 63) && (_ff < 128)) ? \
-		(((u_int64_t) 1) << (_ff - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_ff - 64)) : (u64) 0) | \
 	(((_fg > 63) && (_fg < 128)) ? \
-		(((u_int64_t) 1) << (_fg - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fg - 64)) : (u64) 0) | \
 	(((_fh > 63) && (_fh < 128)) ? \
-		(((u_int64_t) 1) << (_fh - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fh - 64)) : (u64) 0) | \
 	(((_fi > 63) && (_fi < 128)) ? \
-		(((u_int64_t) 1) << (_fi - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fi - 64)) : (u64) 0) | \
 	(((_fj > 63) && (_fj < 128)) ? \
-		(((u_int64_t) 1) << (_fj - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fj - 64)) : (u64) 0) | \
 	(((_fk > 63) && (_fk < 128)) ? \
-		(((u_int64_t) 1) << (_fk - 64)) : (u_int64_t) 0) | \
+		(((u64) 1) << (_fk - 64)) : (u64) 0) | \
 	(((_fl > 63) && (_fl < 128)) ? \
-		(((u_int64_t) 1) << (_fl - 64)) : (u_int64_t) 0)))}
+		(((u64) 1) << (_fl - 64)) : (u64) 0)))}
 
 #define DEF_REGDMN      FCC1_FCCA
 #define DEF_DMN_5       FCC1
@@ -126,10 +126,10 @@
 #define CHAN_FLAGS      (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
 
 #define swap(_a, _b, _size) {                   \
-	u_int8_t *s = _b;                       \
+	u8 *s = _b;                       \
 	int i = _size;                          \
 	do {                                    \
-		u_int8_t tmp = *_a;             \
+		u8 tmp = *_a;             \
 		*_a++ = *s;                     \
 		*s++ = tmp;                     \
 	} while (--i);                          \
@@ -150,23 +150,23 @@
 typedef int ath_hal_cmp_t(const void *, const void *);
 
 struct reg_dmn_pair_mapping {
-	u_int16_t regDmnEnum;
-	u_int16_t regDmn5GHz;
-	u_int16_t regDmn2GHz;
-	u_int32_t flags5GHz;
-	u_int32_t flags2GHz;
-	u_int64_t pscanMask;
-	u_int16_t singleCC;
+	u16 regDmnEnum;
+	u16 regDmn5GHz;
+	u16 regDmn2GHz;
+	u32 flags5GHz;
+	u32 flags2GHz;
+	u64 pscanMask;
+	u16 singleCC;
 };
 
 struct ccmap {
 	char isoName[3];
-	u_int16_t countryCode;
+	u16 countryCode;
 };
 
 struct country_code_to_enum_rd {
-	u_int16_t countryCode;
-	u_int16_t regDmnEnum;
+	u16 countryCode;
+	u16 regDmnEnum;
 	const char *isoName;
 	const char *name;
 	bool allow11g;
@@ -176,52 +176,52 @@ struct country_code_to_enum_rd {
 	bool allow11ng40;
 	bool allow11na20;
 	bool allow11na40;
-	u_int16_t outdoorChanStart;
+	u16 outdoorChanStart;
 };
 
 struct RegDmnFreqBand {
-	u_int16_t lowChannel;
-	u_int16_t highChannel;
-	u_int8_t powerDfs;
-	u_int8_t antennaMax;
-	u_int8_t channelBW;
-	u_int8_t channelSep;
-	u_int64_t useDfs;
-	u_int64_t usePassScan;
-	u_int8_t regClassId;
+	u16 lowChannel;
+	u16 highChannel;
+	u8 powerDfs;
+	u8 antennaMax;
+	u8 channelBW;
+	u8 channelSep;
+	u64 useDfs;
+	u64 usePassScan;
+	u8 regClassId;
 };
 
 struct regDomain {
-	u_int16_t regDmnEnum;
-	u_int8_t conformanceTestLimit;
-	u_int64_t dfsMask;
-	u_int64_t pscan;
-	u_int32_t flags;
-	u_int64_t chan11a[BMLEN];
-	u_int64_t chan11a_turbo[BMLEN];
-	u_int64_t chan11a_dyn_turbo[BMLEN];
-	u_int64_t chan11b[BMLEN];
-	u_int64_t chan11g[BMLEN];
-	u_int64_t chan11g_turbo[BMLEN];
+	u16 regDmnEnum;
+	u8 conformanceTestLimit;
+	u64 dfsMask;
+	u64 pscan;
+	u32 flags;
+	u64 chan11a[BMLEN];
+	u64 chan11a_turbo[BMLEN];
+	u64 chan11a_dyn_turbo[BMLEN];
+	u64 chan11b[BMLEN];
+	u64 chan11g[BMLEN];
+	u64 chan11g_turbo[BMLEN];
 };
 
 struct cmode {
-	u_int32_t mode;
-	u_int32_t flags;
+	u32 mode;
+	u32 flags;
 };
 
 #define YES true
 #define NO  false
 
 struct japan_bandcheck {
-	u_int16_t freqbandbit;
-	u_int32_t eepromflagtocheck;
+	u16 freqbandbit;
+	u32 eepromflagtocheck;
 };
 
 struct common_mode_power {
-	u_int16_t lchan;
-	u_int16_t hchan;
-	u_int8_t pwrlvl;
+	u16 lchan;
+	u16 hchan;
+	u8 pwrlvl;
 };
 
 enum CountryCode {
@@ -407,6 +407,6 @@ enum CountryCode {
 };
 
 void ath9k_regd_get_current_country(struct ath_hal *ah,
-				    struct hal_country_entry *ctry);
+				    struct ath9k_country_entry *ctry);
 
 #endif
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c b/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
index 2e3ae6594..f0297ee5d 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
@@ -37,7 +37,7 @@
 
 #define OFDM_SIFS_TIME    	    16
 
-static u_int32_t bits_per_symbol[][2] = {
+static u32 bits_per_symbol[][2] = {
 	/* 20MHz 40MHz */
 	{    26,   54 },     /*  0: BPSK */
 	{    52,  108 },     /*  1: QPSK 1/2 */
@@ -180,7 +180,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc,
 
 /* Get transmit rate index using rate in Kbps */
 
-static int ath_tx_findindex(const struct hal_rate_table *rt, int rate)
+static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
 {
 	int i;
 	int ndx = 0;
@@ -198,7 +198,7 @@ static int ath_tx_findindex(const struct hal_rate_table *rt, int rate)
 /* Check if it's okay to send out aggregates */
 
 static int ath_aggr_query(struct ath_softc *sc,
-	struct ath_node *an, u_int8_t tidno)
+	struct ath_node *an, u8 tidno)
 {
 	struct ath_atx_tid *tid;
 	tid = ATH_AN_2_TID(an, tidno);
@@ -209,9 +209,9 @@ static int ath_aggr_query(struct ath_softc *sc,
 		return 0;
 }
 
-static enum hal_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
+static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
 {
-	enum hal_pkt_type htype;
+	enum ath9k_pkt_type htype;
 	__le16 fc;
 
 	fc = hdr->frame_control;
@@ -219,15 +219,15 @@ static enum hal_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
 	/* Calculate Atheros packet type from IEEE80211 packet header */
 
 	if (ieee80211_is_beacon(fc))
-		htype = HAL_PKT_TYPE_BEACON;
+		htype = ATH9K_PKT_TYPE_BEACON;
 	else if (ieee80211_is_probe_resp(fc))
-		htype = HAL_PKT_TYPE_PROBE_RESP;
+		htype = ATH9K_PKT_TYPE_PROBE_RESP;
 	else if (ieee80211_is_atim(fc))
-		htype = HAL_PKT_TYPE_ATIM;
+		htype = ATH9K_PKT_TYPE_ATIM;
 	else if (ieee80211_is_pspoll(fc))
-		htype = HAL_PKT_TYPE_PSPOLL;
+		htype = ATH9K_PKT_TYPE_PSPOLL;
 	else
-		htype = HAL_PKT_TYPE_NORMAL;
+		htype = ATH9K_PKT_TYPE_NORMAL;
 
 	return htype;
 }
@@ -248,7 +248,8 @@ static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
 		txctl->min_rate = tx_info_priv->min_rate;
 	} else if (ieee80211_is_data(fc)) {
 		if (ieee80211_is_nullfunc(fc) ||
-		    (tx_info->flags & IEEE80211_TX_CTL_EAPOL_FRAME)) {
+			/* Port Access Entity (IEEE 802.1X) */
+			(skb->protocol == cpu_to_be16(0x888E))) {
 			txctl->use_minrate = 1;
 			txctl->min_rate = tx_info_priv->min_rate;
 		}
@@ -268,11 +269,11 @@ static int ath_tx_prepare(struct ath_softc *sc,
 	struct ieee80211_hdr *hdr;
 	struct ath_rc_series *rcs;
 	struct ath_txq *txq = NULL;
-	const struct hal_rate_table *rt;
+	const struct ath9k_rate_table *rt;
 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
 	struct ath_tx_info_priv *tx_info_priv;
 	int hdrlen;
-	u_int8_t rix, antenna;
+	u8 rix, antenna;
 	__le16 fc;
 	u8 *qc;
 
@@ -307,19 +308,19 @@ static int ath_tx_prepare(struct ath_softc *sc,
 
 	/* Fill Key related fields */
 
-	txctl->keytype = HAL_KEY_TYPE_CLEAR;
-	txctl->keyix = HAL_TXKEYIX_INVALID;
+	txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
+	txctl->keyix = ATH9K_TXKEYIX_INVALID;
 
-	if (!(tx_info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
+	if (tx_info->control.hw_key) {
 		txctl->keyix = tx_info->control.hw_key->hw_key_idx;
 		txctl->frmlen += tx_info->control.icv_len;
 
-		if (sc->sc_keytype == HAL_CIPHER_WEP)
-			txctl->keytype = HAL_KEY_TYPE_WEP;
-		else if (sc->sc_keytype == HAL_CIPHER_TKIP)
-			txctl->keytype = HAL_KEY_TYPE_TKIP;
-		else if (sc->sc_keytype == HAL_CIPHER_AES_CCM)
-			txctl->keytype = HAL_KEY_TYPE_AES;
+		if (sc->sc_keytype == ATH9K_CIPHER_WEP)
+			txctl->keytype = ATH9K_KEY_TYPE_WEP;
+		else if (sc->sc_keytype == ATH9K_CIPHER_TKIP)
+			txctl->keytype = ATH9K_KEY_TYPE_TKIP;
+		else if (sc->sc_keytype == ATH9K_CIPHER_AES_CCM)
+			txctl->keytype = ATH9K_KEY_TYPE_AES;
 	}
 
 	/* Fill packet type */
@@ -353,12 +354,12 @@ static int ath_tx_prepare(struct ath_softc *sc,
 
 	/* Fill flags */
 
-	txctl->flags = HAL_TXDESC_CLRDMASK;    /* needed for crypto errors */
+	txctl->flags = ATH9K_TXDESC_CLRDMASK;    /* needed for crypto errors */
 
 	if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
-		tx_info->flags |= HAL_TXDESC_NOACK;
+		tx_info->flags |= ATH9K_TXDESC_NOACK;
 	if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
-		tx_info->flags |= HAL_TXDESC_RTSENA;
+		tx_info->flags |= ATH9K_TXDESC_RTSENA;
 
 	/*
 	 * Setup for rate calculations.
@@ -373,7 +374,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 			    (tx_info->flags & IEEE80211_TX_CTL_AMPDU));
 
 		if (is_multicast_ether_addr(hdr->addr1)) {
-			rcs[0].rix = (u_int8_t)
+			rcs[0].rix = (u8)
 				ath_tx_findindex(rt, txctl->mcast_rate);
 
 			/*
@@ -390,7 +391,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 		 * not overridden, since it has been
 		 * incremented by the fragmentation routine.
 		 */
-		if (likely(!(txctl->flags & HAL_TXDESC_FRAG_IS_ON)) &&
+		if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
 			txctl->ht && sc->sc_txaggr) {
 			struct ath_atx_tid *tid;
 
@@ -416,8 +417,8 @@ static int ath_tx_prepare(struct ath_softc *sc,
 	 * Calculate duration.  This logically belongs in the 802.11
 	 * layer but it lacks sufficient information to calculate it.
 	 */
-	if ((txctl->flags & HAL_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
-		u_int16_t dur;
+	if ((txctl->flags & ATH9K_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
+		u16 dur;
 		/*
 		 * XXX not right with fragmentation.
 		 */
@@ -475,7 +476,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 	 */
 	spin_lock_bh(&txq->axq_lock);
 	if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
-		txctl->flags |= HAL_TXDESC_INTREQ;
+		txctl->flags |= ATH9K_TXDESC_INTREQ;
 		txq->axq_intrcnt = 0;
 	}
 	spin_unlock_bh(&txq->axq_lock);
@@ -619,8 +620,8 @@ static int ath_tx_num_badfrms(struct ath_softc *sc,
 	int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
 	struct ath_buf *bf_last = bf->bf_lastbf;
 	struct ath_desc *ds = bf_last->bf_desc;
-	u_int16_t seq_st = 0;
-	u_int32_t ba[WME_BA_BMP_SIZE >> 5];
+	u16 seq_st = 0;
+	u32 ba[WME_BA_BMP_SIZE >> 5];
 	int ba_index;
 	int nbad = 0;
 	int isaggr = 0;
@@ -685,16 +686,16 @@ static void ath_tx_update_baw(struct ath_softc *sc,
  * half_gi - to use 4us v/s 3.6 us for symbol time
  */
 
-static u_int32_t ath_pkt_duration(struct ath_softc *sc,
-				  u_int8_t rix,
+static u32 ath_pkt_duration(struct ath_softc *sc,
+				  u8 rix,
 				  struct ath_buf *bf,
 				  int width,
 				  int half_gi,
 				  bool shortPreamble)
 {
-	const struct hal_rate_table *rt = sc->sc_currates;
-	u_int32_t nbits, nsymbits, duration, nsymbols;
-	u_int8_t rc;
+	const struct ath9k_rate_table *rt = sc->sc_currates;
+	u32 nbits, nsymbits, duration, nsymbols;
+	u8 rc;
 	int streams, pktlen;
 
 	pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_frmlen;
@@ -734,14 +735,14 @@ static u_int32_t ath_pkt_duration(struct ath_softc *sc,
 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	const struct hal_rate_table *rt;
+	const struct ath9k_rate_table *rt;
 	struct ath_desc *ds = bf->bf_desc;
 	struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
-	struct hal_11n_rate_series series[4];
+	struct ath9k_11n_rate_series series[4];
 	int i, flags, rtsctsena = 0, dynamic_mimops = 0;
-	u_int ctsduration = 0;
-	u_int8_t rix = 0, cix, ctsrate = 0;
-	u_int32_t aggr_limit_with_rts = sc->sc_rtsaggrlimit;
+	u32 ctsduration = 0;
+	u8 rix = 0, cix, ctsrate = 0;
+	u32 aggr_limit_with_rts = sc->sc_rtsaggrlimit;
 	struct ath_node *an = (struct ath_node *) bf->bf_node;
 
 	/*
@@ -754,7 +755,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 			break;
 		}
 	}
-	flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
+	flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
 	cix = rt->info[rix].controlRate;
 
 	/*
@@ -765,11 +766,11 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	if (sc->sc_protmode != PROT_M_NONE &&
 	    (rt->info[rix].phy == PHY_OFDM ||
 	     rt->info[rix].phy == PHY_HT) &&
-	    (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
+	    (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
 		if (sc->sc_protmode == PROT_M_RTSCTS)
-			flags = HAL_TXDESC_RTSENA;
+			flags = ATH9K_TXDESC_RTSENA;
 		else if (sc->sc_protmode == PROT_M_CTSONLY)
-			flags = HAL_TXDESC_CTSENA;
+			flags = ATH9K_TXDESC_CTSENA;
 
 		cix = rt->info[sc->sc_protrix].controlRate;
 		rtsctsena = 1;
@@ -786,14 +787,14 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 		 * 802.11g protection not needed, use our default behavior
 		 */
 		if (!rtsctsena)
-			flags = HAL_TXDESC_RTSENA;
+			flags = ATH9K_TXDESC_RTSENA;
 		/*
 		 * For dynamic MIMO PS, RTS needs to precede the first aggregate
 		 * and the second aggregate should have any protection at all.
 		 */
 		if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
 			if (!bf->bf_aggrburst) {
-				flags = HAL_TXDESC_RTSENA;
+				flags = ATH9K_TXDESC_RTSENA;
 				dynamic_mimops = 1;
 			} else {
 				flags = 0;
@@ -806,7 +807,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 */
 	if (sc->sc_config.ath_aggr_prot &&
 	    (!bf->bf_isaggr || (bf->bf_isaggr && bf->bf_al < 8192))) {
-		flags = HAL_TXDESC_RTSENA;
+		flags = ATH9K_TXDESC_RTSENA;
 		cix = rt->info[sc->sc_protrix].controlRate;
 		rtsctsena = 1;
 	}
@@ -820,7 +821,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 		 * while we are bursting the second aggregate the
 		 * RTS is cleared.
 		 */
-		flags &= ~(HAL_TXDESC_RTSENA);
+		flags &= ~(ATH9K_TXDESC_RTSENA);
 	}
 
 	/*
@@ -836,7 +837,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	/*
 	 * Setup HAL rate series
 	 */
-	memzero(series, sizeof(struct hal_11n_rate_series) * 4);
+	memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
 
 	for (i = 0; i < 4; i++) {
 		if (!bf->bf_rcs[i].tries)
@@ -851,11 +852,11 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 
 		series[i].RateFlags = (
 			(bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
-				HAL_RATESERIES_RTS_CTS : 0) |
+				ATH9K_RATESERIES_RTS_CTS : 0) |
 			((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
-				HAL_RATESERIES_2040 : 0) |
+				ATH9K_RATESERIES_2040 : 0) |
 			((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
-				HAL_RATESERIES_HALFGI : 0);
+				ATH9K_RATESERIES_HALFGI : 0);
 
 		series[i].PktDuration = ath_pkt_duration(
 			sc, rix, bf,
@@ -882,14 +883,14 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 		}
 
 		if (rtsctsena)
-			series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
+			series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
 
 		/*
 		 * Set RTS for all rates if node is in dynamic powersave
 		 * mode and we are using dual stream rates.
 		 */
 		if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
-			series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
+			series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
 	}
 
 	/*
@@ -906,7 +907,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 		 * NB: CTS is assumed the same size as an ACK so we can
 		 *     use the precalculated ACK durations.
 		 */
-		if (flags & HAL_TXDESC_RTSENA) {    /* SIFS + CTS */
+		if (flags & ATH9K_TXDESC_RTSENA) {    /* SIFS + CTS */
 			ctsduration += bf->bf_shpreamble ?
 				rt->info[cix].spAckDuration :
 				rt->info[cix].lpAckDuration;
@@ -914,7 +915,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 
 		ctsduration += series[0].PktDuration;
 
-		if ((bf->bf_flags & HAL_TXDESC_NOACK) == 0) {  /* SIFS + ACK */
+		if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
 			ctsduration += bf->bf_shpreamble ?
 				rt->info[rix].spAckDuration :
 				rt->info[rix].lpAckDuration;
@@ -924,7 +925,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 		 * Disable multi-rate retry when using RTS/CTS by clearing
 		 * series 1, 2 and 3.
 		 */
-		memzero(&series[1], sizeof(struct hal_11n_rate_series) * 3);
+		memzero(&series[1], sizeof(struct ath9k_11n_rate_series) * 3);
 	}
 
 	/*
@@ -1019,8 +1020,8 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
 	struct ath_desc *ds = bf_last->bf_desc;
 	struct ath_buf *bf_next, *bf_lastq = NULL;
 	struct list_head bf_head, bf_pending;
-	u_int16_t seq_st = 0;
-	u_int32_t ba[WME_BA_BMP_SIZE >> 5];
+	u16 seq_st = 0;
+	u32 ba[WME_BA_BMP_SIZE >> 5];
 	int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
 	int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
 
@@ -1046,7 +1047,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
 				 * when perform internal reset in this routine.
 				 * Only enable reset in STA mode for now.
 				 */
-				if (sc->sc_opmode == HAL_M_STA)
+				if (sc->sc_opmode == ATH9K_M_STA)
 					needreset = 1;
 			}
 		} else {
@@ -1258,7 +1259,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 	struct ieee80211_tx_info *tx_info;
 	struct ath_tx_info_priv *tx_info_priv;
 	int nacked, txok, nbad = 0, isrifs = 0;
-	enum hal_status status;
+	int status;
 
 	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: tx queue %d (%x), link %p\n", __func__,
@@ -1307,7 +1308,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 		ds = lastbf->bf_desc;    /* NB: last decriptor */
 
 		status = ath9k_hw_txprocdesc(ah, ds);
-		if (status == HAL_EINPROGRESS) {
+		if (status == -EINPROGRESS) {
 			spin_unlock_bh(&txq->axq_lock);
 			break;
 		}
@@ -1363,7 +1364,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 		if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
 			tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
 		if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
-				(bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
+				(bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
 			if (ds->ds_txstat.ts_status == 0)
 				nacked++;
 
@@ -1429,11 +1430,11 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
 	struct ath_hal *ah = sc->sc_ah;
 	int i;
 	int npend = 0;
-	enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
+	enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
 
 	/* XXX return value */
 	if (!sc->sc_invalid) {
-		for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+		for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 			if (ATH_TXQ_SETUP(sc, i)) {
 				ath_tx_stopdma(sc, &sc->sc_txq[i]);
 
@@ -1446,7 +1447,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
 	}
 
 	if (npend) {
-		enum hal_status status;
+		int status;
 
 		/* TxDMA not stopped, reset the hal */
 		DPRINTF(sc, ATH_DBG_XMIT,
@@ -1466,7 +1467,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
 		spin_unlock_bh(&sc->sc_resetlock);
 	}
 
-	for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 		if (ATH_TXQ_SETUP(sc, i))
 			ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
 	}
@@ -1559,15 +1560,15 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
  * returns aggr limit based on lowest of the rates
  */
 
-static u_int32_t ath_lookup_rate(struct ath_softc *sc,
+static u32 ath_lookup_rate(struct ath_softc *sc,
 				 struct ath_buf *bf)
 {
-	const struct hal_rate_table *rt = sc->sc_currates;
+	const struct ath9k_rate_table *rt = sc->sc_currates;
 	struct sk_buff *skb;
 	struct ieee80211_tx_info *tx_info;
 	struct ath_tx_info_priv *tx_info_priv;
-	u_int32_t max_4ms_framelen, frame_length;
-	u_int16_t aggr_limit, legacy = 0, maxampdu;
+	u32 max_4ms_framelen, frame_length;
+	u16 aggr_limit, legacy = 0, maxampdu;
 	int i;
 
 
@@ -1607,7 +1608,7 @@ static u_int32_t ath_lookup_rate(struct ath_softc *sc,
 		return 0;
 
 	aggr_limit = min(max_4ms_framelen,
-		(u_int32_t)ATH_AMPDU_LIMIT_DEFAULT);
+		(u32)ATH_AMPDU_LIMIT_DEFAULT);
 
 	/*
 	 * h/w can accept aggregates upto 16 bit lengths (65535).
@@ -1629,12 +1630,12 @@ static u_int32_t ath_lookup_rate(struct ath_softc *sc,
 
 static int ath_compute_num_delims(struct ath_softc *sc,
 				  struct ath_buf *bf,
-				  u_int16_t frmlen)
+				  u16 frmlen)
 {
-	const struct hal_rate_table *rt = sc->sc_currates;
-	u_int32_t nsymbits, nsymbols, mpdudensity;
-	u_int16_t minlen;
-	u_int8_t rc, flags, rix;
+	const struct ath9k_rate_table *rt = sc->sc_currates;
+	u32 nsymbits, nsymbols, mpdudensity;
+	u16 minlen;
+	u8 rc, flags, rix;
 	int width, half_gi, ndelim, mindelim;
 
 	/* Select standard number of delimiters based on frame length alone */
@@ -1646,7 +1647,7 @@ static int ath_compute_num_delims(struct ath_softc *sc,
 	 * TODO - this could be improved to be dependent on the rate.
 	 *      The hardware can keep up at lower rates, but not higher rates
 	 */
-	if (bf->bf_keytype != HAL_KEY_TYPE_CLEAR)
+	if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
 		ndelim += ATH_AGGR_ENCRYPTDELIM;
 
 	/*
@@ -1707,7 +1708,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
 	struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
 	struct list_head bf_head;
 	int rl = 0, nframes = 0, ndelim;
-	u_int16_t aggr_limit = 0, al = 0, bpad = 0,
+	u16 aggr_limit = 0, al = 0, bpad = 0,
 		al_delta, h_baw = tid->baw_size / 2;
 	enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
 	int prev_al = 0, is_ds_rate = 0;
@@ -1981,7 +1982,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
 static int ath_tx_start_dma(struct ath_softc *sc,
 			    struct sk_buff *skb,
 			    struct scatterlist *sg,
-			    u_int32_t n_sg,
+			    u32 n_sg,
 			    struct ath_tx_control *txctl)
 {
 	struct ath_node *an = txctl->an;
@@ -2047,7 +2048,7 @@ static int ath_tx_start_dma(struct ath_softc *sc,
 			       ds,
 			       bf->bf_frmlen, /* frame length */
 			       txctl->atype, /* Atheros packet type */
-			       min(txctl->txpower, (u_int16_t)60), /* txpower */
+			       min(txctl->txpower, (u16)60), /* txpower */
 			       txctl->keyix,            /* key cache index */
 			       txctl->keytype,          /* key type */
 			       txctl->flags);           /* flags */
@@ -2208,14 +2209,14 @@ int ath_tx_cleanup(struct ath_softc *sc)
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	struct hal_txq_info qi;
+	struct ath9k_txq_info qi;
 	int qnum;
 
 	memzero(&qi, sizeof(qi));
 	qi.tqi_subtype = subtype;
-	qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
-	qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
-	qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
+	qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
+	qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
+	qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
 	qi.tqi_compBuf = 0;
 
 	/*
@@ -2233,7 +2234,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
 	 * The UAPSD queue is an exception, since we take a desc-
 	 * based intr on the EOSP frames.
 	 */
-	if (qtype == HAL_TX_QUEUE_UAPSD)
+	if (qtype == ATH9K_TX_QUEUE_UAPSD)
 		qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
 	else
 		qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
@@ -2299,7 +2300,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
 			__func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
 		return 0;
 	}
-	txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
+	txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
 	if (txq != NULL) {
 		sc->sc_haltype2q[haltype] = txq->axq_qnum;
 		return 1;
@@ -2312,7 +2313,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
 	int qnum;
 
 	switch (qtype) {
-	case HAL_TX_QUEUE_DATA:
+	case ATH9K_TX_QUEUE_DATA:
 		if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
 			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: HAL AC %u out of range, max %zu!\n",
@@ -2322,10 +2323,10 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
 		}
 		qnum = sc->sc_haltype2q[haltype];
 		break;
-	case HAL_TX_QUEUE_BEACON:
+	case ATH9K_TX_QUEUE_BEACON:
 		qnum = sc->sc_bhalq;
 		break;
-	case HAL_TX_QUEUE_CAB:
+	case ATH9K_TX_QUEUE_CAB:
 		qnum = sc->sc_cabq->axq_qnum;
 		break;
 	default:
@@ -2336,11 +2337,11 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
 
 /* Update parameters for a transmit queue */
 
-int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
+int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_txq_info *qi0)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	int error = 0;
-	struct hal_txq_info qi;
+	struct ath9k_txq_info qi;
 
 	if (qnum == sc->sc_bhalq) {
 		/*
@@ -2375,7 +2376,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
 
 int ath_cabq_update(struct ath_softc *sc)
 {
-	struct hal_txq_info qi;
+	struct ath9k_txq_info qi;
 	int qnum = sc->sc_cabq->axq_qnum;
 	struct ath_beacon_config conf;
 
@@ -2383,10 +2384,10 @@ int ath_cabq_update(struct ath_softc *sc)
 	/*
 	 * Ensure the readytime % is within the bounds.
 	 */
-	if (sc->sc_config.cabqReadytime < HAL_READY_TIME_LO_BOUND)
-		sc->sc_config.cabqReadytime = HAL_READY_TIME_LO_BOUND;
-	else if (sc->sc_config.cabqReadytime > HAL_READY_TIME_HI_BOUND)
-		sc->sc_config.cabqReadytime = HAL_READY_TIME_HI_BOUND;
+	if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
+		sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
+	else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
+		sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
 
 	ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
 	qi.tqi_readyTime =
@@ -2422,16 +2423,16 @@ int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
 
 void ath_tx_tasklet(struct ath_softc *sc)
 {
-	u_int64_t tsf = ath9k_hw_gettsf64(sc->sc_ah);
+	u64 tsf = ath9k_hw_gettsf64(sc->sc_ah);
 	int i, nacked = 0;
-	u_int32_t qcumask = ((1 << HAL_NUM_TX_QUEUES) - 1);
+	u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
 
 	ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
 
 	/*
 	 * Process each active queue.
 	 */
-	for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 		if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
 			nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
 	}
@@ -2516,12 +2517,12 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx)
 	ath_drain_txdataq(sc, retry_tx);
 }
 
-u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum)
+u32 ath_txq_depth(struct ath_softc *sc, int qnum)
 {
 	return sc->sc_txq[qnum].axq_depth;
 }
 
-u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
+u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
 {
 	return sc->sc_txq[qnum].axq_aggr_depth;
 }
@@ -2620,7 +2621,7 @@ int ath_tx_aggr_stop(struct ath_softc *sc,
  */
 
 void ath_tx_aggr_teardown(struct ath_softc *sc,
-	struct ath_node *an, u_int8_t tid)
+	struct ath_node *an, u8 tid)
 {
 	struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
 	struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
@@ -2784,19 +2785,19 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
 			switch (acno) {
 			case WME_AC_BE:
 				ac->qnum = ath_tx_get_qnum(sc,
-					HAL_TX_QUEUE_DATA, HAL_WME_AC_BE);
+					ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
 				break;
 			case WME_AC_BK:
 				ac->qnum = ath_tx_get_qnum(sc,
-					HAL_TX_QUEUE_DATA, HAL_WME_AC_BK);
+					ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
 				break;
 			case WME_AC_VI:
 				ac->qnum = ath_tx_get_qnum(sc,
-					HAL_TX_QUEUE_DATA, HAL_WME_AC_VI);
+					ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
 				break;
 			case WME_AC_VO:
 				ac->qnum = ath_tx_get_qnum(sc,
-					HAL_TX_QUEUE_DATA, HAL_WME_AC_VO);
+					ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
 				break;
 			}
 		}
@@ -2812,7 +2813,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc,
 	struct ath_atx_ac *ac, *ac_tmp;
 	struct ath_atx_tid *tid, *tid_tmp;
 	struct ath_txq *txq;
-	for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
+	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
 		if (ATH_TXQ_SETUP(sc, i)) {
 			txq = &sc->sc_txq[i];