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authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-03-15 16:57:27 +0000
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-03-15 16:57:27 +0000
commitb5e9c6c090f7cde79953d7ebdcd627e36d2fa838 (patch)
tree636ae93b3d300a9eabaf60284d173da4b019e782
parent4b1477f8c17ff700f2c23d41db998fe5c58226ff (diff)
ar8216: fix a MTU related regression
Switch reset on AR8316 appears to clobber the MTU configuration register and possibly other global config registers. Move global configuration register init writes back to the reset callback. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30951 3c298f89-4303-0410-b956-a3cf2f4a3e73
-rw-r--r--target/linux/generic/files/drivers/net/phy/ar8216.c48
1 files changed, 29 insertions, 19 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c
index 4b67cb6cb..660a11bce 100644
--- a/target/linux/generic/files/drivers/net/phy/ar8216.c
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.c
@@ -648,11 +648,6 @@ ar8216_hw_apply(struct switch_dev *dev)
static int
ar8216_hw_init(struct ar8216_priv *priv)
{
- /* XXX: undocumented magic from atheros, required! */
- priv->write(priv, 0x38, 0xc000050e);
-
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
- AR8216_GCTRL_MTU, 1518 + 8 + 2);
return 0;
}
@@ -675,10 +670,6 @@ ar8236_hw_init(struct ar8216_priv *priv)
}
msleep(1000);
- /* enable jumbo frames */
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
- AR8316_GCTRL_MTU, 9018 + 8 + 2);
-
priv->initialized = true;
return 0;
}
@@ -716,9 +707,6 @@ ar8316_hw_init(struct ar8216_priv *priv)
priv->write(priv, 0x8, newval);
- /* standard atheros magic */
- priv->write(priv, 0x38, 0xc000050e);
-
/* Initialize the ports */
bus = priv->phy->bus;
for (i = 0; i < 5; i++) {
@@ -741,19 +729,39 @@ ar8316_hw_init(struct ar8216_priv *priv)
msleep(1000);
}
- /* enable jumbo frames */
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
- AR8316_GCTRL_MTU, 9018 + 8 + 2);
-
- /* enable cpu port to receive multicast and broadcast frames */
- priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
-
out:
priv->initialized = true;
return 0;
}
static void
+ar8216_init_globals(struct ar8216_priv *priv)
+{
+ switch (priv->chip) {
+ case AR8216:
+ /* standard atheros magic */
+ priv->write(priv, 0x38, 0xc000050e);
+
+ ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8216_GCTRL_MTU, 1518 + 8 + 2);
+ break;
+ case AR8316:
+ /* standard atheros magic */
+ priv->write(priv, 0x38, 0xc000050e);
+
+ /* enable cpu port to receive multicast and broadcast frames */
+ priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
+
+ /* fall through */
+ case AR8236:
+ /* enable jumbo frames */
+ ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8316_GCTRL_MTU, 9018 + 8 + 2);
+ break;
+ }
+}
+
+static void
ar8216_init_port(struct ar8216_priv *priv, int port)
{
/* Enable port learning and tx */
@@ -796,7 +804,9 @@ ar8216_reset_switch(struct switch_dev *dev)
for (i = 0; i < AR8216_NUM_PORTS; i++)
ar8216_init_port(priv, i);
+ ar8216_init_globals(priv);
mutex_unlock(&priv->reg_mutex);
+
return ar8216_hw_apply(dev);
}