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authorjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-07-03 18:05:04 +0000
committerjuhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>2012-07-03 18:05:04 +0000
commit08ec8f0d80ba9971f90f1a8aa29b711a95a25a35 (patch)
tree7e0e982db19910fa30396796ccef7d1ad60dd7ea
parent0a5e27843553ec1beb43428168c9153717a77017 (diff)
mac80211: add support for AR9550
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32588 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat
-rw-r--r--package/mac80211/Makefile2
-rw-r--r--package/mac80211/patches/570-ath9k-define-DEVID-for-QCA955x.patch21
-rw-r--r--package/mac80211/patches/571-ath9k-define-MAC-version-for-AR9550.patch31
-rw-r--r--package/mac80211/patches/572-ath9k-set-MAC-version-for-AR9550.patch23
-rw-r--r--package/mac80211/patches/573-ath9k-add-platform_device_id-for-AR9550.patch24
-rw-r--r--package/mac80211/patches/574-ath9k-add-BB-name-string-for-AR9550.patch21
-rw-r--r--package/mac80211/patches/575-ath9k-clear-pciexpress-flag-for-AR9550.patch22
-rw-r--r--package/mac80211/patches/576-ath9k-enable-TX-RX-data-byte-swap-for-AR9550.patch23
-rw-r--r--package/mac80211/patches/577-ath9k-add-initvals-for-AR9550.patch1317
-rw-r--r--package/mac80211/patches/578-ath9k-add-mode-register-initialization-code-for-AR95.patch224
-rw-r--r--package/mac80211/patches/579-ath9k-read-spur-frequency-information-from-eeprom-fo.patch33
-rw-r--r--package/mac80211/patches/580-ath9k-fix-XPABIASLEVEL-settings-for-AR9550.patch36
-rw-r--r--package/mac80211/patches/581-ath9k-fix-antenna-control-configuration-for-AR9550.patch35
-rw-r--r--package/mac80211/patches/582-ath9k-fix-PAPRD-settings-for-AR9550.patch22
-rw-r--r--package/mac80211/patches/583-ath9k-fix-RF-channel-frequency-configuration-for-AR9.patch32
-rw-r--r--package/mac80211/patches/584-ath9k-disable-SYNC_HOST1_FATAL-interrupts-for-AR9550.patch34
-rw-r--r--package/mac80211/patches/585-ath9k-skip-internal-regulator-configuration-for-AR95.patch22
-rw-r--r--package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch75
-rw-r--r--package/mac80211/patches/587-ath9k-enable-PLL-workaround-for-AR9550.patch23
-rw-r--r--package/mac80211/patches/588-ath9k-set-4ADDRESS-bit-in-RX-filter-for-AR9550.patch34
-rw-r--r--package/mac80211/patches/589-ath9k-enable-support-for-AR9550.patch29
21 files changed, 2082 insertions, 1 deletions
diff --git a/package/mac80211/Makefile b/package/mac80211/Makefile
index 5d40e7e33..0e2b25cac 100644
--- a/package/mac80211/Makefile
+++ b/package/mac80211/Makefile
@@ -11,7 +11,7 @@ include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=mac80211
PKG_VERSION:=2012-06-14
-PKG_RELEASE:=1
+PKG_RELEASE:=2
PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources
PKG_MD5SUM:=009fd7aa420693e30df9090cee9ea189
diff --git a/package/mac80211/patches/570-ath9k-define-DEVID-for-QCA955x.patch b/package/mac80211/patches/570-ath9k-define-DEVID-for-QCA955x.patch
new file mode 100644
index 000000000..8713db18e
--- /dev/null
+++ b/package/mac80211/patches/570-ath9k-define-DEVID-for-QCA955x.patch
@@ -0,0 +1,21 @@
+From ba1e32844fcd396d90b357d3a620ffc1abcde614 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:13 +0200
+Subject: [PATCH 01/20] ath9k: define DEVID for QCA955x
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.h | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -48,6 +48,7 @@
+ #define AR9300_DEVID_AR9580 0x0033
+ #define AR9300_DEVID_AR9462 0x0034
+ #define AR9300_DEVID_AR9330 0x0035
++#define AR9300_DEVID_QCA955X 0x0038
+
+ #define AR5416_AR9100_DEVID 0x000b
+
diff --git a/package/mac80211/patches/571-ath9k-define-MAC-version-for-AR9550.patch b/package/mac80211/patches/571-ath9k-define-MAC-version-for-AR9550.patch
new file mode 100644
index 000000000..8e5a79473
--- /dev/null
+++ b/package/mac80211/patches/571-ath9k-define-MAC-version-for-AR9550.patch
@@ -0,0 +1,31 @@
+From b8122a3554e574b154cdf09ae843e6464d8ad1cc Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:13 +0200
+Subject: [PATCH 02/20] ath9k: define MAC version for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/reg.h | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/reg.h
++++ b/drivers/net/wireless/ath/ath9k/reg.h
+@@ -798,6 +798,7 @@
+ #define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
+ #define AR_SREV_VERSION_9462 0x280
+ #define AR_SREV_REVISION_9462_20 2
++#define AR_SREV_VERSION_9550 0x400
+
+ #define AR_SREV_5416(_ah) \
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
+@@ -905,6 +906,9 @@
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
+ ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
+
++#define AR_SREV_9550(_ah) \
++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
++
+ #define AR_SREV_9580(_ah) \
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
+ ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))
diff --git a/package/mac80211/patches/572-ath9k-set-MAC-version-for-AR9550.patch b/package/mac80211/patches/572-ath9k-set-MAC-version-for-AR9550.patch
new file mode 100644
index 000000000..866ff5fcc
--- /dev/null
+++ b/package/mac80211/patches/572-ath9k-set-MAC-version-for-AR9550.patch
@@ -0,0 +1,23 @@
+From 9bd8677ad5f1814e0f784f92d07ba8bd38c6bc13 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:14 +0200
+Subject: [PATCH 03/20] ath9k: set MAC version for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -343,6 +343,9 @@ static void ath9k_hw_read_revisions(stru
+ val = REG_READ(ah, AR_SREV);
+ ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
+ return;
++ case AR9300_DEVID_QCA955X:
++ ah->hw_version.macVersion = AR_SREV_VERSION_9550;
++ return;
+ }
+
+ val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
diff --git a/package/mac80211/patches/573-ath9k-add-platform_device_id-for-AR9550.patch b/package/mac80211/patches/573-ath9k-add-platform_device_id-for-AR9550.patch
new file mode 100644
index 000000000..15ea82c8c
--- /dev/null
+++ b/package/mac80211/patches/573-ath9k-add-platform_device_id-for-AR9550.patch
@@ -0,0 +1,24 @@
+From 6583f34718e322373130daaca42660c669079384 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:59 +0200
+Subject: [PATCH 04/20] ath9k: add platform_device_id for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ahb.c | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ahb.c
++++ b/drivers/net/wireless/ath/ath9k/ahb.c
+@@ -35,6 +35,10 @@ static const struct platform_device_id a
+ .name = "ar934x_wmac",
+ .driver_data = AR9300_DEVID_AR9340,
+ },
++ {
++ .name = "qca955x_wmac",
++ .driver_data = AR9300_DEVID_QCA955X,
++ },
+ {},
+ };
+
diff --git a/package/mac80211/patches/574-ath9k-add-BB-name-string-for-AR9550.patch b/package/mac80211/patches/574-ath9k-add-BB-name-string-for-AR9550.patch
new file mode 100644
index 000000000..b27efb98e
--- /dev/null
+++ b/package/mac80211/patches/574-ath9k-add-BB-name-string-for-AR9550.patch
@@ -0,0 +1,21 @@
+From 7ea9d187a4334e35d9ed1a3cbeb85d0b1275b24c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:14 +0200
+Subject: [PATCH 05/20] ath9k: add BB name string for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -3135,6 +3135,7 @@ static struct {
+ { AR_SREV_VERSION_9340, "9340" },
+ { AR_SREV_VERSION_9485, "9485" },
+ { AR_SREV_VERSION_9462, "9462" },
++ { AR_SREV_VERSION_9550, "9550" },
+ };
+
+ /* For devices with external radios */
diff --git a/package/mac80211/patches/575-ath9k-clear-pciexpress-flag-for-AR9550.patch b/package/mac80211/patches/575-ath9k-clear-pciexpress-flag-for-AR9550.patch
new file mode 100644
index 000000000..8cb482606
--- /dev/null
+++ b/package/mac80211/patches/575-ath9k-clear-pciexpress-flag-for-AR9550.patch
@@ -0,0 +1,22 @@
+From 68e9cddb98d5a7de130b064ec301e2370679160a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:15 +0200
+Subject: [PATCH 06/20] ath9k: clear pciexpress flag for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -667,7 +667,7 @@ static int __ath9k_hw_init(struct ath_hw
+ }
+
+ if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
+- AR_SREV_9330(ah))
++ AR_SREV_9330(ah) || AR_SREV_9550(ah))
+ ah->is_pciexpress = false;
+
+ ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
diff --git a/package/mac80211/patches/576-ath9k-enable-TX-RX-data-byte-swap-for-AR9550.patch b/package/mac80211/patches/576-ath9k-enable-TX-RX-data-byte-swap-for-AR9550.patch
new file mode 100644
index 000000000..f5b1cac2d
--- /dev/null
+++ b/package/mac80211/patches/576-ath9k-enable-TX-RX-data-byte-swap-for-AR9550.patch
@@ -0,0 +1,23 @@
+From 3fa372b3d51c310023a20432ebc8f718c31feff0 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:15 +0200
+Subject: [PATCH 07/20] ath9k: enable TX/RX data byte swap for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -1985,7 +1985,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+ REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
+ }
+ #ifdef __BIG_ENDIAN
+- else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
++ else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
++ AR_SREV_9550(ah))
+ REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
+ else
+ REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
diff --git a/package/mac80211/patches/577-ath9k-add-initvals-for-AR9550.patch b/package/mac80211/patches/577-ath9k-add-initvals-for-AR9550.patch
new file mode 100644
index 000000000..a2d60f913
--- /dev/null
+++ b/package/mac80211/patches/577-ath9k-add-initvals-for-AR9550.patch
@@ -0,0 +1,1317 @@
+From 33b61be1c9174ed3f779a1d05aee0e4753eb4068 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:16 +0200
+Subject: [PATCH 08/20] ath9k: add initvals for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+Note: Some lines are longer than the 80 character limit,
+and checkpatch.pl complains about those. However I would like
+to keep the existing format because the initval arrays are
+more readable in this form.
+
+Gabor
+
+ drivers/net/wireless/ath/ath9k/ar9003_hw.c | 1 +
+ .../net/wireless/ath/ath9k/ar955x_1p0_initvals.h | 1284 ++++++++++++++++++++
+ 2 files changed, 1285 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -21,6 +21,7 @@
+ #include "ar9340_initvals.h"
+ #include "ar9330_1p1_initvals.h"
+ #include "ar9330_1p2_initvals.h"
++#include "ar955x_1p0_initvals.h"
+ #include "ar9580_1p0_initvals.h"
+ #include "ar9462_2p0_initvals.h"
+
+--- /dev/null
++++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
+@@ -0,0 +1,1284 @@
++/*
++ * Copyright (c) 2010-2011 Atheros Communications Inc.
++ * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef INITVALS_955X_1P0_H
++#define INITVALS_955X_1P0_H
++
++/* AR955X 1.0 */
++
++static const u32 ar955x_1p0_radio_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
++ {0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x06345f2a, 0x06345f2a},
++ {0x000160ac, 0xa4647c00, 0xa4647c00, 0xa4646800, 0xa4646800},
++ {0x000160b0, 0x01885f52, 0x01885f52, 0x04accf3a, 0x04accf3a},
++ {0x00016104, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
++ {0x0001610c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
++ {0x00016140, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
++ {0x00016504, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
++ {0x0001650c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
++ {0x00016540, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
++ {0x00016904, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
++ {0x0001690c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
++ {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
++};
++
++static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
++ /* Addr allmodes */
++ {0x0000a398, 0x00000000},
++ {0x0000a39c, 0x6f7f0301},
++ {0x0000a3a0, 0xca9228ee},
++};
++
++static const u32 ar955x_1p0_baseband_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
++ {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
++ {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
++ {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
++ {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
++ {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
++ {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
++ {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
++ {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
++ {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
++ {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
++ {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
++ {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
++ {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
++ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
++ {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10822, 0xcfa10822},
++ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
++ {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
++ {0x0000a204, 0x005c0ec0, 0x005c0ec4, 0x005c0ec4, 0x005c0ec0},
++ {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
++ {0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
++ {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
++ {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
++ {0x0000a238, 0xffb01018, 0xffb01018, 0xffb01018, 0xffb01018},
++ {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
++ {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
++ {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
++ {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
++ {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
++ {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
++ {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
++ {0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
++ {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
++ {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
++ {0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
++ {0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
++ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
++ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
++ {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
++ {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
++ {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
++ {0x0000b284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
++ {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
++ {0x0000be04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
++ {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
++ {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
++ {0x0000c284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
++};
++
++static const u32 ar955x_1p0_radio_core[][2] = {
++ /* Addr allmodes */
++ {0x00016000, 0x36db6db6},
++ {0x00016004, 0x6db6db40},
++ {0x00016008, 0x73f00000},
++ {0x0001600c, 0x00000000},
++ {0x00016040, 0x7f80fff8},
++ {0x0001604c, 0x76d005b5},
++ {0x00016050, 0x557cf031},
++ {0x00016054, 0x13449440},
++ {0x00016058, 0x0c51c92c},
++ {0x0001605c, 0x3db7fffc},
++ {0x00016060, 0xfffffffc},
++ {0x00016064, 0x000f0278},
++ {0x00016068, 0x6db6db6c},
++ {0x0001606c, 0x6db60000},
++ {0x00016080, 0x00080000},
++ {0x00016084, 0x0e48048c},
++ {0x00016088, 0x14214514},
++ {0x0001608c, 0x119f101e},
++ {0x00016090, 0x24926490},
++ {0x00016094, 0x00000000},
++ {0x000160a0, 0x0a108ffe},
++ {0x000160a4, 0x812fc370},
++ {0x000160a8, 0x423c8000},
++ {0x000160b4, 0x92480080},
++ {0x000160c0, 0x006db6d0},
++ {0x000160c4, 0x6db6db60},
++ {0x000160c8, 0x6db6db6c},
++ {0x000160cc, 0x01e6c000},
++ {0x00016100, 0x11999601},
++ {0x00016108, 0x00080010},
++ {0x00016144, 0x02084080},
++ {0x00016148, 0x000080c0},
++ {0x00016280, 0x01800804},
++ {0x00016284, 0x00038dc5},
++ {0x00016288, 0x00000000},
++ {0x0001628c, 0x00000040},
++ {0x00016380, 0x00000000},
++ {0x00016384, 0x00000000},
++ {0x00016388, 0x00400705},
++ {0x0001638c, 0x00800700},
++ {0x00016390, 0x00800700},
++ {0x00016394, 0x00000000},
++ {0x00016398, 0x00000000},
++ {0x0001639c, 0x00000000},
++ {0x000163a0, 0x00000001},
++ {0x000163a4, 0x00000001},
++ {0x000163a8, 0x00000000},
++ {0x000163ac, 0x00000000},
++ {0x000163b0, 0x00000000},
++ {0x000163b4, 0x00000000},
++ {0x000163b8, 0x00000000},
++ {0x000163bc, 0x00000000},
++ {0x000163c0, 0x000000a0},
++ {0x000163c4, 0x000c0000},
++ {0x000163c8, 0x14021402},
++ {0x000163cc, 0x00001402},
++ {0x000163d0, 0x00000000},
++ {0x000163d4, 0x00000000},
++ {0x00016400, 0x36db6db6},
++ {0x00016404, 0x6db6db40},
++ {0x00016408, 0x73f00000},
++ {0x0001640c, 0x00000000},
++ {0x00016440, 0x7f80fff8},
++ {0x0001644c, 0x76d005b5},
++ {0x00016450, 0x557cf031},
++ {0x00016454, 0x13449440},
++ {0x00016458, 0x0c51c92c},
++ {0x0001645c, 0x3db7fffc},
++ {0x00016460, 0xfffffffc},
++ {0x00016464, 0x000f0278},
++ {0x00016468, 0x6db6db6c},
++ {0x0001646c, 0x6db60000},
++ {0x00016500, 0x11999601},
++ {0x00016508, 0x00080010},
++ {0x00016544, 0x02084080},
++ {0x00016548, 0x000080c0},
++ {0x00016780, 0x00000000},
++ {0x00016784, 0x00000000},
++ {0x00016788, 0x00400705},
++ {0x0001678c, 0x00800700},
++ {0x00016790, 0x00800700},
++ {0x00016794, 0x00000000},
++ {0x00016798, 0x00000000},
++ {0x0001679c, 0x00000000},
++ {0x000167a0, 0x00000001},
++ {0x000167a4, 0x00000001},
++ {0x000167a8, 0x00000000},
++ {0x000167ac, 0x00000000},
++ {0x000167b0, 0x00000000},
++ {0x000167b4, 0x00000000},
++ {0x000167b8, 0x00000000},
++ {0x000167bc, 0x00000000},
++ {0x000167c0, 0x000000a0},
++ {0x000167c4, 0x000c0000},
++ {0x000167c8, 0x14021402},
++ {0x000167cc, 0x00001402},
++ {0x000167d0, 0x00000000},
++ {0x000167d4, 0x00000000},
++ {0x00016800, 0x36db6db6},
++ {0x00016804, 0x6db6db40},
++ {0x00016808, 0x73f00000},
++ {0x0001680c, 0x00000000},
++ {0x00016840, 0x7f80fff8},
++ {0x0001684c, 0x76d005b5},
++ {0x00016850, 0x557cf031},
++ {0x00016854, 0x13449440},
++ {0x00016858, 0x0c51c92c},
++ {0x0001685c, 0x3db7fffc},
++ {0x00016860, 0xfffffffc},
++ {0x00016864, 0x000f0278},
++ {0x00016868, 0x6db6db6c},
++ {0x0001686c, 0x6db60000},
++ {0x00016900, 0x11999601},
++ {0x00016908, 0x00080010},
++ {0x00016944, 0x02084080},
++ {0x00016948, 0x000080c0},
++ {0x00016b80, 0x00000000},
++ {0x00016b84, 0x00000000},
++ {0x00016b88, 0x00400705},
++ {0x00016b8c, 0x00800700},
++ {0x00016b90, 0x00800700},
++ {0x00016b94, 0x00000000},
++ {0x00016b98, 0x00000000},
++ {0x00016b9c, 0x00000000},
++ {0x00016ba0, 0x00000001},
++ {0x00016ba4, 0x00000001},
++ {0x00016ba8, 0x00000000},
++ {0x00016bac, 0x00000000},
++ {0x00016bb0, 0x00000000},
++ {0x00016bb4, 0x00000000},
++ {0x00016bb8, 0x00000000},
++ {0x00016bbc, 0x00000000},
++ {0x00016bc0, 0x000000a0},
++ {0x00016bc4, 0x000c0000},
++ {0x00016bc8, 0x14021402},
++ {0x00016bcc, 0x00001402},
++ {0x00016bd0, 0x00000000},
++ {0x00016bd4, 0x00000000},
++};
++
++static const u32 ar955x_1p0_modes_xpa_tx_gain_table[][9] = {
++ /* Addr 5G_HT20_L 5G_HT40_L 5G_HT20_M 5G_HT40_M 5G_HT20_H 5G_HT40_H 2G_HT40 2G_HT20 */
++ {0x0000a2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
++ {0x0000a2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
++ {0x0000a2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
++ {0x0000a2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
++ {0x0000a410, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050da, 0x000050da},
++ {0x0000a500, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000000, 0x00000000},
++ {0x0000a504, 0x04000005, 0x04000005, 0x04000005, 0x04000005, 0x04000005, 0x04000005, 0x04000002, 0x04000002},
++ {0x0000a508, 0x08000009, 0x08000009, 0x08000009, 0x08000009, 0x08000009, 0x08000009, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c000006, 0x0c000006},
++ {0x0000a510, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x0f00000a, 0x0f00000a},
++ {0x0000a514, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x1300000c, 0x1300000c},
++ {0x0000a518, 0x19004008, 0x19004008, 0x19004008, 0x19004008, 0x18004008, 0x18004008, 0x1700000e, 0x1700000e},
++ {0x0000a51c, 0x1d00400a, 0x1d00400a, 0x1d00400a, 0x1d00400a, 0x1c00400a, 0x1c00400a, 0x1b000064, 0x1b000064},
++ {0x0000a520, 0x230020a2, 0x230020a2, 0x210020a2, 0x210020a2, 0x200020a2, 0x200020a2, 0x1f000242, 0x1f000242},
++ {0x0000a524, 0x2500006e, 0x2500006e, 0x2500006e, 0x2500006e, 0x2400006e, 0x2400006e, 0x23000229, 0x23000229},
++ {0x0000a528, 0x29022221, 0x29022221, 0x28022221, 0x28022221, 0x27022221, 0x27022221, 0x270002a2, 0x270002a2},
++ {0x0000a52c, 0x2d00062a, 0x2d00062a, 0x2c00062a, 0x2c00062a, 0x2a00062a, 0x2a00062a, 0x2c001203, 0x2c001203},
++ {0x0000a530, 0x340220a5, 0x340220a5, 0x320220a5, 0x320220a5, 0x2f0220a5, 0x2f0220a5, 0x30001803, 0x30001803},
++ {0x0000a534, 0x380022c5, 0x380022c5, 0x350022c5, 0x350022c5, 0x320022c5, 0x320022c5, 0x33000881, 0x33000881},
++ {0x0000a538, 0x3b002486, 0x3b002486, 0x39002486, 0x39002486, 0x36002486, 0x36002486, 0x38001809, 0x38001809},
++ {0x0000a53c, 0x3f00248a, 0x3f00248a, 0x3d00248a, 0x3d00248a, 0x3a00248a, 0x3a00248a, 0x3a000814, 0x3a000814},
++ {0x0000a540, 0x4202242c, 0x4202242c, 0x4102242c, 0x4102242c, 0x3f02242c, 0x3f02242c, 0x3f001a0c, 0x3f001a0c},
++ {0x0000a544, 0x490044c6, 0x490044c6, 0x460044c6, 0x460044c6, 0x420044c6, 0x420044c6, 0x43001a0e, 0x43001a0e},
++ {0x0000a548, 0x4d024485, 0x4d024485, 0x4a024485, 0x4a024485, 0x46024485, 0x46024485, 0x46001812, 0x46001812},
++ {0x0000a54c, 0x51044483, 0x51044483, 0x4e044483, 0x4e044483, 0x4a044483, 0x4a044483, 0x49001884, 0x49001884},
++ {0x0000a550, 0x5404a40c, 0x5404a40c, 0x5204a40c, 0x5204a40c, 0x4d04a40c, 0x4d04a40c, 0x4d001e84, 0x4d001e84},
++ {0x0000a554, 0x57024632, 0x57024632, 0x55024632, 0x55024632, 0x52024632, 0x52024632, 0x50001e69, 0x50001e69},
++ {0x0000a558, 0x5c00a634, 0x5c00a634, 0x5900a634, 0x5900a634, 0x5600a634, 0x5600a634, 0x550006f4, 0x550006f4},
++ {0x0000a55c, 0x5f026832, 0x5f026832, 0x5d026832, 0x5d026832, 0x5a026832, 0x5a026832, 0x59000ad3, 0x59000ad3},
++ {0x0000a560, 0x6602b012, 0x6602b012, 0x6202b012, 0x6202b012, 0x5d02b012, 0x5d02b012, 0x5e000ad5, 0x5e000ad5},
++ {0x0000a564, 0x6e02d0e1, 0x6e02d0e1, 0x6802d0e1, 0x6802d0e1, 0x6002d0e1, 0x6002d0e1, 0x61001ced, 0x61001ced},
++ {0x0000a568, 0x7202b4c4, 0x7202b4c4, 0x6c02b4c4, 0x6c02b4c4, 0x6502b4c4, 0x6502b4c4, 0x660018d4, 0x660018d4},
++ {0x0000a56c, 0x75007894, 0x75007894, 0x70007894, 0x70007894, 0x6b007894, 0x6b007894, 0x660018d4, 0x660018d4},
++ {0x0000a570, 0x7b025c74, 0x7b025c74, 0x75025c74, 0x75025c74, 0x70025c74, 0x70025c74, 0x660018d4, 0x660018d4},
++ {0x0000a574, 0x8300bcb5, 0x8300bcb5, 0x7a00bcb5, 0x7a00bcb5, 0x7600bcb5, 0x7600bcb5, 0x660018d4, 0x660018d4},
++ {0x0000a578, 0x8a04dc74, 0x8a04dc74, 0x7f04dc74, 0x7f04dc74, 0x7c04dc74, 0x7c04dc74, 0x660018d4, 0x660018d4},
++ {0x0000a57c, 0x8a04dc74, 0x8a04dc74, 0x7f04dc74, 0x7f04dc74, 0x7c04dc74, 0x7c04dc74, 0x660018d4, 0x660018d4},
++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03804000, 0x03804000},
++ {0x0000a610, 0x04c08c01, 0x04c08c01, 0x04808b01, 0x04808b01, 0x04808a01, 0x04808a01, 0x0300ca02, 0x0300ca02},
++ {0x0000a614, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00000e04, 0x00000e04},
++ {0x0000a618, 0x04010c01, 0x04010c01, 0x03c10b01, 0x03c10b01, 0x03810a01, 0x03810a01, 0x03014000, 0x03014000},
++ {0x0000a61c, 0x03814e05, 0x03814e05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03414d05, 0x00000000, 0x00000000},
++ {0x0000a620, 0x04010303, 0x04010303, 0x03c10303, 0x03c10303, 0x03810303, 0x03810303, 0x00000000, 0x00000000},
++ {0x0000a624, 0x03814e05, 0x03814e05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03014000, 0x03014000},
++ {0x0000a628, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x03804c05, 0x03804c05},
++ {0x0000a62c, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x0701de06, 0x0701de06},
++ {0x0000a630, 0x03418000, 0x03418000, 0x03018000, 0x03018000, 0x02c18000, 0x02c18000, 0x07819c07, 0x07819c07},
++ {0x0000a634, 0x03815004, 0x03815004, 0x03414f04, 0x03414f04, 0x03414e04, 0x03414e04, 0x0701dc07, 0x0701dc07},
++ {0x0000a638, 0x03005302, 0x03005302, 0x02c05202, 0x02c05202, 0x02805202, 0x02805202, 0x0701dc07, 0x0701dc07},
++ {0x0000a63c, 0x04c09302, 0x04c09302, 0x04809202, 0x04809202, 0x04809202, 0x04809202, 0x0701dc07, 0x0701dc07},
++ {0x0000b2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
++ {0x0000b2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
++ {0x0000b2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
++ {0x0000b2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
++ {0x0000c2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
++ {0x0000c2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
++ {0x0000c2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
++ {0x0000c2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
++ {0x00016044, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
++ {0x00016048, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
++ {0x00016280, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01808e84, 0x01808e84},
++ {0x00016444, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
++ {0x00016448, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
++ {0x00016844, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
++ {0x00016848, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
++};
++
++static const u32 ar955x_1p0_mac_core[][2] = {
++ /* Addr allmodes */
++ {0x00000008, 0x00000000},
++ {0x00000030, 0x00020085},
++ {0x00000034, 0x00000005},
++ {0x00000040, 0x00000000},
++ {0x00000044, 0x00000000},
++ {0x00000048, 0x00000008},
++ {0x0000004c, 0x00000010},
++ {0x00000050, 0x00000000},
++ {0x00001040, 0x002ffc0f},
++ {0x00001044, 0x002ffc0f},
++ {0x00001048, 0x002ffc0f},
++ {0x0000104c, 0x002ffc0f},
++ {0x00001050, 0x002ffc0f},
++ {0x00001054, 0x002ffc0f},
++ {0x00001058, 0x002ffc0f},
++ {0x0000105c, 0x002ffc0f},
++ {0x00001060, 0x002ffc0f},
++ {0x00001064, 0x002ffc0f},
++ {0x000010f0, 0x00000100},
++ {0x00001270, 0x00000000},
++ {0x000012b0, 0x00000000},
++ {0x000012f0, 0x00000000},
++ {0x0000143c, 0x00000000},
++ {0x0000147c, 0x00000000},
++ {0x00008000, 0x00000000},
++ {0x00008004, 0x00000000},
++ {0x00008008, 0x00000000},
++ {0x0000800c, 0x00000000},
++ {0x00008018, 0x00000000},
++ {0x00008020, 0x00000000},
++ {0x00008038, 0x00000000},
++ {0x0000803c, 0x00000000},
++ {0x00008040, 0x00000000},
++ {0x00008044, 0x00000000},
++ {0x00008048, 0x00000000},
++ {0x0000804c, 0xffffffff},
++ {0x00008054, 0x00000000},
++ {0x00008058, 0x00000000},
++ {0x0000805c, 0x000fc78f},
++ {0x00008060, 0x0000000f},
++ {0x00008064, 0x00000000},
++ {0x00008070, 0x00000310},
++ {0x00008074, 0x00000020},
++ {0x00008078, 0x00000000},
++ {0x0000809c, 0x0000000f},
++ {0x000080a0, 0x00000000},
++ {0x000080a4, 0x02ff0000},
++ {0x000080a8, 0x0e070605},
++ {0x000080ac, 0x0000000d},
++ {0x000080b0, 0x00000000},
++ {0x000080b4, 0x00000000},
++ {0x000080b8, 0x00000000},
++ {0x000080bc, 0x00000000},
++ {0x000080c0, 0x2a800000},
++ {0x000080c4, 0x06900168},
++ {0x000080c8, 0x13881c22},
++ {0x000080cc, 0x01f40000},
++ {0x000080d0, 0x00252500},
++ {0x000080d4, 0x00a00000},
++ {0x000080d8, 0x00400000},
++ {0x000080dc, 0x00000000},
++ {0x000080e0, 0xffffffff},
++ {0x000080e4, 0x0000ffff},
++ {0x000080e8, 0x3f3f3f3f},
++ {0x000080ec, 0x00000000},
++ {0x000080f0, 0x00000000},
++ {0x000080f4, 0x00000000},
++ {0x000080fc, 0x00020000},
++ {0x00008100, 0x00000000},
++ {0x00008108, 0x00000052},
++ {0x0000810c, 0x00000000},
++ {0x00008110, 0x00000000},
++ {0x00008114, 0x000007ff},
++ {0x00008118, 0x000000aa},
++ {0x0000811c, 0x00003210},
++ {0x00008124, 0x00000000},
++ {0x00008128, 0x00000000},
++ {0x0000812c, 0x00000000},
++ {0x00008130, 0x00000000},
++ {0x00008134, 0x00000000},
++ {0x00008138, 0x00000000},
++ {0x0000813c, 0x0000ffff},
++ {0x00008140, 0x000000fe},
++ {0x00008144, 0xffffffff},
++ {0x00008168, 0x00000000},
++ {0x0000816c, 0x00000000},
++ {0x000081c0, 0x00000000},
++ {0x000081c4, 0x33332210},
++ {0x000081ec, 0x00000000},
++ {0x000081f0, 0x00000000},
++ {0x000081f4, 0x00000000},
++ {0x000081f8, 0x00000000},
++ {0x000081fc, 0x00000000},
++ {0x00008240, 0x00100000},
++ {0x00008244, 0x0010f400},
++ {0x00008248, 0x00000800},
++ {0x0000824c, 0x0001e800},
++ {0x00008250, 0x00000000},
++ {0x00008254, 0x00000000},
++ {0x00008258, 0x00000000},
++ {0x0000825c, 0x40000000},
++ {0x00008260, 0x00080922},
++ {0x00008264, 0x9d400010},
++ {0x00008268, 0xffffffff},
++ {0x0000826c, 0x0000ffff},
++ {0x00008270, 0x00000000},
++ {0x00008274, 0x40000000},
++ {0x00008278, 0x003e4180},
++ {0x0000827c, 0x00000004},
++ {0x00008284, 0x0000002c},
++ {0x00008288, 0x0000002c},
++ {0x0000828c, 0x000000ff},
++ {0x00008294, 0x00000000},
++ {0x00008298, 0x00000000},
++ {0x0000829c, 0x00000000},
++ {0x00008300, 0x00001d40},
++ {0x00008314, 0x00000000},
++ {0x0000831c, 0x0000010d},
++ {0x00008328, 0x00000000},
++ {0x0000832c, 0x0000001f},
++ {0x00008330, 0x00000302},
++ {0x00008334, 0x00000700},
++ {0x00008338, 0xffff0000},
++ {0x0000833c, 0x02400000},
++ {0x00008340, 0x000107ff},
++ {0x00008344, 0xaa48107b},
++ {0x00008348, 0x008f0000},
++ {0x0000835c, 0x00000000},
++ {0x00008360, 0xffffffff},
++ {0x00008364, 0xffffffff},
++ {0x00008368, 0x00000000},
++ {0x00008370, 0x00000000},
++ {0x00008374, 0x000000ff},
++ {0x00008378, 0x00000000},
++ {0x0000837c, 0x00000000},
++ {0x00008380, 0xffffffff},
++ {0x00008384, 0xffffffff},
++ {0x00008390, 0xffffffff},
++ {0x00008394, 0xffffffff},
++ {0x00008398, 0x00000000},
++ {0x0000839c, 0x00000000},
++ {0x000083a0, 0x00000000},
++ {0x000083a4, 0x0000fa14},
++ {0x000083a8, 0x000f0c00},
++ {0x000083ac, 0x33332210},
++ {0x000083b0, 0x33332210},
++ {0x000083b4, 0x33332210},
++ {0x000083b8, 0x33332210},
++ {0x000083bc, 0x00000000},
++ {0x000083c0, 0x00000000},
++ {0x000083c4, 0x00000000},
++ {0x000083c8, 0x00000000},
++ {0x000083cc, 0x00000200},
++ {0x000083d0, 0x8c7901ff},
++};
++
++static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
++ /* Addr allmodes */
++ {0x0000a000, 0x00010000},
++ {0x0000a004, 0x00030002},
++ {0x0000a008, 0x00050004},
++ {0x0000a00c, 0x00810080},
++ {0x0000a010, 0x00830082},
++ {0x0000a014, 0x01810180},
++ {0x0000a018, 0x01830182},
++ {0x0000a01c, 0x01850184},
++ {0x0000a020, 0x01890188},
++ {0x0000a024, 0x018b018a},
++ {0x0000a028, 0x018d018c},
++ {0x0000a02c, 0x01910190},
++ {0x0000a030, 0x01930192},
++ {0x0000a034, 0x01950194},
++ {0x0000a038, 0x038a0196},
++ {0x0000a03c, 0x038c038b},
++ {0x0000a040, 0x0390038d},
++ {0x0000a044, 0x03920391},
++ {0x0000a048, 0x03940393},
++ {0x0000a04c, 0x03960395},
++ {0x0000a050, 0x00000000},
++ {0x0000a054, 0x00000000},
++ {0x0000a058, 0x00000000},
++ {0x0000a05c, 0x00000000},
++ {0x0000a060, 0x00000000},
++ {0x0000a064, 0x00000000},
++ {0x0000a068, 0x00000000},
++ {0x0000a06c, 0x00000000},
++ {0x0000a070, 0x00000000},
++ {0x0000a074, 0x00000000},
++ {0x0000a078, 0x00000000},
++ {0x0000a07c, 0x00000000},
++ {0x0000a080, 0x22222229},
++ {0x0000a084, 0x1d1d1d1d},
++ {0x0000a088, 0x1d1d1d1d},
++ {0x0000a08c, 0x1d1d1d1d},
++ {0x0000a090, 0x171d1d1d},
++ {0x0000a094, 0x11111717},
++ {0x0000a098, 0x00030311},
++ {0x0000a09c, 0x00000000},
++ {0x0000a0a0, 0x00000000},
++ {0x0000a0a4, 0x00000000},
++ {0x0000a0a8, 0x00000000},
++ {0x0000a0ac, 0x00000000},
++ {0x0000a0b0, 0x00000000},
++ {0x0000a0b4, 0x00000000},
++ {0x0000a0b8, 0x00000000},
++ {0x0000a0bc, 0x00000000},
++ {0x0000a0c0, 0x001f0000},
++ {0x0000a0c4, 0x01000101},
++ {0x0000a0c8, 0x011e011f},
++ {0x0000a0cc, 0x011c011d},
++ {0x0000a0d0, 0x02030204},
++ {0x0000a0d4, 0x02010202},
++ {0x0000a0d8, 0x021f0200},
++ {0x0000a0dc, 0x0302021e},
++ {0x0000a0e0, 0x03000301},
++ {0x0000a0e4, 0x031e031f},
++ {0x0000a0e8, 0x0402031d},
++ {0x0000a0ec, 0x04000401},
++ {0x0000a0f0, 0x041e041f},
++ {0x0000a0f4, 0x0502041d},
++ {0x0000a0f8, 0x05000501},
++ {0x0000a0fc, 0x051e051f},
++ {0x0000a100, 0x06010602},
++ {0x0000a104, 0x061f0600},
++ {0x0000a108, 0x061d061e},
++ {0x0000a10c, 0x07020703},
++ {0x0000a110, 0x07000701},
++ {0x0000a114, 0x00000000},
++ {0x0000a118, 0x00000000},
++ {0x0000a11c, 0x00000000},
++ {0x0000a120, 0x00000000},
++ {0x0000a124, 0x00000000},
++ {0x0000a128, 0x00000000},
++ {0x0000a12c, 0x00000000},
++ {0x0000a130, 0x00000000},
++ {0x0000a134, 0x00000000},
++ {0x0000a138, 0x00000000},
++ {0x0000a13c, 0x00000000},
++ {0x0000a140, 0x001f0000},
++ {0x0000a144, 0x01000101},
++ {0x0000a148, 0x011e011f},
++ {0x0000a14c, 0x011c011d},
++ {0x0000a150, 0x02030204},
++ {0x0000a154, 0x02010202},
++ {0x0000a158, 0x021f0200},
++ {0x0000a15c, 0x0302021e},
++ {0x0000a160, 0x03000301},
++ {0x0000a164, 0x031e031f},
++ {0x0000a168, 0x0402031d},
++ {0x0000a16c, 0x04000401},
++ {0x0000a170, 0x041e041f},
++ {0x0000a174, 0x0502041d},
++ {0x0000a178, 0x05000501},
++ {0x0000a17c, 0x051e051f},
++ {0x0000a180, 0x06010602},
++ {0x0000a184, 0x061f0600},
++ {0x0000a188, 0x061d061e},
++ {0x0000a18c, 0x07020703},
++ {0x0000a190, 0x07000701},
++ {0x0000a194, 0x00000000},
++ {0x0000a198, 0x00000000},
++ {0x0000a19c, 0x00000000},
++ {0x0000a1a0, 0x00000000},
++ {0x0000a1a4, 0x00000000},
++ {0x0000a1a8, 0x00000000},
++ {0x0000a1ac, 0x00000000},
++ {0x0000a1b0, 0x00000000},
++ {0x0000a1b4, 0x00000000},
++ {0x0000a1b8, 0x00000000},
++ {0x0000a1bc, 0x00000000},
++ {0x0000a1c0, 0x00000000},
++ {0x0000a1c4, 0x00000000},
++ {0x0000a1c8, 0x00000000},
++ {0x0000a1cc, 0x00000000},
++ {0x0000a1d0, 0x00000000},
++ {0x0000a1d4, 0x00000000},
++ {0x0000a1d8, 0x00000000},
++ {0x0000a1dc, 0x00000000},
++ {0x0000a1e0, 0x00000000},
++ {0x0000a1e4, 0x00000000},
++ {0x0000a1e8, 0x00000000},
++ {0x0000a1ec, 0x00000000},
++ {0x0000a1f0, 0x00000396},
++ {0x0000a1f4, 0x00000396},
++ {0x0000a1f8, 0x00000396},
++ {0x0000a1fc, 0x00000196},
++ {0x0000b000, 0x00010000},
++ {0x0000b004, 0x00030002},
++ {0x0000b008, 0x00050004},
++ {0x0000b00c, 0x00810080},
++ {0x0000b010, 0x00830082},
++ {0x0000b014, 0x01810180},
++ {0x0000b018, 0x01830182},
++ {0x0000b01c, 0x01850184},
++ {0x0000b020, 0x02810280},
++ {0x0000b024, 0x02830282},
++ {0x0000b028, 0x02850284},
++ {0x0000b02c, 0x02890288},
++ {0x0000b030, 0x028b028a},
++ {0x0000b034, 0x0388028c},
++ {0x0000b038, 0x038a0389},
++ {0x0000b03c, 0x038c038b},
++ {0x0000b040, 0x0390038d},
++ {0x0000b044, 0x03920391},
++ {0x0000b048, 0x03940393},
++ {0x0000b04c, 0x03960395},
++ {0x0000b050, 0x00000000},
++ {0x0000b054, 0x00000000},
++ {0x0000b058, 0x00000000},
++ {0x0000b05c, 0x00000000},
++ {0x0000b060, 0x00000000},
++ {0x0000b064, 0x00000000},
++ {0x0000b068, 0x00000000},
++ {0x0000b06c, 0x00000000},
++ {0x0000b070, 0x00000000},
++ {0x0000b074, 0x00000000},
++ {0x0000b078, 0x00000000},
++ {0x0000b07c, 0x00000000},
++ {0x0000b080, 0x23232323},
++ {0x0000b084, 0x21232323},
++ {0x0000b088, 0x19191c1e},
++ {0x0000b08c, 0x12141417},
++ {0x0000b090, 0x07070e0e},
++ {0x0000b094, 0x03030305},
++ {0x0000b098, 0x00000003},
++ {0x0000b09c, 0x00000000},
++ {0x0000b0a0, 0x00000000},
++ {0x0000b0a4, 0x00000000},
++ {0x0000b0a8, 0x00000000},
++ {0x0000b0ac, 0x00000000},
++ {0x0000b0b0, 0x00000000},
++ {0x0000b0b4, 0x00000000},
++ {0x0000b0b8, 0x00000000},
++ {0x0000b0bc, 0x00000000},
++ {0x0000b0c0, 0x003f0020},
++ {0x0000b0c4, 0x00400041},
++ {0x0000b0c8, 0x0140005f},
++ {0x0000b0cc, 0x0160015f},
++ {0x0000b0d0, 0x017e017f},
++ {0x0000b0d4, 0x02410242},
++ {0x0000b0d8, 0x025f0240},
++ {0x0000b0dc, 0x027f0260},
++ {0x0000b0e0, 0x0341027e},
++ {0x0000b0e4, 0x035f0340},
++ {0x0000b0e8, 0x037f0360},
++ {0x0000b0ec, 0x04400441},
++ {0x0000b0f0, 0x0460045f},
++ {0x0000b0f4, 0x0541047f},
++ {0x0000b0f8, 0x055f0540},
++ {0x0000b0fc, 0x057f0560},
++ {0x0000b100, 0x06400641},
++ {0x0000b104, 0x0660065f},
++ {0x0000b108, 0x067e067f},
++ {0x0000b10c, 0x07410742},
++ {0x0000b110, 0x075f0740},
++ {0x0000b114, 0x077f0760},
++ {0x0000b118, 0x07800781},
++ {0x0000b11c, 0x07a0079f},
++ {0x0000b120, 0x07c107bf},
++ {0x0000b124, 0x000007c0},
++ {0x0000b128, 0x00000000},
++ {0x0000b12c, 0x00000000},
++ {0x0000b130, 0x00000000},
++ {0x0000b134, 0x00000000},
++ {0x0000b138, 0x00000000},
++ {0x0000b13c, 0x00000000},
++ {0x0000b140, 0x003f0020},
++ {0x0000b144, 0x00400041},
++ {0x0000b148, 0x0140005f},
++ {0x0000b14c, 0x0160015f},
++ {0x0000b150, 0x017e017f},
++ {0x0000b154, 0x02410242},
++ {0x0000b158, 0x025f0240},
++ {0x0000b15c, 0x027f0260},
++ {0x0000b160, 0x0341027e},
++ {0x0000b164, 0x035f0340},
++ {0x0000b168, 0x037f0360},
++ {0x0000b16c, 0x04400441},
++ {0x0000b170, 0x0460045f},
++ {0x0000b174, 0x0541047f},
++ {0x0000b178, 0x055f0540},
++ {0x0000b17c, 0x057f0560},
++ {0x0000b180, 0x06400641},
++ {0x0000b184, 0x0660065f},
++ {0x0000b188, 0x067e067f},
++ {0x0000b18c, 0x07410742},
++ {0x0000b190, 0x075f0740},
++ {0x0000b194, 0x077f0760},
++ {0x0000b198, 0x07800781},
++ {0x0000b19c, 0x07a0079f},
++ {0x0000b1a0, 0x07c107bf},
++ {0x0000b1a4, 0x000007c0},
++ {0x0000b1a8, 0x00000000},
++ {0x0000b1ac, 0x00000000},
++ {0x0000b1b0, 0x00000000},
++ {0x0000b1b4, 0x00000000},
++ {0x0000b1b8, 0x00000000},
++ {0x0000b1bc, 0x00000000},
++ {0x0000b1c0, 0x00000000},
++ {0x0000b1c4, 0x00000000},
++ {0x0000b1c8, 0x00000000},
++ {0x0000b1cc, 0x00000000},
++ {0x0000b1d0, 0x00000000},
++ {0x0000b1d4, 0x00000000},
++ {0x0000b1d8, 0x00000000},
++ {0x0000b1dc, 0x00000000},
++ {0x0000b1e0, 0x00000000},
++ {0x0000b1e4, 0x00000000},
++ {0x0000b1e8, 0x00000000},
++ {0x0000b1ec, 0x00000000},
++ {0x0000b1f0, 0x00000396},
++ {0x0000b1f4, 0x00000396},
++ {0x0000b1f8, 0x00000396},
++ {0x0000b1fc, 0x00000196},
++};
++
++static const u32 ar955x_1p0_baseband_core[][2] = {
++ /* Addr allmodes */
++ {0x00009800, 0xafe68e30},
++ {0x00009804, 0xfd14e000},
++ {0x00009808, 0x9c0a9f6b},
++ {0x0000980c, 0x04900000},
++ {0x00009814, 0x0280c00a},
++ {0x00009818, 0x00000000},
++ {0x0000981c, 0x00020028},
++ {0x00009834, 0x6400a190},
++ {0x00009838, 0x0108ecff},
++ {0x0000983c, 0x14000600},
++ {0x00009880, 0x201fff00},
++ {0x00009884, 0x00001042},
++ {0x000098a4, 0x00200400},
++ {0x000098b0, 0x32840bbe},
++ {0x000098bc, 0x00000002},
++ {0x000098d0, 0x004b6a8e},
++ {0x000098d4, 0x00000820},
++ {0x000098dc, 0x00000000},
++ {0x000098f0, 0x00000000},
++ {0x000098f4, 0x00000000},
++ {0x00009c04, 0xff55ff55},
++ {0x00009c08, 0x0320ff55},
++ {0x00009c0c, 0x00000000},
++ {0x00009c10, 0x00000000},
++ {0x00009c14, 0x00046384},
++ {0x00009c18, 0x05b6b440},
++ {0x00009c1c, 0x00b6b440},
++ {0x00009d00, 0xc080a333},
++ {0x00009d04, 0x40206c10},
++ {0x00009d08, 0x009c4060},
++ {0x00009d0c, 0x9883800a},
++ {0x00009d10, 0x01834061},
++ {0x00009d14, 0x00c0040b},
++ {0x00009d18, 0x00000000},
++ {0x00009e08, 0x0038230c},
++ {0x00009e24, 0x990bb515},
++ {0x00009e28, 0x0c6f0000},
++ {0x00009e30, 0x06336f77},
++ {0x00009e34, 0x6af6532f},
++ {0x00009e38, 0x0cc80c00},
++ {0x00009e40, 0x0d261820},
++ {0x00009e4c, 0x00001004},
++ {0x00009e50, 0x00ff03f1},
++ {0x00009fc0, 0x813e4788},
++ {0x00009fc4, 0x0001efb5},
++ {0x00009fcc, 0x40000014},
++ {0x00009fd0, 0x01193b93},
++ {0x0000a20c, 0x00000000},
++ {0x0000a220, 0x00000000},
++ {0x0000a224, 0x00000000},
++ {0x0000a228, 0x10002310},
++ {0x0000a23c, 0x00000000},
++ {0x0000a244, 0x0c000000},
++ {0x0000a248, 0x00000140},
++ {0x0000a2a0, 0x00000007},
++ {0x0000a2c0, 0x00000007},
++ {0x0000a2c8, 0x00000000},
++ {0x0000a2d4, 0x00000000},
++ {0x0000a2ec, 0x00000000},
++ {0x0000a2f0, 0x00000000},
++ {0x0000a2f4, 0x00000000},
++ {0x0000a2f8, 0x00000000},
++ {0x0000a344, 0x00000000},
++ {0x0000a34c, 0x00000000},
++ {0x0000a350, 0x0000a000},
++ {0x0000a364, 0x00000000},
++ {0x0000a370, 0x00000000},
++ {0x0000a390, 0x00000001},
++ {0x0000a394, 0x00000444},
++ {0x0000a398, 0x1f020503},
++ {0x0000a39c, 0x29180c03},
++ {0x0000a3a0, 0x9a8b6844},
++ {0x0000a3a4, 0x00000000},
++ {0x0000a3a8, 0xaaaaaaaa},
++ {0x0000a3ac, 0x3c466478},
++ {0x0000a3c0, 0x20202020},
++ {0x0000a3c4, 0x22222220},
++ {0x0000a3c8, 0x20200020},
++ {0x0000a3cc, 0x20202020},
++ {0x0000a3d0, 0x20202020},
++ {0x0000a3d4, 0x20202020},
++ {0x0000a3d8, 0x20202020},
++ {0x0000a3dc, 0x20202020},
++ {0x0000a3e0, 0x20202020},
++ {0x0000a3e4, 0x20202020},
++ {0x0000a3e8, 0x20202020},
++ {0x0000a3ec, 0x20202020},
++ {0x0000a3f0, 0x00000000},
++ {0x0000a3f4, 0x00000000},
++ {0x0000a3f8, 0x0c9bd380},
++ {0x0000a3fc, 0x000f0f01},
++ {0x0000a400, 0x8fa91f01},
++ {0x0000a404, 0x00000000},
++ {0x0000a408, 0x0e79e5c6},
++ {0x0000a40c, 0x00820820},
++ {0x0000a414, 0x1ce739ce},
++ {0x0000a418, 0x2d001dce},
++ {0x0000a41c, 0x1ce739ce},
++ {0x0000a420, 0x000001ce},
++ {0x0000a424, 0x1ce739ce},
++ {0x0000a428, 0x000001ce},
++ {0x0000a42c, 0x1ce739ce},
++ {0x0000a430, 0x1ce739ce},
++ {0x0000a434, 0x00000000},
++ {0x0000a438, 0x00001801},
++ {0x0000a43c, 0x00100000},
++ {0x0000a444, 0x00000000},
++ {0x0000a448, 0x05000080},
++ {0x0000a44c, 0x00000001},
++ {0x0000a450, 0x00010000},
++ {0x0000a458, 0x00000000},
++ {0x0000a644, 0x3fad9d74},
++ {0x0000a648, 0x0048060a},
++ {0x0000a64c, 0x00003c37},
++ {0x0000a670, 0x03020100},
++ {0x0000a674, 0x09080504},
++ {0x0000a678, 0x0d0c0b0a},
++ {0x0000a67c, 0x13121110},
++ {0x0000a680, 0x31301514},
++ {0x0000a684, 0x35343332},
++ {0x0000a688, 0x00000036},
++ {0x0000a690, 0x00000838},
++ {0x0000a7cc, 0x00000000},
++ {0x0000a7d0, 0x00000000},
++ {0x0000a7d4, 0x00000004},
++ {0x0000a7dc, 0x00000000},
++ {0x0000a8d0, 0x004b6a8e},
++ {0x0000a8d4, 0x00000820},
++ {0x0000a8dc, 0x00000000},
++ {0x0000a8f0, 0x00000000},
++ {0x0000a8f4, 0x00000000},
++ {0x0000b2d0, 0x00000080},
++ {0x0000b2d4, 0x00000000},
++ {0x0000b2ec, 0x00000000},
++ {0x0000b2f0, 0x00000000},
++ {0x0000b2f4, 0x00000000},
++ {0x0000b2f8, 0x00000000},
++ {0x0000b408, 0x0e79e5c0},
++ {0x0000b40c, 0x00820820},
++ {0x0000b420, 0x00000000},
++ {0x0000b8d0, 0x004b6a8e},
++ {0x0000b8d4, 0x00000820},
++ {0x0000b8dc, 0x00000000},
++ {0x0000b8f0, 0x00000000},
++ {0x0000b8f4, 0x00000000},
++ {0x0000c2d0, 0x00000080},
++ {0x0000c2d4, 0x00000000},
++ {0x0000c2ec, 0x00000000},
++ {0x0000c2f0, 0x00000000},
++ {0x0000c2f4, 0x00000000},
++ {0x0000c2f8, 0x00000000},
++ {0x0000c408, 0x0e79e5c0},
++ {0x0000c40c, 0x00820820},
++ {0x0000c420, 0x00000000},
++};
++
++static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
++ /* Addr allmodes */
++ {0x0000a000, 0x00010000},
++ {0x0000a004, 0x00030002},
++ {0x0000a008, 0x00050004},
++ {0x0000a00c, 0x00810080},
++ {0x0000a010, 0x00830082},
++ {0x0000a014, 0x01810180},
++ {0x0000a018, 0x01830182},
++ {0x0000a01c, 0x01850184},
++ {0x0000a020, 0x01890188},
++ {0x0000a024, 0x018b018a},
++ {0x0000a028, 0x018d018c},
++ {0x0000a02c, 0x03820190},
++ {0x0000a030, 0x03840383},
++ {0x0000a034, 0x03880385},
++ {0x0000a038, 0x038a0389},
++ {0x0000a03c, 0x038c038b},
++ {0x0000a040, 0x0390038d},
++ {0x0000a044, 0x03920391},
++ {0x0000a048, 0x03940393},
++ {0x0000a04c, 0x03960395},
++ {0x0000a050, 0x00000000},
++ {0x0000a054, 0x00000000},
++ {0x0000a058, 0x00000000},
++ {0x0000a05c, 0x00000000},
++ {0x0000a060, 0x00000000},
++ {0x0000a064, 0x00000000},
++ {0x0000a068, 0x00000000},
++ {0x0000a06c, 0x00000000},
++ {0x0000a070, 0x00000000},
++ {0x0000a074, 0x00000000},
++ {0x0000a078, 0x00000000},
++ {0x0000a07c, 0x00000000},
++ {0x0000a080, 0x29292929},
++ {0x0000a084, 0x29292929},
++ {0x0000a088, 0x29292929},
++ {0x0000a08c, 0x29292929},
++ {0x0000a090, 0x22292929},
++ {0x0000a094, 0x1d1d2222},
++ {0x0000a098, 0x0c111117},
++ {0x0000a09c, 0x00030303},
++ {0x0000a0a0, 0x00000000},
++ {0x0000a0a4, 0x00000000},
++ {0x0000a0a8, 0x00000000},
++ {0x0000a0ac, 0x00000000},
++ {0x0000a0b0, 0x00000000},
++ {0x0000a0b4, 0x00000000},
++ {0x0000a0b8, 0x00000000},
++ {0x0000a0bc, 0x00000000},
++ {0x0000a0c0, 0x001f0000},
++ {0x0000a0c4, 0x01000101},
++ {0x0000a0c8, 0x011e011f},
++ {0x0000a0cc, 0x011c011d},
++ {0x0000a0d0, 0x02030204},
++ {0x0000a0d4, 0x02010202},
++ {0x0000a0d8, 0x021f0200},
++ {0x0000a0dc, 0x0302021e},
++ {0x0000a0e0, 0x03000301},
++ {0x0000a0e4, 0x031e031f},
++ {0x0000a0e8, 0x0402031d},
++ {0x0000a0ec, 0x04000401},
++ {0x0000a0f0, 0x041e041f},
++ {0x0000a0f4, 0x0502041d},
++ {0x0000a0f8, 0x05000501},
++ {0x0000a0fc, 0x051e051f},
++ {0x0000a100, 0x06010602},
++ {0x0000a104, 0x061f0600},
++ {0x0000a108, 0x061d061e},
++ {0x0000a10c, 0x07020703},
++ {0x0000a110, 0x07000701},
++ {0x0000a114, 0x00000000},
++ {0x0000a118, 0x00000000},
++ {0x0000a11c, 0x00000000},
++ {0x0000a120, 0x00000000},
++ {0x0000a124, 0x00000000},
++ {0x0000a128, 0x00000000},
++ {0x0000a12c, 0x00000000},
++ {0x0000a130, 0x00000000},
++ {0x0000a134, 0x00000000},
++ {0x0000a138, 0x00000000},
++ {0x0000a13c, 0x00000000},
++ {0x0000a140, 0x001f0000},
++ {0x0000a144, 0x01000101},
++ {0x0000a148, 0x011e011f},
++ {0x0000a14c, 0x011c011d},
++ {0x0000a150, 0x02030204},
++ {0x0000a154, 0x02010202},
++ {0x0000a158, 0x021f0200},
++ {0x0000a15c, 0x0302021e},
++ {0x0000a160, 0x03000301},
++ {0x0000a164, 0x031e031f},
++ {0x0000a168, 0x0402031d},
++ {0x0000a16c, 0x04000401},
++ {0x0000a170, 0x041e041f},
++ {0x0000a174, 0x0502041d},
++ {0x0000a178, 0x05000501},
++ {0x0000a17c, 0x051e051f},
++ {0x0000a180, 0x06010602},
++ {0x0000a184, 0x061f0600},
++ {0x0000a188, 0x061d061e},
++ {0x0000a18c, 0x07020703},
++ {0x0000a190, 0x07000701},
++ {0x0000a194, 0x00000000},
++ {0x0000a198, 0x00000000},
++ {0x0000a19c, 0x00000000},
++ {0x0000a1a0, 0x00000000},
++ {0x0000a1a4, 0x00000000},
++ {0x0000a1a8, 0x00000000},
++ {0x0000a1ac, 0x00000000},
++ {0x0000a1b0, 0x00000000},
++ {0x0000a1b4, 0x00000000},
++ {0x0000a1b8, 0x00000000},
++ {0x0000a1bc, 0x00000000},
++ {0x0000a1c0, 0x00000000},
++ {0x0000a1c4, 0x00000000},
++ {0x0000a1c8, 0x00000000},
++ {0x0000a1cc, 0x00000000},
++ {0x0000a1d0, 0x00000000},
++ {0x0000a1d4, 0x00000000},
++ {0x0000a1d8, 0x00000000},
++ {0x0000a1dc, 0x00000000},
++ {0x0000a1e0, 0x00000000},
++ {0x0000a1e4, 0x00000000},
++ {0x0000a1e8, 0x00000000},
++ {0x0000a1ec, 0x00000000},
++ {0x0000a1f0, 0x00000396},
++ {0x0000a1f4, 0x00000396},
++ {0x0000a1f8, 0x00000396},
++ {0x0000a1fc, 0x00000196},
++ {0x0000b000, 0x00010000},
++ {0x0000b004, 0x00030002},
++ {0x0000b008, 0x00050004},
++ {0x0000b00c, 0x00810080},
++ {0x0000b010, 0x00830082},
++ {0x0000b014, 0x01810180},
++ {0x0000b018, 0x01830182},
++ {0x0000b01c, 0x01850184},
++ {0x0000b020, 0x02810280},
++ {0x0000b024, 0x02830282},
++ {0x0000b028, 0x02850284},
++ {0x0000b02c, 0x02890288},
++ {0x0000b030, 0x028b028a},
++ {0x0000b034, 0x0388028c},
++ {0x0000b038, 0x038a0389},
++ {0x0000b03c, 0x038c038b},
++ {0x0000b040, 0x0390038d},
++ {0x0000b044, 0x03920391},
++ {0x0000b048, 0x03940393},
++ {0x0000b04c, 0x03960395},
++ {0x0000b050, 0x00000000},
++ {0x0000b054, 0x00000000},
++ {0x0000b058, 0x00000000},
++ {0x0000b05c, 0x00000000},
++ {0x0000b060, 0x00000000},
++ {0x0000b064, 0x00000000},
++ {0x0000b068, 0x00000000},
++ {0x0000b06c, 0x00000000},
++ {0x0000b070, 0x00000000},
++ {0x0000b074, 0x00000000},
++ {0x0000b078, 0x00000000},
++ {0x0000b07c, 0x00000000},
++ {0x0000b080, 0x32323232},
++ {0x0000b084, 0x2f2f3232},
++ {0x0000b088, 0x23282a2d},
++ {0x0000b08c, 0x1c1e2123},
++ {0x0000b090, 0x14171919},
++ {0x0000b094, 0x0e0e1214},
++ {0x0000b098, 0x03050707},
++ {0x0000b09c, 0x00030303},
++ {0x0000b0a0, 0x00000000},
++ {0x0000b0a4, 0x00000000},
++ {0x0000b0a8, 0x00000000},
++ {0x0000b0ac, 0x00000000},
++ {0x0000b0b0, 0x00000000},
++ {0x0000b0b4, 0x00000000},
++ {0x0000b0b8, 0x00000000},
++ {0x0000b0bc, 0x00000000},
++ {0x0000b0c0, 0x003f0020},
++ {0x0000b0c4, 0x00400041},
++ {0x0000b0c8, 0x0140005f},
++ {0x0000b0cc, 0x0160015f},
++ {0x0000b0d0, 0x017e017f},
++ {0x0000b0d4, 0x02410242},
++ {0x0000b0d8, 0x025f0240},
++ {0x0000b0dc, 0x027f0260},
++ {0x0000b0e0, 0x0341027e},
++ {0x0000b0e4, 0x035f0340},
++ {0x0000b0e8, 0x037f0360},
++ {0x0000b0ec, 0x04400441},
++ {0x0000b0f0, 0x0460045f},
++ {0x0000b0f4, 0x0541047f},
++ {0x0000b0f8, 0x055f0540},
++ {0x0000b0fc, 0x057f0560},
++ {0x0000b100, 0x06400641},
++ {0x0000b104, 0x0660065f},
++ {0x0000b108, 0x067e067f},
++ {0x0000b10c, 0x07410742},
++ {0x0000b110, 0x075f0740},
++ {0x0000b114, 0x077f0760},
++ {0x0000b118, 0x07800781},
++ {0x0000b11c, 0x07a0079f},
++ {0x0000b120, 0x07c107bf},
++ {0x0000b124, 0x000007c0},
++ {0x0000b128, 0x00000000},
++ {0x0000b12c, 0x00000000},
++ {0x0000b130, 0x00000000},
++ {0x0000b134, 0x00000000},
++ {0x0000b138, 0x00000000},
++ {0x0000b13c, 0x00000000},
++ {0x0000b140, 0x003f0020},
++ {0x0000b144, 0x00400041},
++ {0x0000b148, 0x0140005f},
++ {0x0000b14c, 0x0160015f},
++ {0x0000b150, 0x017e017f},
++ {0x0000b154, 0x02410242},
++ {0x0000b158, 0x025f0240},
++ {0x0000b15c, 0x027f0260},
++ {0x0000b160, 0x0341027e},
++ {0x0000b164, 0x035f0340},
++ {0x0000b168, 0x037f0360},
++ {0x0000b16c, 0x04400441},
++ {0x0000b170, 0x0460045f},
++ {0x0000b174, 0x0541047f},
++ {0x0000b178, 0x055f0540},
++ {0x0000b17c, 0x057f0560},
++ {0x0000b180, 0x06400641},
++ {0x0000b184, 0x0660065f},
++ {0x0000b188, 0x067e067f},
++ {0x0000b18c, 0x07410742},
++ {0x0000b190, 0x075f0740},
++ {0x0000b194, 0x077f0760},
++ {0x0000b198, 0x07800781},
++ {0x0000b19c, 0x07a0079f},
++ {0x0000b1a0, 0x07c107bf},
++ {0x0000b1a4, 0x000007c0},
++ {0x0000b1a8, 0x00000000},
++ {0x0000b1ac, 0x00000000},
++ {0x0000b1b0, 0x00000000},
++ {0x0000b1b4, 0x00000000},
++ {0x0000b1b8, 0x00000000},
++ {0x0000b1bc, 0x00000000},
++ {0x0000b1c0, 0x00000000},
++ {0x0000b1c4, 0x00000000},
++ {0x0000b1c8, 0x00000000},
++ {0x0000b1cc, 0x00000000},
++ {0x0000b1d0, 0x00000000},
++ {0x0000b1d4, 0x00000000},
++ {0x0000b1d8, 0x00000000},
++ {0x0000b1dc, 0x00000000},
++ {0x0000b1e0, 0x00000000},
++ {0x0000b1e4, 0x00000000},
++ {0x0000b1e8, 0x00000000},
++ {0x0000b1ec, 0x00000000},
++ {0x0000b1f0, 0x00000396},
++ {0x0000b1f4, 0x00000396},
++ {0x0000b1f8, 0x00000396},
++ {0x0000b1fc, 0x00000196},
++};
++
++static const u32 ar955x_1p0_soc_preamble[][2] = {
++ /* Addr allmodes */
++ {0x00007000, 0x00000000},
++ {0x00007004, 0x00000000},
++ {0x00007008, 0x00000000},
++ {0x0000700c, 0x00000000},
++ {0x0000701c, 0x00000000},
++ {0x00007020, 0x00000000},
++ {0x00007024, 0x00000000},
++ {0x00007028, 0x00000000},
++ {0x0000702c, 0x00000000},
++ {0x00007030, 0x00000000},
++ {0x00007034, 0x00000002},
++ {0x00007038, 0x000004c2},
++ {0x00007048, 0x00000000},
++};
++
++static const u32 ar955x_1p0_common_wo_xlna_rx_gain_bounds[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
++};
++
++static const u32 ar955x_1p0_mac_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
++ {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
++ {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
++ {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
++ {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
++ {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
++ {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
++ {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
++};
++
++static const u32 ar955x_1p0_common_rx_gain_bounds[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302018, 0x50302018},
++};
++
++static const u32 ar955x_1p0_modes_no_xpa_tx_gain_table[][9] = {
++ /* Addr 5G_HT20_L 5G_HT40_L 5G_HT20_M 5G_HT40_M 5G_HT20_H 5G_HT40_H 2G_HT40 2G_HT20 */
++ {0x0000a2dc, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0xfffe5aaa, 0xfffe5aaa},
++ {0x0000a2e0, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0xfffe9ccc, 0xfffe9ccc},
++ {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0xffffe0f0, 0xffffe0f0},
++ {0x0000a2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffef00, 0xffffef00},
++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d7, 0x000050d7},
++ {0x0000a500, 0x00002220, 0x00002220, 0x00002220, 0x00002220, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
++ {0x0000a504, 0x04002222, 0x04002222, 0x04002222, 0x04002222, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
++ {0x0000a508, 0x09002421, 0x09002421, 0x09002421, 0x09002421, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0d002621, 0x0d002621, 0x0d002621, 0x0d002621, 0x0b000006, 0x0b000006},
++ {0x0000a510, 0x13004620, 0x13004620, 0x13004620, 0x13004620, 0x13004620, 0x13004620, 0x0f00000a, 0x0f00000a},
++ {0x0000a514, 0x19004a20, 0x19004a20, 0x19004a20, 0x19004a20, 0x19004a20, 0x19004a20, 0x1300000c, 0x1300000c},
++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1700000e, 0x1700000e},
++ {0x0000a51c, 0x21005420, 0x21005420, 0x21005420, 0x21005420, 0x21005420, 0x21005420, 0x1b000012, 0x1b000012},
++ {0x0000a520, 0x26005e20, 0x26005e20, 0x26005e20, 0x26005e20, 0x26005e20, 0x26005e20, 0x1f00004a, 0x1f00004a},
++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x23000244, 0x23000244},
++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2700022b, 0x2700022b},
++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x33005e44, 0x33005e44, 0x33005e44, 0x33005e44, 0x2b000625, 0x2b000625},
++ {0x0000a530, 0x38005e65, 0x38005e65, 0x38005e65, 0x38005e65, 0x38005e65, 0x38005e65, 0x2f001006, 0x2f001006},
++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x330008a0, 0x330008a0},
++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x37000a2a, 0x37000a2a},
++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x3b001c23, 0x3b001c23},
++ {0x0000a540, 0x49005e72, 0x49005e72, 0x49005e72, 0x49005e72, 0x49005e72, 0x49005e72, 0x3f0014a0, 0x3f0014a0},
++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x43001882, 0x43001882},
++ {0x0000a548, 0x53005f12, 0x53005f12, 0x53005f12, 0x53005f12, 0x53005f12, 0x53005f12, 0x47001ca2, 0x47001ca2},
++ {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x4b001ec3, 0x4b001ec3},
++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x4f00148c, 0x4f00148c},
++ {0x0000a554, 0x61027f12, 0x61027f12, 0x61027f12, 0x61027f12, 0x61027f12, 0x61027f12, 0x53001c6e, 0x53001c6e},
++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x57001c92, 0x57001c92},
++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x5c001af6, 0x5c001af6},
++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
++ {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
++ {0x0000a610, 0x00804000, 0x00804000, 0x00804000, 0x00804000, 0x00804000, 0x00804000, 0x04005001, 0x04005001},
++ {0x0000a614, 0x00804201, 0x00804201, 0x00804201, 0x00804201, 0x00804201, 0x00804201, 0x03808e02, 0x03808e02},
++ {0x0000a618, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802, 0x0300c000, 0x0300c000},
++ {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x03808e02, 0x03808e02},
++ {0x0000a620, 0x04c15104, 0x04c15104, 0x04c15104, 0x04c15104, 0x04c15104, 0x04c15104, 0x03410c03, 0x03410c03},
++ {0x0000a624, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04014c03, 0x04014c03},
++ {0x0000a628, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x05818d04, 0x05818d04},
++ {0x0000a62c, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801cd04, 0x0801cd04},
++ {0x0000a630, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
++ {0x0000a634, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
++ {0x0000a638, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
++ {0x0000a63c, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
++ {0x0000b2dc, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0xfffe5aaa, 0xfffe5aaa},
++ {0x0000b2e0, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0xfffe9ccc, 0xfffe9ccc},
++ {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0xffffe0f0, 0xffffe0f0},
++ {0x0000b2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffef00, 0xffffef00},
++ {0x0000c2dc, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0xfffe5aaa, 0xfffe5aaa},
++ {0x0000c2e0, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0xfffe9ccc, 0xfffe9ccc},
++ {0x0000c2e4, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0xffffe0f0, 0xffffe0f0},
++ {0x0000c2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffef00, 0xffffef00},
++ {0x00016044, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x054922d4, 0x054922d4},
++ {0x00016048, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
++ {0x00016444, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x054922d4, 0x054922d4},
++ {0x00016448, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
++ {0x00016844, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x054922d4, 0x054922d4},
++ {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
++};
++
++static const u32 ar955x_1p0_soc_postamble[][5] = {
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
++ {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
++};
++
++static const u32 ar955x_1p0_modes_fast_clock[][3] = {
++ /* Addr 5G_HT20 5G_HT40 */
++ {0x00001030, 0x00000268, 0x000004d0},
++ {0x00001070, 0x0000018c, 0x00000318},
++ {0x000010b0, 0x00000fd0, 0x00001fa0},
++ {0x00008014, 0x044c044c, 0x08980898},
++ {0x0000801c, 0x148ec02b, 0x148ec057},
++ {0x00008318, 0x000044c0, 0x00008980},
++ {0x00009e00, 0x0372131c, 0x0372131c},
++ {0x0000a230, 0x0000000b, 0x00000016},
++ {0x0000a254, 0x00000898, 0x00001130},
++};
++
++#endif /* INITVALS_955X_1P0_H */
diff --git a/package/mac80211/patches/578-ath9k-add-mode-register-initialization-code-for-AR95.patch b/package/mac80211/patches/578-ath9k-add-mode-register-initialization-code-for-AR95.patch
new file mode 100644
index 000000000..8a0501271
--- /dev/null
+++ b/package/mac80211/patches/578-ath9k-add-mode-register-initialization-code-for-AR95.patch
@@ -0,0 +1,224 @@
+From 2b4e3da2e595e1c76f65f7da752ec1f037446bd2 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:10:16 +0200
+Subject: [PATCH 09/20] ath9k: add mode register initialization code for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_hw.c | 86 ++++++++++++++++++++++++++-
+ drivers/net/wireless/ath/ath9k/ar9003_phy.c | 61 +++++++++++++++++++-
+ drivers/net/wireless/ath/ath9k/hw.h | 1 +
+ 3 files changed, 145 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -328,7 +328,61 @@ static void ar9003_hw_init_mode_regs(str
+
+ INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
+ ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
++ } else if (AR_SREV_9550(ah)) {
++ /* mac */
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
++ ar955x_1p0_mac_core,
++ ARRAY_SIZE(ar955x_1p0_mac_core), 2);
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
++ ar955x_1p0_mac_postamble,
++ ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
++
++ /* bb */
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
++ ar955x_1p0_baseband_core,
++ ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
++ ar955x_1p0_baseband_postamble,
++ ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
++
++ /* radio */
++ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
++ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
++ ar955x_1p0_radio_core,
++ ARRAY_SIZE(ar955x_1p0_radio_core), 2);
++ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
++ ar955x_1p0_radio_postamble,
++ ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
++
++ /* soc */
++ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
++ ar955x_1p0_soc_preamble,
++ ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
++ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
++ ar955x_1p0_soc_postamble,
++ ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
+
++ /* rx/tx gain */
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
++ ar955x_1p0_common_wo_xlna_rx_gain_table,
++ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
++ 2);
++ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
++ ar955x_1p0_common_wo_xlna_rx_gain_bounds,
++ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
++ 5);
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar955x_1p0_modes_xpa_tx_gain_table,
++ ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
++ 9);
++
++ /* Fast clock modal settings */
++ INIT_INI_ARRAY(&ah->iniModesFastClock,
++ ar955x_1p0_modes_fast_clock,
++ ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
+ } else if (AR_SREV_9580(ah)) {
+ /* mac */
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+@@ -471,6 +525,11 @@ static void ar9003_tx_gain_table_mode0(s
+ ar9485_modes_lowest_ob_db_tx_gain_1_1,
+ ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+ 5);
++ else if (AR_SREV_9550(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar955x_1p0_modes_xpa_tx_gain_table,
++ ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
++ 9);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9580_1p0_lowest_ob_db_tx_gain_table,
+@@ -515,6 +574,11 @@ static void ar9003_tx_gain_table_mode1(s
+ ar9580_1p0_high_ob_db_tx_gain_table,
+ ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
+ 5);
++ else if (AR_SREV_9550(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar955x_1p0_modes_no_xpa_tx_gain_table,
++ ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
++ 9);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9462_modes_high_ob_db_tx_gain_table_2p0,
+@@ -636,7 +700,16 @@ static void ar9003_rx_gain_table_mode0(s
+ ar9485Common_wo_xlna_rx_gain_1_1,
+ ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+ 2);
+- else if (AR_SREV_9580(ah))
++ else if (AR_SREV_9550(ah)) {
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
++ ar955x_1p0_common_rx_gain_table,
++ ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
++ 2);
++ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
++ ar955x_1p0_common_rx_gain_bounds,
++ ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
++ 5);
++ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9580_1p0_rx_gain_table,
+ ARRAY_SIZE(ar9580_1p0_rx_gain_table),
+@@ -680,7 +753,16 @@ static void ar9003_rx_gain_table_mode1(s
+ ar9462_common_wo_xlna_rx_gain_table_2p0,
+ ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
+ 2);
+- else if (AR_SREV_9580(ah))
++ else if (AR_SREV_9550(ah)) {
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
++ ar955x_1p0_common_wo_xlna_rx_gain_table,
++ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
++ 2);
++ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
++ ar955x_1p0_common_wo_xlna_rx_gain_bounds,
++ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
++ 5);
++ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9580_1p0_wo_xlna_rx_gain_table,
+ ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -620,6 +620,50 @@ static void ar9003_hw_prog_ini(struct at
+ }
+ }
+
++static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
++ struct ath9k_channel *chan)
++{
++ int ret;
++
++ switch (chan->chanmode) {
++ case CHANNEL_A:
++ case CHANNEL_A_HT20:
++ if (chan->channel <= 5350)
++ ret = 1;
++ else if ((chan->channel > 5350) && (chan->channel <= 5600))
++ ret = 3;
++ else
++ ret = 5;
++ break;
++
++ case CHANNEL_A_HT40PLUS:
++ case CHANNEL_A_HT40MINUS:
++ if (chan->channel <= 5350)
++ ret = 2;
++ else if ((chan->channel > 5350) && (chan->channel <= 5600))
++ ret = 4;
++ else
++ ret = 6;
++ break;
++
++ case CHANNEL_G:
++ case CHANNEL_G_HT20:
++ case CHANNEL_B:
++ ret = 8;
++ break;
++
++ case CHANNEL_G_HT40PLUS:
++ case CHANNEL_G_HT40MINUS:
++ ret = 7;
++ break;
++
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
+ static int ar9003_hw_process_ini(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+ {
+@@ -661,7 +705,22 @@ static int ar9003_hw_process_ini(struct
+ }
+
+ REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
+- REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
++ if (AR_SREV_9550(ah))
++ REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
++ regWrites);
++
++ if (AR_SREV_9550(ah)) {
++ int modes_txgain_index;
++
++ modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
++ if (modes_txgain_index < 0)
++ return -EINVAL;
++
++ REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
++ regWrites);
++ } else {
++ REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
++ }
+
+ /*
+ * For 5GHz channels requiring Fast Clock, apply
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -820,6 +820,7 @@ struct ath_hw {
+ struct ar5416IniArray iniModesFastClock;
+ struct ar5416IniArray iniAdditional;
+ struct ar5416IniArray iniModesRxGain;
++ struct ar5416IniArray ini_modes_rx_gain_bounds;
+ struct ar5416IniArray iniModesTxGain;
+ struct ar5416IniArray iniCckfirNormal;
+ struct ar5416IniArray iniCckfirJapan2484;
diff --git a/package/mac80211/patches/579-ath9k-read-spur-frequency-information-from-eeprom-fo.patch b/package/mac80211/patches/579-ath9k-read-spur-frequency-information-from-eeprom-fo.patch
new file mode 100644
index 000000000..fe2f8189d
--- /dev/null
+++ b/package/mac80211/patches/579-ath9k-read-spur-frequency-information-from-eeprom-fo.patch
@@ -0,0 +1,33 @@
+From 987807e9e1a0ec0767635d0bd63003766fb527ad Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:16:06 +0200
+Subject: [PATCH 10/20] ath9k: read spur frequency information from eeprom for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_phy.c | 6 ++++--
+ 1 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -180,7 +180,8 @@ static void ar9003_hw_spur_mitigate_mrc_
+ * is out-of-band and can be ignored.
+ */
+
+- if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
++ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
++ AR_SREV_9550(ah)) {
+ spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
+ IS_CHAN_2GHZ(chan));
+ if (spur_fbin_ptr[0] == 0) /* No spur */
+@@ -207,7 +208,8 @@ static void ar9003_hw_spur_mitigate_mrc_
+ if (AR_SREV_9462(ah) && (i == 0 || i == 3))
+ continue;
+ negative = 0;
+- if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
++ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
++ AR_SREV_9550(ah))
+ cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
+ IS_CHAN_2GHZ(chan));
+ else
diff --git a/package/mac80211/patches/580-ath9k-fix-XPABIASLEVEL-settings-for-AR9550.patch b/package/mac80211/patches/580-ath9k-fix-XPABIASLEVEL-settings-for-AR9550.patch
new file mode 100644
index 000000000..5fc02f9fb
--- /dev/null
+++ b/package/mac80211/patches/580-ath9k-fix-XPABIASLEVEL-settings-for-AR9550.patch
@@ -0,0 +1,36 @@
+From a317eaa189d885e53400dc86c131390be17fd760 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:58 +0200
+Subject: [PATCH 11/20] ath9k: fix XPABIASLEVEL settings for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 2 +-
+ drivers/net/wireless/ath/ath9k/ar9003_phy.h | 4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -3519,7 +3519,7 @@ static void ar9003_hw_xpa_bias_level_app
+
+ if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
+ REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+- else if (AR_SREV_9462(ah))
++ else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
+ REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+ else {
+ REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+@@ -636,8 +636,8 @@
+
+ #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
+ ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
+-#define AR_CH0_TOP_XPABIASLVL (0x300)
+-#define AR_CH0_TOP_XPABIASLVL_S (8)
++#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
++#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
+
+ #define AR_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : \
+ ((AR_SREV_9485(ah) ? 0x1628c : 0x16294)))
diff --git a/package/mac80211/patches/581-ath9k-fix-antenna-control-configuration-for-AR9550.patch b/package/mac80211/patches/581-ath9k-fix-antenna-control-configuration-for-AR9550.patch
new file mode 100644
index 000000000..324e3a0a9
--- /dev/null
+++ b/package/mac80211/patches/581-ath9k-fix-antenna-control-configuration-for-AR9550.patch
@@ -0,0 +1,35 @@
+From 48032d5c88c936fc84a2d676474c5fe714d8ef94 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:58 +0200
+Subject: [PATCH 12/20] ath9k: fix antenna control configuration for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 3 +++
+ drivers/net/wireless/ath/ath9k/ar9003_phy.h | 2 ++
+ 2 files changed, 5 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -3601,6 +3601,9 @@ static void ar9003_hw_ant_ctrl_apply(str
+ if (AR_SREV_9462(ah)) {
+ REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
+ AR_SWITCH_TABLE_COM_AR9462_ALL, value);
++ } else if (AR_SREV_9550(ah)) {
++ REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
++ AR_SWITCH_TABLE_COM_AR9550_ALL, value);
+ } else
+ REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
+ AR_SWITCH_TABLE_COM_ALL, value);
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+@@ -650,6 +650,8 @@
+ #define AR_SWITCH_TABLE_COM_ALL_S (0)
+ #define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
+ #define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
++#define AR_SWITCH_TABLE_COM_AR9550_ALL (0xffffff)
++#define AR_SWITCH_TABLE_COM_AR9550_ALL_S (0)
+ #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
+ #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
+ #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
diff --git a/package/mac80211/patches/582-ath9k-fix-PAPRD-settings-for-AR9550.patch b/package/mac80211/patches/582-ath9k-fix-PAPRD-settings-for-AR9550.patch
new file mode 100644
index 000000000..11188bcd6
--- /dev/null
+++ b/package/mac80211/patches/582-ath9k-fix-PAPRD-settings-for-AR9550.patch
@@ -0,0 +1,22 @@
+From 76ea066dcf42308aec8d20ef75170c1ecae82e60 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:58 +0200
+Subject: [PATCH 13/20] ath9k: fix PAPRD settings for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_paprd.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+@@ -211,7 +211,7 @@ static int ar9003_paprd_setup_single_tab
+ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
+ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
+- if (AR_SREV_9485(ah) || AR_SREV_9462(ah))
++ if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9550(ah))
+ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+ -3);
diff --git a/package/mac80211/patches/583-ath9k-fix-RF-channel-frequency-configuration-for-AR9.patch b/package/mac80211/patches/583-ath9k-fix-RF-channel-frequency-configuration-for-AR9.patch
new file mode 100644
index 000000000..b191bfd22
--- /dev/null
+++ b/package/mac80211/patches/583-ath9k-fix-RF-channel-frequency-configuration-for-AR9.patch
@@ -0,0 +1,32 @@
+From 5e08c36e3ef57712fee83248d0db3d2837e13f5f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:58 +0200
+Subject: [PATCH 14/20] ath9k: fix RF channel frequency configuration for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_phy.c | 5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -99,7 +99,7 @@ static int ar9003_hw_set_channel(struct
+ channelSel = (freq * 4) / 120;
+ chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
+ channelSel = (channelSel << 17) | chan_frac;
+- } else if (AR_SREV_9340(ah)) {
++ } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
+ if (ah->is_clk_25mhz) {
+ u32 chan_frac;
+
+@@ -113,7 +113,8 @@ static int ar9003_hw_set_channel(struct
+ /* Set to 2G mode */
+ bMode = 1;
+ } else {
+- if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
++ if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
++ ah->is_clk_25mhz) {
+ u32 chan_frac;
+
+ channelSel = (freq * 2) / 75;
diff --git a/package/mac80211/patches/584-ath9k-disable-SYNC_HOST1_FATAL-interrupts-for-AR9550.patch b/package/mac80211/patches/584-ath9k-disable-SYNC_HOST1_FATAL-interrupts-for-AR9550.patch
new file mode 100644
index 000000000..9846fcf38
--- /dev/null
+++ b/package/mac80211/patches/584-ath9k-disable-SYNC_HOST1_FATAL-interrupts-for-AR9550.patch
@@ -0,0 +1,34 @@
+From 70a436c98a8479f15fe6ba7f894f88eede238dfa Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:58 +0200
+Subject: [PATCH 15/20] ath9k: disable SYNC_HOST1_FATAL interrupts for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 2 +-
+ drivers/net/wireless/ath/ath9k/mac.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -939,7 +939,7 @@ static void ath9k_hw_init_interrupt_mask
+ AR_IMR_RXORN |
+ AR_IMR_BCNMISC;
+
+- if (AR_SREV_9340(ah))
++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
+ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
+
+ if (AR_SREV_9300_20_OR_LATER(ah)) {
+--- a/drivers/net/wireless/ath/ath9k/mac.c
++++ b/drivers/net/wireless/ath/ath9k/mac.c
+@@ -810,7 +810,7 @@ void ath9k_hw_enable_interrupts(struct a
+ return;
+ }
+
+- if (AR_SREV_9340(ah))
++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
+ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
+
+ async_mask = AR_INTR_MAC_IRQ;
diff --git a/package/mac80211/patches/585-ath9k-skip-internal-regulator-configuration-for-AR95.patch b/package/mac80211/patches/585-ath9k-skip-internal-regulator-configuration-for-AR95.patch
new file mode 100644
index 000000000..9e91f8d99
--- /dev/null
+++ b/package/mac80211/patches/585-ath9k-skip-internal-regulator-configuration-for-AR95.patch
@@ -0,0 +1,22 @@
+From 9c598271929ea9a54f57e82af15260dc4afea590 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:58 +0200
+Subject: [PATCH 16/20] ath9k: skip internal regulator configuration for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -3970,7 +3970,7 @@ static void ath9k_hw_ar9300_set_board_va
+ ar9003_hw_drive_strength_apply(ah);
+ ar9003_hw_atten_apply(ah, chan);
+ ar9003_hw_quick_drop_apply(ah, chan->channel);
+- if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
++ if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
+ ar9003_hw_internal_regulator_apply(ah);
+ if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
+ ar9003_hw_apply_tuning_caps(ah);
diff --git a/package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch b/package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch
new file mode 100644
index 000000000..102363066
--- /dev/null
+++ b/package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch
@@ -0,0 +1,75 @@
+From d211df2956ae9d696bb0cab985426e0d236544b8 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:16:00 +0200
+Subject: [PATCH 17/20] ath9k: fix PLL initialization for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 27 +++++++++++++++++++--------
+ 1 files changed, 19 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -861,7 +861,7 @@ static void ath9k_hw_init_pll(struct ath
+ /* program BB PLL phase_shift */
+ REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
+ AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
+- } else if (AR_SREV_9340(ah)) {
++ } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
+ u32 regval, pll2_divint, pll2_divfrac, refdiv;
+
+ REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
+@@ -875,9 +875,15 @@ static void ath9k_hw_init_pll(struct ath
+ pll2_divfrac = 0x1eb85;
+ refdiv = 3;
+ } else {
+- pll2_divint = 88;
+- pll2_divfrac = 0;
+- refdiv = 5;
++ if (AR_SREV_9340(ah)) {
++ pll2_divint = 88;
++ pll2_divfrac = 0;
++ refdiv = 5;
++ } else {
++ pll2_divint = 0x11;
++ pll2_divfrac = 0x26666;
++ refdiv = 1;
++ }
+ }
+
+ regval = REG_READ(ah, AR_PHY_PLL_MODE);
+@@ -890,8 +896,12 @@ static void ath9k_hw_init_pll(struct ath
+ udelay(100);
+
+ regval = REG_READ(ah, AR_PHY_PLL_MODE);
+- regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
+- (0x4 << 26) | (0x18 << 19);
++ if (AR_SREV_9340(ah))
++ regval = (regval & 0x80071fff) | (0x1 << 30) |
++ (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
++ else
++ regval = (regval & 0x80071fff) | (0x3 << 30) |
++ (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
+ REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
+ REG_WRITE(ah, AR_PHY_PLL_MODE,
+ REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
+@@ -902,7 +912,8 @@ static void ath9k_hw_init_pll(struct ath
+
+ REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+
+- if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
++ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
++ AR_SREV_9550(ah))
+ udelay(1000);
+
+ /* Switch the core clock for ar9271 to 117Mhz */
+@@ -915,7 +926,7 @@ static void ath9k_hw_init_pll(struct ath
+
+ REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
+
+- if (AR_SREV_9340(ah)) {
++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
+ if (ah->is_clk_25mhz) {
+ REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
+ REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
diff --git a/package/mac80211/patches/587-ath9k-enable-PLL-workaround-for-AR9550.patch b/package/mac80211/patches/587-ath9k-enable-PLL-workaround-for-AR9550.patch
new file mode 100644
index 000000000..af03ecd11
--- /dev/null
+++ b/package/mac80211/patches/587-ath9k-enable-PLL-workaround-for-AR9550.patch
@@ -0,0 +1,23 @@
+From 29fe3ae617d86bf1b39d15e43cee29b723118648 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:59 +0200
+Subject: [PATCH 18/20] ath9k: enable PLL workaround for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/main.c | 3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -167,7 +167,8 @@ static void ath_restart_work(struct ath_
+
+ ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
+
+- if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
++ if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
++ AR_SREV_9550(sc->sc_ah))
+ ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
+ msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
+
diff --git a/package/mac80211/patches/588-ath9k-set-4ADDRESS-bit-in-RX-filter-for-AR9550.patch b/package/mac80211/patches/588-ath9k-set-4ADDRESS-bit-in-RX-filter-for-AR9550.patch
new file mode 100644
index 000000000..aba87db0a
--- /dev/null
+++ b/package/mac80211/patches/588-ath9k-set-4ADDRESS-bit-in-RX-filter-for-AR9550.patch
@@ -0,0 +1,34 @@
+From f8e7d8fcb297db362c9288ef5f1cd778e7ddd1a9 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:15:59 +0200
+Subject: [PATCH 19/20] ath9k: set 4ADDRESS bit in RX filter for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/mac.h | 1 +
+ drivers/net/wireless/ath/ath9k/recv.c | 3 +++
+ 2 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/mac.h
++++ b/drivers/net/wireless/ath/ath9k/mac.h
+@@ -642,6 +642,7 @@ enum ath9k_rx_filter {
+ ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
+ ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
+ ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,
++ ATH9K_RX_FILTER_4ADDRESS = 0x00100000,
+ };
+
+ #define ATH9K_RATESERIES_RTS_CTS 0x0001
+--- a/drivers/net/wireless/ath/ath9k/recv.c
++++ b/drivers/net/wireless/ath/ath9k/recv.c
+@@ -430,6 +430,9 @@ u32 ath_calcrxfilter(struct ath_softc *s
+ rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
+ }
+
++ if (AR_SREV_9550(sc->sc_ah))
++ rfilt |= ATH9K_RX_FILTER_4ADDRESS;
++
+ return rfilt;
+
+ }
diff --git a/package/mac80211/patches/589-ath9k-enable-support-for-AR9550.patch b/package/mac80211/patches/589-ath9k-enable-support-for-AR9550.patch
new file mode 100644
index 000000000..5574941c8
--- /dev/null
+++ b/package/mac80211/patches/589-ath9k-enable-support-for-AR9550.patch
@@ -0,0 +1,29 @@
+From 23693513280521914ceb6d92c1bd7613e7b19c58 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 2 Jul 2012 17:16:00 +0200
+Subject: [PATCH 20/20] ath9k: enable support for AR9550
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -658,6 +658,7 @@ static int __ath9k_hw_init(struct ath_hw
+ case AR_SREV_VERSION_9485:
+ case AR_SREV_VERSION_9340:
+ case AR_SREV_VERSION_9462:
++ case AR_SREV_VERSION_9550:
+ break;
+ default:
+ ath_err(common,
+@@ -735,6 +736,7 @@ int ath9k_hw_init(struct ath_hw *ah)
+ case AR9300_DEVID_AR9485_PCIE:
+ case AR9300_DEVID_AR9330:
+ case AR9300_DEVID_AR9340:
++ case AR9300_DEVID_QCA955X:
+ case AR9300_DEVID_AR9580:
+ case AR9300_DEVID_AR9462:
+ break;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 13:23:26 +0000